1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu_ras.h"
24 #include "amdgpu.h"
25 #include "amdgpu_mca.h"
26
27 #define smnMCMP0_STATUST0 0x03830408
28 #define smnMCMP1_STATUST0 0x03b30408
29 #define smnMCMPIO_STATUST0 0x0c930408
30
31
mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)32 static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
33 void *ras_error_status)
34 {
35 amdgpu_mca_query_ras_error_count(adev,
36 smnMCMP0_STATUST0,
37 ras_error_status);
38 }
39
mca_v3_0_mp0_ras_late_init(struct amdgpu_device * adev)40 static int mca_v3_0_mp0_ras_late_init(struct amdgpu_device *adev)
41 {
42 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp0);
43 }
44
mca_v3_0_mp0_ras_fini(struct amdgpu_device * adev)45 static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
46 {
47 amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
48 }
49
50 const struct amdgpu_mca_ras_funcs mca_v3_0_mp0_ras_funcs = {
51 .ras_late_init = mca_v3_0_mp0_ras_late_init,
52 .ras_fini = mca_v3_0_mp0_ras_fini,
53 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
54 .query_ras_error_address = NULL,
55 .ras_block = AMDGPU_RAS_BLOCK__MP0,
56 .sysfs_name = "mp0_err_count",
57 };
58
mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)59 static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
60 void *ras_error_status)
61 {
62 amdgpu_mca_query_ras_error_count(adev,
63 smnMCMP1_STATUST0,
64 ras_error_status);
65 }
66
mca_v3_0_mp1_ras_late_init(struct amdgpu_device * adev)67 static int mca_v3_0_mp1_ras_late_init(struct amdgpu_device *adev)
68 {
69 return amdgpu_mca_ras_late_init(adev, &adev->mca.mp1);
70 }
71
mca_v3_0_mp1_ras_fini(struct amdgpu_device * adev)72 static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev)
73 {
74 amdgpu_mca_ras_fini(adev, &adev->mca.mp1);
75 }
76
77 const struct amdgpu_mca_ras_funcs mca_v3_0_mp1_ras_funcs = {
78 .ras_late_init = mca_v3_0_mp1_ras_late_init,
79 .ras_fini = mca_v3_0_mp1_ras_fini,
80 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
81 .query_ras_error_address = NULL,
82 .ras_block = AMDGPU_RAS_BLOCK__MP1,
83 .sysfs_name = "mp1_err_count",
84 };
85
mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device * adev,void * ras_error_status)86 static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
87 void *ras_error_status)
88 {
89 amdgpu_mca_query_ras_error_count(adev,
90 smnMCMPIO_STATUST0,
91 ras_error_status);
92 }
93
mca_v3_0_mpio_ras_late_init(struct amdgpu_device * adev)94 static int mca_v3_0_mpio_ras_late_init(struct amdgpu_device *adev)
95 {
96 return amdgpu_mca_ras_late_init(adev, &adev->mca.mpio);
97 }
98
mca_v3_0_mpio_ras_fini(struct amdgpu_device * adev)99 static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev)
100 {
101 amdgpu_mca_ras_fini(adev, &adev->mca.mpio);
102 }
103
104 const struct amdgpu_mca_ras_funcs mca_v3_0_mpio_ras_funcs = {
105 .ras_late_init = mca_v3_0_mpio_ras_late_init,
106 .ras_fini = mca_v3_0_mpio_ras_fini,
107 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
108 .query_ras_error_address = NULL,
109 .ras_block = AMDGPU_RAS_BLOCK__MPIO,
110 .sysfs_name = "mpio_err_count",
111 };
112
113
mca_v3_0_init(struct amdgpu_device * adev)114 static void mca_v3_0_init(struct amdgpu_device *adev)
115 {
116 struct amdgpu_mca *mca = &adev->mca;
117
118 mca->mp0.ras_funcs = &mca_v3_0_mp0_ras_funcs;
119 mca->mp1.ras_funcs = &mca_v3_0_mp1_ras_funcs;
120 mca->mpio.ras_funcs = &mca_v3_0_mpio_ras_funcs;
121 }
122
123 const struct amdgpu_mca_funcs mca_v3_0_funcs = {
124 .init = mca_v3_0_init,
125 };