1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v12_0_ppsmc.h"
29 #include "smu12_driver_if.h"
30 #include "smu_v12_0.h"
31 #include "renoir_ppt.h"
32 #include "smu_cmn.h"
33
34 /*
35 * DO NOT use these for err/warn/info/debug messages.
36 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
37 * They are more MGPU friendly.
38 */
39 #undef pr_err
40 #undef pr_warn
41 #undef pr_info
42 #undef pr_debug
43
44 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
45 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
46 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
47 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
48 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
49 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
50 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
51 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
52 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
53 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
54 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
55 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
56 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
57 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
58 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
59 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
60 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
61 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
62 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
63 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
64 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
65 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
66 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
67 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
68 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
69 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
70 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
71 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
72 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
73 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
74 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
75 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
76 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
77 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
78 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
79 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
80 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
81 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
82 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
83 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
84 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
85 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
86 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
87 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
88 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
89 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
90 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
91 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
92 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
93 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
94 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
95 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
96 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
97 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
98 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
99 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
100 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
101 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
102 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
103 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
104 };
105
106 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
107 CLK_MAP(GFXCLK, CLOCK_GFXCLK),
108 CLK_MAP(SCLK, CLOCK_GFXCLK),
109 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
110 CLK_MAP(UCLK, CLOCK_FCLK),
111 CLK_MAP(MCLK, CLOCK_FCLK),
112 CLK_MAP(VCLK, CLOCK_VCLK),
113 CLK_MAP(DCLK, CLOCK_DCLK),
114 };
115
116 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
117 TAB_MAP_VALID(WATERMARKS),
118 TAB_MAP_INVALID(CUSTOM_DPM),
119 TAB_MAP_VALID(DPMCLOCKS),
120 TAB_MAP_VALID(SMU_METRICS),
121 };
122
123 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
124 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
125 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
126 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
127 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
128 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
129 };
130
131 static const uint8_t renoir_throttler_map[] = {
132 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
133 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
134 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
135 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
136 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
137 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
138 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
139 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
140 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
141 [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT),
142 [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
143 [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT),
144 [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT),
145 };
146
renoir_init_smc_tables(struct smu_context * smu)147 static int renoir_init_smc_tables(struct smu_context *smu)
148 {
149 struct smu_table_context *smu_table = &smu->smu_table;
150 struct smu_table *tables = smu_table->tables;
151
152 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
153 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
154 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
155 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
156 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
157 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
158
159 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
160 if (!smu_table->clocks_table)
161 goto err0_out;
162
163 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
164 if (!smu_table->metrics_table)
165 goto err1_out;
166 smu_table->metrics_time = 0;
167
168 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
169 if (!smu_table->watermarks_table)
170 goto err2_out;
171
172 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
173 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
174 if (!smu_table->gpu_metrics_table)
175 goto err3_out;
176
177 return 0;
178
179 err3_out:
180 kfree(smu_table->watermarks_table);
181 err2_out:
182 kfree(smu_table->metrics_table);
183 err1_out:
184 kfree(smu_table->clocks_table);
185 err0_out:
186 return -ENOMEM;
187 }
188
189 /*
190 * This interface just for getting uclk ultimate freq and should't introduce
191 * other likewise function result in overmuch callback.
192 */
renoir_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)193 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
194 uint32_t dpm_level, uint32_t *freq)
195 {
196 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
197
198 if (!clk_table || clk_type >= SMU_CLK_COUNT)
199 return -EINVAL;
200
201 switch (clk_type) {
202 case SMU_SOCCLK:
203 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
204 return -EINVAL;
205 *freq = clk_table->SocClocks[dpm_level].Freq;
206 break;
207 case SMU_UCLK:
208 case SMU_MCLK:
209 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
210 return -EINVAL;
211 *freq = clk_table->FClocks[dpm_level].Freq;
212 break;
213 case SMU_DCEFCLK:
214 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
215 return -EINVAL;
216 *freq = clk_table->DcfClocks[dpm_level].Freq;
217 break;
218 case SMU_FCLK:
219 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
220 return -EINVAL;
221 *freq = clk_table->FClocks[dpm_level].Freq;
222 break;
223 case SMU_VCLK:
224 if (dpm_level >= NUM_VCN_DPM_LEVELS)
225 return -EINVAL;
226 *freq = clk_table->VClocks[dpm_level].Freq;
227 break;
228 case SMU_DCLK:
229 if (dpm_level >= NUM_VCN_DPM_LEVELS)
230 return -EINVAL;
231 *freq = clk_table->DClocks[dpm_level].Freq;
232 break;
233
234 default:
235 return -EINVAL;
236 }
237
238 return 0;
239 }
240
renoir_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)241 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
242 enum amd_dpm_forced_level level,
243 uint32_t *sclk_mask,
244 uint32_t *mclk_mask,
245 uint32_t *soc_mask)
246 {
247
248 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
249 if (sclk_mask)
250 *sclk_mask = 0;
251 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
252 if (mclk_mask)
253 /* mclk levels are in reverse order */
254 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
255 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
256 if(sclk_mask)
257 /* The sclk as gfxclk and has three level about max/min/current */
258 *sclk_mask = 3 - 1;
259
260 if(mclk_mask)
261 /* mclk levels are in reverse order */
262 *mclk_mask = 0;
263
264 if(soc_mask)
265 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
266 }
267
268 return 0;
269 }
270
renoir_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)271 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
272 enum smu_clk_type clk_type,
273 uint32_t *min,
274 uint32_t *max)
275 {
276 int ret = 0;
277 uint32_t mclk_mask, soc_mask;
278 uint32_t clock_limit;
279
280 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
281 switch (clk_type) {
282 case SMU_MCLK:
283 case SMU_UCLK:
284 clock_limit = smu->smu_table.boot_values.uclk;
285 break;
286 case SMU_GFXCLK:
287 case SMU_SCLK:
288 clock_limit = smu->smu_table.boot_values.gfxclk;
289 break;
290 case SMU_SOCCLK:
291 clock_limit = smu->smu_table.boot_values.socclk;
292 break;
293 default:
294 clock_limit = 0;
295 break;
296 }
297
298 /* clock in Mhz unit */
299 if (min)
300 *min = clock_limit / 100;
301 if (max)
302 *max = clock_limit / 100;
303
304 return 0;
305 }
306
307 if (max) {
308 ret = renoir_get_profiling_clk_mask(smu,
309 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
310 NULL,
311 &mclk_mask,
312 &soc_mask);
313 if (ret)
314 goto failed;
315
316 switch (clk_type) {
317 case SMU_GFXCLK:
318 case SMU_SCLK:
319 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
320 if (ret) {
321 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
322 goto failed;
323 }
324 break;
325 case SMU_UCLK:
326 case SMU_FCLK:
327 case SMU_MCLK:
328 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
329 if (ret)
330 goto failed;
331 break;
332 case SMU_SOCCLK:
333 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
334 if (ret)
335 goto failed;
336 break;
337 default:
338 ret = -EINVAL;
339 goto failed;
340 }
341 }
342
343 if (min) {
344 switch (clk_type) {
345 case SMU_GFXCLK:
346 case SMU_SCLK:
347 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
348 if (ret) {
349 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
350 goto failed;
351 }
352 break;
353 case SMU_UCLK:
354 case SMU_FCLK:
355 case SMU_MCLK:
356 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
357 if (ret)
358 goto failed;
359 break;
360 case SMU_SOCCLK:
361 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
362 if (ret)
363 goto failed;
364 break;
365 default:
366 ret = -EINVAL;
367 goto failed;
368 }
369 }
370 failed:
371 return ret;
372 }
373
renoir_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)374 static int renoir_od_edit_dpm_table(struct smu_context *smu,
375 enum PP_OD_DPM_TABLE_COMMAND type,
376 long input[], uint32_t size)
377 {
378 int ret = 0;
379 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
380
381 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
382 dev_warn(smu->adev->dev,
383 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
384 return -EINVAL;
385 }
386
387 switch (type) {
388 case PP_OD_EDIT_SCLK_VDDC_TABLE:
389 if (size != 2) {
390 dev_err(smu->adev->dev, "Input parameter number not correct\n");
391 return -EINVAL;
392 }
393
394 if (input[0] == 0) {
395 if (input[1] < smu->gfx_default_hard_min_freq) {
396 dev_warn(smu->adev->dev,
397 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
398 input[1], smu->gfx_default_hard_min_freq);
399 return -EINVAL;
400 }
401 smu->gfx_actual_hard_min_freq = input[1];
402 } else if (input[0] == 1) {
403 if (input[1] > smu->gfx_default_soft_max_freq) {
404 dev_warn(smu->adev->dev,
405 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
406 input[1], smu->gfx_default_soft_max_freq);
407 return -EINVAL;
408 }
409 smu->gfx_actual_soft_max_freq = input[1];
410 } else {
411 return -EINVAL;
412 }
413 break;
414 case PP_OD_RESTORE_DEFAULT_TABLE:
415 if (size != 0) {
416 dev_err(smu->adev->dev, "Input parameter number not correct\n");
417 return -EINVAL;
418 }
419 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
420 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
421 break;
422 case PP_OD_COMMIT_DPM_TABLE:
423 if (size != 0) {
424 dev_err(smu->adev->dev, "Input parameter number not correct\n");
425 return -EINVAL;
426 } else {
427 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
428 dev_err(smu->adev->dev,
429 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
430 smu->gfx_actual_hard_min_freq,
431 smu->gfx_actual_soft_max_freq);
432 return -EINVAL;
433 }
434
435 ret = smu_cmn_send_smc_msg_with_param(smu,
436 SMU_MSG_SetHardMinGfxClk,
437 smu->gfx_actual_hard_min_freq,
438 NULL);
439 if (ret) {
440 dev_err(smu->adev->dev, "Set hard min sclk failed!");
441 return ret;
442 }
443
444 ret = smu_cmn_send_smc_msg_with_param(smu,
445 SMU_MSG_SetSoftMaxGfxClk,
446 smu->gfx_actual_soft_max_freq,
447 NULL);
448 if (ret) {
449 dev_err(smu->adev->dev, "Set soft max sclk failed!");
450 return ret;
451 }
452 }
453 break;
454 default:
455 return -ENOSYS;
456 }
457
458 return ret;
459 }
460
renoir_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)461 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
462 {
463 uint32_t min = 0, max = 0;
464 uint32_t ret = 0;
465
466 ret = smu_cmn_send_smc_msg_with_param(smu,
467 SMU_MSG_GetMinGfxclkFrequency,
468 0, &min);
469 if (ret)
470 return ret;
471 ret = smu_cmn_send_smc_msg_with_param(smu,
472 SMU_MSG_GetMaxGfxclkFrequency,
473 0, &max);
474 if (ret)
475 return ret;
476
477 smu->gfx_default_hard_min_freq = min;
478 smu->gfx_default_soft_max_freq = max;
479 smu->gfx_actual_hard_min_freq = 0;
480 smu->gfx_actual_soft_max_freq = 0;
481
482 return 0;
483 }
484
renoir_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)485 static int renoir_print_clk_levels(struct smu_context *smu,
486 enum smu_clk_type clk_type, char *buf)
487 {
488 int i, idx, size = 0, ret = 0;
489 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
490 SmuMetrics_t metrics;
491 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
492 bool cur_value_match_level = false;
493
494 memset(&metrics, 0, sizeof(metrics));
495
496 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
497 if (ret)
498 return ret;
499
500 smu_cmn_get_sysfs_buf(&buf, &size);
501
502 switch (clk_type) {
503 case SMU_OD_RANGE:
504 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
505 ret = smu_cmn_send_smc_msg_with_param(smu,
506 SMU_MSG_GetMinGfxclkFrequency,
507 0, &min);
508 if (ret)
509 return ret;
510 ret = smu_cmn_send_smc_msg_with_param(smu,
511 SMU_MSG_GetMaxGfxclkFrequency,
512 0, &max);
513 if (ret)
514 return ret;
515 size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
516 }
517 break;
518 case SMU_OD_SCLK:
519 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
520 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
521 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
522 size += sysfs_emit_at(buf, size, "OD_SCLK\n");
523 size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
524 size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
525 }
526 break;
527 case SMU_GFXCLK:
528 case SMU_SCLK:
529 /* retirve table returned paramters unit is MHz */
530 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
531 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
532 if (!ret) {
533 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
534 if (cur_value == max)
535 i = 2;
536 else if (cur_value == min)
537 i = 0;
538 else
539 i = 1;
540
541 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
542 i == 0 ? "*" : "");
543 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
544 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
545 i == 1 ? "*" : "");
546 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
547 i == 2 ? "*" : "");
548 }
549 return size;
550 case SMU_SOCCLK:
551 count = NUM_SOCCLK_DPM_LEVELS;
552 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
553 break;
554 case SMU_MCLK:
555 count = NUM_MEMCLK_DPM_LEVELS;
556 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
557 break;
558 case SMU_DCEFCLK:
559 count = NUM_DCFCLK_DPM_LEVELS;
560 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
561 break;
562 case SMU_FCLK:
563 count = NUM_FCLK_DPM_LEVELS;
564 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
565 break;
566 case SMU_VCLK:
567 count = NUM_VCN_DPM_LEVELS;
568 cur_value = metrics.ClockFrequency[CLOCK_VCLK];
569 break;
570 case SMU_DCLK:
571 count = NUM_VCN_DPM_LEVELS;
572 cur_value = metrics.ClockFrequency[CLOCK_DCLK];
573 break;
574 default:
575 break;
576 }
577
578 switch (clk_type) {
579 case SMU_GFXCLK:
580 case SMU_SCLK:
581 case SMU_SOCCLK:
582 case SMU_MCLK:
583 case SMU_DCEFCLK:
584 case SMU_FCLK:
585 case SMU_VCLK:
586 case SMU_DCLK:
587 for (i = 0; i < count; i++) {
588 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
589 ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);
590 if (ret)
591 return ret;
592 if (!value)
593 continue;
594 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
595 cur_value == value ? "*" : "");
596 if (cur_value == value)
597 cur_value_match_level = true;
598 }
599
600 if (!cur_value_match_level)
601 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
602
603 break;
604 default:
605 break;
606 }
607
608 return size;
609 }
610
renoir_get_current_power_state(struct smu_context * smu)611 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
612 {
613 enum amd_pm_state_type pm_type;
614 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
615
616 if (!smu_dpm_ctx->dpm_context ||
617 !smu_dpm_ctx->dpm_current_power_state)
618 return -EINVAL;
619
620 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
621 case SMU_STATE_UI_LABEL_BATTERY:
622 pm_type = POWER_STATE_TYPE_BATTERY;
623 break;
624 case SMU_STATE_UI_LABEL_BALLANCED:
625 pm_type = POWER_STATE_TYPE_BALANCED;
626 break;
627 case SMU_STATE_UI_LABEL_PERFORMANCE:
628 pm_type = POWER_STATE_TYPE_PERFORMANCE;
629 break;
630 default:
631 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
632 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
633 else
634 pm_type = POWER_STATE_TYPE_DEFAULT;
635 break;
636 }
637
638 return pm_type;
639 }
640
renoir_dpm_set_vcn_enable(struct smu_context * smu,bool enable)641 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
642 {
643 int ret = 0;
644
645 if (enable) {
646 /* vcn dpm on is a prerequisite for vcn power gate messages */
647 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
648 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
649 if (ret)
650 return ret;
651 }
652 } else {
653 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
654 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
655 if (ret)
656 return ret;
657 }
658 }
659
660 return ret;
661 }
662
renoir_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)663 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
664 {
665 int ret = 0;
666
667 if (enable) {
668 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
669 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
670 if (ret)
671 return ret;
672 }
673 } else {
674 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
675 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
676 if (ret)
677 return ret;
678 }
679 }
680
681 return ret;
682 }
683
renoir_force_dpm_limit_value(struct smu_context * smu,bool highest)684 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
685 {
686 int ret = 0, i = 0;
687 uint32_t min_freq, max_freq, force_freq;
688 enum smu_clk_type clk_type;
689
690 enum smu_clk_type clks[] = {
691 SMU_GFXCLK,
692 SMU_MCLK,
693 SMU_SOCCLK,
694 };
695
696 for (i = 0; i < ARRAY_SIZE(clks); i++) {
697 clk_type = clks[i];
698 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
699 if (ret)
700 return ret;
701
702 force_freq = highest ? max_freq : min_freq;
703 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
704 if (ret)
705 return ret;
706 }
707
708 return ret;
709 }
710
renoir_unforce_dpm_levels(struct smu_context * smu)711 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
712
713 int ret = 0, i = 0;
714 uint32_t min_freq, max_freq;
715 enum smu_clk_type clk_type;
716
717 struct clk_feature_map {
718 enum smu_clk_type clk_type;
719 uint32_t feature;
720 } clk_feature_map[] = {
721 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
722 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
723 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
724 };
725
726 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
727 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
728 continue;
729
730 clk_type = clk_feature_map[i].clk_type;
731
732 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
733 if (ret)
734 return ret;
735
736 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
737 if (ret)
738 return ret;
739 }
740
741 return ret;
742 }
743
744 /*
745 * This interface get dpm clock table for dc
746 */
renoir_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)747 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
748 {
749 DpmClocks_t *table = smu->smu_table.clocks_table;
750 int i;
751
752 if (!clock_table || !table)
753 return -EINVAL;
754
755 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
756 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
757 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
758 }
759
760 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
761 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
762 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
763 }
764
765 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
766 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
767 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
768 }
769
770 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
771 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
772 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
773 }
774
775 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
776 clock_table->VClocks[i].Freq = table->VClocks[i].Freq;
777 clock_table->VClocks[i].Vol = table->VClocks[i].Vol;
778 }
779
780 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
781 clock_table->DClocks[i].Freq = table->DClocks[i].Freq;
782 clock_table->DClocks[i].Vol = table->DClocks[i].Vol;
783 }
784
785 return 0;
786 }
787
renoir_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)788 static int renoir_force_clk_levels(struct smu_context *smu,
789 enum smu_clk_type clk_type, uint32_t mask)
790 {
791
792 int ret = 0 ;
793 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
794
795 soft_min_level = mask ? (ffs(mask) - 1) : 0;
796 soft_max_level = mask ? (fls(mask) - 1) : 0;
797
798 switch (clk_type) {
799 case SMU_GFXCLK:
800 case SMU_SCLK:
801 if (soft_min_level > 2 || soft_max_level > 2) {
802 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
803 return -EINVAL;
804 }
805
806 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
807 if (ret)
808 return ret;
809 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
810 soft_max_level == 0 ? min_freq :
811 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
812 NULL);
813 if (ret)
814 return ret;
815 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
816 soft_min_level == 2 ? max_freq :
817 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
818 NULL);
819 if (ret)
820 return ret;
821 break;
822 case SMU_SOCCLK:
823 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
824 if (ret)
825 return ret;
826 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
827 if (ret)
828 return ret;
829 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
830 if (ret)
831 return ret;
832 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
833 if (ret)
834 return ret;
835 break;
836 case SMU_MCLK:
837 case SMU_FCLK:
838 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
839 if (ret)
840 return ret;
841 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
842 if (ret)
843 return ret;
844 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
845 if (ret)
846 return ret;
847 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
848 if (ret)
849 return ret;
850 break;
851 default:
852 break;
853 }
854
855 return ret;
856 }
857
renoir_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)858 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
859 {
860 int workload_type, ret;
861 uint32_t profile_mode = input[size];
862
863 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
864 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
865 return -EINVAL;
866 }
867
868 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
869 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
870 return 0;
871
872 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
873 workload_type = smu_cmn_to_asic_specific_index(smu,
874 CMN2ASIC_MAPPING_WORKLOAD,
875 profile_mode);
876 if (workload_type < 0) {
877 /*
878 * TODO: If some case need switch to powersave/default power mode
879 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
880 */
881 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
882 return -EINVAL;
883 }
884
885 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
886 1 << workload_type,
887 NULL);
888 if (ret) {
889 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
890 return ret;
891 }
892
893 smu->power_profile_mode = profile_mode;
894
895 return 0;
896 }
897
renoir_set_peak_clock_by_device(struct smu_context * smu)898 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
899 {
900 int ret = 0;
901 uint32_t sclk_freq = 0, uclk_freq = 0;
902
903 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
904 if (ret)
905 return ret;
906
907 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
908 if (ret)
909 return ret;
910
911 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
912 if (ret)
913 return ret;
914
915 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
916 if (ret)
917 return ret;
918
919 return ret;
920 }
921
renoir_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)922 static int renoir_set_performance_level(struct smu_context *smu,
923 enum amd_dpm_forced_level level)
924 {
925 int ret = 0;
926 uint32_t sclk_mask, mclk_mask, soc_mask;
927
928 switch (level) {
929 case AMD_DPM_FORCED_LEVEL_HIGH:
930 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
931 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
932
933 ret = renoir_force_dpm_limit_value(smu, true);
934 break;
935 case AMD_DPM_FORCED_LEVEL_LOW:
936 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
937 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
938
939 ret = renoir_force_dpm_limit_value(smu, false);
940 break;
941 case AMD_DPM_FORCED_LEVEL_AUTO:
942 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
943 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
944
945 ret = renoir_unforce_dpm_levels(smu);
946 break;
947 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
948 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
949 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
950
951 ret = smu_cmn_send_smc_msg_with_param(smu,
952 SMU_MSG_SetHardMinGfxClk,
953 RENOIR_UMD_PSTATE_GFXCLK,
954 NULL);
955 if (ret)
956 return ret;
957 ret = smu_cmn_send_smc_msg_with_param(smu,
958 SMU_MSG_SetHardMinFclkByFreq,
959 RENOIR_UMD_PSTATE_FCLK,
960 NULL);
961 if (ret)
962 return ret;
963 ret = smu_cmn_send_smc_msg_with_param(smu,
964 SMU_MSG_SetHardMinSocclkByFreq,
965 RENOIR_UMD_PSTATE_SOCCLK,
966 NULL);
967 if (ret)
968 return ret;
969 ret = smu_cmn_send_smc_msg_with_param(smu,
970 SMU_MSG_SetHardMinVcn,
971 RENOIR_UMD_PSTATE_VCNCLK,
972 NULL);
973 if (ret)
974 return ret;
975
976 ret = smu_cmn_send_smc_msg_with_param(smu,
977 SMU_MSG_SetSoftMaxGfxClk,
978 RENOIR_UMD_PSTATE_GFXCLK,
979 NULL);
980 if (ret)
981 return ret;
982 ret = smu_cmn_send_smc_msg_with_param(smu,
983 SMU_MSG_SetSoftMaxFclkByFreq,
984 RENOIR_UMD_PSTATE_FCLK,
985 NULL);
986 if (ret)
987 return ret;
988 ret = smu_cmn_send_smc_msg_with_param(smu,
989 SMU_MSG_SetSoftMaxSocclkByFreq,
990 RENOIR_UMD_PSTATE_SOCCLK,
991 NULL);
992 if (ret)
993 return ret;
994 ret = smu_cmn_send_smc_msg_with_param(smu,
995 SMU_MSG_SetSoftMaxVcn,
996 RENOIR_UMD_PSTATE_VCNCLK,
997 NULL);
998 if (ret)
999 return ret;
1000 break;
1001 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1002 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1003 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1004 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1005
1006 ret = renoir_get_profiling_clk_mask(smu, level,
1007 &sclk_mask,
1008 &mclk_mask,
1009 &soc_mask);
1010 if (ret)
1011 return ret;
1012 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1013 renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1014 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1015 break;
1016 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1017 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1018 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1019
1020 ret = renoir_set_peak_clock_by_device(smu);
1021 break;
1022 case AMD_DPM_FORCED_LEVEL_MANUAL:
1023 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1024 default:
1025 break;
1026 }
1027 return ret;
1028 }
1029
1030 /* save watermark settings into pplib smu structure,
1031 * also pass data to smu controller
1032 */
renoir_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1033 static int renoir_set_watermarks_table(
1034 struct smu_context *smu,
1035 struct pp_smu_wm_range_sets *clock_ranges)
1036 {
1037 Watermarks_t *table = smu->smu_table.watermarks_table;
1038 int ret = 0;
1039 int i;
1040
1041 if (clock_ranges) {
1042 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1043 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1044 return -EINVAL;
1045
1046 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
1047 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1048 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1049 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1050 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1051 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1052 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1053 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1054 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1055 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1056
1057 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1058 clock_ranges->reader_wm_sets[i].wm_inst;
1059 table->WatermarkRow[WM_DCFCLK][i].WmType =
1060 clock_ranges->reader_wm_sets[i].wm_type;
1061 }
1062
1063 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1064 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1065 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1066 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1067 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1068 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1069 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1070 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1071 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1072
1073 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1074 clock_ranges->writer_wm_sets[i].wm_inst;
1075 table->WatermarkRow[WM_SOCCLK][i].WmType =
1076 clock_ranges->writer_wm_sets[i].wm_type;
1077 }
1078
1079 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1080 }
1081
1082 /* pass data to smu controller */
1083 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1084 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1085 ret = smu_cmn_write_watermarks_table(smu);
1086 if (ret) {
1087 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1088 return ret;
1089 }
1090 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1091 }
1092
1093 return 0;
1094 }
1095
renoir_get_power_profile_mode(struct smu_context * smu,char * buf)1096 static int renoir_get_power_profile_mode(struct smu_context *smu,
1097 char *buf)
1098 {
1099 static const char *profile_name[] = {
1100 "BOOTUP_DEFAULT",
1101 "3D_FULL_SCREEN",
1102 "POWER_SAVING",
1103 "VIDEO",
1104 "VR",
1105 "COMPUTE",
1106 "CUSTOM"};
1107 uint32_t i, size = 0;
1108 int16_t workload_type = 0;
1109
1110 if (!buf)
1111 return -EINVAL;
1112
1113 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1114 /*
1115 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1116 * Not all profile modes are supported on arcturus.
1117 */
1118 workload_type = smu_cmn_to_asic_specific_index(smu,
1119 CMN2ASIC_MAPPING_WORKLOAD,
1120 i);
1121 if (workload_type < 0)
1122 continue;
1123
1124 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1125 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1126 }
1127
1128 return size;
1129 }
1130
renoir_get_ss_power_percent(SmuMetrics_t * metrics,uint32_t * apu_percent,uint32_t * dgpu_percent)1131 static void renoir_get_ss_power_percent(SmuMetrics_t *metrics,
1132 uint32_t *apu_percent, uint32_t *dgpu_percent)
1133 {
1134 uint32_t apu_boost = 0;
1135 uint32_t dgpu_boost = 0;
1136 uint16_t apu_limit = 0;
1137 uint16_t dgpu_limit = 0;
1138 uint16_t apu_power = 0;
1139 uint16_t dgpu_power = 0;
1140
1141 apu_power = metrics->ApuPower;
1142 apu_limit = metrics->StapmOriginalLimit;
1143 if (apu_power > apu_limit && apu_limit != 0)
1144 apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
1145 apu_boost = (apu_boost > 100) ? 100 : apu_boost;
1146
1147 dgpu_power = metrics->dGpuPower;
1148 if (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit)
1149 dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOriginalLimit;
1150 if (dgpu_power > dgpu_limit && dgpu_limit != 0)
1151 dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
1152 dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
1153
1154 if (dgpu_boost >= apu_boost)
1155 apu_boost = 0;
1156 else
1157 dgpu_boost = 0;
1158
1159 *apu_percent = apu_boost;
1160 *dgpu_percent = dgpu_boost;
1161 }
1162
1163
renoir_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1164 static int renoir_get_smu_metrics_data(struct smu_context *smu,
1165 MetricsMember_t member,
1166 uint32_t *value)
1167 {
1168 struct smu_table_context *smu_table = &smu->smu_table;
1169
1170 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
1171 int ret = 0;
1172 uint32_t apu_percent = 0;
1173 uint32_t dgpu_percent = 0;
1174
1175
1176 mutex_lock(&smu->metrics_lock);
1177
1178 ret = smu_cmn_get_metrics_table_locked(smu,
1179 NULL,
1180 false);
1181 if (ret) {
1182 mutex_unlock(&smu->metrics_lock);
1183 return ret;
1184 }
1185
1186 switch (member) {
1187 case METRICS_AVERAGE_GFXCLK:
1188 *value = metrics->ClockFrequency[CLOCK_GFXCLK];
1189 break;
1190 case METRICS_AVERAGE_SOCCLK:
1191 *value = metrics->ClockFrequency[CLOCK_SOCCLK];
1192 break;
1193 case METRICS_AVERAGE_UCLK:
1194 *value = metrics->ClockFrequency[CLOCK_FCLK];
1195 break;
1196 case METRICS_AVERAGE_GFXACTIVITY:
1197 *value = metrics->AverageGfxActivity / 100;
1198 break;
1199 case METRICS_AVERAGE_VCNACTIVITY:
1200 *value = metrics->AverageUvdActivity / 100;
1201 break;
1202 case METRICS_AVERAGE_SOCKETPOWER:
1203 *value = (metrics->CurrentSocketPower << 8) / 1000;
1204 break;
1205 case METRICS_TEMPERATURE_EDGE:
1206 *value = (metrics->GfxTemperature / 100) *
1207 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1208 break;
1209 case METRICS_TEMPERATURE_HOTSPOT:
1210 *value = (metrics->SocTemperature / 100) *
1211 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1212 break;
1213 case METRICS_THROTTLER_STATUS:
1214 *value = metrics->ThrottlerStatus;
1215 break;
1216 case METRICS_VOLTAGE_VDDGFX:
1217 *value = metrics->Voltage[0];
1218 break;
1219 case METRICS_VOLTAGE_VDDSOC:
1220 *value = metrics->Voltage[1];
1221 break;
1222 case METRICS_SS_APU_SHARE:
1223 /* return the percentage of APU power boost
1224 * with respect to APU's power limit.
1225 */
1226 renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1227 *value = apu_percent;
1228 break;
1229 case METRICS_SS_DGPU_SHARE:
1230 /* return the percentage of dGPU power boost
1231 * with respect to dGPU's power limit.
1232 */
1233 renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1234 *value = dgpu_percent;
1235 break;
1236 default:
1237 *value = UINT_MAX;
1238 break;
1239 }
1240
1241 mutex_unlock(&smu->metrics_lock);
1242
1243 return ret;
1244 }
1245
renoir_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1246 static int renoir_read_sensor(struct smu_context *smu,
1247 enum amd_pp_sensors sensor,
1248 void *data, uint32_t *size)
1249 {
1250 int ret = 0;
1251
1252 if (!data || !size)
1253 return -EINVAL;
1254
1255 mutex_lock(&smu->sensor_lock);
1256 switch (sensor) {
1257 case AMDGPU_PP_SENSOR_GPU_LOAD:
1258 ret = renoir_get_smu_metrics_data(smu,
1259 METRICS_AVERAGE_GFXACTIVITY,
1260 (uint32_t *)data);
1261 *size = 4;
1262 break;
1263 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1264 ret = renoir_get_smu_metrics_data(smu,
1265 METRICS_TEMPERATURE_EDGE,
1266 (uint32_t *)data);
1267 *size = 4;
1268 break;
1269 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1270 ret = renoir_get_smu_metrics_data(smu,
1271 METRICS_TEMPERATURE_HOTSPOT,
1272 (uint32_t *)data);
1273 *size = 4;
1274 break;
1275 case AMDGPU_PP_SENSOR_GFX_MCLK:
1276 ret = renoir_get_smu_metrics_data(smu,
1277 METRICS_AVERAGE_UCLK,
1278 (uint32_t *)data);
1279 *(uint32_t *)data *= 100;
1280 *size = 4;
1281 break;
1282 case AMDGPU_PP_SENSOR_GFX_SCLK:
1283 ret = renoir_get_smu_metrics_data(smu,
1284 METRICS_AVERAGE_GFXCLK,
1285 (uint32_t *)data);
1286 *(uint32_t *)data *= 100;
1287 *size = 4;
1288 break;
1289 case AMDGPU_PP_SENSOR_VDDGFX:
1290 ret = renoir_get_smu_metrics_data(smu,
1291 METRICS_VOLTAGE_VDDGFX,
1292 (uint32_t *)data);
1293 *size = 4;
1294 break;
1295 case AMDGPU_PP_SENSOR_VDDNB:
1296 ret = renoir_get_smu_metrics_data(smu,
1297 METRICS_VOLTAGE_VDDSOC,
1298 (uint32_t *)data);
1299 *size = 4;
1300 break;
1301 case AMDGPU_PP_SENSOR_GPU_POWER:
1302 ret = renoir_get_smu_metrics_data(smu,
1303 METRICS_AVERAGE_SOCKETPOWER,
1304 (uint32_t *)data);
1305 *size = 4;
1306 break;
1307 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1308 ret = renoir_get_smu_metrics_data(smu,
1309 METRICS_SS_APU_SHARE,
1310 (uint32_t *)data);
1311 *size = 4;
1312 break;
1313 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1314 ret = renoir_get_smu_metrics_data(smu,
1315 METRICS_SS_DGPU_SHARE,
1316 (uint32_t *)data);
1317 *size = 4;
1318 break;
1319 default:
1320 ret = -EOPNOTSUPP;
1321 break;
1322 }
1323 mutex_unlock(&smu->sensor_lock);
1324
1325 return ret;
1326 }
1327
renoir_is_dpm_running(struct smu_context * smu)1328 static bool renoir_is_dpm_running(struct smu_context *smu)
1329 {
1330 struct amdgpu_device *adev = smu->adev;
1331
1332 /*
1333 * Until now, the pmfw hasn't exported the interface of SMU
1334 * feature mask to APU SKU so just force on all the feature
1335 * at early initial stage.
1336 */
1337 if (adev->in_suspend)
1338 return false;
1339 else
1340 return true;
1341
1342 }
1343
renoir_get_gpu_metrics(struct smu_context * smu,void ** table)1344 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1345 void **table)
1346 {
1347 struct smu_table_context *smu_table = &smu->smu_table;
1348 struct gpu_metrics_v2_2 *gpu_metrics =
1349 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1350 SmuMetrics_t metrics;
1351 int ret = 0;
1352
1353 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1354 if (ret)
1355 return ret;
1356
1357 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1358
1359 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1360 gpu_metrics->temperature_soc = metrics.SocTemperature;
1361 memcpy(&gpu_metrics->temperature_core[0],
1362 &metrics.CoreTemperature[0],
1363 sizeof(uint16_t) * 8);
1364 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1365 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1366
1367 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1368 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1369
1370 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1371 gpu_metrics->average_cpu_power = metrics.Power[0];
1372 gpu_metrics->average_soc_power = metrics.Power[1];
1373 memcpy(&gpu_metrics->average_core_power[0],
1374 &metrics.CorePower[0],
1375 sizeof(uint16_t) * 8);
1376
1377 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1378 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1379 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1380 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1381
1382 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1383 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1384 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1385 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1386 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1387 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1388 memcpy(&gpu_metrics->current_coreclk[0],
1389 &metrics.CoreFrequency[0],
1390 sizeof(uint16_t) * 8);
1391 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1392 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1393
1394 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1395 gpu_metrics->indep_throttle_status =
1396 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1397 renoir_throttler_map);
1398
1399 gpu_metrics->fan_pwm = metrics.FanPwm;
1400
1401 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1402
1403 *table = (void *)gpu_metrics;
1404
1405 return sizeof(struct gpu_metrics_v2_2);
1406 }
1407
renoir_gfx_state_change_set(struct smu_context * smu,uint32_t state)1408 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1409 {
1410
1411 return 0;
1412 }
1413
1414 static const struct pptable_funcs renoir_ppt_funcs = {
1415 .set_power_state = NULL,
1416 .print_clk_levels = renoir_print_clk_levels,
1417 .get_current_power_state = renoir_get_current_power_state,
1418 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1419 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1420 .force_clk_levels = renoir_force_clk_levels,
1421 .set_power_profile_mode = renoir_set_power_profile_mode,
1422 .set_performance_level = renoir_set_performance_level,
1423 .get_dpm_clock_table = renoir_get_dpm_clock_table,
1424 .set_watermarks_table = renoir_set_watermarks_table,
1425 .get_power_profile_mode = renoir_get_power_profile_mode,
1426 .read_sensor = renoir_read_sensor,
1427 .check_fw_status = smu_v12_0_check_fw_status,
1428 .check_fw_version = smu_v12_0_check_fw_version,
1429 .powergate_sdma = smu_v12_0_powergate_sdma,
1430 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1431 .send_smc_msg = smu_cmn_send_smc_msg,
1432 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1433 .gfx_off_control = smu_v12_0_gfx_off_control,
1434 .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1435 .init_smc_tables = renoir_init_smc_tables,
1436 .fini_smc_tables = smu_v12_0_fini_smc_tables,
1437 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1438 .get_enabled_mask = smu_cmn_get_enabled_mask,
1439 .feature_is_enabled = smu_cmn_feature_is_enabled,
1440 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1441 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1442 .mode2_reset = smu_v12_0_mode2_reset,
1443 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1444 .set_driver_table_location = smu_v12_0_set_driver_table_location,
1445 .is_dpm_running = renoir_is_dpm_running,
1446 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1447 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1448 .get_gpu_metrics = renoir_get_gpu_metrics,
1449 .gfx_state_change_set = renoir_gfx_state_change_set,
1450 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
1451 .od_edit_dpm_table = renoir_od_edit_dpm_table,
1452 .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values,
1453 };
1454
renoir_set_ppt_funcs(struct smu_context * smu)1455 void renoir_set_ppt_funcs(struct smu_context *smu)
1456 {
1457 smu->ppt_funcs = &renoir_ppt_funcs;
1458 smu->message_map = renoir_message_map;
1459 smu->clock_map = renoir_clk_map;
1460 smu->table_map = renoir_table_map;
1461 smu->workload_map = renoir_workload_map;
1462 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1463 smu->is_apu = true;
1464 }
1465