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1 /*
2  * Copyright 2012 Red Hat Inc.
3  * Parts based on xf86-video-ast
4  * Copyright (c) 2005 ASPEED Technology Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * The above copyright notice and this permission notice (including the
23  * next paragraph) shall be included in all copies or substantial portions
24  * of the Software.
25  *
26  */
27 /*
28  * Authors: Dave Airlie <airlied@redhat.com>
29  */
30 
31 #include <linux/export.h>
32 #include <linux/pci.h>
33 
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_atomic_state_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fourcc.h>
40 #include <drm/drm_gem_atomic_helper.h>
41 #include <drm/drm_gem_framebuffer_helper.h>
42 #include <drm/drm_gem_vram_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_simple_kms_helper.h>
46 
47 #include "ast_drv.h"
48 #include "ast_tables.h"
49 
50 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
51 static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
52 
ast_load_palette_index(struct ast_private * ast,u8 index,u8 red,u8 green,u8 blue)53 static inline void ast_load_palette_index(struct ast_private *ast,
54 				     u8 index, u8 red, u8 green,
55 				     u8 blue)
56 {
57 	ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
58 	ast_io_read8(ast, AST_IO_SEQ_PORT);
59 	ast_io_write8(ast, AST_IO_DAC_DATA, red);
60 	ast_io_read8(ast, AST_IO_SEQ_PORT);
61 	ast_io_write8(ast, AST_IO_DAC_DATA, green);
62 	ast_io_read8(ast, AST_IO_SEQ_PORT);
63 	ast_io_write8(ast, AST_IO_DAC_DATA, blue);
64 	ast_io_read8(ast, AST_IO_SEQ_PORT);
65 }
66 
ast_crtc_load_lut(struct ast_private * ast,struct drm_crtc * crtc)67 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
68 {
69 	u16 *r, *g, *b;
70 	int i;
71 
72 	if (!crtc->enabled)
73 		return;
74 
75 	r = crtc->gamma_store;
76 	g = r + crtc->gamma_size;
77 	b = g + crtc->gamma_size;
78 
79 	for (i = 0; i < 256; i++)
80 		ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
81 }
82 
ast_get_vbios_mode_info(const struct drm_format_info * format,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,struct ast_vbios_mode_info * vbios_mode)83 static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
84 				    const struct drm_display_mode *mode,
85 				    struct drm_display_mode *adjusted_mode,
86 				    struct ast_vbios_mode_info *vbios_mode)
87 {
88 	u32 refresh_rate_index = 0, refresh_rate;
89 	const struct ast_vbios_enhtable *best = NULL;
90 	u32 hborder, vborder;
91 	bool check_sync;
92 
93 	switch (format->cpp[0] * 8) {
94 	case 8:
95 		vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
96 		break;
97 	case 16:
98 		vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
99 		break;
100 	case 24:
101 	case 32:
102 		vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
103 		break;
104 	default:
105 		return false;
106 	}
107 
108 	switch (mode->crtc_hdisplay) {
109 	case 640:
110 		vbios_mode->enh_table = &res_640x480[refresh_rate_index];
111 		break;
112 	case 800:
113 		vbios_mode->enh_table = &res_800x600[refresh_rate_index];
114 		break;
115 	case 1024:
116 		vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
117 		break;
118 	case 1280:
119 		if (mode->crtc_vdisplay == 800)
120 			vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
121 		else
122 			vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
123 		break;
124 	case 1360:
125 		vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
126 		break;
127 	case 1440:
128 		vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
129 		break;
130 	case 1600:
131 		if (mode->crtc_vdisplay == 900)
132 			vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
133 		else
134 			vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
135 		break;
136 	case 1680:
137 		vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
138 		break;
139 	case 1920:
140 		if (mode->crtc_vdisplay == 1080)
141 			vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
142 		else
143 			vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
144 		break;
145 	default:
146 		return false;
147 	}
148 
149 	refresh_rate = drm_mode_vrefresh(mode);
150 	check_sync = vbios_mode->enh_table->flags & WideScreenMode;
151 
152 	while (1) {
153 		const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
154 
155 		while (loop->refresh_rate != 0xff) {
156 			if ((check_sync) &&
157 			    (((mode->flags & DRM_MODE_FLAG_NVSYNC)  &&
158 			      (loop->flags & PVSync))  ||
159 			     ((mode->flags & DRM_MODE_FLAG_PVSYNC)  &&
160 			      (loop->flags & NVSync))  ||
161 			     ((mode->flags & DRM_MODE_FLAG_NHSYNC)  &&
162 			      (loop->flags & PHSync))  ||
163 			     ((mode->flags & DRM_MODE_FLAG_PHSYNC)  &&
164 			      (loop->flags & NHSync)))) {
165 				loop++;
166 				continue;
167 			}
168 			if (loop->refresh_rate <= refresh_rate
169 			    && (!best || loop->refresh_rate > best->refresh_rate))
170 				best = loop;
171 			loop++;
172 		}
173 		if (best || !check_sync)
174 			break;
175 		check_sync = 0;
176 	}
177 
178 	if (best)
179 		vbios_mode->enh_table = best;
180 
181 	hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
182 	vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
183 
184 	adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
185 	adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
186 	adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
187 	adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
188 		vbios_mode->enh_table->hfp;
189 	adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
190 					 vbios_mode->enh_table->hfp +
191 					 vbios_mode->enh_table->hsync);
192 
193 	adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
194 	adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
195 	adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
196 	adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
197 		vbios_mode->enh_table->vfp;
198 	adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
199 					 vbios_mode->enh_table->vfp +
200 					 vbios_mode->enh_table->vsync);
201 
202 	return true;
203 }
204 
ast_set_vbios_color_reg(struct ast_private * ast,const struct drm_format_info * format,const struct ast_vbios_mode_info * vbios_mode)205 static void ast_set_vbios_color_reg(struct ast_private *ast,
206 				    const struct drm_format_info *format,
207 				    const struct ast_vbios_mode_info *vbios_mode)
208 {
209 	u32 color_index;
210 
211 	switch (format->cpp[0]) {
212 	case 1:
213 		color_index = VGAModeIndex - 1;
214 		break;
215 	case 2:
216 		color_index = HiCModeIndex;
217 		break;
218 	case 3:
219 	case 4:
220 		color_index = TrueCModeIndex;
221 		break;
222 	default:
223 		return;
224 	}
225 
226 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
227 
228 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
229 
230 	if (vbios_mode->enh_table->flags & NewModeInfo) {
231 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
232 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
233 	}
234 }
235 
ast_set_vbios_mode_reg(struct ast_private * ast,const struct drm_display_mode * adjusted_mode,const struct ast_vbios_mode_info * vbios_mode)236 static void ast_set_vbios_mode_reg(struct ast_private *ast,
237 				   const struct drm_display_mode *adjusted_mode,
238 				   const struct ast_vbios_mode_info *vbios_mode)
239 {
240 	u32 refresh_rate_index, mode_id;
241 
242 	refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
243 	mode_id = vbios_mode->enh_table->mode_id;
244 
245 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
246 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
247 
248 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
249 
250 	if (vbios_mode->enh_table->flags & NewModeInfo) {
251 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
252 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
253 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
254 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
255 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
256 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
257 	}
258 }
259 
ast_set_std_reg(struct ast_private * ast,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)260 static void ast_set_std_reg(struct ast_private *ast,
261 			    struct drm_display_mode *mode,
262 			    struct ast_vbios_mode_info *vbios_mode)
263 {
264 	const struct ast_vbios_stdtable *stdtable;
265 	u32 i;
266 	u8 jreg;
267 
268 	stdtable = vbios_mode->std_table;
269 
270 	jreg = stdtable->misc;
271 	ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
272 
273 	/* Set SEQ; except Screen Disable field */
274 	ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
275 	ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
276 	for (i = 1; i < 4; i++) {
277 		jreg = stdtable->seq[i];
278 		ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1), jreg);
279 	}
280 
281 	/* Set CRTC; except base address and offset */
282 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
283 	for (i = 0; i < 12; i++)
284 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
285 	for (i = 14; i < 19; i++)
286 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
287 	for (i = 20; i < 25; i++)
288 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
289 
290 	/* set AR */
291 	jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
292 	for (i = 0; i < 20; i++) {
293 		jreg = stdtable->ar[i];
294 		ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
295 		ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
296 	}
297 	ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
298 	ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
299 
300 	jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
301 	ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
302 
303 	/* Set GR */
304 	for (i = 0; i < 9; i++)
305 		ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
306 }
307 
ast_set_crtc_reg(struct ast_private * ast,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)308 static void ast_set_crtc_reg(struct ast_private *ast,
309 			     struct drm_display_mode *mode,
310 			     struct ast_vbios_mode_info *vbios_mode)
311 {
312 	u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
313 	u16 temp, precache = 0;
314 
315 	if ((ast->chip == AST2500) &&
316 	    (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
317 		precache = 40;
318 
319 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
320 
321 	temp = (mode->crtc_htotal >> 3) - 5;
322 	if (temp & 0x100)
323 		jregAC |= 0x01; /* HT D[8] */
324 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
325 
326 	temp = (mode->crtc_hdisplay >> 3) - 1;
327 	if (temp & 0x100)
328 		jregAC |= 0x04; /* HDE D[8] */
329 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
330 
331 	temp = (mode->crtc_hblank_start >> 3) - 1;
332 	if (temp & 0x100)
333 		jregAC |= 0x10; /* HBS D[8] */
334 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
335 
336 	temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
337 	if (temp & 0x20)
338 		jreg05 |= 0x80;  /* HBE D[5] */
339 	if (temp & 0x40)
340 		jregAD |= 0x01;  /* HBE D[5] */
341 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
342 
343 	temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
344 	if (temp & 0x100)
345 		jregAC |= 0x40; /* HRS D[5] */
346 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
347 
348 	temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
349 	if (temp & 0x20)
350 		jregAD |= 0x04; /* HRE D[5] */
351 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
352 
353 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
354 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
355 
356 	/* vert timings */
357 	temp = (mode->crtc_vtotal) - 2;
358 	if (temp & 0x100)
359 		jreg07 |= 0x01;
360 	if (temp & 0x200)
361 		jreg07 |= 0x20;
362 	if (temp & 0x400)
363 		jregAE |= 0x01;
364 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
365 
366 	temp = (mode->crtc_vsync_start) - 1;
367 	if (temp & 0x100)
368 		jreg07 |= 0x04;
369 	if (temp & 0x200)
370 		jreg07 |= 0x80;
371 	if (temp & 0x400)
372 		jregAE |= 0x08;
373 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
374 
375 	temp = (mode->crtc_vsync_end - 1) & 0x3f;
376 	if (temp & 0x10)
377 		jregAE |= 0x20;
378 	if (temp & 0x20)
379 		jregAE |= 0x40;
380 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
381 
382 	temp = mode->crtc_vdisplay - 1;
383 	if (temp & 0x100)
384 		jreg07 |= 0x02;
385 	if (temp & 0x200)
386 		jreg07 |= 0x40;
387 	if (temp & 0x400)
388 		jregAE |= 0x02;
389 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
390 
391 	temp = mode->crtc_vblank_start - 1;
392 	if (temp & 0x100)
393 		jreg07 |= 0x08;
394 	if (temp & 0x200)
395 		jreg09 |= 0x20;
396 	if (temp & 0x400)
397 		jregAE |= 0x04;
398 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
399 
400 	temp = mode->crtc_vblank_end - 1;
401 	if (temp & 0x100)
402 		jregAE |= 0x10;
403 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
404 
405 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
406 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
407 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
408 
409 	if (precache)
410 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
411 	else
412 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
413 
414 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
415 }
416 
ast_set_offset_reg(struct ast_private * ast,struct drm_framebuffer * fb)417 static void ast_set_offset_reg(struct ast_private *ast,
418 			       struct drm_framebuffer *fb)
419 {
420 	u16 offset;
421 
422 	offset = fb->pitches[0] >> 3;
423 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
424 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
425 }
426 
ast_set_dclk_reg(struct ast_private * ast,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)427 static void ast_set_dclk_reg(struct ast_private *ast,
428 			     struct drm_display_mode *mode,
429 			     struct ast_vbios_mode_info *vbios_mode)
430 {
431 	const struct ast_vbios_dclk_info *clk_info;
432 
433 	if (ast->chip == AST2500)
434 		clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
435 	else
436 		clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
437 
438 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
439 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
440 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
441 			       (clk_info->param3 & 0xc0) |
442 			       ((clk_info->param3 & 0x3) << 4));
443 }
444 
ast_set_color_reg(struct ast_private * ast,const struct drm_format_info * format)445 static void ast_set_color_reg(struct ast_private *ast,
446 			      const struct drm_format_info *format)
447 {
448 	u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
449 
450 	switch (format->cpp[0] * 8) {
451 	case 8:
452 		jregA0 = 0x70;
453 		jregA3 = 0x01;
454 		jregA8 = 0x00;
455 		break;
456 	case 15:
457 	case 16:
458 		jregA0 = 0x70;
459 		jregA3 = 0x04;
460 		jregA8 = 0x02;
461 		break;
462 	case 32:
463 		jregA0 = 0x70;
464 		jregA3 = 0x08;
465 		jregA8 = 0x02;
466 		break;
467 	}
468 
469 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
470 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
471 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
472 }
473 
ast_set_crtthd_reg(struct ast_private * ast)474 static void ast_set_crtthd_reg(struct ast_private *ast)
475 {
476 	/* Set Threshold */
477 	if (ast->chip == AST2600) {
478 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0xe0);
479 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0xa0);
480 	} else if (ast->chip == AST2300 || ast->chip == AST2400 ||
481 	    ast->chip == AST2500) {
482 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
483 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
484 	} else if (ast->chip == AST2100 ||
485 		   ast->chip == AST1100 ||
486 		   ast->chip == AST2200 ||
487 		   ast->chip == AST2150) {
488 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
489 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
490 	} else {
491 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
492 		ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
493 	}
494 }
495 
ast_set_sync_reg(struct ast_private * ast,struct drm_display_mode * mode,struct ast_vbios_mode_info * vbios_mode)496 static void ast_set_sync_reg(struct ast_private *ast,
497 			     struct drm_display_mode *mode,
498 			     struct ast_vbios_mode_info *vbios_mode)
499 {
500 	u8 jreg;
501 
502 	jreg  = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
503 	jreg &= ~0xC0;
504 	if (vbios_mode->enh_table->flags & NVSync)
505 		jreg |= 0x80;
506 	if (vbios_mode->enh_table->flags & NHSync)
507 		jreg |= 0x40;
508 	ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
509 }
510 
ast_set_start_address_crt1(struct ast_private * ast,unsigned int offset)511 static void ast_set_start_address_crt1(struct ast_private *ast,
512 				       unsigned int offset)
513 {
514 	u32 addr;
515 
516 	addr = offset >> 2;
517 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
518 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
519 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
520 
521 }
522 
ast_wait_for_vretrace(struct ast_private * ast)523 static void ast_wait_for_vretrace(struct ast_private *ast)
524 {
525 	unsigned long timeout = jiffies + HZ;
526 	u8 vgair1;
527 
528 	do {
529 		vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
530 	} while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
531 }
532 
533 /*
534  * Primary plane
535  */
536 
537 static const uint32_t ast_primary_plane_formats[] = {
538 	DRM_FORMAT_XRGB8888,
539 	DRM_FORMAT_RGB565,
540 	DRM_FORMAT_C8,
541 };
542 
ast_primary_plane_helper_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)543 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
544 						 struct drm_atomic_state *state)
545 {
546 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
547 										 plane);
548 	struct drm_crtc_state *crtc_state;
549 	struct ast_crtc_state *ast_crtc_state;
550 	int ret;
551 
552 	if (!new_plane_state->crtc)
553 		return 0;
554 
555 	crtc_state = drm_atomic_get_new_crtc_state(state,
556 						   new_plane_state->crtc);
557 
558 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
559 						  DRM_PLANE_HELPER_NO_SCALING,
560 						  DRM_PLANE_HELPER_NO_SCALING,
561 						  false, true);
562 	if (ret)
563 		return ret;
564 
565 	if (!new_plane_state->visible)
566 		return 0;
567 
568 	ast_crtc_state = to_ast_crtc_state(crtc_state);
569 
570 	ast_crtc_state->format = new_plane_state->fb->format;
571 
572 	return 0;
573 }
574 
575 static void
ast_primary_plane_helper_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)576 ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
577 				       struct drm_atomic_state *state)
578 {
579 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
580 									   plane);
581 	struct drm_device *dev = plane->dev;
582 	struct ast_private *ast = to_ast_private(dev);
583 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
584 									   plane);
585 	struct drm_gem_vram_object *gbo;
586 	s64 gpu_addr;
587 	struct drm_framebuffer *fb = new_state->fb;
588 	struct drm_framebuffer *old_fb = old_state->fb;
589 
590 	if (!old_fb || (fb->format != old_fb->format)) {
591 		struct drm_crtc_state *crtc_state = new_state->crtc->state;
592 		struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
593 		struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
594 
595 		ast_set_color_reg(ast, fb->format);
596 		ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
597 	}
598 
599 	gbo = drm_gem_vram_of_gem(fb->obj[0]);
600 	gpu_addr = drm_gem_vram_offset(gbo);
601 	if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
602 		return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
603 
604 	ast_set_offset_reg(ast, fb);
605 	ast_set_start_address_crt1(ast, (u32)gpu_addr);
606 
607 	ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
608 }
609 
610 static void
ast_primary_plane_helper_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)611 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
612 					struct drm_atomic_state *state)
613 {
614 	struct ast_private *ast = to_ast_private(plane->dev);
615 
616 	ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
617 }
618 
619 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
620 	DRM_GEM_VRAM_PLANE_HELPER_FUNCS,
621 	.atomic_check = ast_primary_plane_helper_atomic_check,
622 	.atomic_update = ast_primary_plane_helper_atomic_update,
623 	.atomic_disable = ast_primary_plane_helper_atomic_disable,
624 };
625 
626 static const struct drm_plane_funcs ast_primary_plane_funcs = {
627 	.update_plane = drm_atomic_helper_update_plane,
628 	.disable_plane = drm_atomic_helper_disable_plane,
629 	.destroy = drm_plane_cleanup,
630 	.reset = drm_atomic_helper_plane_reset,
631 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
632 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
633 };
634 
ast_primary_plane_init(struct ast_private * ast)635 static int ast_primary_plane_init(struct ast_private *ast)
636 {
637 	struct drm_device *dev = &ast->base;
638 	struct drm_plane *primary_plane = &ast->primary_plane;
639 	int ret;
640 
641 	ret = drm_universal_plane_init(dev, primary_plane, 0x01,
642 				       &ast_primary_plane_funcs,
643 				       ast_primary_plane_formats,
644 				       ARRAY_SIZE(ast_primary_plane_formats),
645 				       NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
646 	if (ret) {
647 		drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
648 		return ret;
649 	}
650 	drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
651 
652 	return 0;
653 }
654 
655 /*
656  * Cursor plane
657  */
658 
ast_update_cursor_image(u8 __iomem * dst,const u8 * src,int width,int height)659 static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
660 {
661 	union {
662 		u32 ul;
663 		u8 b[4];
664 	} srcdata32[2], data32;
665 	union {
666 		u16 us;
667 		u8 b[2];
668 	} data16;
669 	u32 csum = 0;
670 	s32 alpha_dst_delta, last_alpha_dst_delta;
671 	u8 __iomem *dstxor;
672 	const u8 *srcxor;
673 	int i, j;
674 	u32 per_pixel_copy, two_pixel_copy;
675 
676 	alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
677 	last_alpha_dst_delta = alpha_dst_delta - (width << 1);
678 
679 	srcxor = src;
680 	dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
681 	per_pixel_copy = width & 1;
682 	two_pixel_copy = width >> 1;
683 
684 	for (j = 0; j < height; j++) {
685 		for (i = 0; i < two_pixel_copy; i++) {
686 			srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
687 			srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
688 			data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
689 			data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
690 			data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
691 			data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
692 
693 			writel(data32.ul, dstxor);
694 			csum += data32.ul;
695 
696 			dstxor += 4;
697 			srcxor += 8;
698 
699 		}
700 
701 		for (i = 0; i < per_pixel_copy; i++) {
702 			srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
703 			data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
704 			data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
705 			writew(data16.us, dstxor);
706 			csum += (u32)data16.us;
707 
708 			dstxor += 2;
709 			srcxor += 4;
710 		}
711 		dstxor += last_alpha_dst_delta;
712 	}
713 
714 	/* write checksum + signature */
715 	dst += AST_HWC_SIZE;
716 	writel(csum, dst);
717 	writel(width, dst + AST_HWC_SIGNATURE_SizeX);
718 	writel(height, dst + AST_HWC_SIGNATURE_SizeY);
719 	writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
720 	writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
721 }
722 
ast_set_cursor_base(struct ast_private * ast,u64 address)723 static void ast_set_cursor_base(struct ast_private *ast, u64 address)
724 {
725 	u8 addr0 = (address >> 3) & 0xff;
726 	u8 addr1 = (address >> 11) & 0xff;
727 	u8 addr2 = (address >> 19) & 0xff;
728 
729 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
730 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
731 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
732 }
733 
ast_set_cursor_location(struct ast_private * ast,u16 x,u16 y,u8 x_offset,u8 y_offset)734 static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y,
735 				    u8 x_offset, u8 y_offset)
736 {
737 	u8 x0 = (x & 0x00ff);
738 	u8 x1 = (x & 0x0f00) >> 8;
739 	u8 y0 = (y & 0x00ff);
740 	u8 y1 = (y & 0x0700) >> 8;
741 
742 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
743 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
744 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0);
745 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1);
746 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0);
747 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1);
748 }
749 
ast_set_cursor_enabled(struct ast_private * ast,bool enabled)750 static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled)
751 {
752 	static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
753 				     AST_IO_VGACRCB_HWC_ENABLED);
754 
755 	u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
756 
757 	if (enabled)
758 		vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
759 
760 	ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb);
761 }
762 
763 static const uint32_t ast_cursor_plane_formats[] = {
764 	DRM_FORMAT_ARGB8888,
765 };
766 
ast_cursor_plane_helper_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)767 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
768 						struct drm_atomic_state *state)
769 {
770 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
771 										 plane);
772 	struct drm_framebuffer *fb = new_plane_state->fb;
773 	struct drm_crtc_state *crtc_state;
774 	int ret;
775 
776 	if (!new_plane_state->crtc)
777 		return 0;
778 
779 	crtc_state = drm_atomic_get_new_crtc_state(state,
780 						   new_plane_state->crtc);
781 
782 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
783 						  DRM_PLANE_HELPER_NO_SCALING,
784 						  DRM_PLANE_HELPER_NO_SCALING,
785 						  true, true);
786 	if (ret)
787 		return ret;
788 
789 	if (!new_plane_state->visible)
790 		return 0;
791 
792 	if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
793 		return -EINVAL;
794 
795 	return 0;
796 }
797 
798 static void
ast_cursor_plane_helper_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)799 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
800 				      struct drm_atomic_state *state)
801 {
802 	struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
803 	struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
804 									   plane);
805 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
806 									   plane);
807 	struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);
808 	struct drm_framebuffer *fb = new_state->fb;
809 	struct ast_private *ast = to_ast_private(plane->dev);
810 	struct dma_buf_map dst_map =
811 		ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
812 	u64 dst_off =
813 		ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off;
814 	struct dma_buf_map src_map = shadow_plane_state->data[0];
815 	unsigned int offset_x, offset_y;
816 	u16 x, y;
817 	u8 x_offset, y_offset;
818 	u8 __iomem *dst;
819 	u8 __iomem *sig;
820 	const u8 *src;
821 
822 	src = src_map.vaddr; /* TODO: Use mapping abstraction properly */
823 	dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */
824 	sig = dst + AST_HWC_SIZE; /* TODO: Use mapping abstraction properly */
825 
826 	/*
827 	 * Do data transfer to HW cursor BO. If a new cursor image was installed,
828 	 * point the scanout engine to dst_gbo's offset and page-flip the HWC buffers.
829 	 */
830 
831 	ast_update_cursor_image(dst, src, fb->width, fb->height);
832 
833 	if (new_state->fb != old_state->fb) {
834 		ast_set_cursor_base(ast, dst_off);
835 
836 		++ast_cursor_plane->next_hwc_index;
837 		ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc);
838 	}
839 
840 	/*
841 	 * Update location in HWC signature and registers.
842 	 */
843 
844 	writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
845 	writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
846 
847 	offset_x = AST_MAX_HWC_WIDTH - fb->width;
848 	offset_y = AST_MAX_HWC_HEIGHT - fb->height;
849 
850 	if (new_state->crtc_x < 0) {
851 		x_offset = (-new_state->crtc_x) + offset_x;
852 		x = 0;
853 	} else {
854 		x_offset = offset_x;
855 		x = new_state->crtc_x;
856 	}
857 	if (new_state->crtc_y < 0) {
858 		y_offset = (-new_state->crtc_y) + offset_y;
859 		y = 0;
860 	} else {
861 		y_offset = offset_y;
862 		y = new_state->crtc_y;
863 	}
864 
865 	ast_set_cursor_location(ast, x, y, x_offset, y_offset);
866 
867 	/* Dummy write to enable HWC and make the HW pick-up the changes. */
868 	ast_set_cursor_enabled(ast, true);
869 }
870 
871 static void
ast_cursor_plane_helper_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)872 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
873 				       struct drm_atomic_state *state)
874 {
875 	struct ast_private *ast = to_ast_private(plane->dev);
876 
877 	ast_set_cursor_enabled(ast, false);
878 }
879 
880 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
881 	DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
882 	.atomic_check = ast_cursor_plane_helper_atomic_check,
883 	.atomic_update = ast_cursor_plane_helper_atomic_update,
884 	.atomic_disable = ast_cursor_plane_helper_atomic_disable,
885 };
886 
ast_cursor_plane_destroy(struct drm_plane * plane)887 static void ast_cursor_plane_destroy(struct drm_plane *plane)
888 {
889 	struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
890 	size_t i;
891 	struct drm_gem_vram_object *gbo;
892 	struct dma_buf_map map;
893 
894 	for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
895 		gbo = ast_cursor_plane->hwc[i].gbo;
896 		map = ast_cursor_plane->hwc[i].map;
897 		drm_gem_vram_vunmap(gbo, &map);
898 		drm_gem_vram_unpin(gbo);
899 		drm_gem_vram_put(gbo);
900 	}
901 
902 	drm_plane_cleanup(plane);
903 }
904 
905 static const struct drm_plane_funcs ast_cursor_plane_funcs = {
906 	.update_plane = drm_atomic_helper_update_plane,
907 	.disable_plane = drm_atomic_helper_disable_plane,
908 	.destroy = ast_cursor_plane_destroy,
909 	DRM_GEM_SHADOW_PLANE_FUNCS,
910 };
911 
ast_cursor_plane_init(struct ast_private * ast)912 static int ast_cursor_plane_init(struct ast_private *ast)
913 {
914 	struct drm_device *dev = &ast->base;
915 	struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane;
916 	struct drm_plane *cursor_plane = &ast_cursor_plane->base;
917 	size_t size, i;
918 	struct drm_gem_vram_object *gbo;
919 	struct dma_buf_map map;
920 	int ret;
921 	s64 off;
922 
923 	/*
924 	 * Allocate backing storage for cursors. The BOs are permanently
925 	 * pinned to the top end of the VRAM.
926 	 */
927 
928 	size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
929 
930 	for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
931 		gbo = drm_gem_vram_create(dev, size, 0);
932 		if (IS_ERR(gbo)) {
933 			ret = PTR_ERR(gbo);
934 			goto err_hwc;
935 		}
936 		ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
937 					    DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
938 		if (ret)
939 			goto err_drm_gem_vram_put;
940 		ret = drm_gem_vram_vmap(gbo, &map);
941 		if (ret)
942 			goto err_drm_gem_vram_unpin;
943 		off = drm_gem_vram_offset(gbo);
944 		if (off < 0) {
945 			ret = off;
946 			goto err_drm_gem_vram_vunmap;
947 		}
948 		ast_cursor_plane->hwc[i].gbo = gbo;
949 		ast_cursor_plane->hwc[i].map = map;
950 		ast_cursor_plane->hwc[i].off = off;
951 	}
952 
953 	/*
954 	 * Create the cursor plane. The plane's destroy callback will release
955 	 * the backing storages' BO memory.
956 	 */
957 
958 	ret = drm_universal_plane_init(dev, cursor_plane, 0x01,
959 				       &ast_cursor_plane_funcs,
960 				       ast_cursor_plane_formats,
961 				       ARRAY_SIZE(ast_cursor_plane_formats),
962 				       NULL, DRM_PLANE_TYPE_CURSOR, NULL);
963 	if (ret) {
964 		drm_err(dev, "drm_universal_plane failed(): %d\n", ret);
965 		goto err_hwc;
966 	}
967 	drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
968 
969 	return 0;
970 
971 err_hwc:
972 	while (i) {
973 		--i;
974 		gbo = ast_cursor_plane->hwc[i].gbo;
975 		map = ast_cursor_plane->hwc[i].map;
976 err_drm_gem_vram_vunmap:
977 		drm_gem_vram_vunmap(gbo, &map);
978 err_drm_gem_vram_unpin:
979 		drm_gem_vram_unpin(gbo);
980 err_drm_gem_vram_put:
981 		drm_gem_vram_put(gbo);
982 	}
983 	return ret;
984 }
985 
986 /*
987  * CRTC
988  */
989 
ast_crtc_dpms(struct drm_crtc * crtc,int mode)990 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
991 {
992 	struct ast_private *ast = to_ast_private(crtc->dev);
993 
994 	/* TODO: Maybe control display signal generation with
995 	 *       Sync Enable (bit CR17.7).
996 	 */
997 	switch (mode) {
998 	case DRM_MODE_DPMS_ON:
999 	case DRM_MODE_DPMS_STANDBY:
1000 	case DRM_MODE_DPMS_SUSPEND:
1001 		if (ast->tx_chip_type == AST_TX_DP501)
1002 			ast_set_dp501_video_output(crtc->dev, 1);
1003 		break;
1004 	case DRM_MODE_DPMS_OFF:
1005 		if (ast->tx_chip_type == AST_TX_DP501)
1006 			ast_set_dp501_video_output(crtc->dev, 0);
1007 		break;
1008 	}
1009 }
1010 
ast_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1011 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1012 					struct drm_atomic_state *state)
1013 {
1014 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1015 									  crtc);
1016 	struct drm_device *dev = crtc->dev;
1017 	struct ast_crtc_state *ast_state;
1018 	const struct drm_format_info *format;
1019 	bool succ;
1020 
1021 	if (!crtc_state->enable)
1022 		return 0; /* no mode checks if CRTC is being disabled */
1023 
1024 	ast_state = to_ast_crtc_state(crtc_state);
1025 
1026 	format = ast_state->format;
1027 	if (drm_WARN_ON_ONCE(dev, !format))
1028 		return -EINVAL; /* BUG: We didn't set format in primary check(). */
1029 
1030 	succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1031 				       &crtc_state->adjusted_mode,
1032 				       &ast_state->vbios_mode_info);
1033 	if (!succ)
1034 		return -EINVAL;
1035 
1036 	return 0;
1037 }
1038 
1039 static void
ast_crtc_helper_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)1040 ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1041 			     struct drm_atomic_state *state)
1042 {
1043 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1044 									  crtc);
1045 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1046 									      crtc);
1047 	struct ast_private *ast = to_ast_private(crtc->dev);
1048 	struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1049 	struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1050 
1051 	/*
1052 	 * The gamma LUT has to be reloaded after changing the primary
1053 	 * plane's color format.
1054 	 */
1055 	if (old_ast_crtc_state->format != ast_crtc_state->format)
1056 		ast_crtc_load_lut(ast, crtc);
1057 }
1058 
1059 static void
ast_crtc_helper_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1060 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
1061 			      struct drm_atomic_state *state)
1062 {
1063 	struct drm_device *dev = crtc->dev;
1064 	struct ast_private *ast = to_ast_private(dev);
1065 	struct drm_crtc_state *crtc_state = crtc->state;
1066 	struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1067 	struct ast_vbios_mode_info *vbios_mode_info =
1068 		&ast_crtc_state->vbios_mode_info;
1069 	struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1070 
1071 	ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1072 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
1073 	ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1074 	ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1075 	ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1076 	ast_set_crtthd_reg(ast);
1077 	ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1078 
1079 	ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1080 }
1081 
1082 static void
ast_crtc_helper_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)1083 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
1084 			       struct drm_atomic_state *state)
1085 {
1086 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1087 									      crtc);
1088 	struct drm_device *dev = crtc->dev;
1089 	struct ast_private *ast = to_ast_private(dev);
1090 
1091 	ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1092 
1093 	/*
1094 	 * HW cursors require the underlying primary plane and CRTC to
1095 	 * display a valid mode and image. This is not the case during
1096 	 * full modeset operations. So we temporarily disable any active
1097 	 * plane, including the HW cursor. Each plane's atomic_update()
1098 	 * helper will re-enable it if necessary.
1099 	 *
1100 	 * We only do this during *full* modesets. It does not affect
1101 	 * simple pageflips on the planes.
1102 	 */
1103 	drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1104 
1105 	/*
1106 	 * Ensure that no scanout takes place before reprogramming mode
1107 	 * and format registers.
1108 	 */
1109 	ast_wait_for_vretrace(ast);
1110 }
1111 
1112 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1113 	.atomic_check = ast_crtc_helper_atomic_check,
1114 	.atomic_flush = ast_crtc_helper_atomic_flush,
1115 	.atomic_enable = ast_crtc_helper_atomic_enable,
1116 	.atomic_disable = ast_crtc_helper_atomic_disable,
1117 };
1118 
ast_crtc_reset(struct drm_crtc * crtc)1119 static void ast_crtc_reset(struct drm_crtc *crtc)
1120 {
1121 	struct ast_crtc_state *ast_state =
1122 		kzalloc(sizeof(*ast_state), GFP_KERNEL);
1123 
1124 	if (crtc->state)
1125 		crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1126 
1127 	if (ast_state)
1128 		__drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1129 	else
1130 		__drm_atomic_helper_crtc_reset(crtc, NULL);
1131 }
1132 
1133 static struct drm_crtc_state *
ast_crtc_atomic_duplicate_state(struct drm_crtc * crtc)1134 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1135 {
1136 	struct ast_crtc_state *new_ast_state, *ast_state;
1137 	struct drm_device *dev = crtc->dev;
1138 
1139 	if (drm_WARN_ON(dev, !crtc->state))
1140 		return NULL;
1141 
1142 	new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1143 	if (!new_ast_state)
1144 		return NULL;
1145 	__drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1146 
1147 	ast_state = to_ast_crtc_state(crtc->state);
1148 
1149 	new_ast_state->format = ast_state->format;
1150 	memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1151 	       sizeof(new_ast_state->vbios_mode_info));
1152 
1153 	return &new_ast_state->base;
1154 }
1155 
ast_crtc_atomic_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)1156 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1157 					  struct drm_crtc_state *state)
1158 {
1159 	struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1160 
1161 	__drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1162 	kfree(ast_state);
1163 }
1164 
1165 static const struct drm_crtc_funcs ast_crtc_funcs = {
1166 	.reset = ast_crtc_reset,
1167 	.destroy = drm_crtc_cleanup,
1168 	.set_config = drm_atomic_helper_set_config,
1169 	.page_flip = drm_atomic_helper_page_flip,
1170 	.atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1171 	.atomic_destroy_state = ast_crtc_atomic_destroy_state,
1172 };
1173 
ast_crtc_init(struct drm_device * dev)1174 static int ast_crtc_init(struct drm_device *dev)
1175 {
1176 	struct ast_private *ast = to_ast_private(dev);
1177 	struct drm_crtc *crtc = &ast->crtc;
1178 	int ret;
1179 
1180 	ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane,
1181 					&ast->cursor_plane.base, &ast_crtc_funcs,
1182 					NULL);
1183 	if (ret)
1184 		return ret;
1185 
1186 	drm_mode_crtc_set_gamma_size(crtc, 256);
1187 	drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1188 
1189 	return 0;
1190 }
1191 
1192 /*
1193  * Encoder
1194  */
1195 
ast_encoder_init(struct drm_device * dev)1196 static int ast_encoder_init(struct drm_device *dev)
1197 {
1198 	struct ast_private *ast = to_ast_private(dev);
1199 	struct drm_encoder *encoder = &ast->encoder;
1200 	int ret;
1201 
1202 	ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1203 	if (ret)
1204 		return ret;
1205 
1206 	encoder->possible_crtcs = 1;
1207 
1208 	return 0;
1209 }
1210 
1211 /*
1212  * Connector
1213  */
1214 
ast_get_modes(struct drm_connector * connector)1215 static int ast_get_modes(struct drm_connector *connector)
1216 {
1217 	struct ast_connector *ast_connector = to_ast_connector(connector);
1218 	struct ast_private *ast = to_ast_private(connector->dev);
1219 	struct edid *edid;
1220 	int ret;
1221 	bool flags = false;
1222 
1223 	if (ast->tx_chip_type == AST_TX_DP501) {
1224 		ast->dp501_maxclk = 0xff;
1225 		edid = kmalloc(128, GFP_KERNEL);
1226 		if (!edid)
1227 			return -ENOMEM;
1228 
1229 		flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1230 		if (flags)
1231 			ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1232 		else
1233 			kfree(edid);
1234 	}
1235 	if (!flags)
1236 		edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1237 	if (edid) {
1238 		drm_connector_update_edid_property(&ast_connector->base, edid);
1239 		ret = drm_add_edid_modes(connector, edid);
1240 		kfree(edid);
1241 		return ret;
1242 	}
1243 	drm_connector_update_edid_property(&ast_connector->base, NULL);
1244 	return 0;
1245 }
1246 
ast_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1247 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1248 			  struct drm_display_mode *mode)
1249 {
1250 	struct ast_private *ast = to_ast_private(connector->dev);
1251 	int flags = MODE_NOMODE;
1252 	uint32_t jtemp;
1253 
1254 	if (ast->support_wide_screen) {
1255 		if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1256 			return MODE_OK;
1257 		if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1258 			return MODE_OK;
1259 		if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1260 			return MODE_OK;
1261 		if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1262 			return MODE_OK;
1263 		if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1264 			return MODE_OK;
1265 
1266 		if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1267 		    (ast->chip == AST2300) || (ast->chip == AST2400) ||
1268 		    (ast->chip == AST2500)) {
1269 			if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1270 				return MODE_OK;
1271 
1272 			if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1273 				jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1274 				if (jtemp & 0x01)
1275 					return MODE_NOMODE;
1276 				else
1277 					return MODE_OK;
1278 			}
1279 		}
1280 	}
1281 	switch (mode->hdisplay) {
1282 	case 640:
1283 		if (mode->vdisplay == 480)
1284 			flags = MODE_OK;
1285 		break;
1286 	case 800:
1287 		if (mode->vdisplay == 600)
1288 			flags = MODE_OK;
1289 		break;
1290 	case 1024:
1291 		if (mode->vdisplay == 768)
1292 			flags = MODE_OK;
1293 		break;
1294 	case 1280:
1295 		if (mode->vdisplay == 1024)
1296 			flags = MODE_OK;
1297 		break;
1298 	case 1600:
1299 		if (mode->vdisplay == 1200)
1300 			flags = MODE_OK;
1301 		break;
1302 	default:
1303 		return flags;
1304 	}
1305 
1306 	return flags;
1307 }
1308 
ast_connector_destroy(struct drm_connector * connector)1309 static void ast_connector_destroy(struct drm_connector *connector)
1310 {
1311 	struct ast_connector *ast_connector = to_ast_connector(connector);
1312 
1313 	ast_i2c_destroy(ast_connector->i2c);
1314 	drm_connector_cleanup(connector);
1315 }
1316 
1317 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1318 	.get_modes = ast_get_modes,
1319 	.mode_valid = ast_mode_valid,
1320 };
1321 
1322 static const struct drm_connector_funcs ast_connector_funcs = {
1323 	.reset = drm_atomic_helper_connector_reset,
1324 	.fill_modes = drm_helper_probe_single_connector_modes,
1325 	.destroy = ast_connector_destroy,
1326 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1327 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1328 };
1329 
ast_connector_init(struct drm_device * dev)1330 static int ast_connector_init(struct drm_device *dev)
1331 {
1332 	struct ast_private *ast = to_ast_private(dev);
1333 	struct ast_connector *ast_connector = &ast->connector;
1334 	struct drm_connector *connector = &ast_connector->base;
1335 	struct drm_encoder *encoder = &ast->encoder;
1336 
1337 	ast_connector->i2c = ast_i2c_create(dev);
1338 	if (!ast_connector->i2c)
1339 		drm_err(dev, "failed to add ddc bus for connector\n");
1340 
1341 	drm_connector_init_with_ddc(dev, connector,
1342 				    &ast_connector_funcs,
1343 				    DRM_MODE_CONNECTOR_VGA,
1344 				    &ast_connector->i2c->adapter);
1345 
1346 	drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1347 
1348 	connector->interlace_allowed = 0;
1349 	connector->doublescan_allowed = 0;
1350 
1351 	connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1352 
1353 	drm_connector_attach_encoder(connector, encoder);
1354 
1355 	return 0;
1356 }
1357 
1358 /*
1359  * Mode config
1360  */
1361 
1362 static const struct drm_mode_config_helper_funcs
1363 ast_mode_config_helper_funcs = {
1364 	.atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
1365 };
1366 
1367 static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1368 	.fb_create = drm_gem_fb_create,
1369 	.mode_valid = drm_vram_helper_mode_valid,
1370 	.atomic_check = drm_atomic_helper_check,
1371 	.atomic_commit = drm_atomic_helper_commit,
1372 };
1373 
ast_mode_config_init(struct ast_private * ast)1374 int ast_mode_config_init(struct ast_private *ast)
1375 {
1376 	struct drm_device *dev = &ast->base;
1377 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1378 	int ret;
1379 
1380 	ret = drmm_mode_config_init(dev);
1381 	if (ret)
1382 		return ret;
1383 
1384 	dev->mode_config.funcs = &ast_mode_config_funcs;
1385 	dev->mode_config.min_width = 0;
1386 	dev->mode_config.min_height = 0;
1387 	dev->mode_config.preferred_depth = 24;
1388 	dev->mode_config.prefer_shadow = 1;
1389 	dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1390 
1391 	if (ast->chip == AST2100 ||
1392 	    ast->chip == AST2200 ||
1393 	    ast->chip == AST2300 ||
1394 	    ast->chip == AST2400 ||
1395 	    ast->chip == AST2500) {
1396 		dev->mode_config.max_width = 1920;
1397 		dev->mode_config.max_height = 2048;
1398 	} else {
1399 		dev->mode_config.max_width = 1600;
1400 		dev->mode_config.max_height = 1200;
1401 	}
1402 
1403 	dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1404 
1405 
1406 	ret = ast_primary_plane_init(ast);
1407 	if (ret)
1408 		return ret;
1409 
1410 	ret = ast_cursor_plane_init(ast);
1411 	if (ret)
1412 		return ret;
1413 
1414 	ast_crtc_init(dev);
1415 	ast_encoder_init(dev);
1416 	ast_connector_init(dev);
1417 
1418 	drm_mode_config_reset(dev);
1419 
1420 	return 0;
1421 }
1422 
get_clock(void * i2c_priv)1423 static int get_clock(void *i2c_priv)
1424 {
1425 	struct ast_i2c_chan *i2c = i2c_priv;
1426 	struct ast_private *ast = to_ast_private(i2c->dev);
1427 	uint32_t val, val2, count, pass;
1428 
1429 	count = 0;
1430 	pass = 0;
1431 	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1432 	do {
1433 		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1434 		if (val == val2) {
1435 			pass++;
1436 		} else {
1437 			pass = 0;
1438 			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1439 		}
1440 	} while ((pass < 5) && (count++ < 0x10000));
1441 
1442 	return val & 1 ? 1 : 0;
1443 }
1444 
get_data(void * i2c_priv)1445 static int get_data(void *i2c_priv)
1446 {
1447 	struct ast_i2c_chan *i2c = i2c_priv;
1448 	struct ast_private *ast = to_ast_private(i2c->dev);
1449 	uint32_t val, val2, count, pass;
1450 
1451 	count = 0;
1452 	pass = 0;
1453 	val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1454 	do {
1455 		val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1456 		if (val == val2) {
1457 			pass++;
1458 		} else {
1459 			pass = 0;
1460 			val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1461 		}
1462 	} while ((pass < 5) && (count++ < 0x10000));
1463 
1464 	return val & 1 ? 1 : 0;
1465 }
1466 
set_clock(void * i2c_priv,int clock)1467 static void set_clock(void *i2c_priv, int clock)
1468 {
1469 	struct ast_i2c_chan *i2c = i2c_priv;
1470 	struct ast_private *ast = to_ast_private(i2c->dev);
1471 	int i;
1472 	u8 ujcrb7, jtemp;
1473 
1474 	for (i = 0; i < 0x10000; i++) {
1475 		ujcrb7 = ((clock & 0x01) ? 0 : 1);
1476 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1477 		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1478 		if (ujcrb7 == jtemp)
1479 			break;
1480 	}
1481 }
1482 
set_data(void * i2c_priv,int data)1483 static void set_data(void *i2c_priv, int data)
1484 {
1485 	struct ast_i2c_chan *i2c = i2c_priv;
1486 	struct ast_private *ast = to_ast_private(i2c->dev);
1487 	int i;
1488 	u8 ujcrb7, jtemp;
1489 
1490 	for (i = 0; i < 0x10000; i++) {
1491 		ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1492 		ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1493 		jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1494 		if (ujcrb7 == jtemp)
1495 			break;
1496 	}
1497 }
1498 
ast_i2c_create(struct drm_device * dev)1499 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1500 {
1501 	struct ast_i2c_chan *i2c;
1502 	int ret;
1503 
1504 	i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1505 	if (!i2c)
1506 		return NULL;
1507 
1508 	i2c->adapter.owner = THIS_MODULE;
1509 	i2c->adapter.class = I2C_CLASS_DDC;
1510 	i2c->adapter.dev.parent = dev->dev;
1511 	i2c->dev = dev;
1512 	i2c_set_adapdata(&i2c->adapter, i2c);
1513 	snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1514 		 "AST i2c bit bus");
1515 	i2c->adapter.algo_data = &i2c->bit;
1516 
1517 	i2c->bit.udelay = 20;
1518 	i2c->bit.timeout = 2;
1519 	i2c->bit.data = i2c;
1520 	i2c->bit.setsda = set_data;
1521 	i2c->bit.setscl = set_clock;
1522 	i2c->bit.getsda = get_data;
1523 	i2c->bit.getscl = get_clock;
1524 	ret = i2c_bit_add_bus(&i2c->adapter);
1525 	if (ret) {
1526 		drm_err(dev, "Failed to register bit i2c\n");
1527 		goto out_free;
1528 	}
1529 
1530 	return i2c;
1531 out_free:
1532 	kfree(i2c);
1533 	return NULL;
1534 }
1535 
ast_i2c_destroy(struct ast_i2c_chan * i2c)1536 static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1537 {
1538 	if (!i2c)
1539 		return;
1540 	i2c_del_adapter(&i2c->adapter);
1541 	kfree(i2c);
1542 }
1543