1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6 #include <drm/drm_fourcc.h>
7
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/of_irq.h>
13 #include <linux/platform_device.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
15
16 #include "mtk_disp_drv.h"
17 #include "mtk_drm_crtc.h"
18 #include "mtk_drm_ddp_comp.h"
19
20 #define DISP_REG_OVL_INTEN 0x0004
21 #define OVL_FME_CPL_INT BIT(1)
22 #define DISP_REG_OVL_INTSTA 0x0008
23 #define DISP_REG_OVL_EN 0x000c
24 #define DISP_REG_OVL_RST 0x0014
25 #define DISP_REG_OVL_ROI_SIZE 0x0020
26 #define DISP_REG_OVL_DATAPATH_CON 0x0024
27 #define OVL_LAYER_SMI_ID_EN BIT(0)
28 #define OVL_BGCLR_SEL_IN BIT(2)
29 #define DISP_REG_OVL_ROI_BGCLR 0x0028
30 #define DISP_REG_OVL_SRC_CON 0x002c
31 #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
32 #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
33 #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
34 #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
35 #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
36 #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
37 #define DISP_REG_OVL_ADDR_MT2701 0x0040
38 #define DISP_REG_OVL_ADDR_MT8173 0x0f40
39 #define DISP_REG_OVL_ADDR(ovl, n) ((ovl)->data->addr + 0x20 * (n))
40
41 #define GMC_THRESHOLD_BITS 16
42 #define GMC_THRESHOLD_HIGH ((1 << GMC_THRESHOLD_BITS) / 4)
43 #define GMC_THRESHOLD_LOW ((1 << GMC_THRESHOLD_BITS) / 8)
44
45 #define OVL_CON_BYTE_SWAP BIT(24)
46 #define OVL_CON_MTX_YUV_TO_RGB (6 << 16)
47 #define OVL_CON_CLRFMT_RGB (1 << 12)
48 #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
49 #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
50 #define OVL_CON_CLRFMT_UYVY (4 << 12)
51 #define OVL_CON_CLRFMT_YUYV (5 << 12)
52 #define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
53 0 : OVL_CON_CLRFMT_RGB)
54 #define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \
55 OVL_CON_CLRFMT_RGB : 0)
56 #define OVL_CON_AEN BIT(8)
57 #define OVL_CON_ALPHA 0xff
58 #define OVL_CON_VIRT_FLIP BIT(9)
59 #define OVL_CON_HORZ_FLIP BIT(10)
60
61 struct mtk_disp_ovl_data {
62 unsigned int addr;
63 unsigned int gmc_bits;
64 unsigned int layer_nr;
65 bool fmt_rgb565_is_0;
66 bool smi_id_en;
67 };
68
69 /*
70 * struct mtk_disp_ovl - DISP_OVL driver structure
71 * @crtc: associated crtc to report vblank events to
72 * @data: platform data
73 */
74 struct mtk_disp_ovl {
75 struct drm_crtc *crtc;
76 struct clk *clk;
77 void __iomem *regs;
78 struct cmdq_client_reg cmdq_reg;
79 const struct mtk_disp_ovl_data *data;
80 void (*vblank_cb)(void *data);
81 void *vblank_cb_data;
82 };
83
mtk_disp_ovl_irq_handler(int irq,void * dev_id)84 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
85 {
86 struct mtk_disp_ovl *priv = dev_id;
87
88 /* Clear frame completion interrupt */
89 writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
90
91 if (!priv->vblank_cb)
92 return IRQ_NONE;
93
94 priv->vblank_cb(priv->vblank_cb_data);
95
96 return IRQ_HANDLED;
97 }
98
mtk_ovl_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)99 void mtk_ovl_register_vblank_cb(struct device *dev,
100 void (*vblank_cb)(void *),
101 void *vblank_cb_data)
102 {
103 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
104
105 ovl->vblank_cb = vblank_cb;
106 ovl->vblank_cb_data = vblank_cb_data;
107 }
108
mtk_ovl_unregister_vblank_cb(struct device * dev)109 void mtk_ovl_unregister_vblank_cb(struct device *dev)
110 {
111 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
112
113 ovl->vblank_cb = NULL;
114 ovl->vblank_cb_data = NULL;
115 }
116
mtk_ovl_enable_vblank(struct device * dev)117 void mtk_ovl_enable_vblank(struct device *dev)
118 {
119 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
120
121 writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
122 writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
123 }
124
mtk_ovl_disable_vblank(struct device * dev)125 void mtk_ovl_disable_vblank(struct device *dev)
126 {
127 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
128
129 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
130 }
131
mtk_ovl_clk_enable(struct device * dev)132 int mtk_ovl_clk_enable(struct device *dev)
133 {
134 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
135
136 return clk_prepare_enable(ovl->clk);
137 }
138
mtk_ovl_clk_disable(struct device * dev)139 void mtk_ovl_clk_disable(struct device *dev)
140 {
141 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
142
143 clk_disable_unprepare(ovl->clk);
144 }
145
mtk_ovl_start(struct device * dev)146 void mtk_ovl_start(struct device *dev)
147 {
148 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
149
150 if (ovl->data->smi_id_en) {
151 unsigned int reg;
152
153 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
154 reg = reg | OVL_LAYER_SMI_ID_EN;
155 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
156 }
157 writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
158 }
159
mtk_ovl_stop(struct device * dev)160 void mtk_ovl_stop(struct device *dev)
161 {
162 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
163
164 writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
165 if (ovl->data->smi_id_en) {
166 unsigned int reg;
167
168 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
169 reg = reg & ~OVL_LAYER_SMI_ID_EN;
170 writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
171 }
172
173 }
174
mtk_ovl_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)175 void mtk_ovl_config(struct device *dev, unsigned int w,
176 unsigned int h, unsigned int vrefresh,
177 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
178 {
179 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
180
181 if (w != 0 && h != 0)
182 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
183 DISP_REG_OVL_ROI_SIZE);
184 mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
185
186 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
187 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
188 }
189
mtk_ovl_layer_nr(struct device * dev)190 unsigned int mtk_ovl_layer_nr(struct device *dev)
191 {
192 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
193
194 return ovl->data->layer_nr;
195 }
196
mtk_ovl_supported_rotations(struct device * dev)197 unsigned int mtk_ovl_supported_rotations(struct device *dev)
198 {
199 return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
200 DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
201 }
202
mtk_ovl_layer_check(struct device * dev,unsigned int idx,struct mtk_plane_state * mtk_state)203 int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
204 struct mtk_plane_state *mtk_state)
205 {
206 struct drm_plane_state *state = &mtk_state->base;
207 unsigned int rotation = 0;
208
209 rotation = drm_rotation_simplify(state->rotation,
210 DRM_MODE_ROTATE_0 |
211 DRM_MODE_REFLECT_X |
212 DRM_MODE_REFLECT_Y);
213 rotation &= ~DRM_MODE_ROTATE_0;
214
215 /* We can only do reflection, not rotation */
216 if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
217 return -EINVAL;
218
219 /*
220 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
221 * Only RGB[AX] variants are supported.
222 */
223 if (state->fb->format->is_yuv && rotation != 0)
224 return -EINVAL;
225
226 state->rotation = rotation;
227
228 return 0;
229 }
230
mtk_ovl_layer_on(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)231 void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
232 struct cmdq_pkt *cmdq_pkt)
233 {
234 unsigned int gmc_thrshd_l;
235 unsigned int gmc_thrshd_h;
236 unsigned int gmc_value;
237 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
238
239 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
240 DISP_REG_OVL_RDMA_CTRL(idx));
241 gmc_thrshd_l = GMC_THRESHOLD_LOW >>
242 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
243 gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
244 (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
245 if (ovl->data->gmc_bits == 10)
246 gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
247 else
248 gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
249 gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
250 mtk_ddp_write(cmdq_pkt, gmc_value,
251 &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
252 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
253 DISP_REG_OVL_SRC_CON, BIT(idx));
254 }
255
mtk_ovl_layer_off(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)256 void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
257 struct cmdq_pkt *cmdq_pkt)
258 {
259 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
260
261 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
262 DISP_REG_OVL_SRC_CON, BIT(idx));
263 mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
264 DISP_REG_OVL_RDMA_CTRL(idx));
265 }
266
ovl_fmt_convert(struct mtk_disp_ovl * ovl,unsigned int fmt)267 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
268 {
269 /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
270 * is defined in mediatek HW data sheet.
271 * The alphabet order in XXX is no relation to data
272 * arrangement in memory.
273 */
274 switch (fmt) {
275 default:
276 case DRM_FORMAT_RGB565:
277 return OVL_CON_CLRFMT_RGB565(ovl);
278 case DRM_FORMAT_BGR565:
279 return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
280 case DRM_FORMAT_RGB888:
281 return OVL_CON_CLRFMT_RGB888(ovl);
282 case DRM_FORMAT_BGR888:
283 return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
284 case DRM_FORMAT_RGBX8888:
285 case DRM_FORMAT_RGBA8888:
286 return OVL_CON_CLRFMT_ARGB8888;
287 case DRM_FORMAT_BGRX8888:
288 case DRM_FORMAT_BGRA8888:
289 return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
290 case DRM_FORMAT_XRGB8888:
291 case DRM_FORMAT_ARGB8888:
292 return OVL_CON_CLRFMT_RGBA8888;
293 case DRM_FORMAT_XBGR8888:
294 case DRM_FORMAT_ABGR8888:
295 return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
296 case DRM_FORMAT_UYVY:
297 return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
298 case DRM_FORMAT_YUYV:
299 return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
300 }
301 }
302
mtk_ovl_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)303 void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
304 struct mtk_plane_state *state,
305 struct cmdq_pkt *cmdq_pkt)
306 {
307 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
308 struct mtk_plane_pending_state *pending = &state->pending;
309 unsigned int addr = pending->addr;
310 unsigned int pitch = pending->pitch & 0xffff;
311 unsigned int fmt = pending->format;
312 unsigned int offset = (pending->y << 16) | pending->x;
313 unsigned int src_size = (pending->height << 16) | pending->width;
314 unsigned int con;
315
316 if (!pending->enable) {
317 mtk_ovl_layer_off(dev, idx, cmdq_pkt);
318 return;
319 }
320
321 con = ovl_fmt_convert(ovl, fmt);
322 if (state->base.fb && state->base.fb->format->has_alpha)
323 con |= OVL_CON_AEN | OVL_CON_ALPHA;
324
325 if (pending->rotation & DRM_MODE_REFLECT_Y) {
326 con |= OVL_CON_VIRT_FLIP;
327 addr += (pending->height - 1) * pending->pitch;
328 }
329
330 if (pending->rotation & DRM_MODE_REFLECT_X) {
331 con |= OVL_CON_HORZ_FLIP;
332 addr += pending->pitch - 1;
333 }
334
335 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
336 DISP_REG_OVL_CON(idx));
337 mtk_ddp_write_relaxed(cmdq_pkt, pitch, &ovl->cmdq_reg, ovl->regs,
338 DISP_REG_OVL_PITCH(idx));
339 mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
340 DISP_REG_OVL_SRC_SIZE(idx));
341 mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
342 DISP_REG_OVL_OFFSET(idx));
343 mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
344 DISP_REG_OVL_ADDR(ovl, idx));
345
346 mtk_ovl_layer_on(dev, idx, cmdq_pkt);
347 }
348
mtk_ovl_bgclr_in_on(struct device * dev)349 void mtk_ovl_bgclr_in_on(struct device *dev)
350 {
351 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
352 unsigned int reg;
353
354 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
355 reg = reg | OVL_BGCLR_SEL_IN;
356 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
357 }
358
mtk_ovl_bgclr_in_off(struct device * dev)359 void mtk_ovl_bgclr_in_off(struct device *dev)
360 {
361 struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
362 unsigned int reg;
363
364 reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
365 reg = reg & ~OVL_BGCLR_SEL_IN;
366 writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
367 }
368
mtk_disp_ovl_bind(struct device * dev,struct device * master,void * data)369 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
370 void *data)
371 {
372 return 0;
373 }
374
mtk_disp_ovl_unbind(struct device * dev,struct device * master,void * data)375 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
376 void *data)
377 {
378 }
379
380 static const struct component_ops mtk_disp_ovl_component_ops = {
381 .bind = mtk_disp_ovl_bind,
382 .unbind = mtk_disp_ovl_unbind,
383 };
384
mtk_disp_ovl_probe(struct platform_device * pdev)385 static int mtk_disp_ovl_probe(struct platform_device *pdev)
386 {
387 struct device *dev = &pdev->dev;
388 struct mtk_disp_ovl *priv;
389 struct resource *res;
390 int irq;
391 int ret;
392
393 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
394 if (!priv)
395 return -ENOMEM;
396
397 irq = platform_get_irq(pdev, 0);
398 if (irq < 0)
399 return irq;
400
401 priv->clk = devm_clk_get(dev, NULL);
402 if (IS_ERR(priv->clk)) {
403 dev_err(dev, "failed to get ovl clk\n");
404 return PTR_ERR(priv->clk);
405 }
406
407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
408 priv->regs = devm_ioremap_resource(dev, res);
409 if (IS_ERR(priv->regs)) {
410 dev_err(dev, "failed to ioremap ovl\n");
411 return PTR_ERR(priv->regs);
412 }
413 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
414 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
415 if (ret)
416 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
417 #endif
418
419 priv->data = of_device_get_match_data(dev);
420 platform_set_drvdata(pdev, priv);
421
422 ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
423 IRQF_TRIGGER_NONE, dev_name(dev), priv);
424 if (ret < 0) {
425 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
426 return ret;
427 }
428
429 ret = component_add(dev, &mtk_disp_ovl_component_ops);
430 if (ret)
431 dev_err(dev, "Failed to add component: %d\n", ret);
432
433 return ret;
434 }
435
mtk_disp_ovl_remove(struct platform_device * pdev)436 static int mtk_disp_ovl_remove(struct platform_device *pdev)
437 {
438 component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
439
440 return 0;
441 }
442
443 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
444 .addr = DISP_REG_OVL_ADDR_MT2701,
445 .gmc_bits = 8,
446 .layer_nr = 4,
447 .fmt_rgb565_is_0 = false,
448 };
449
450 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
451 .addr = DISP_REG_OVL_ADDR_MT8173,
452 .gmc_bits = 8,
453 .layer_nr = 4,
454 .fmt_rgb565_is_0 = true,
455 };
456
457 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
458 .addr = DISP_REG_OVL_ADDR_MT8173,
459 .gmc_bits = 10,
460 .layer_nr = 4,
461 .fmt_rgb565_is_0 = true,
462 };
463
464 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
465 .addr = DISP_REG_OVL_ADDR_MT8173,
466 .gmc_bits = 10,
467 .layer_nr = 2,
468 .fmt_rgb565_is_0 = true,
469 };
470
471 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
472 { .compatible = "mediatek,mt2701-disp-ovl",
473 .data = &mt2701_ovl_driver_data},
474 { .compatible = "mediatek,mt8173-disp-ovl",
475 .data = &mt8173_ovl_driver_data},
476 { .compatible = "mediatek,mt8183-disp-ovl",
477 .data = &mt8183_ovl_driver_data},
478 { .compatible = "mediatek,mt8183-disp-ovl-2l",
479 .data = &mt8183_ovl_2l_driver_data},
480 {},
481 };
482 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
483
484 struct platform_driver mtk_disp_ovl_driver = {
485 .probe = mtk_disp_ovl_probe,
486 .remove = mtk_disp_ovl_remove,
487 .driver = {
488 .name = "mediatek-disp-ovl",
489 .owner = THIS_MODULE,
490 .of_match_table = mtk_disp_ovl_driver_dt_match,
491 },
492 };
493