1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * rcar_lvds.c -- R-Car LVDS Encoder
4 *
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_device.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/sys_soc.h>
20
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_of.h>
25 #include <drm/drm_panel.h>
26 #include <drm/drm_print.h>
27 #include <drm/drm_probe_helper.h>
28
29 #include "rcar_lvds.h"
30 #include "rcar_lvds_regs.h"
31
32 struct rcar_lvds;
33
34 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
35 enum rcar_lvds_mode {
36 RCAR_LVDS_MODE_JEIDA = 0,
37 RCAR_LVDS_MODE_MIRROR = 1,
38 RCAR_LVDS_MODE_VESA = 4,
39 };
40
41 enum rcar_lvds_link_type {
42 RCAR_LVDS_SINGLE_LINK = 0,
43 RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 1,
44 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 2,
45 };
46
47 #define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
48 #define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
49 #define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
50 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
52
53 struct rcar_lvds_device_info {
54 unsigned int gen;
55 unsigned int quirks;
56 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
57 };
58
59 struct rcar_lvds {
60 struct device *dev;
61 const struct rcar_lvds_device_info *info;
62
63 struct drm_bridge bridge;
64
65 struct drm_bridge *next_bridge;
66 struct drm_panel *panel;
67
68 void __iomem *mmio;
69 struct {
70 struct clk *mod; /* CPG module clock */
71 struct clk *extal; /* External clock */
72 struct clk *dotclkin[2]; /* External DU clocks */
73 } clocks;
74
75 struct drm_bridge *companion;
76 enum rcar_lvds_link_type link_type;
77 };
78
79 #define bridge_to_rcar_lvds(b) \
80 container_of(b, struct rcar_lvds, bridge)
81
rcar_lvds_write(struct rcar_lvds * lvds,u32 reg,u32 data)82 static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
83 {
84 iowrite32(data, lvds->mmio + reg);
85 }
86
87 /* -----------------------------------------------------------------------------
88 * PLL Setup
89 */
90
rcar_lvds_pll_setup_gen2(struct rcar_lvds * lvds,unsigned int freq)91 static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
92 {
93 u32 val;
94
95 if (freq < 39000000)
96 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
97 else if (freq < 61000000)
98 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
99 else if (freq < 121000000)
100 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
101 else
102 val = LVDPLLCR_PLLDLYCNT_150M;
103
104 rcar_lvds_write(lvds, LVDPLLCR, val);
105 }
106
rcar_lvds_pll_setup_gen3(struct rcar_lvds * lvds,unsigned int freq)107 static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
108 {
109 u32 val;
110
111 if (freq < 42000000)
112 val = LVDPLLCR_PLLDIVCNT_42M;
113 else if (freq < 85000000)
114 val = LVDPLLCR_PLLDIVCNT_85M;
115 else if (freq < 128000000)
116 val = LVDPLLCR_PLLDIVCNT_128M;
117 else
118 val = LVDPLLCR_PLLDIVCNT_148M;
119
120 rcar_lvds_write(lvds, LVDPLLCR, val);
121 }
122
123 struct pll_info {
124 unsigned long diff;
125 unsigned int pll_m;
126 unsigned int pll_n;
127 unsigned int pll_e;
128 unsigned int div;
129 u32 clksel;
130 };
131
rcar_lvds_d3_e3_pll_calc(struct rcar_lvds * lvds,struct clk * clk,unsigned long target,struct pll_info * pll,u32 clksel,bool dot_clock_only)132 static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
133 unsigned long target, struct pll_info *pll,
134 u32 clksel, bool dot_clock_only)
135 {
136 unsigned int div7 = dot_clock_only ? 1 : 7;
137 unsigned long output;
138 unsigned long fin;
139 unsigned int m_min;
140 unsigned int m_max;
141 unsigned int m;
142 int error;
143
144 if (!clk)
145 return;
146
147 /*
148 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
149 * enough called M and N respectively), followed by a post-divider E.
150 *
151 * ,-----. ,-----. ,-----. ,-----.
152 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
153 * `-----' ,-> | | `-----' | `-----'
154 * | `-----' |
155 * | ,-----. |
156 * `-------- | 1/N | <-------'
157 * `-----'
158 *
159 * The clock output by the PLL is then further divided by a programmable
160 * divider DIV to achieve the desired target frequency. Finally, an
161 * optional fixed /7 divider is used to convert the bit clock to a pixel
162 * clock (as LVDS transmits 7 bits per lane per clock sample).
163 *
164 * ,-------. ,-----. |\
165 * Fout --> | 1/DIV | --> | 1/7 | --> | |
166 * `-------' | `-----' | | --> dot clock
167 * `------------> | |
168 * |/
169 *
170 * The /7 divider is optional, it is enabled when the LVDS PLL is used
171 * to drive the LVDS encoder, and disabled when used to generate a dot
172 * clock for the DU RGB output, without using the LVDS encoder.
173 *
174 * The PLL allowed input frequency range is 12 MHz to 192 MHz.
175 */
176
177 fin = clk_get_rate(clk);
178 if (fin < 12000000 || fin > 192000000)
179 return;
180
181 /*
182 * The comparison frequency range is 12 MHz to 24 MHz, which limits the
183 * allowed values for the pre-divider M (normal range 1-8).
184 *
185 * Fpfd = Fin / M
186 */
187 m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
188 m_max = min_t(unsigned int, 8, fin / 12000000);
189
190 for (m = m_min; m <= m_max; ++m) {
191 unsigned long fpfd;
192 unsigned int n_min;
193 unsigned int n_max;
194 unsigned int n;
195
196 /*
197 * The VCO operating range is 900 Mhz to 1800 MHz, which limits
198 * the allowed values for the multiplier N (normal range
199 * 60-120).
200 *
201 * Fvco = Fin * N / M
202 */
203 fpfd = fin / m;
204 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
205 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
206
207 for (n = n_min; n < n_max; ++n) {
208 unsigned long fvco;
209 unsigned int e_min;
210 unsigned int e;
211
212 /*
213 * The output frequency is limited to 1039.5 MHz,
214 * limiting again the allowed values for the
215 * post-divider E (normal value 1, 2 or 4).
216 *
217 * Fout = Fvco / E
218 */
219 fvco = fpfd * n;
220 e_min = fvco > 1039500000 ? 1 : 0;
221
222 for (e = e_min; e < 3; ++e) {
223 unsigned long fout;
224 unsigned long diff;
225 unsigned int div;
226
227 /*
228 * Finally we have a programable divider after
229 * the PLL, followed by a an optional fixed /7
230 * divider.
231 */
232 fout = fvco / (1 << e) / div7;
233 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
234 diff = abs(fout / div - target);
235
236 if (diff < pll->diff) {
237 pll->diff = diff;
238 pll->pll_m = m;
239 pll->pll_n = n;
240 pll->pll_e = e;
241 pll->div = div;
242 pll->clksel = clksel;
243
244 if (diff == 0)
245 goto done;
246 }
247 }
248 }
249 }
250
251 done:
252 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
253 / div7 / pll->div;
254 error = (long)(output - target) * 10000 / (long)target;
255
256 dev_dbg(lvds->dev,
257 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
258 clk, fin, output, target, error / 100,
259 error < 0 ? -error % 100 : error % 100,
260 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
261 }
262
__rcar_lvds_pll_setup_d3_e3(struct rcar_lvds * lvds,unsigned int freq,bool dot_clock_only)263 static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
264 unsigned int freq, bool dot_clock_only)
265 {
266 struct pll_info pll = { .diff = (unsigned long)-1 };
267 u32 lvdpllcr;
268
269 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
270 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
271 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
272 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
273 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
274 LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
275
276 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
277 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
278
279 if (pll.pll_e > 0)
280 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
281 | LVDPLLCR_PLLE(pll.pll_e - 1);
282
283 if (dot_clock_only)
284 lvdpllcr |= LVDPLLCR_OCKSEL;
285
286 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
287
288 if (pll.div > 1)
289 /*
290 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
291 * divisor reset.
292 */
293 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
294 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
295 else
296 rcar_lvds_write(lvds, LVDDIV, 0);
297 }
298
rcar_lvds_pll_setup_d3_e3(struct rcar_lvds * lvds,unsigned int freq)299 static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
300 {
301 __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
302 }
303
304 /* -----------------------------------------------------------------------------
305 * Clock - D3/E3 only
306 */
307
rcar_lvds_clk_enable(struct drm_bridge * bridge,unsigned long freq)308 int rcar_lvds_clk_enable(struct drm_bridge *bridge, unsigned long freq)
309 {
310 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
311 int ret;
312
313 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
314 return -ENODEV;
315
316 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
317
318 ret = clk_prepare_enable(lvds->clocks.mod);
319 if (ret < 0)
320 return ret;
321
322 __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
323
324 return 0;
325 }
326 EXPORT_SYMBOL_GPL(rcar_lvds_clk_enable);
327
rcar_lvds_clk_disable(struct drm_bridge * bridge)328 void rcar_lvds_clk_disable(struct drm_bridge *bridge)
329 {
330 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
331
332 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
333 return;
334
335 dev_dbg(lvds->dev, "disabling LVDS PLL\n");
336
337 rcar_lvds_write(lvds, LVDPLLCR, 0);
338
339 clk_disable_unprepare(lvds->clocks.mod);
340 }
341 EXPORT_SYMBOL_GPL(rcar_lvds_clk_disable);
342
343 /* -----------------------------------------------------------------------------
344 * Bridge
345 */
346
rcar_lvds_get_lvds_mode(struct rcar_lvds * lvds,const struct drm_connector * connector)347 static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds,
348 const struct drm_connector *connector)
349 {
350 const struct drm_display_info *info;
351 enum rcar_lvds_mode mode;
352
353 /*
354 * There is no API yet to retrieve LVDS mode from a bridge, only panels
355 * are supported.
356 */
357 if (!lvds->panel)
358 return RCAR_LVDS_MODE_JEIDA;
359
360 info = &connector->display_info;
361 if (!info->num_bus_formats || !info->bus_formats) {
362 dev_warn(lvds->dev,
363 "no LVDS bus format reported, using JEIDA\n");
364 return RCAR_LVDS_MODE_JEIDA;
365 }
366
367 switch (info->bus_formats[0]) {
368 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
369 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
370 mode = RCAR_LVDS_MODE_JEIDA;
371 break;
372 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
373 mode = RCAR_LVDS_MODE_VESA;
374 break;
375 default:
376 dev_warn(lvds->dev,
377 "unsupported LVDS bus format 0x%04x, using JEIDA\n",
378 info->bus_formats[0]);
379 return RCAR_LVDS_MODE_JEIDA;
380 }
381
382 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
383 mode |= RCAR_LVDS_MODE_MIRROR;
384
385 return mode;
386 }
387
__rcar_lvds_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state,struct drm_crtc * crtc,struct drm_connector * connector)388 static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge,
389 struct drm_atomic_state *state,
390 struct drm_crtc *crtc,
391 struct drm_connector *connector)
392 {
393 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
394 u32 lvdhcr;
395 u32 lvdcr0;
396 int ret;
397
398 ret = clk_prepare_enable(lvds->clocks.mod);
399 if (ret < 0)
400 return;
401
402 /* Enable the companion LVDS encoder in dual-link mode. */
403 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
404 __rcar_lvds_atomic_enable(lvds->companion, state, crtc,
405 connector);
406
407 /*
408 * Hardcode the channels and control signals routing for now.
409 *
410 * HSYNC -> CTRL0
411 * VSYNC -> CTRL1
412 * DISP -> CTRL2
413 * 0 -> CTRL3
414 */
415 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
416 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
417 LVDCTRCR_CTR0SEL_HSYNC);
418
419 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
420 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
421 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
422 else
423 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
424 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
425
426 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
427
428 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
429 u32 lvdstripe = 0;
430
431 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) {
432 /*
433 * By default we generate even pixels from the primary
434 * encoder and odd pixels from the companion encoder.
435 * Swap pixels around if the sink requires odd pixels
436 * from the primary encoder and even pixels from the
437 * companion encoder.
438 */
439 bool swap_pixels = lvds->link_type ==
440 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
441
442 /*
443 * Configure vertical stripe since we are dealing with
444 * an LVDS dual-link connection.
445 *
446 * ST_SWAP is reserved for the companion encoder, only
447 * set it in the primary encoder.
448 */
449 lvdstripe = LVDSTRIPE_ST_ON
450 | (lvds->companion && swap_pixels ?
451 LVDSTRIPE_ST_SWAP : 0);
452 }
453 rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe);
454 }
455
456 /*
457 * PLL clock configuration on all instances but the companion in
458 * dual-link mode.
459 */
460 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) {
461 const struct drm_crtc_state *crtc_state =
462 drm_atomic_get_new_crtc_state(state, crtc);
463 const struct drm_display_mode *mode =
464 &crtc_state->adjusted_mode;
465
466 lvds->info->pll_setup(lvds, mode->clock * 1000);
467 }
468
469 /* Set the LVDS mode and select the input. */
470 lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT;
471
472 if (lvds->bridge.encoder) {
473 if (drm_crtc_index(crtc) == 2)
474 lvdcr0 |= LVDCR0_DUSEL;
475 }
476
477 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
478
479 /* Turn all the channels on. */
480 rcar_lvds_write(lvds, LVDCR1,
481 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
482 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
483
484 if (lvds->info->gen < 3) {
485 /* Enable LVDS operation and turn the bias circuitry on. */
486 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
487 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
488 }
489
490 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
491 /*
492 * Turn the PLL on (simple PLL only, extended PLL is fully
493 * controlled through LVDPLLCR).
494 */
495 lvdcr0 |= LVDCR0_PLLON;
496 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
497 }
498
499 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
500 /* Set LVDS normal mode. */
501 lvdcr0 |= LVDCR0_PWD;
502 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
503 }
504
505 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
506 /*
507 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
508 * set at the same time, so don't write the register yet.
509 */
510 lvdcr0 |= LVDCR0_LVEN;
511 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
512 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
513 }
514
515 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
516 /* Wait for the PLL startup delay (simple PLL only). */
517 usleep_range(100, 150);
518 }
519
520 /* Turn the output on. */
521 lvdcr0 |= LVDCR0_LVRES;
522 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
523 }
524
rcar_lvds_atomic_enable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)525 static void rcar_lvds_atomic_enable(struct drm_bridge *bridge,
526 struct drm_bridge_state *old_bridge_state)
527 {
528 struct drm_atomic_state *state = old_bridge_state->base.state;
529 struct drm_connector *connector;
530 struct drm_crtc *crtc;
531
532 connector = drm_atomic_get_new_connector_for_encoder(state,
533 bridge->encoder);
534 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
535
536 __rcar_lvds_atomic_enable(bridge, state, crtc, connector);
537 }
538
rcar_lvds_atomic_disable(struct drm_bridge * bridge,struct drm_bridge_state * old_bridge_state)539 static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
540 struct drm_bridge_state *old_bridge_state)
541 {
542 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
543
544 rcar_lvds_write(lvds, LVDCR0, 0);
545 rcar_lvds_write(lvds, LVDCR1, 0);
546 rcar_lvds_write(lvds, LVDPLLCR, 0);
547
548 /* Disable the companion LVDS encoder in dual-link mode. */
549 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
550 lvds->companion->funcs->atomic_disable(lvds->companion,
551 old_bridge_state);
552
553 clk_disable_unprepare(lvds->clocks.mod);
554 }
555
rcar_lvds_mode_fixup(struct drm_bridge * bridge,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)556 static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
557 const struct drm_display_mode *mode,
558 struct drm_display_mode *adjusted_mode)
559 {
560 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
561 int min_freq;
562
563 /*
564 * The internal LVDS encoder has a restricted clock frequency operating
565 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
566 * 148.5MHz on all other platforms. Clamp the clock accordingly.
567 */
568 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
569 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
570
571 return true;
572 }
573
rcar_lvds_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)574 static int rcar_lvds_attach(struct drm_bridge *bridge,
575 enum drm_bridge_attach_flags flags)
576 {
577 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
578
579 if (!lvds->next_bridge)
580 return 0;
581
582 return drm_bridge_attach(bridge->encoder, lvds->next_bridge, bridge,
583 flags);
584 }
585
586 static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
587 .attach = rcar_lvds_attach,
588 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
589 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
590 .atomic_reset = drm_atomic_helper_bridge_reset,
591 .atomic_enable = rcar_lvds_atomic_enable,
592 .atomic_disable = rcar_lvds_atomic_disable,
593 .mode_fixup = rcar_lvds_mode_fixup,
594 };
595
rcar_lvds_dual_link(struct drm_bridge * bridge)596 bool rcar_lvds_dual_link(struct drm_bridge *bridge)
597 {
598 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
599
600 return lvds->link_type != RCAR_LVDS_SINGLE_LINK;
601 }
602 EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
603
rcar_lvds_is_connected(struct drm_bridge * bridge)604 bool rcar_lvds_is_connected(struct drm_bridge *bridge)
605 {
606 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
607
608 return lvds->next_bridge != NULL;
609 }
610 EXPORT_SYMBOL_GPL(rcar_lvds_is_connected);
611
612 /* -----------------------------------------------------------------------------
613 * Probe & Remove
614 */
615
rcar_lvds_parse_dt_companion(struct rcar_lvds * lvds)616 static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
617 {
618 const struct of_device_id *match;
619 struct device_node *companion;
620 struct device_node *port0, *port1;
621 struct rcar_lvds *companion_lvds;
622 struct device *dev = lvds->dev;
623 int dual_link;
624 int ret = 0;
625
626 /* Locate the companion LVDS encoder for dual-link operation, if any. */
627 companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
628 if (!companion)
629 return 0;
630
631 /*
632 * Sanity check: the companion encoder must have the same compatible
633 * string.
634 */
635 match = of_match_device(dev->driver->of_match_table, dev);
636 if (!of_device_is_compatible(companion, match->compatible)) {
637 dev_err(dev, "Companion LVDS encoder is invalid\n");
638 ret = -ENXIO;
639 goto done;
640 }
641
642 /*
643 * We need to work out if the sink is expecting us to function in
644 * dual-link mode. We do this by looking at the DT port nodes we are
645 * connected to, if they are marked as expecting even pixels and
646 * odd pixels than we need to enable vertical stripe output.
647 */
648 port0 = of_graph_get_port_by_id(dev->of_node, 1);
649 port1 = of_graph_get_port_by_id(companion, 1);
650 dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
651 of_node_put(port0);
652 of_node_put(port1);
653
654 switch (dual_link) {
655 case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
656 lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
657 break;
658 case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
659 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
660 break;
661 default:
662 /*
663 * Early dual-link bridge specific implementations populate the
664 * timings field of drm_bridge. If the flag is set, we assume
665 * that we are expected to generate even pixels from the primary
666 * encoder, and odd pixels from the companion encoder.
667 */
668 if (lvds->next_bridge->timings &&
669 lvds->next_bridge->timings->dual_link)
670 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
671 else
672 lvds->link_type = RCAR_LVDS_SINGLE_LINK;
673 }
674
675 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) {
676 dev_dbg(dev, "Single-link configuration detected\n");
677 goto done;
678 }
679
680 lvds->companion = of_drm_find_bridge(companion);
681 if (!lvds->companion) {
682 ret = -EPROBE_DEFER;
683 goto done;
684 }
685
686 dev_dbg(dev,
687 "Dual-link configuration detected (companion encoder %pOF)\n",
688 companion);
689
690 if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
691 dev_dbg(dev, "Data swapping required\n");
692
693 /*
694 * FIXME: We should not be messing with the companion encoder private
695 * data from the primary encoder, we should rather let the companion
696 * encoder work things out on its own. However, the companion encoder
697 * doesn't hold a reference to the primary encoder, and
698 * drm_of_lvds_get_dual_link_pixel_order needs to be given references
699 * to the output ports of both encoders, therefore leave it like this
700 * for the time being.
701 */
702 companion_lvds = bridge_to_rcar_lvds(lvds->companion);
703 companion_lvds->link_type = lvds->link_type;
704
705 done:
706 of_node_put(companion);
707
708 return ret;
709 }
710
rcar_lvds_parse_dt(struct rcar_lvds * lvds)711 static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
712 {
713 int ret;
714
715 ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0,
716 &lvds->panel, &lvds->next_bridge);
717 if (ret)
718 goto done;
719
720 if (lvds->panel) {
721 lvds->next_bridge = devm_drm_panel_bridge_add(lvds->dev,
722 lvds->panel);
723 if (IS_ERR_OR_NULL(lvds->next_bridge)) {
724 ret = -EINVAL;
725 goto done;
726 }
727 }
728
729 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
730 ret = rcar_lvds_parse_dt_companion(lvds);
731
732 done:
733 /*
734 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
735 * used for the DPAD output even when the LVDS output is not connected.
736 * Don't fail probe in that case as the DU will need the bridge to
737 * control the clock.
738 */
739 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
740 return ret == -ENODEV ? 0 : ret;
741
742 return ret;
743 }
744
rcar_lvds_get_clock(struct rcar_lvds * lvds,const char * name,bool optional)745 static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
746 bool optional)
747 {
748 struct clk *clk;
749
750 clk = devm_clk_get(lvds->dev, name);
751 if (!IS_ERR(clk))
752 return clk;
753
754 if (PTR_ERR(clk) == -ENOENT && optional)
755 return NULL;
756
757 dev_err_probe(lvds->dev, PTR_ERR(clk), "failed to get %s clock\n",
758 name ? name : "module");
759
760 return clk;
761 }
762
rcar_lvds_get_clocks(struct rcar_lvds * lvds)763 static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
764 {
765 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
766 if (IS_ERR(lvds->clocks.mod))
767 return PTR_ERR(lvds->clocks.mod);
768
769 /*
770 * LVDS encoders without an extended PLL have no external clock inputs.
771 */
772 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
773 return 0;
774
775 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
776 if (IS_ERR(lvds->clocks.extal))
777 return PTR_ERR(lvds->clocks.extal);
778
779 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
780 if (IS_ERR(lvds->clocks.dotclkin[0]))
781 return PTR_ERR(lvds->clocks.dotclkin[0]);
782
783 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
784 if (IS_ERR(lvds->clocks.dotclkin[1]))
785 return PTR_ERR(lvds->clocks.dotclkin[1]);
786
787 /* At least one input to the PLL must be available. */
788 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
789 !lvds->clocks.dotclkin[1]) {
790 dev_err(lvds->dev,
791 "no input clock (extal, dclkin.0 or dclkin.1)\n");
792 return -EINVAL;
793 }
794
795 return 0;
796 }
797
798 static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = {
799 .gen = 2,
800 .quirks = RCAR_LVDS_QUIRK_LANES,
801 .pll_setup = rcar_lvds_pll_setup_gen2,
802 };
803
804 static const struct soc_device_attribute lvds_quirk_matches[] = {
805 {
806 .soc_id = "r8a7790", .revision = "ES1.*",
807 .data = &rcar_lvds_r8a7790es1_info,
808 },
809 { /* sentinel */ }
810 };
811
rcar_lvds_probe(struct platform_device * pdev)812 static int rcar_lvds_probe(struct platform_device *pdev)
813 {
814 const struct soc_device_attribute *attr;
815 struct rcar_lvds *lvds;
816 struct resource *mem;
817 int ret;
818
819 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
820 if (lvds == NULL)
821 return -ENOMEM;
822
823 platform_set_drvdata(pdev, lvds);
824
825 lvds->dev = &pdev->dev;
826 lvds->info = of_device_get_match_data(&pdev->dev);
827
828 attr = soc_device_match(lvds_quirk_matches);
829 if (attr)
830 lvds->info = attr->data;
831
832 ret = rcar_lvds_parse_dt(lvds);
833 if (ret < 0)
834 return ret;
835
836 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
837 lvds->bridge.of_node = pdev->dev.of_node;
838
839 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
840 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
841 if (IS_ERR(lvds->mmio))
842 return PTR_ERR(lvds->mmio);
843
844 ret = rcar_lvds_get_clocks(lvds);
845 if (ret < 0)
846 return ret;
847
848 drm_bridge_add(&lvds->bridge);
849
850 return 0;
851 }
852
rcar_lvds_remove(struct platform_device * pdev)853 static int rcar_lvds_remove(struct platform_device *pdev)
854 {
855 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
856
857 drm_bridge_remove(&lvds->bridge);
858
859 return 0;
860 }
861
862 static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
863 .gen = 2,
864 .pll_setup = rcar_lvds_pll_setup_gen2,
865 };
866
867 static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
868 .gen = 3,
869 .quirks = RCAR_LVDS_QUIRK_PWD,
870 .pll_setup = rcar_lvds_pll_setup_gen3,
871 };
872
873 static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
874 .gen = 3,
875 .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
876 .pll_setup = rcar_lvds_pll_setup_gen2,
877 };
878
879 static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
880 .gen = 3,
881 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
882 | RCAR_LVDS_QUIRK_DUAL_LINK,
883 .pll_setup = rcar_lvds_pll_setup_d3_e3,
884 };
885
886 static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
887 .gen = 3,
888 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
889 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
890 .pll_setup = rcar_lvds_pll_setup_d3_e3,
891 };
892
893 static const struct of_device_id rcar_lvds_of_table[] = {
894 { .compatible = "renesas,r8a7742-lvds", .data = &rcar_lvds_gen2_info },
895 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
896 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
897 { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
898 { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
899 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
900 { .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info },
901 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
902 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
903 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
904 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
905 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
906 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
907 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
908 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
909 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
910 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
911 { }
912 };
913
914 MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
915
916 static struct platform_driver rcar_lvds_platform_driver = {
917 .probe = rcar_lvds_probe,
918 .remove = rcar_lvds_remove,
919 .driver = {
920 .name = "rcar-lvds",
921 .of_match_table = rcar_lvds_of_table,
922 },
923 };
924
925 module_platform_driver(rcar_lvds_platform_driver);
926
927 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
928 MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
929 MODULE_LICENSE("GPL");
930