1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Free Electrons
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/regmap.h>
14 #include <linux/reset.h>
15
16 #include <drm/drm_device.h>
17 #include <drm/drm_fb_cma_helper.h>
18 #include <drm/drm_fourcc.h>
19 #include <drm/drm_framebuffer.h>
20 #include <drm/drm_gem_cma_helper.h>
21 #include <drm/drm_plane.h>
22
23 #include "sun4i_drv.h"
24 #include "sun4i_frontend.h"
25
26 static const u32 sun4i_frontend_vert_coef[32] = {
27 0x00004000, 0x000140ff, 0x00033ffe, 0x00043ffd,
28 0x00063efc, 0xff083dfc, 0x000a3bfb, 0xff0d39fb,
29 0xff0f37fb, 0xff1136fa, 0xfe1433fb, 0xfe1631fb,
30 0xfd192ffb, 0xfd1c2cfb, 0xfd1f29fb, 0xfc2127fc,
31 0xfc2424fc, 0xfc2721fc, 0xfb291ffd, 0xfb2c1cfd,
32 0xfb2f19fd, 0xfb3116fe, 0xfb3314fe, 0xfa3611ff,
33 0xfb370fff, 0xfb390dff, 0xfb3b0a00, 0xfc3d08ff,
34 0xfc3e0600, 0xfd3f0400, 0xfe3f0300, 0xff400100,
35 };
36
37 static const u32 sun4i_frontend_horz_coef[64] = {
38 0x40000000, 0x00000000, 0x40fe0000, 0x0000ff03,
39 0x3ffd0000, 0x0000ff05, 0x3ffc0000, 0x0000ff06,
40 0x3efb0000, 0x0000ff08, 0x3dfb0000, 0x0000ff09,
41 0x3bfa0000, 0x0000fe0d, 0x39fa0000, 0x0000fe0f,
42 0x38fa0000, 0x0000fe10, 0x36fa0000, 0x0000fe12,
43 0x33fa0000, 0x0000fd16, 0x31fa0000, 0x0000fd18,
44 0x2ffa0000, 0x0000fd1a, 0x2cfa0000, 0x0000fc1e,
45 0x29fa0000, 0x0000fc21, 0x27fb0000, 0x0000fb23,
46 0x24fb0000, 0x0000fb26, 0x21fb0000, 0x0000fb29,
47 0x1ffc0000, 0x0000fa2b, 0x1cfc0000, 0x0000fa2e,
48 0x19fd0000, 0x0000fa30, 0x16fd0000, 0x0000fa33,
49 0x14fd0000, 0x0000fa35, 0x11fe0000, 0x0000fa37,
50 0x0ffe0000, 0x0000fa39, 0x0dfe0000, 0x0000fa3b,
51 0x0afe0000, 0x0000fa3e, 0x08ff0000, 0x0000fb3e,
52 0x06ff0000, 0x0000fb40, 0x05ff0000, 0x0000fc40,
53 0x03ff0000, 0x0000fd41, 0x01ff0000, 0x0000fe42,
54 };
55
56 /*
57 * These coefficients are taken from the A33 BSP from Allwinner.
58 *
59 * The first three values of each row are coded as 13-bit signed fixed-point
60 * numbers, with 10 bits for the fractional part. The fourth value is a
61 * constant coded as a 14-bit signed fixed-point number with 4 bits for the
62 * fractional part.
63 *
64 * The values in table order give the following colorspace translation:
65 * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
66 * R = 1.164 * Y + 1.596 * V - 222
67 * B = 1.164 * Y + 2.018 * U + 276
68 *
69 * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
70 * following the BT601 spec.
71 */
72 const u32 sunxi_bt601_yuv2rgb_coef[12] = {
73 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
74 0x000004a7, 0x00000000, 0x00000662, 0x00003211,
75 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
76 };
77 EXPORT_SYMBOL(sunxi_bt601_yuv2rgb_coef);
78
sun4i_frontend_scaler_init(struct sun4i_frontend * frontend)79 static void sun4i_frontend_scaler_init(struct sun4i_frontend *frontend)
80 {
81 int i;
82
83 if (frontend->data->has_coef_access_ctrl)
84 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
85 SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL,
86 SUN4I_FRONTEND_FRM_CTRL_COEF_ACCESS_CTRL);
87
88 for (i = 0; i < 32; i++) {
89 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF0_REG(i),
90 sun4i_frontend_horz_coef[2 * i]);
91 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF0_REG(i),
92 sun4i_frontend_horz_coef[2 * i]);
93 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZCOEF1_REG(i),
94 sun4i_frontend_horz_coef[2 * i + 1]);
95 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZCOEF1_REG(i),
96 sun4i_frontend_horz_coef[2 * i + 1]);
97 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTCOEF_REG(i),
98 sun4i_frontend_vert_coef[i]);
99 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTCOEF_REG(i),
100 sun4i_frontend_vert_coef[i]);
101 }
102
103 if (frontend->data->has_coef_rdy)
104 regmap_write_bits(frontend->regs,
105 SUN4I_FRONTEND_FRM_CTRL_REG,
106 SUN4I_FRONTEND_FRM_CTRL_COEF_RDY,
107 SUN4I_FRONTEND_FRM_CTRL_COEF_RDY);
108 }
109
sun4i_frontend_init(struct sun4i_frontend * frontend)110 int sun4i_frontend_init(struct sun4i_frontend *frontend)
111 {
112 return pm_runtime_get_sync(frontend->dev);
113 }
114 EXPORT_SYMBOL(sun4i_frontend_init);
115
sun4i_frontend_exit(struct sun4i_frontend * frontend)116 void sun4i_frontend_exit(struct sun4i_frontend *frontend)
117 {
118 pm_runtime_put(frontend->dev);
119 }
120 EXPORT_SYMBOL(sun4i_frontend_exit);
121
sun4i_frontend_format_chroma_requires_swap(uint32_t fmt)122 static bool sun4i_frontend_format_chroma_requires_swap(uint32_t fmt)
123 {
124 switch (fmt) {
125 case DRM_FORMAT_YVU411:
126 case DRM_FORMAT_YVU420:
127 case DRM_FORMAT_YVU422:
128 case DRM_FORMAT_YVU444:
129 return true;
130
131 default:
132 return false;
133 }
134 }
135
sun4i_frontend_format_supports_tiling(uint32_t fmt)136 static bool sun4i_frontend_format_supports_tiling(uint32_t fmt)
137 {
138 switch (fmt) {
139 case DRM_FORMAT_NV12:
140 case DRM_FORMAT_NV16:
141 case DRM_FORMAT_NV21:
142 case DRM_FORMAT_NV61:
143 case DRM_FORMAT_YUV411:
144 case DRM_FORMAT_YUV420:
145 case DRM_FORMAT_YUV422:
146 case DRM_FORMAT_YVU420:
147 case DRM_FORMAT_YVU422:
148 case DRM_FORMAT_YVU411:
149 return true;
150
151 default:
152 return false;
153 }
154 }
155
sun4i_frontend_update_buffer(struct sun4i_frontend * frontend,struct drm_plane * plane)156 void sun4i_frontend_update_buffer(struct sun4i_frontend *frontend,
157 struct drm_plane *plane)
158 {
159 struct drm_plane_state *state = plane->state;
160 struct drm_framebuffer *fb = state->fb;
161 unsigned int strides[3] = {};
162
163 dma_addr_t paddr;
164 bool swap;
165
166 if (fb->modifier == DRM_FORMAT_MOD_ALLWINNER_TILED) {
167 unsigned int width = state->src_w >> 16;
168 unsigned int offset;
169
170 strides[0] = SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[0]);
171
172 /*
173 * The X1 offset is the offset to the bottom-right point in the
174 * end tile, which is the final pixel (at offset width - 1)
175 * within the end tile (with a 32-byte mask).
176 */
177 offset = (width - 1) & (32 - 1);
178
179 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF0_REG,
180 SUN4I_FRONTEND_TB_OFF_X1(offset));
181
182 if (fb->format->num_planes > 1) {
183 strides[1] =
184 SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[1]);
185
186 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF1_REG,
187 SUN4I_FRONTEND_TB_OFF_X1(offset));
188 }
189
190 if (fb->format->num_planes > 2) {
191 strides[2] =
192 SUN4I_FRONTEND_LINESTRD_TILED(fb->pitches[2]);
193
194 regmap_write(frontend->regs, SUN4I_FRONTEND_TB_OFF2_REG,
195 SUN4I_FRONTEND_TB_OFF_X1(offset));
196 }
197 } else {
198 strides[0] = fb->pitches[0];
199
200 if (fb->format->num_planes > 1)
201 strides[1] = fb->pitches[1];
202
203 if (fb->format->num_planes > 2)
204 strides[2] = fb->pitches[2];
205 }
206
207 /* Set the line width */
208 DRM_DEBUG_DRIVER("Frontend stride: %d bytes\n", fb->pitches[0]);
209 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD0_REG,
210 strides[0]);
211
212 if (fb->format->num_planes > 1)
213 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD1_REG,
214 strides[1]);
215
216 if (fb->format->num_planes > 2)
217 regmap_write(frontend->regs, SUN4I_FRONTEND_LINESTRD2_REG,
218 strides[2]);
219
220 /* Some planar formats require chroma channel swapping by hand. */
221 swap = sun4i_frontend_format_chroma_requires_swap(fb->format->format);
222
223 /* Set the physical address of the buffer in memory */
224 paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
225 DRM_DEBUG_DRIVER("Setting buffer #0 address to %pad\n", &paddr);
226 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR0_REG, paddr);
227
228 if (fb->format->num_planes > 1) {
229 paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 2 : 1);
230 DRM_DEBUG_DRIVER("Setting buffer #1 address to %pad\n", &paddr);
231 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR1_REG,
232 paddr);
233 }
234
235 if (fb->format->num_planes > 2) {
236 paddr = drm_fb_cma_get_gem_addr(fb, state, swap ? 1 : 2);
237 DRM_DEBUG_DRIVER("Setting buffer #2 address to %pad\n", &paddr);
238 regmap_write(frontend->regs, SUN4I_FRONTEND_BUF_ADDR2_REG,
239 paddr);
240 }
241 }
242 EXPORT_SYMBOL(sun4i_frontend_update_buffer);
243
244 static int
sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info * format,u32 * val)245 sun4i_frontend_drm_format_to_input_fmt(const struct drm_format_info *format,
246 u32 *val)
247 {
248 if (!format->is_yuv)
249 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_RGB;
250 else if (drm_format_info_is_yuv_sampling_411(format))
251 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV411;
252 else if (drm_format_info_is_yuv_sampling_420(format))
253 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV420;
254 else if (drm_format_info_is_yuv_sampling_422(format))
255 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV422;
256 else if (drm_format_info_is_yuv_sampling_444(format))
257 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_FMT_YUV444;
258 else
259 return -EINVAL;
260
261 return 0;
262 }
263
264 static int
sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info * format,uint64_t modifier,u32 * val)265 sun4i_frontend_drm_format_to_input_mode(const struct drm_format_info *format,
266 uint64_t modifier, u32 *val)
267 {
268 bool tiled = (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED);
269
270 switch (format->num_planes) {
271 case 1:
272 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PACKED;
273 return 0;
274
275 case 2:
276 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_SEMIPLANAR
277 : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_SEMIPLANAR;
278 return 0;
279
280 case 3:
281 *val = tiled ? SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_MB32_PLANAR
282 : SUN4I_FRONTEND_INPUT_FMT_DATA_MOD_PLANAR;
283 return 0;
284
285 default:
286 return -EINVAL;
287 }
288 }
289
290 static int
sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info * format,u32 * val)291 sun4i_frontend_drm_format_to_input_sequence(const struct drm_format_info *format,
292 u32 *val)
293 {
294 /* Planar formats have an explicit input sequence. */
295 if (drm_format_info_is_yuv_planar(format)) {
296 *val = 0;
297 return 0;
298 }
299
300 switch (format->format) {
301 case DRM_FORMAT_BGRX8888:
302 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_BGRX;
303 return 0;
304
305 case DRM_FORMAT_NV12:
306 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
307 return 0;
308
309 case DRM_FORMAT_NV16:
310 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UV;
311 return 0;
312
313 case DRM_FORMAT_NV21:
314 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
315 return 0;
316
317 case DRM_FORMAT_NV61:
318 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VU;
319 return 0;
320
321 case DRM_FORMAT_UYVY:
322 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_UYVY;
323 return 0;
324
325 case DRM_FORMAT_VYUY:
326 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_VYUY;
327 return 0;
328
329 case DRM_FORMAT_XRGB8888:
330 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_XRGB;
331 return 0;
332
333 case DRM_FORMAT_YUYV:
334 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YUYV;
335 return 0;
336
337 case DRM_FORMAT_YVYU:
338 *val = SUN4I_FRONTEND_INPUT_FMT_DATA_PS_YVYU;
339 return 0;
340
341 default:
342 return -EINVAL;
343 }
344 }
345
sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt,u32 * val)346 static int sun4i_frontend_drm_format_to_output_fmt(uint32_t fmt, u32 *val)
347 {
348 switch (fmt) {
349 case DRM_FORMAT_BGRX8888:
350 *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_BGRX8888;
351 return 0;
352
353 case DRM_FORMAT_XRGB8888:
354 *val = SUN4I_FRONTEND_OUTPUT_FMT_DATA_FMT_XRGB8888;
355 return 0;
356
357 default:
358 return -EINVAL;
359 }
360 }
361
362 static const uint32_t sun4i_frontend_formats[] = {
363 DRM_FORMAT_BGRX8888,
364 DRM_FORMAT_NV12,
365 DRM_FORMAT_NV16,
366 DRM_FORMAT_NV21,
367 DRM_FORMAT_NV61,
368 DRM_FORMAT_UYVY,
369 DRM_FORMAT_VYUY,
370 DRM_FORMAT_XRGB8888,
371 DRM_FORMAT_YUV411,
372 DRM_FORMAT_YUV420,
373 DRM_FORMAT_YUV422,
374 DRM_FORMAT_YUV444,
375 DRM_FORMAT_YUYV,
376 DRM_FORMAT_YVU411,
377 DRM_FORMAT_YVU420,
378 DRM_FORMAT_YVU422,
379 DRM_FORMAT_YVU444,
380 DRM_FORMAT_YVYU,
381 };
382
sun4i_frontend_format_is_supported(uint32_t fmt,uint64_t modifier)383 bool sun4i_frontend_format_is_supported(uint32_t fmt, uint64_t modifier)
384 {
385 unsigned int i;
386
387 if (modifier == DRM_FORMAT_MOD_ALLWINNER_TILED)
388 return sun4i_frontend_format_supports_tiling(fmt);
389 else if (modifier != DRM_FORMAT_MOD_LINEAR)
390 return false;
391
392 for (i = 0; i < ARRAY_SIZE(sun4i_frontend_formats); i++)
393 if (sun4i_frontend_formats[i] == fmt)
394 return true;
395
396 return false;
397 }
398 EXPORT_SYMBOL(sun4i_frontend_format_is_supported);
399
sun4i_frontend_update_formats(struct sun4i_frontend * frontend,struct drm_plane * plane,uint32_t out_fmt)400 int sun4i_frontend_update_formats(struct sun4i_frontend *frontend,
401 struct drm_plane *plane, uint32_t out_fmt)
402 {
403 struct drm_plane_state *state = plane->state;
404 struct drm_framebuffer *fb = state->fb;
405 const struct drm_format_info *format = fb->format;
406 uint64_t modifier = fb->modifier;
407 unsigned int ch1_phase_idx;
408 u32 out_fmt_val;
409 u32 in_fmt_val, in_mod_val, in_ps_val;
410 unsigned int i;
411 u32 bypass;
412 int ret;
413
414 ret = sun4i_frontend_drm_format_to_input_fmt(format, &in_fmt_val);
415 if (ret) {
416 DRM_DEBUG_DRIVER("Invalid input format\n");
417 return ret;
418 }
419
420 ret = sun4i_frontend_drm_format_to_input_mode(format, modifier,
421 &in_mod_val);
422 if (ret) {
423 DRM_DEBUG_DRIVER("Invalid input mode\n");
424 return ret;
425 }
426
427 ret = sun4i_frontend_drm_format_to_input_sequence(format, &in_ps_val);
428 if (ret) {
429 DRM_DEBUG_DRIVER("Invalid pixel sequence\n");
430 return ret;
431 }
432
433 ret = sun4i_frontend_drm_format_to_output_fmt(out_fmt, &out_fmt_val);
434 if (ret) {
435 DRM_DEBUG_DRIVER("Invalid output format\n");
436 return ret;
437 }
438
439 /*
440 * I have no idea what this does exactly, but it seems to be
441 * related to the scaler FIR filter phase parameters.
442 */
443 ch1_phase_idx = (format->num_planes > 1) ? 1 : 0;
444 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZPHASE_REG,
445 frontend->data->ch_phase[0]);
446 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZPHASE_REG,
447 frontend->data->ch_phase[ch1_phase_idx]);
448 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE0_REG,
449 frontend->data->ch_phase[0]);
450 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE0_REG,
451 frontend->data->ch_phase[ch1_phase_idx]);
452 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTPHASE1_REG,
453 frontend->data->ch_phase[0]);
454 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTPHASE1_REG,
455 frontend->data->ch_phase[ch1_phase_idx]);
456
457 /*
458 * Checking the input format is sufficient since we currently only
459 * support RGB output formats to the backend. If YUV output formats
460 * ever get supported, an YUV input and output would require bypassing
461 * the CSC engine too.
462 */
463 if (format->is_yuv) {
464 /* Setup the CSC engine for YUV to RGB conversion. */
465 bypass = 0;
466
467 for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
468 regmap_write(frontend->regs,
469 SUN4I_FRONTEND_CSC_COEF_REG(i),
470 sunxi_bt601_yuv2rgb_coef[i]);
471 } else {
472 bypass = SUN4I_FRONTEND_BYPASS_CSC_EN;
473 }
474
475 regmap_update_bits(frontend->regs, SUN4I_FRONTEND_BYPASS_REG,
476 SUN4I_FRONTEND_BYPASS_CSC_EN, bypass);
477
478 regmap_write(frontend->regs, SUN4I_FRONTEND_INPUT_FMT_REG,
479 in_mod_val | in_fmt_val | in_ps_val);
480
481 /*
482 * TODO: It look like the A31 and A80 at least will need the
483 * bit 7 (ALPHA_EN) enabled when using a format with alpha (so
484 * ARGB8888).
485 */
486 regmap_write(frontend->regs, SUN4I_FRONTEND_OUTPUT_FMT_REG,
487 out_fmt_val);
488
489 return 0;
490 }
491 EXPORT_SYMBOL(sun4i_frontend_update_formats);
492
sun4i_frontend_update_coord(struct sun4i_frontend * frontend,struct drm_plane * plane)493 void sun4i_frontend_update_coord(struct sun4i_frontend *frontend,
494 struct drm_plane *plane)
495 {
496 struct drm_plane_state *state = plane->state;
497 struct drm_framebuffer *fb = state->fb;
498 uint32_t luma_width, luma_height;
499 uint32_t chroma_width, chroma_height;
500
501 /* Set height and width */
502 DRM_DEBUG_DRIVER("Frontend size W: %u H: %u\n",
503 state->crtc_w, state->crtc_h);
504
505 luma_width = state->src_w >> 16;
506 luma_height = state->src_h >> 16;
507
508 chroma_width = DIV_ROUND_UP(luma_width, fb->format->hsub);
509 chroma_height = DIV_ROUND_UP(luma_height, fb->format->vsub);
510
511 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_INSIZE_REG,
512 SUN4I_FRONTEND_INSIZE(luma_height, luma_width));
513 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_INSIZE_REG,
514 SUN4I_FRONTEND_INSIZE(chroma_height, chroma_width));
515
516 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_OUTSIZE_REG,
517 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
518 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_OUTSIZE_REG,
519 SUN4I_FRONTEND_OUTSIZE(state->crtc_h, state->crtc_w));
520
521 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_HORZFACT_REG,
522 (luma_width << 16) / state->crtc_w);
523 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_HORZFACT_REG,
524 (chroma_width << 16) / state->crtc_w);
525
526 regmap_write(frontend->regs, SUN4I_FRONTEND_CH0_VERTFACT_REG,
527 (luma_height << 16) / state->crtc_h);
528 regmap_write(frontend->regs, SUN4I_FRONTEND_CH1_VERTFACT_REG,
529 (chroma_height << 16) / state->crtc_h);
530
531 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
532 SUN4I_FRONTEND_FRM_CTRL_REG_RDY,
533 SUN4I_FRONTEND_FRM_CTRL_REG_RDY);
534 }
535 EXPORT_SYMBOL(sun4i_frontend_update_coord);
536
sun4i_frontend_enable(struct sun4i_frontend * frontend)537 int sun4i_frontend_enable(struct sun4i_frontend *frontend)
538 {
539 regmap_write_bits(frontend->regs, SUN4I_FRONTEND_FRM_CTRL_REG,
540 SUN4I_FRONTEND_FRM_CTRL_FRM_START,
541 SUN4I_FRONTEND_FRM_CTRL_FRM_START);
542
543 return 0;
544 }
545 EXPORT_SYMBOL(sun4i_frontend_enable);
546
547 static const struct regmap_config sun4i_frontend_regmap_config = {
548 .reg_bits = 32,
549 .val_bits = 32,
550 .reg_stride = 4,
551 .max_register = 0x0a14,
552 };
553
sun4i_frontend_bind(struct device * dev,struct device * master,void * data)554 static int sun4i_frontend_bind(struct device *dev, struct device *master,
555 void *data)
556 {
557 struct platform_device *pdev = to_platform_device(dev);
558 struct sun4i_frontend *frontend;
559 struct drm_device *drm = data;
560 struct sun4i_drv *drv = drm->dev_private;
561 struct resource *res;
562 void __iomem *regs;
563
564 frontend = devm_kzalloc(dev, sizeof(*frontend), GFP_KERNEL);
565 if (!frontend)
566 return -ENOMEM;
567
568 dev_set_drvdata(dev, frontend);
569 frontend->dev = dev;
570 frontend->node = dev->of_node;
571
572 frontend->data = of_device_get_match_data(dev);
573 if (!frontend->data)
574 return -ENODEV;
575
576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577 regs = devm_ioremap_resource(dev, res);
578 if (IS_ERR(regs))
579 return PTR_ERR(regs);
580
581 frontend->regs = devm_regmap_init_mmio(dev, regs,
582 &sun4i_frontend_regmap_config);
583 if (IS_ERR(frontend->regs)) {
584 dev_err(dev, "Couldn't create the frontend regmap\n");
585 return PTR_ERR(frontend->regs);
586 }
587
588 frontend->reset = devm_reset_control_get(dev, NULL);
589 if (IS_ERR(frontend->reset)) {
590 dev_err(dev, "Couldn't get our reset line\n");
591 return PTR_ERR(frontend->reset);
592 }
593
594 frontend->bus_clk = devm_clk_get(dev, "ahb");
595 if (IS_ERR(frontend->bus_clk)) {
596 dev_err(dev, "Couldn't get our bus clock\n");
597 return PTR_ERR(frontend->bus_clk);
598 }
599
600 frontend->mod_clk = devm_clk_get(dev, "mod");
601 if (IS_ERR(frontend->mod_clk)) {
602 dev_err(dev, "Couldn't get our mod clock\n");
603 return PTR_ERR(frontend->mod_clk);
604 }
605
606 frontend->ram_clk = devm_clk_get(dev, "ram");
607 if (IS_ERR(frontend->ram_clk)) {
608 dev_err(dev, "Couldn't get our ram clock\n");
609 return PTR_ERR(frontend->ram_clk);
610 }
611
612 list_add_tail(&frontend->list, &drv->frontend_list);
613 pm_runtime_enable(dev);
614
615 return 0;
616 }
617
sun4i_frontend_unbind(struct device * dev,struct device * master,void * data)618 static void sun4i_frontend_unbind(struct device *dev, struct device *master,
619 void *data)
620 {
621 struct sun4i_frontend *frontend = dev_get_drvdata(dev);
622
623 list_del(&frontend->list);
624 pm_runtime_force_suspend(dev);
625 }
626
627 static const struct component_ops sun4i_frontend_ops = {
628 .bind = sun4i_frontend_bind,
629 .unbind = sun4i_frontend_unbind,
630 };
631
sun4i_frontend_probe(struct platform_device * pdev)632 static int sun4i_frontend_probe(struct platform_device *pdev)
633 {
634 return component_add(&pdev->dev, &sun4i_frontend_ops);
635 }
636
sun4i_frontend_remove(struct platform_device * pdev)637 static int sun4i_frontend_remove(struct platform_device *pdev)
638 {
639 component_del(&pdev->dev, &sun4i_frontend_ops);
640
641 return 0;
642 }
643
sun4i_frontend_runtime_resume(struct device * dev)644 static int sun4i_frontend_runtime_resume(struct device *dev)
645 {
646 struct sun4i_frontend *frontend = dev_get_drvdata(dev);
647 int ret;
648
649 clk_set_rate(frontend->mod_clk, 300000000);
650
651 clk_prepare_enable(frontend->bus_clk);
652 clk_prepare_enable(frontend->mod_clk);
653 clk_prepare_enable(frontend->ram_clk);
654
655 ret = reset_control_reset(frontend->reset);
656 if (ret) {
657 dev_err(dev, "Couldn't reset our device\n");
658 return ret;
659 }
660
661 regmap_update_bits(frontend->regs, SUN4I_FRONTEND_EN_REG,
662 SUN4I_FRONTEND_EN_EN,
663 SUN4I_FRONTEND_EN_EN);
664
665 sun4i_frontend_scaler_init(frontend);
666
667 return 0;
668 }
669
sun4i_frontend_runtime_suspend(struct device * dev)670 static int sun4i_frontend_runtime_suspend(struct device *dev)
671 {
672 struct sun4i_frontend *frontend = dev_get_drvdata(dev);
673
674 clk_disable_unprepare(frontend->ram_clk);
675 clk_disable_unprepare(frontend->mod_clk);
676 clk_disable_unprepare(frontend->bus_clk);
677
678 reset_control_assert(frontend->reset);
679
680 return 0;
681 }
682
683 static const struct dev_pm_ops sun4i_frontend_pm_ops = {
684 .runtime_resume = sun4i_frontend_runtime_resume,
685 .runtime_suspend = sun4i_frontend_runtime_suspend,
686 };
687
688 static const struct sun4i_frontend_data sun4i_a10_frontend = {
689 .ch_phase = { 0x000, 0xfc000 },
690 .has_coef_rdy = true,
691 };
692
693 static const struct sun4i_frontend_data sun8i_a33_frontend = {
694 .ch_phase = { 0x400, 0xfc400 },
695 .has_coef_access_ctrl = true,
696 };
697
698 const struct of_device_id sun4i_frontend_of_table[] = {
699 {
700 .compatible = "allwinner,sun4i-a10-display-frontend",
701 .data = &sun4i_a10_frontend
702 },
703 {
704 .compatible = "allwinner,sun7i-a20-display-frontend",
705 .data = &sun4i_a10_frontend
706 },
707 {
708 .compatible = "allwinner,sun8i-a23-display-frontend",
709 .data = &sun8i_a33_frontend
710 },
711 {
712 .compatible = "allwinner,sun8i-a33-display-frontend",
713 .data = &sun8i_a33_frontend
714 },
715 { }
716 };
717 EXPORT_SYMBOL(sun4i_frontend_of_table);
718 MODULE_DEVICE_TABLE(of, sun4i_frontend_of_table);
719
720 static struct platform_driver sun4i_frontend_driver = {
721 .probe = sun4i_frontend_probe,
722 .remove = sun4i_frontend_remove,
723 .driver = {
724 .name = "sun4i-frontend",
725 .of_match_table = sun4i_frontend_of_table,
726 .pm = &sun4i_frontend_pm_ops,
727 },
728 };
729 module_platform_driver(sun4i_frontend_driver);
730
731 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
732 MODULE_DESCRIPTION("Allwinner A10 Display Engine Frontend Driver");
733 MODULE_LICENSE("GPL");
734