1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, NVIDIA Corporation.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/host1x.h>
10 #include <linux/iommu.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18
19 #include <soc/tegra/pmc.h>
20
21 #include "drm.h"
22 #include "falcon.h"
23 #include "vic.h"
24
25 struct vic_config {
26 const char *firmware;
27 unsigned int version;
28 bool supports_sid;
29 };
30
31 struct vic {
32 struct falcon falcon;
33
34 void __iomem *regs;
35 struct tegra_drm_client client;
36 struct host1x_channel *channel;
37 struct device *dev;
38 struct clk *clk;
39 struct reset_control *rst;
40
41 /* Platform configuration */
42 const struct vic_config *config;
43 };
44
to_vic(struct tegra_drm_client * client)45 static inline struct vic *to_vic(struct tegra_drm_client *client)
46 {
47 return container_of(client, struct vic, client);
48 }
49
vic_writel(struct vic * vic,u32 value,unsigned int offset)50 static void vic_writel(struct vic *vic, u32 value, unsigned int offset)
51 {
52 writel(value, vic->regs + offset);
53 }
54
vic_boot(struct vic * vic)55 static int vic_boot(struct vic *vic)
56 {
57 #ifdef CONFIG_IOMMU_API
58 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev);
59 #endif
60 u32 fce_ucode_size, fce_bin_data_offset;
61 void *hdr;
62 int err = 0;
63
64 #ifdef CONFIG_IOMMU_API
65 if (vic->config->supports_sid && spec) {
66 u32 value;
67
68 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
69 TRANSCFG_ATT(0, TRANSCFG_SID_HW);
70 vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
71
72 if (spec->num_ids > 0) {
73 value = spec->ids[0] & 0xffff;
74
75 /*
76 * STREAMID0 is used for input/output buffers.
77 * Initialize it to SID_VIC in case context isolation
78 * is not enabled, and SID_VIC is used for both firmware
79 * and data buffers.
80 *
81 * If context isolation is enabled, it will be
82 * overridden by the SETSTREAMID opcode as part of
83 * each job.
84 */
85 vic_writel(vic, value, VIC_THI_STREAMID0);
86
87 /* STREAMID1 is used for firmware loading. */
88 vic_writel(vic, value, VIC_THI_STREAMID1);
89 }
90 }
91 #endif
92
93 /* setup clockgating registers */
94 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
95 CG_IDLE_CG_EN |
96 CG_WAKEUP_DLY_CNT(4),
97 NV_PVIC_MISC_PRI_VIC_CG);
98
99 err = falcon_boot(&vic->falcon);
100 if (err < 0)
101 return err;
102
103 hdr = vic->falcon.firmware.virt;
104 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET);
105
106 /* Old VIC firmware needs kernel help with setting up FCE microcode. */
107 if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
108 hdr = vic->falcon.firmware.virt +
109 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET);
110 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET);
111
112 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE,
113 fce_ucode_size);
114 falcon_execute_method(
115 &vic->falcon, VIC_SET_FCE_UCODE_OFFSET,
116 (vic->falcon.firmware.iova + fce_bin_data_offset) >> 8);
117 }
118
119 err = falcon_wait_idle(&vic->falcon);
120 if (err < 0) {
121 dev_err(vic->dev,
122 "failed to set application ID and FCE base\n");
123 return err;
124 }
125
126 return 0;
127 }
128
vic_init(struct host1x_client * client)129 static int vic_init(struct host1x_client *client)
130 {
131 struct tegra_drm_client *drm = host1x_to_drm_client(client);
132 struct drm_device *dev = dev_get_drvdata(client->host);
133 struct tegra_drm *tegra = dev->dev_private;
134 struct vic *vic = to_vic(drm);
135 int err;
136
137 err = host1x_client_iommu_attach(client);
138 if (err < 0 && err != -ENODEV) {
139 dev_err(vic->dev, "failed to attach to domain: %d\n", err);
140 return err;
141 }
142
143 vic->channel = host1x_channel_request(client);
144 if (!vic->channel) {
145 err = -ENOMEM;
146 goto detach;
147 }
148
149 client->syncpts[0] = host1x_syncpt_request(client, 0);
150 if (!client->syncpts[0]) {
151 err = -ENOMEM;
152 goto free_channel;
153 }
154
155 err = tegra_drm_register_client(tegra, drm);
156 if (err < 0)
157 goto free_syncpt;
158
159 /*
160 * Inherit the DMA parameters (such as maximum segment size) from the
161 * parent host1x device.
162 */
163 client->dev->dma_parms = client->host->dma_parms;
164
165 return 0;
166
167 free_syncpt:
168 host1x_syncpt_put(client->syncpts[0]);
169 free_channel:
170 host1x_channel_put(vic->channel);
171 detach:
172 host1x_client_iommu_detach(client);
173
174 return err;
175 }
176
vic_exit(struct host1x_client * client)177 static int vic_exit(struct host1x_client *client)
178 {
179 struct tegra_drm_client *drm = host1x_to_drm_client(client);
180 struct drm_device *dev = dev_get_drvdata(client->host);
181 struct tegra_drm *tegra = dev->dev_private;
182 struct vic *vic = to_vic(drm);
183 int err;
184
185 /* avoid a dangling pointer just in case this disappears */
186 client->dev->dma_parms = NULL;
187
188 err = tegra_drm_unregister_client(tegra, drm);
189 if (err < 0)
190 return err;
191
192 host1x_syncpt_put(client->syncpts[0]);
193 host1x_channel_put(vic->channel);
194 host1x_client_iommu_detach(client);
195
196 if (client->group) {
197 dma_unmap_single(vic->dev, vic->falcon.firmware.phys,
198 vic->falcon.firmware.size, DMA_TO_DEVICE);
199 tegra_drm_free(tegra, vic->falcon.firmware.size,
200 vic->falcon.firmware.virt,
201 vic->falcon.firmware.iova);
202 } else {
203 dma_free_coherent(vic->dev, vic->falcon.firmware.size,
204 vic->falcon.firmware.virt,
205 vic->falcon.firmware.iova);
206 }
207
208 return 0;
209 }
210
211 static const struct host1x_client_ops vic_client_ops = {
212 .init = vic_init,
213 .exit = vic_exit,
214 };
215
vic_load_firmware(struct vic * vic)216 static int vic_load_firmware(struct vic *vic)
217 {
218 struct host1x_client *client = &vic->client.base;
219 struct tegra_drm *tegra = vic->client.drm;
220 dma_addr_t iova;
221 size_t size;
222 void *virt;
223 int err;
224
225 if (vic->falcon.firmware.virt)
226 return 0;
227
228 err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
229 if (err < 0)
230 return err;
231
232 size = vic->falcon.firmware.size;
233
234 if (!client->group) {
235 virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
236 if (!virt)
237 return -ENOMEM;
238 } else {
239 virt = tegra_drm_alloc(tegra, size, &iova);
240 }
241
242 vic->falcon.firmware.virt = virt;
243 vic->falcon.firmware.iova = iova;
244
245 err = falcon_load_firmware(&vic->falcon);
246 if (err < 0)
247 goto cleanup;
248
249 /*
250 * In this case we have received an IOVA from the shared domain, so we
251 * need to make sure to get the physical address so that the DMA API
252 * knows what memory pages to flush the cache for.
253 */
254 if (client->group) {
255 dma_addr_t phys;
256
257 phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE);
258
259 err = dma_mapping_error(vic->dev, phys);
260 if (err < 0)
261 goto cleanup;
262
263 vic->falcon.firmware.phys = phys;
264 }
265
266 return 0;
267
268 cleanup:
269 if (!client->group)
270 dma_free_coherent(vic->dev, size, virt, iova);
271 else
272 tegra_drm_free(tegra, size, virt, iova);
273
274 return err;
275 }
276
277
vic_runtime_resume(struct device * dev)278 static int __maybe_unused vic_runtime_resume(struct device *dev)
279 {
280 struct vic *vic = dev_get_drvdata(dev);
281 int err;
282
283 err = clk_prepare_enable(vic->clk);
284 if (err < 0)
285 return err;
286
287 usleep_range(10, 20);
288
289 err = reset_control_deassert(vic->rst);
290 if (err < 0)
291 goto disable;
292
293 usleep_range(10, 20);
294
295 err = vic_load_firmware(vic);
296 if (err < 0)
297 goto assert;
298
299 err = vic_boot(vic);
300 if (err < 0)
301 goto assert;
302
303 return 0;
304
305 assert:
306 reset_control_assert(vic->rst);
307 disable:
308 clk_disable_unprepare(vic->clk);
309 return err;
310 }
311
vic_runtime_suspend(struct device * dev)312 static int __maybe_unused vic_runtime_suspend(struct device *dev)
313 {
314 struct vic *vic = dev_get_drvdata(dev);
315 int err;
316
317 err = reset_control_assert(vic->rst);
318 if (err < 0)
319 return err;
320
321 usleep_range(2000, 4000);
322
323 clk_disable_unprepare(vic->clk);
324
325 return 0;
326 }
327
vic_open_channel(struct tegra_drm_client * client,struct tegra_drm_context * context)328 static int vic_open_channel(struct tegra_drm_client *client,
329 struct tegra_drm_context *context)
330 {
331 struct vic *vic = to_vic(client);
332 int err;
333
334 err = pm_runtime_resume_and_get(vic->dev);
335 if (err < 0)
336 return err;
337
338 context->channel = host1x_channel_get(vic->channel);
339 if (!context->channel) {
340 pm_runtime_put(vic->dev);
341 return -ENOMEM;
342 }
343
344 return 0;
345 }
346
vic_close_channel(struct tegra_drm_context * context)347 static void vic_close_channel(struct tegra_drm_context *context)
348 {
349 struct vic *vic = to_vic(context->client);
350
351 host1x_channel_put(context->channel);
352 pm_runtime_put(vic->dev);
353 }
354
355 static const struct tegra_drm_client_ops vic_ops = {
356 .open_channel = vic_open_channel,
357 .close_channel = vic_close_channel,
358 .submit = tegra_drm_submit,
359 };
360
361 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
362
363 static const struct vic_config vic_t124_config = {
364 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
365 .version = 0x40,
366 .supports_sid = false,
367 };
368
369 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
370
371 static const struct vic_config vic_t210_config = {
372 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
373 .version = 0x21,
374 .supports_sid = false,
375 };
376
377 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
378
379 static const struct vic_config vic_t186_config = {
380 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
381 .version = 0x18,
382 .supports_sid = true,
383 };
384
385 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
386
387 static const struct vic_config vic_t194_config = {
388 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
389 .version = 0x19,
390 .supports_sid = true,
391 };
392
393 static const struct of_device_id tegra_vic_of_match[] = {
394 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
395 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
396 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
397 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
398 { },
399 };
400 MODULE_DEVICE_TABLE(of, tegra_vic_of_match);
401
vic_probe(struct platform_device * pdev)402 static int vic_probe(struct platform_device *pdev)
403 {
404 struct device *dev = &pdev->dev;
405 struct host1x_syncpt **syncpts;
406 struct resource *regs;
407 struct vic *vic;
408 int err;
409
410 /* inherit DMA mask from host1x parent */
411 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask);
412 if (err < 0) {
413 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
414 return err;
415 }
416
417 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL);
418 if (!vic)
419 return -ENOMEM;
420
421 vic->config = of_device_get_match_data(dev);
422
423 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL);
424 if (!syncpts)
425 return -ENOMEM;
426
427 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 if (!regs) {
429 dev_err(&pdev->dev, "failed to get registers\n");
430 return -ENXIO;
431 }
432
433 vic->regs = devm_ioremap_resource(dev, regs);
434 if (IS_ERR(vic->regs))
435 return PTR_ERR(vic->regs);
436
437 vic->clk = devm_clk_get(dev, NULL);
438 if (IS_ERR(vic->clk)) {
439 dev_err(&pdev->dev, "failed to get clock\n");
440 return PTR_ERR(vic->clk);
441 }
442
443 if (!dev->pm_domain) {
444 vic->rst = devm_reset_control_get(dev, "vic");
445 if (IS_ERR(vic->rst)) {
446 dev_err(&pdev->dev, "failed to get reset\n");
447 return PTR_ERR(vic->rst);
448 }
449 }
450
451 vic->falcon.dev = dev;
452 vic->falcon.regs = vic->regs;
453
454 err = falcon_init(&vic->falcon);
455 if (err < 0)
456 return err;
457
458 platform_set_drvdata(pdev, vic);
459
460 INIT_LIST_HEAD(&vic->client.base.list);
461 vic->client.base.ops = &vic_client_ops;
462 vic->client.base.dev = dev;
463 vic->client.base.class = HOST1X_CLASS_VIC;
464 vic->client.base.syncpts = syncpts;
465 vic->client.base.num_syncpts = 1;
466 vic->dev = dev;
467
468 INIT_LIST_HEAD(&vic->client.list);
469 vic->client.version = vic->config->version;
470 vic->client.ops = &vic_ops;
471
472 err = host1x_client_register(&vic->client.base);
473 if (err < 0) {
474 dev_err(dev, "failed to register host1x client: %d\n", err);
475 goto exit_falcon;
476 }
477
478 pm_runtime_enable(&pdev->dev);
479 if (!pm_runtime_enabled(&pdev->dev)) {
480 err = vic_runtime_resume(&pdev->dev);
481 if (err < 0)
482 goto unregister_client;
483 }
484
485 return 0;
486
487 unregister_client:
488 host1x_client_unregister(&vic->client.base);
489 exit_falcon:
490 falcon_exit(&vic->falcon);
491
492 return err;
493 }
494
vic_remove(struct platform_device * pdev)495 static int vic_remove(struct platform_device *pdev)
496 {
497 struct vic *vic = platform_get_drvdata(pdev);
498 int err;
499
500 err = host1x_client_unregister(&vic->client.base);
501 if (err < 0) {
502 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
503 err);
504 return err;
505 }
506
507 if (pm_runtime_enabled(&pdev->dev))
508 pm_runtime_disable(&pdev->dev);
509 else
510 vic_runtime_suspend(&pdev->dev);
511
512 falcon_exit(&vic->falcon);
513
514 return 0;
515 }
516
517 static const struct dev_pm_ops vic_pm_ops = {
518 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL)
519 };
520
521 struct platform_driver tegra_vic_driver = {
522 .driver = {
523 .name = "tegra-vic",
524 .of_match_table = tegra_vic_of_match,
525 .pm = &vic_pm_ops
526 },
527 .probe = vic_probe,
528 .remove = vic_remove,
529 };
530
531 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
532 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE);
533 #endif
534 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
535 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE);
536 #endif
537 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
538 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE);
539 #endif
540 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
541 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE);
542 #endif
543