1 /*
2 * Copyright (C) 2014 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23
24 #define IDM_CTRL_DIRECT_OFFSET 0x00
25 #define CFG_OFFSET 0x00
26 #define CFG_RESET_SHIFT 31
27 #define CFG_EN_SHIFT 30
28 #define CFG_SLAVE_ADDR_0_SHIFT 28
29 #define CFG_M_RETRY_CNT_SHIFT 16
30 #define CFG_M_RETRY_CNT_MASK 0x0f
31
32 #define TIM_CFG_OFFSET 0x04
33 #define TIM_CFG_MODE_400_SHIFT 31
34 #define TIM_RAND_SLAVE_STRETCH_SHIFT 24
35 #define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
36 #define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
37 #define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
38
39 #define S_CFG_SMBUS_ADDR_OFFSET 0x08
40 #define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
41 #define S_CFG_NIC_SMB_ADDR3_SHIFT 24
42 #define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
43 #define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
44 #define S_CFG_NIC_SMB_ADDR2_SHIFT 16
45 #define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
46 #define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
47 #define S_CFG_NIC_SMB_ADDR1_SHIFT 8
48 #define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
49 #define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
50 #define S_CFG_NIC_SMB_ADDR0_SHIFT 0
51 #define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
52
53 #define M_FIFO_CTRL_OFFSET 0x0c
54 #define M_FIFO_RX_FLUSH_SHIFT 31
55 #define M_FIFO_TX_FLUSH_SHIFT 30
56 #define M_FIFO_RX_CNT_SHIFT 16
57 #define M_FIFO_RX_CNT_MASK 0x7f
58 #define M_FIFO_RX_THLD_SHIFT 8
59 #define M_FIFO_RX_THLD_MASK 0x3f
60
61 #define S_FIFO_CTRL_OFFSET 0x10
62 #define S_FIFO_RX_FLUSH_SHIFT 31
63 #define S_FIFO_TX_FLUSH_SHIFT 30
64 #define S_FIFO_RX_CNT_SHIFT 16
65 #define S_FIFO_RX_CNT_MASK 0x7f
66 #define S_FIFO_RX_THLD_SHIFT 8
67 #define S_FIFO_RX_THLD_MASK 0x3f
68
69 #define M_CMD_OFFSET 0x30
70 #define M_CMD_START_BUSY_SHIFT 31
71 #define M_CMD_STATUS_SHIFT 25
72 #define M_CMD_STATUS_MASK 0x07
73 #define M_CMD_STATUS_SUCCESS 0x0
74 #define M_CMD_STATUS_LOST_ARB 0x1
75 #define M_CMD_STATUS_NACK_ADDR 0x2
76 #define M_CMD_STATUS_NACK_DATA 0x3
77 #define M_CMD_STATUS_TIMEOUT 0x4
78 #define M_CMD_STATUS_FIFO_UNDERRUN 0x5
79 #define M_CMD_STATUS_RX_FIFO_FULL 0x6
80 #define M_CMD_PROTOCOL_SHIFT 9
81 #define M_CMD_PROTOCOL_MASK 0xf
82 #define M_CMD_PROTOCOL_QUICK 0x0
83 #define M_CMD_PROTOCOL_BLK_WR 0x7
84 #define M_CMD_PROTOCOL_BLK_RD 0x8
85 #define M_CMD_PROTOCOL_PROCESS 0xa
86 #define M_CMD_PEC_SHIFT 8
87 #define M_CMD_RD_CNT_SHIFT 0
88 #define M_CMD_RD_CNT_MASK 0xff
89
90 #define S_CMD_OFFSET 0x34
91 #define S_CMD_START_BUSY_SHIFT 31
92 #define S_CMD_STATUS_SHIFT 23
93 #define S_CMD_STATUS_MASK 0x07
94 #define S_CMD_STATUS_SUCCESS 0x0
95 #define S_CMD_STATUS_TIMEOUT 0x5
96 #define S_CMD_STATUS_MASTER_ABORT 0x7
97
98 #define IE_OFFSET 0x38
99 #define IE_M_RX_FIFO_FULL_SHIFT 31
100 #define IE_M_RX_THLD_SHIFT 30
101 #define IE_M_START_BUSY_SHIFT 28
102 #define IE_M_TX_UNDERRUN_SHIFT 27
103 #define IE_S_RX_FIFO_FULL_SHIFT 26
104 #define IE_S_RX_THLD_SHIFT 25
105 #define IE_S_RX_EVENT_SHIFT 24
106 #define IE_S_START_BUSY_SHIFT 23
107 #define IE_S_TX_UNDERRUN_SHIFT 22
108 #define IE_S_RD_EVENT_SHIFT 21
109
110 #define IS_OFFSET 0x3c
111 #define IS_M_RX_FIFO_FULL_SHIFT 31
112 #define IS_M_RX_THLD_SHIFT 30
113 #define IS_M_START_BUSY_SHIFT 28
114 #define IS_M_TX_UNDERRUN_SHIFT 27
115 #define IS_S_RX_FIFO_FULL_SHIFT 26
116 #define IS_S_RX_THLD_SHIFT 25
117 #define IS_S_RX_EVENT_SHIFT 24
118 #define IS_S_START_BUSY_SHIFT 23
119 #define IS_S_TX_UNDERRUN_SHIFT 22
120 #define IS_S_RD_EVENT_SHIFT 21
121
122 #define M_TX_OFFSET 0x40
123 #define M_TX_WR_STATUS_SHIFT 31
124 #define M_TX_DATA_SHIFT 0
125 #define M_TX_DATA_MASK 0xff
126
127 #define M_RX_OFFSET 0x44
128 #define M_RX_STATUS_SHIFT 30
129 #define M_RX_STATUS_MASK 0x03
130 #define M_RX_PEC_ERR_SHIFT 29
131 #define M_RX_DATA_SHIFT 0
132 #define M_RX_DATA_MASK 0xff
133
134 #define S_TX_OFFSET 0x48
135 #define S_TX_WR_STATUS_SHIFT 31
136 #define S_TX_DATA_SHIFT 0
137 #define S_TX_DATA_MASK 0xff
138
139 #define S_RX_OFFSET 0x4c
140 #define S_RX_STATUS_SHIFT 30
141 #define S_RX_STATUS_MASK 0x03
142 #define S_RX_PEC_ERR_SHIFT 29
143 #define S_RX_DATA_SHIFT 0
144 #define S_RX_DATA_MASK 0xff
145
146 #define I2C_TIMEOUT_MSEC 50000
147 #define M_TX_RX_FIFO_SIZE 64
148 #define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
149
150 #define M_RX_MAX_READ_LEN 255
151 #define M_RX_FIFO_THLD_VALUE 50
152
153 #define IE_M_ALL_INTERRUPT_SHIFT 27
154 #define IE_M_ALL_INTERRUPT_MASK 0x1e
155
156 #define SLAVE_READ_WRITE_BIT_MASK 0x1
157 #define SLAVE_READ_WRITE_BIT_SHIFT 0x1
158 #define SLAVE_MAX_SIZE_TRANSACTION 64
159 #define SLAVE_CLOCK_STRETCH_TIME 25
160
161 #define IE_S_ALL_INTERRUPT_SHIFT 21
162 #define IE_S_ALL_INTERRUPT_MASK 0x3f
163 /*
164 * It takes ~18us to reading 10bytes of data, hence to keep tasklet
165 * running for less time, max slave read per tasklet is set to 10 bytes.
166 */
167 #define MAX_SLAVE_RX_PER_INT 10
168
169 enum i2c_slave_read_status {
170 I2C_SLAVE_RX_FIFO_EMPTY = 0,
171 I2C_SLAVE_RX_START,
172 I2C_SLAVE_RX_DATA,
173 I2C_SLAVE_RX_END,
174 };
175
176 enum bus_speed_index {
177 I2C_SPD_100K = 0,
178 I2C_SPD_400K,
179 };
180
181 enum bcm_iproc_i2c_type {
182 IPROC_I2C,
183 IPROC_I2C_NIC
184 };
185
186 struct bcm_iproc_i2c_dev {
187 struct device *device;
188 enum bcm_iproc_i2c_type type;
189 int irq;
190
191 void __iomem *base;
192 void __iomem *idm_base;
193
194 u32 ape_addr_mask;
195
196 /* lock for indirect access through IDM */
197 spinlock_t idm_lock;
198
199 struct i2c_adapter adapter;
200 unsigned int bus_speed;
201
202 struct completion done;
203 int xfer_is_done;
204
205 struct i2c_msg *msg;
206
207 struct i2c_client *slave;
208
209 /* bytes that have been transferred */
210 unsigned int tx_bytes;
211 /* bytes that have been read */
212 unsigned int rx_bytes;
213 unsigned int thld_bytes;
214
215 bool slave_rx_only;
216 bool rx_start_rcvd;
217 bool slave_read_complete;
218 u32 tx_underrun;
219 u32 slave_int_mask;
220 struct tasklet_struct slave_rx_tasklet;
221 };
222
223 /* tasklet to process slave rx data */
224 static void slave_rx_tasklet_fn(unsigned long);
225
226 /*
227 * Can be expanded in the future if more interrupt status bits are utilized
228 */
229 #define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
230 | BIT(IS_M_RX_THLD_SHIFT))
231
232 #define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
233 | BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT)\
234 | BIT(IS_S_TX_UNDERRUN_SHIFT) | BIT(IS_S_RX_FIFO_FULL_SHIFT)\
235 | BIT(IS_S_RX_THLD_SHIFT))
236
237 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
238 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
239 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
240 bool enable);
241
iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset)242 static inline u32 iproc_i2c_rd_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
243 u32 offset)
244 {
245 u32 val;
246 unsigned long flags;
247
248 if (iproc_i2c->idm_base) {
249 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
250 writel(iproc_i2c->ape_addr_mask,
251 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
252 val = readl(iproc_i2c->base + offset);
253 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);
254 } else {
255 val = readl(iproc_i2c->base + offset);
256 }
257
258 return val;
259 }
260
iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev * iproc_i2c,u32 offset,u32 val)261 static inline void iproc_i2c_wr_reg(struct bcm_iproc_i2c_dev *iproc_i2c,
262 u32 offset, u32 val)
263 {
264 unsigned long flags;
265
266 if (iproc_i2c->idm_base) {
267 spin_lock_irqsave(&iproc_i2c->idm_lock, flags);
268 writel(iproc_i2c->ape_addr_mask,
269 iproc_i2c->idm_base + IDM_CTRL_DIRECT_OFFSET);
270 writel(val, iproc_i2c->base + offset);
271 spin_unlock_irqrestore(&iproc_i2c->idm_lock, flags);
272 } else {
273 writel(val, iproc_i2c->base + offset);
274 }
275 }
276
bcm_iproc_i2c_slave_init(struct bcm_iproc_i2c_dev * iproc_i2c,bool need_reset)277 static void bcm_iproc_i2c_slave_init(
278 struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
279 {
280 u32 val;
281
282 iproc_i2c->tx_underrun = 0;
283 if (need_reset) {
284 /* put controller in reset */
285 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
286 val |= BIT(CFG_RESET_SHIFT);
287 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
288
289 /* wait 100 usec per spec */
290 udelay(100);
291
292 /* bring controller out of reset */
293 val &= ~(BIT(CFG_RESET_SHIFT));
294 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
295 }
296
297 /* flush TX/RX FIFOs */
298 val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
299 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
300
301 /* Maximum slave stretch time */
302 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
303 val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
304 val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
305 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
306
307 /* Configure the slave address */
308 val = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
309 val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
310 val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
311 val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
312 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, val);
313
314 /* clear all pending slave interrupts */
315 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
316
317 /* Enable interrupt register to indicate a valid byte in receive fifo */
318 val = BIT(IE_S_RX_EVENT_SHIFT);
319 /* Enable interrupt register to indicate Slave Rx FIFO Full */
320 val |= BIT(IE_S_RX_FIFO_FULL_SHIFT);
321 /* Enable interrupt register to indicate a Master read transaction */
322 val |= BIT(IE_S_RD_EVENT_SHIFT);
323 /* Enable interrupt register for the Slave BUSY command */
324 val |= BIT(IE_S_START_BUSY_SHIFT);
325 iproc_i2c->slave_int_mask = val;
326 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
327 }
328
bcm_iproc_i2c_check_slave_status(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)329 static bool bcm_iproc_i2c_check_slave_status
330 (struct bcm_iproc_i2c_dev *iproc_i2c, u32 status)
331 {
332 u32 val;
333 bool recover = false;
334
335 /* check slave transmit status only if slave is transmitting */
336 if (!iproc_i2c->slave_rx_only) {
337 val = iproc_i2c_rd_reg(iproc_i2c, S_CMD_OFFSET);
338 /* status is valid only when START_BUSY is cleared */
339 if (!(val & BIT(S_CMD_START_BUSY_SHIFT))) {
340 val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
341 if (val == S_CMD_STATUS_TIMEOUT ||
342 val == S_CMD_STATUS_MASTER_ABORT) {
343 dev_warn(iproc_i2c->device,
344 (val == S_CMD_STATUS_TIMEOUT) ?
345 "slave random stretch time timeout\n" :
346 "Master aborted read transaction\n");
347 recover = true;
348 }
349 }
350 }
351
352 /* RX_EVENT is not valid when START_BUSY is set */
353 if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
354 (status & BIT(IS_S_START_BUSY_SHIFT))) {
355 dev_warn(iproc_i2c->device, "Slave aborted read transaction\n");
356 recover = true;
357 }
358
359 if (recover) {
360 /* re-initialize i2c for recovery */
361 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
362 bcm_iproc_i2c_slave_init(iproc_i2c, true);
363 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
364 }
365
366 return recover;
367 }
368
bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev * iproc_i2c)369 static void bcm_iproc_i2c_slave_read(struct bcm_iproc_i2c_dev *iproc_i2c)
370 {
371 u8 rx_data, rx_status;
372 u32 rx_bytes = 0;
373 u32 val;
374
375 while (rx_bytes < MAX_SLAVE_RX_PER_INT) {
376 val = iproc_i2c_rd_reg(iproc_i2c, S_RX_OFFSET);
377 rx_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
378 rx_data = ((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
379
380 if (rx_status == I2C_SLAVE_RX_START) {
381 /* Start of SMBUS Master write */
382 i2c_slave_event(iproc_i2c->slave,
383 I2C_SLAVE_WRITE_REQUESTED, &rx_data);
384 iproc_i2c->rx_start_rcvd = true;
385 iproc_i2c->slave_read_complete = false;
386 } else if (rx_status == I2C_SLAVE_RX_DATA &&
387 iproc_i2c->rx_start_rcvd) {
388 /* Middle of SMBUS Master write */
389 i2c_slave_event(iproc_i2c->slave,
390 I2C_SLAVE_WRITE_RECEIVED, &rx_data);
391 } else if (rx_status == I2C_SLAVE_RX_END &&
392 iproc_i2c->rx_start_rcvd) {
393 /* End of SMBUS Master write */
394 if (iproc_i2c->slave_rx_only)
395 i2c_slave_event(iproc_i2c->slave,
396 I2C_SLAVE_WRITE_RECEIVED,
397 &rx_data);
398
399 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
400 &rx_data);
401 } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
402 iproc_i2c->rx_start_rcvd = false;
403 iproc_i2c->slave_read_complete = true;
404 break;
405 }
406
407 rx_bytes++;
408 }
409 }
410
slave_rx_tasklet_fn(unsigned long data)411 static void slave_rx_tasklet_fn(unsigned long data)
412 {
413 struct bcm_iproc_i2c_dev *iproc_i2c = (struct bcm_iproc_i2c_dev *)data;
414 u32 int_clr;
415
416 bcm_iproc_i2c_slave_read(iproc_i2c);
417
418 /* clear pending IS_S_RX_EVENT_SHIFT interrupt */
419 int_clr = BIT(IS_S_RX_EVENT_SHIFT);
420
421 if (!iproc_i2c->slave_rx_only && iproc_i2c->slave_read_complete) {
422 /*
423 * In case of single byte master-read request,
424 * IS_S_TX_UNDERRUN_SHIFT event is generated before
425 * IS_S_START_BUSY_SHIFT event. Hence start slave data send
426 * from first IS_S_TX_UNDERRUN_SHIFT event.
427 *
428 * This means don't send any data from slave when
429 * IS_S_RD_EVENT_SHIFT event is generated else it will increment
430 * eeprom or other backend slave driver read pointer twice.
431 */
432 iproc_i2c->tx_underrun = 0;
433 iproc_i2c->slave_int_mask |= BIT(IE_S_TX_UNDERRUN_SHIFT);
434
435 /* clear IS_S_RD_EVENT_SHIFT interrupt */
436 int_clr |= BIT(IS_S_RD_EVENT_SHIFT);
437 }
438
439 /* clear slave interrupt */
440 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, int_clr);
441 /* enable slave interrupts */
442 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, iproc_i2c->slave_int_mask);
443 }
444
bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)445 static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
446 u32 status)
447 {
448 u32 val;
449 u8 value;
450
451
452 if (status & BIT(IS_S_TX_UNDERRUN_SHIFT)) {
453 iproc_i2c->tx_underrun++;
454 if (iproc_i2c->tx_underrun == 1)
455 /* Start of SMBUS for Master Read */
456 i2c_slave_event(iproc_i2c->slave,
457 I2C_SLAVE_READ_REQUESTED,
458 &value);
459 else
460 /* Master read other than start */
461 i2c_slave_event(iproc_i2c->slave,
462 I2C_SLAVE_READ_PROCESSED,
463 &value);
464
465 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
466 /* start transfer */
467 val = BIT(S_CMD_START_BUSY_SHIFT);
468 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
469
470 /* clear interrupt */
471 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
472 BIT(IS_S_TX_UNDERRUN_SHIFT));
473 }
474
475 /* Stop received from master in case of master read transaction */
476 if (status & BIT(IS_S_START_BUSY_SHIFT)) {
477 /*
478 * Disable interrupt for TX FIFO becomes empty and
479 * less than PKT_LENGTH bytes were output on the SMBUS
480 */
481 iproc_i2c->slave_int_mask &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
482 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
483 val &= ~BIT(IE_S_TX_UNDERRUN_SHIFT);
484 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
485
486 /* End of SMBUS for Master Read */
487 val = BIT(S_TX_WR_STATUS_SHIFT);
488 iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, val);
489
490 val = BIT(S_CMD_START_BUSY_SHIFT);
491 iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
492
493 /* flush TX FIFOs */
494 val = iproc_i2c_rd_reg(iproc_i2c, S_FIFO_CTRL_OFFSET);
495 val |= (BIT(S_FIFO_TX_FLUSH_SHIFT));
496 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, val);
497
498 i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
499
500 /* clear interrupt */
501 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
502 BIT(IS_S_START_BUSY_SHIFT));
503 }
504
505 /* if the controller has been reset, immediately return from the ISR */
506 if (bcm_iproc_i2c_check_slave_status(iproc_i2c, status))
507 return true;
508
509 /*
510 * Slave events in case of master-write, master-write-read and,
511 * master-read
512 *
513 * Master-write : only IS_S_RX_EVENT_SHIFT event
514 * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
515 * events
516 * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
517 * events or only IS_S_RD_EVENT_SHIFT
518 *
519 * iproc has a slave rx fifo size of 64 bytes. Rx fifo full interrupt
520 * (IS_S_RX_FIFO_FULL_SHIFT) will be generated when RX fifo becomes
521 * full. This can happen if Master issues write requests of more than
522 * 64 bytes.
523 */
524 if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
525 status & BIT(IS_S_RD_EVENT_SHIFT) ||
526 status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
527 /* disable slave interrupts */
528 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
529 val &= ~iproc_i2c->slave_int_mask;
530 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
531
532 if (status & BIT(IS_S_RD_EVENT_SHIFT))
533 /* Master-write-read request */
534 iproc_i2c->slave_rx_only = false;
535 else
536 /* Master-write request only */
537 iproc_i2c->slave_rx_only = true;
538
539 /* schedule tasklet to read data later */
540 tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
541
542 /* clear IS_S_RX_FIFO_FULL_SHIFT interrupt */
543 if (status & BIT(IS_S_RX_FIFO_FULL_SHIFT)) {
544 val = BIT(IS_S_RX_FIFO_FULL_SHIFT);
545 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, val);
546 }
547 }
548
549 return true;
550 }
551
bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev * iproc_i2c)552 static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
553 {
554 struct i2c_msg *msg = iproc_i2c->msg;
555 uint32_t val;
556
557 /* Read valid data from RX FIFO */
558 while (iproc_i2c->rx_bytes < msg->len) {
559 val = iproc_i2c_rd_reg(iproc_i2c, M_RX_OFFSET);
560
561 /* rx fifo empty */
562 if (!((val >> M_RX_STATUS_SHIFT) & M_RX_STATUS_MASK))
563 break;
564
565 msg->buf[iproc_i2c->rx_bytes] =
566 (val >> M_RX_DATA_SHIFT) & M_RX_DATA_MASK;
567 iproc_i2c->rx_bytes++;
568 }
569 }
570
bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev * iproc_i2c)571 static void bcm_iproc_i2c_send(struct bcm_iproc_i2c_dev *iproc_i2c)
572 {
573 struct i2c_msg *msg = iproc_i2c->msg;
574 unsigned int tx_bytes = msg->len - iproc_i2c->tx_bytes;
575 unsigned int i;
576 u32 val;
577
578 /* can only fill up to the FIFO size */
579 tx_bytes = min_t(unsigned int, tx_bytes, M_TX_RX_FIFO_SIZE);
580 for (i = 0; i < tx_bytes; i++) {
581 /* start from where we left over */
582 unsigned int idx = iproc_i2c->tx_bytes + i;
583
584 val = msg->buf[idx];
585
586 /* mark the last byte */
587 if (idx == msg->len - 1) {
588 val |= BIT(M_TX_WR_STATUS_SHIFT);
589
590 if (iproc_i2c->irq) {
591 u32 tmp;
592
593 /*
594 * Since this is the last byte, we should now
595 * disable TX FIFO underrun interrupt
596 */
597 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
598 tmp &= ~BIT(IE_M_TX_UNDERRUN_SHIFT);
599 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET,
600 tmp);
601 }
602 }
603
604 /* load data into TX FIFO */
605 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
606 }
607
608 /* update number of transferred bytes */
609 iproc_i2c->tx_bytes += tx_bytes;
610 }
611
bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev * iproc_i2c)612 static void bcm_iproc_i2c_read(struct bcm_iproc_i2c_dev *iproc_i2c)
613 {
614 struct i2c_msg *msg = iproc_i2c->msg;
615 u32 bytes_left, val;
616
617 bcm_iproc_i2c_read_valid_bytes(iproc_i2c);
618 bytes_left = msg->len - iproc_i2c->rx_bytes;
619 if (bytes_left == 0) {
620 if (iproc_i2c->irq) {
621 /* finished reading all data, disable rx thld event */
622 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
623 val &= ~BIT(IS_M_RX_THLD_SHIFT);
624 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
625 }
626 } else if (bytes_left < iproc_i2c->thld_bytes) {
627 /* set bytes left as threshold */
628 val = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
629 val &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
630 val |= (bytes_left << M_FIFO_RX_THLD_SHIFT);
631 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
632 iproc_i2c->thld_bytes = bytes_left;
633 }
634 /*
635 * bytes_left >= iproc_i2c->thld_bytes,
636 * hence no need to change the THRESHOLD SET.
637 * It will remain as iproc_i2c->thld_bytes itself
638 */
639 }
640
bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev * iproc_i2c,u32 status)641 static void bcm_iproc_i2c_process_m_event(struct bcm_iproc_i2c_dev *iproc_i2c,
642 u32 status)
643 {
644 /* TX FIFO is empty and we have more data to send */
645 if (status & BIT(IS_M_TX_UNDERRUN_SHIFT))
646 bcm_iproc_i2c_send(iproc_i2c);
647
648 /* RX FIFO threshold is reached and data needs to be read out */
649 if (status & BIT(IS_M_RX_THLD_SHIFT))
650 bcm_iproc_i2c_read(iproc_i2c);
651
652 /* transfer is done */
653 if (status & BIT(IS_M_START_BUSY_SHIFT)) {
654 iproc_i2c->xfer_is_done = 1;
655 if (iproc_i2c->irq)
656 complete(&iproc_i2c->done);
657 }
658 }
659
bcm_iproc_i2c_isr(int irq,void * data)660 static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
661 {
662 struct bcm_iproc_i2c_dev *iproc_i2c = data;
663 u32 slave_status;
664 u32 status;
665 bool ret;
666
667 status = iproc_i2c_rd_reg(iproc_i2c, IS_OFFSET);
668 /* process only slave interrupt which are enabled */
669 slave_status = status & iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET) &
670 ISR_MASK_SLAVE;
671
672 if (slave_status) {
673 ret = bcm_iproc_i2c_slave_isr(iproc_i2c, slave_status);
674 if (ret)
675 return IRQ_HANDLED;
676 else
677 return IRQ_NONE;
678 }
679
680 status &= ISR_MASK;
681 if (!status)
682 return IRQ_NONE;
683
684 /* process all master based events */
685 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
686 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
687
688 return IRQ_HANDLED;
689 }
690
bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev * iproc_i2c)691 static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
692 {
693 u32 val;
694
695 /* put controller in reset */
696 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
697 val |= BIT(CFG_RESET_SHIFT);
698 val &= ~(BIT(CFG_EN_SHIFT));
699 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
700
701 /* wait 100 usec per spec */
702 udelay(100);
703
704 /* bring controller out of reset */
705 val &= ~(BIT(CFG_RESET_SHIFT));
706 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
707
708 /* flush TX/RX FIFOs and set RX FIFO threshold to zero */
709 val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
710 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
711 /* disable all interrupts */
712 val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
713 val &= ~(IE_M_ALL_INTERRUPT_MASK <<
714 IE_M_ALL_INTERRUPT_SHIFT);
715 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
716
717 /* clear all pending interrupts */
718 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, 0xffffffff);
719
720 return 0;
721 }
722
bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev * iproc_i2c,bool enable)723 static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
724 bool enable)
725 {
726 u32 val;
727
728 val = iproc_i2c_rd_reg(iproc_i2c, CFG_OFFSET);
729 if (enable)
730 val |= BIT(CFG_EN_SHIFT);
731 else
732 val &= ~BIT(CFG_EN_SHIFT);
733 iproc_i2c_wr_reg(iproc_i2c, CFG_OFFSET, val);
734 }
735
bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg)736 static int bcm_iproc_i2c_check_status(struct bcm_iproc_i2c_dev *iproc_i2c,
737 struct i2c_msg *msg)
738 {
739 u32 val;
740
741 val = iproc_i2c_rd_reg(iproc_i2c, M_CMD_OFFSET);
742 val = (val >> M_CMD_STATUS_SHIFT) & M_CMD_STATUS_MASK;
743
744 switch (val) {
745 case M_CMD_STATUS_SUCCESS:
746 return 0;
747
748 case M_CMD_STATUS_LOST_ARB:
749 dev_dbg(iproc_i2c->device, "lost bus arbitration\n");
750 return -EAGAIN;
751
752 case M_CMD_STATUS_NACK_ADDR:
753 dev_dbg(iproc_i2c->device, "NAK addr:0x%02x\n", msg->addr);
754 return -ENXIO;
755
756 case M_CMD_STATUS_NACK_DATA:
757 dev_dbg(iproc_i2c->device, "NAK data\n");
758 return -ENXIO;
759
760 case M_CMD_STATUS_TIMEOUT:
761 dev_dbg(iproc_i2c->device, "bus timeout\n");
762 return -ETIMEDOUT;
763
764 case M_CMD_STATUS_FIFO_UNDERRUN:
765 dev_dbg(iproc_i2c->device, "FIFO under-run\n");
766 return -ENXIO;
767
768 case M_CMD_STATUS_RX_FIFO_FULL:
769 dev_dbg(iproc_i2c->device, "RX FIFO full\n");
770 return -ETIMEDOUT;
771
772 default:
773 dev_dbg(iproc_i2c->device, "unknown error code=%d\n", val);
774
775 /* re-initialize i2c for recovery */
776 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
777 bcm_iproc_i2c_init(iproc_i2c);
778 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
779
780 return -EIO;
781 }
782 }
783
bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msg,u32 cmd)784 static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c,
785 struct i2c_msg *msg,
786 u32 cmd)
787 {
788 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT_MSEC);
789 u32 val, status;
790 int ret;
791
792 iproc_i2c_wr_reg(iproc_i2c, M_CMD_OFFSET, cmd);
793
794 if (iproc_i2c->irq) {
795 time_left = wait_for_completion_timeout(&iproc_i2c->done,
796 time_left);
797 /* disable all interrupts */
798 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
799 /* read it back to flush the write */
800 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
801 /* make sure the interrupt handler isn't running */
802 synchronize_irq(iproc_i2c->irq);
803
804 } else { /* polling mode */
805 unsigned long timeout = jiffies + time_left;
806
807 do {
808 status = iproc_i2c_rd_reg(iproc_i2c,
809 IS_OFFSET) & ISR_MASK;
810 bcm_iproc_i2c_process_m_event(iproc_i2c, status);
811 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, status);
812
813 if (time_after(jiffies, timeout)) {
814 time_left = 0;
815 break;
816 }
817
818 cpu_relax();
819 cond_resched();
820 } while (!iproc_i2c->xfer_is_done);
821 }
822
823 if (!time_left && !iproc_i2c->xfer_is_done) {
824 dev_err(iproc_i2c->device, "transaction timed out\n");
825
826 /* flush both TX/RX FIFOs */
827 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
828 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
829 return -ETIMEDOUT;
830 }
831
832 ret = bcm_iproc_i2c_check_status(iproc_i2c, msg);
833 if (ret) {
834 /* flush both TX/RX FIFOs */
835 val = BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT);
836 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, val);
837 return ret;
838 }
839
840 return 0;
841 }
842
843 /*
844 * If 'process_call' is true, then this is a multi-msg transfer that requires
845 * a repeated start between the messages.
846 * More specifically, it must be a write (reg) followed by a read (data).
847 * The i2c quirks are set to enforce this rule.
848 */
bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev * iproc_i2c,struct i2c_msg * msgs,bool process_call)849 static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c,
850 struct i2c_msg *msgs, bool process_call)
851 {
852 int i;
853 u8 addr;
854 u32 val, tmp, val_intr_en;
855 unsigned int tx_bytes;
856 struct i2c_msg *msg = &msgs[0];
857
858 /* check if bus is busy */
859 if (!!(iproc_i2c_rd_reg(iproc_i2c,
860 M_CMD_OFFSET) & BIT(M_CMD_START_BUSY_SHIFT))) {
861 dev_warn(iproc_i2c->device, "bus is busy\n");
862 return -EBUSY;
863 }
864
865 iproc_i2c->msg = msg;
866
867 /* format and load slave address into the TX FIFO */
868 addr = i2c_8bit_addr_from_msg(msg);
869 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, addr);
870
871 /*
872 * For a write transaction, load data into the TX FIFO. Only allow
873 * loading up to TX FIFO size - 1 bytes of data since the first byte
874 * has been used up by the slave address
875 */
876 tx_bytes = min_t(unsigned int, msg->len, M_TX_RX_FIFO_SIZE - 1);
877 if (!(msg->flags & I2C_M_RD)) {
878 for (i = 0; i < tx_bytes; i++) {
879 val = msg->buf[i];
880
881 /* mark the last byte */
882 if (!process_call && (i == msg->len - 1))
883 val |= BIT(M_TX_WR_STATUS_SHIFT);
884
885 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
886 }
887 iproc_i2c->tx_bytes = tx_bytes;
888 }
889
890 /* Process the read message if this is process call */
891 if (process_call) {
892 msg++;
893 iproc_i2c->msg = msg; /* point to second msg */
894
895 /*
896 * The last byte to be sent out should be a slave
897 * address with read operation
898 */
899 addr = i2c_8bit_addr_from_msg(msg);
900 /* mark it the last byte out */
901 val = addr | BIT(M_TX_WR_STATUS_SHIFT);
902 iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val);
903 }
904
905 /* mark as incomplete before starting the transaction */
906 if (iproc_i2c->irq)
907 reinit_completion(&iproc_i2c->done);
908
909 iproc_i2c->xfer_is_done = 0;
910
911 /*
912 * Enable the "start busy" interrupt, which will be triggered after the
913 * transaction is done, i.e., the internal start_busy bit, transitions
914 * from 1 to 0.
915 */
916 val_intr_en = BIT(IE_M_START_BUSY_SHIFT);
917
918 /*
919 * If TX data size is larger than the TX FIFO, need to enable TX
920 * underrun interrupt, which will be triggerred when the TX FIFO is
921 * empty. When that happens we can then pump more data into the FIFO
922 */
923 if (!process_call && !(msg->flags & I2C_M_RD) &&
924 msg->len > iproc_i2c->tx_bytes)
925 val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT);
926
927 /*
928 * Now we can activate the transfer. For a read operation, specify the
929 * number of bytes to read
930 */
931 val = BIT(M_CMD_START_BUSY_SHIFT);
932
933 if (msg->len == 0) {
934 /* SMBUS QUICK Command (Read/Write) */
935 val |= (M_CMD_PROTOCOL_QUICK << M_CMD_PROTOCOL_SHIFT);
936 } else if (msg->flags & I2C_M_RD) {
937 u32 protocol;
938
939 iproc_i2c->rx_bytes = 0;
940 if (msg->len > M_RX_FIFO_MAX_THLD_VALUE)
941 iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE;
942 else
943 iproc_i2c->thld_bytes = msg->len;
944
945 /* set threshold value */
946 tmp = iproc_i2c_rd_reg(iproc_i2c, M_FIFO_CTRL_OFFSET);
947 tmp &= ~(M_FIFO_RX_THLD_MASK << M_FIFO_RX_THLD_SHIFT);
948 tmp |= iproc_i2c->thld_bytes << M_FIFO_RX_THLD_SHIFT;
949 iproc_i2c_wr_reg(iproc_i2c, M_FIFO_CTRL_OFFSET, tmp);
950
951 /* enable the RX threshold interrupt */
952 val_intr_en |= BIT(IE_M_RX_THLD_SHIFT);
953
954 protocol = process_call ?
955 M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD;
956
957 val |= (protocol << M_CMD_PROTOCOL_SHIFT) |
958 (msg->len << M_CMD_RD_CNT_SHIFT);
959 } else {
960 val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT);
961 }
962
963 if (iproc_i2c->irq)
964 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val_intr_en);
965
966 return bcm_iproc_i2c_xfer_wait(iproc_i2c, msg, val);
967 }
968
bcm_iproc_i2c_xfer(struct i2c_adapter * adapter,struct i2c_msg msgs[],int num)969 static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
970 struct i2c_msg msgs[], int num)
971 {
972 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter);
973 bool process_call = false;
974 int ret;
975
976 if (num == 2) {
977 /* Repeated start, use process call */
978 process_call = true;
979 if (msgs[1].flags & I2C_M_NOSTART) {
980 dev_err(iproc_i2c->device, "Invalid repeated start\n");
981 return -EOPNOTSUPP;
982 }
983 }
984
985 ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call);
986 if (ret) {
987 dev_dbg(iproc_i2c->device, "xfer failed\n");
988 return ret;
989 }
990
991 return num;
992 }
993
bcm_iproc_i2c_functionality(struct i2c_adapter * adap)994 static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
995 {
996 u32 val;
997
998 val = I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
999
1000 if (adap->algo->reg_slave)
1001 val |= I2C_FUNC_SLAVE;
1002
1003 return val;
1004 }
1005
1006 static struct i2c_algorithm bcm_iproc_algo = {
1007 .master_xfer = bcm_iproc_i2c_xfer,
1008 .functionality = bcm_iproc_i2c_functionality,
1009 .reg_slave = bcm_iproc_i2c_reg_slave,
1010 .unreg_slave = bcm_iproc_i2c_unreg_slave,
1011 };
1012
1013 static const struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
1014 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
1015 .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE,
1016 .max_read_len = M_RX_MAX_READ_LEN,
1017 };
1018
bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev * iproc_i2c)1019 static int bcm_iproc_i2c_cfg_speed(struct bcm_iproc_i2c_dev *iproc_i2c)
1020 {
1021 unsigned int bus_speed;
1022 u32 val;
1023 int ret = of_property_read_u32(iproc_i2c->device->of_node,
1024 "clock-frequency", &bus_speed);
1025 if (ret < 0) {
1026 dev_info(iproc_i2c->device,
1027 "unable to interpret clock-frequency DT property\n");
1028 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1029 }
1030
1031 if (bus_speed < I2C_MAX_STANDARD_MODE_FREQ) {
1032 dev_err(iproc_i2c->device, "%d Hz bus speed not supported\n",
1033 bus_speed);
1034 dev_err(iproc_i2c->device,
1035 "valid speeds are 100khz and 400khz\n");
1036 return -EINVAL;
1037 } else if (bus_speed < I2C_MAX_FAST_MODE_FREQ) {
1038 bus_speed = I2C_MAX_STANDARD_MODE_FREQ;
1039 } else {
1040 bus_speed = I2C_MAX_FAST_MODE_FREQ;
1041 }
1042
1043 iproc_i2c->bus_speed = bus_speed;
1044 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1045 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1046 val |= (bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1047 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1048
1049 dev_info(iproc_i2c->device, "bus set to %u Hz\n", bus_speed);
1050
1051 return 0;
1052 }
1053
bcm_iproc_i2c_probe(struct platform_device * pdev)1054 static int bcm_iproc_i2c_probe(struct platform_device *pdev)
1055 {
1056 int irq, ret = 0;
1057 struct bcm_iproc_i2c_dev *iproc_i2c;
1058 struct i2c_adapter *adap;
1059 struct resource *res;
1060
1061 iproc_i2c = devm_kzalloc(&pdev->dev, sizeof(*iproc_i2c),
1062 GFP_KERNEL);
1063 if (!iproc_i2c)
1064 return -ENOMEM;
1065
1066 platform_set_drvdata(pdev, iproc_i2c);
1067 iproc_i2c->device = &pdev->dev;
1068 iproc_i2c->type =
1069 (enum bcm_iproc_i2c_type)of_device_get_match_data(&pdev->dev);
1070 init_completion(&iproc_i2c->done);
1071
1072 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1073 iproc_i2c->base = devm_ioremap_resource(iproc_i2c->device, res);
1074 if (IS_ERR(iproc_i2c->base))
1075 return PTR_ERR(iproc_i2c->base);
1076
1077 if (iproc_i2c->type == IPROC_I2C_NIC) {
1078 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1079 iproc_i2c->idm_base = devm_ioremap_resource(iproc_i2c->device,
1080 res);
1081 if (IS_ERR(iproc_i2c->idm_base))
1082 return PTR_ERR(iproc_i2c->idm_base);
1083
1084 ret = of_property_read_u32(iproc_i2c->device->of_node,
1085 "brcm,ape-hsls-addr-mask",
1086 &iproc_i2c->ape_addr_mask);
1087 if (ret < 0) {
1088 dev_err(iproc_i2c->device,
1089 "'brcm,ape-hsls-addr-mask' missing\n");
1090 return -EINVAL;
1091 }
1092
1093 spin_lock_init(&iproc_i2c->idm_lock);
1094
1095 /* no slave support */
1096 bcm_iproc_algo.reg_slave = NULL;
1097 bcm_iproc_algo.unreg_slave = NULL;
1098 }
1099
1100 ret = bcm_iproc_i2c_init(iproc_i2c);
1101 if (ret)
1102 return ret;
1103
1104 ret = bcm_iproc_i2c_cfg_speed(iproc_i2c);
1105 if (ret)
1106 return ret;
1107
1108 irq = platform_get_irq(pdev, 0);
1109 if (irq > 0) {
1110 ret = devm_request_irq(iproc_i2c->device, irq,
1111 bcm_iproc_i2c_isr, 0, pdev->name,
1112 iproc_i2c);
1113 if (ret < 0) {
1114 dev_err(iproc_i2c->device,
1115 "unable to request irq %i\n", irq);
1116 return ret;
1117 }
1118
1119 iproc_i2c->irq = irq;
1120 } else {
1121 dev_warn(iproc_i2c->device,
1122 "no irq resource, falling back to poll mode\n");
1123 }
1124
1125 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1126
1127 adap = &iproc_i2c->adapter;
1128 i2c_set_adapdata(adap, iproc_i2c);
1129 snprintf(adap->name, sizeof(adap->name),
1130 "Broadcom iProc (%s)",
1131 of_node_full_name(iproc_i2c->device->of_node));
1132 adap->algo = &bcm_iproc_algo;
1133 adap->quirks = &bcm_iproc_i2c_quirks;
1134 adap->dev.parent = &pdev->dev;
1135 adap->dev.of_node = pdev->dev.of_node;
1136
1137 return i2c_add_adapter(adap);
1138 }
1139
bcm_iproc_i2c_remove(struct platform_device * pdev)1140 static int bcm_iproc_i2c_remove(struct platform_device *pdev)
1141 {
1142 struct bcm_iproc_i2c_dev *iproc_i2c = platform_get_drvdata(pdev);
1143
1144 if (iproc_i2c->irq) {
1145 /*
1146 * Make sure there's no pending interrupt when we remove the
1147 * adapter
1148 */
1149 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1150 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1151 synchronize_irq(iproc_i2c->irq);
1152 }
1153
1154 i2c_del_adapter(&iproc_i2c->adapter);
1155 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1156
1157 return 0;
1158 }
1159
1160 #ifdef CONFIG_PM_SLEEP
1161
bcm_iproc_i2c_suspend(struct device * dev)1162 static int bcm_iproc_i2c_suspend(struct device *dev)
1163 {
1164 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1165
1166 if (iproc_i2c->irq) {
1167 /*
1168 * Make sure there's no pending interrupt when we go into
1169 * suspend
1170 */
1171 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, 0);
1172 iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1173 synchronize_irq(iproc_i2c->irq);
1174 }
1175
1176 /* now disable the controller */
1177 bcm_iproc_i2c_enable_disable(iproc_i2c, false);
1178
1179 return 0;
1180 }
1181
bcm_iproc_i2c_resume(struct device * dev)1182 static int bcm_iproc_i2c_resume(struct device *dev)
1183 {
1184 struct bcm_iproc_i2c_dev *iproc_i2c = dev_get_drvdata(dev);
1185 int ret;
1186 u32 val;
1187
1188 /*
1189 * Power domain could have been shut off completely in system deep
1190 * sleep, so re-initialize the block here
1191 */
1192 ret = bcm_iproc_i2c_init(iproc_i2c);
1193 if (ret)
1194 return ret;
1195
1196 /* configure to the desired bus speed */
1197 val = iproc_i2c_rd_reg(iproc_i2c, TIM_CFG_OFFSET);
1198 val &= ~BIT(TIM_CFG_MODE_400_SHIFT);
1199 val |= (iproc_i2c->bus_speed == I2C_MAX_FAST_MODE_FREQ) << TIM_CFG_MODE_400_SHIFT;
1200 iproc_i2c_wr_reg(iproc_i2c, TIM_CFG_OFFSET, val);
1201
1202 bcm_iproc_i2c_enable_disable(iproc_i2c, true);
1203
1204 return 0;
1205 }
1206
1207 static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
1208 .suspend_late = &bcm_iproc_i2c_suspend,
1209 .resume_early = &bcm_iproc_i2c_resume
1210 };
1211
1212 #define BCM_IPROC_I2C_PM_OPS (&bcm_iproc_i2c_pm_ops)
1213 #else
1214 #define BCM_IPROC_I2C_PM_OPS NULL
1215 #endif /* CONFIG_PM_SLEEP */
1216
1217
bcm_iproc_i2c_reg_slave(struct i2c_client * slave)1218 static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
1219 {
1220 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1221
1222 if (iproc_i2c->slave)
1223 return -EBUSY;
1224
1225 if (slave->flags & I2C_CLIENT_TEN)
1226 return -EAFNOSUPPORT;
1227
1228 iproc_i2c->slave = slave;
1229
1230 tasklet_init(&iproc_i2c->slave_rx_tasklet, slave_rx_tasklet_fn,
1231 (unsigned long)iproc_i2c);
1232
1233 bcm_iproc_i2c_slave_init(iproc_i2c, false);
1234 return 0;
1235 }
1236
bcm_iproc_i2c_unreg_slave(struct i2c_client * slave)1237 static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
1238 {
1239 u32 tmp;
1240 struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
1241
1242 if (!iproc_i2c->slave)
1243 return -EINVAL;
1244
1245 disable_irq(iproc_i2c->irq);
1246
1247 tasklet_kill(&iproc_i2c->slave_rx_tasklet);
1248
1249 /* disable all slave interrupts */
1250 tmp = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
1251 tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
1252 IE_S_ALL_INTERRUPT_SHIFT);
1253 iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, tmp);
1254
1255 /* Erase the slave address programmed */
1256 tmp = iproc_i2c_rd_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET);
1257 tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
1258 iproc_i2c_wr_reg(iproc_i2c, S_CFG_SMBUS_ADDR_OFFSET, tmp);
1259
1260 /* flush TX/RX FIFOs */
1261 tmp = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
1262 iproc_i2c_wr_reg(iproc_i2c, S_FIFO_CTRL_OFFSET, tmp);
1263
1264 /* clear all pending slave interrupts */
1265 iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET, ISR_MASK_SLAVE);
1266
1267 iproc_i2c->slave = NULL;
1268
1269 enable_irq(iproc_i2c->irq);
1270
1271 return 0;
1272 }
1273
1274 static const struct of_device_id bcm_iproc_i2c_of_match[] = {
1275 {
1276 .compatible = "brcm,iproc-i2c",
1277 .data = (int *)IPROC_I2C,
1278 }, {
1279 .compatible = "brcm,iproc-nic-i2c",
1280 .data = (int *)IPROC_I2C_NIC,
1281 },
1282 { /* sentinel */ }
1283 };
1284 MODULE_DEVICE_TABLE(of, bcm_iproc_i2c_of_match);
1285
1286 static struct platform_driver bcm_iproc_i2c_driver = {
1287 .driver = {
1288 .name = "bcm-iproc-i2c",
1289 .of_match_table = bcm_iproc_i2c_of_match,
1290 .pm = BCM_IPROC_I2C_PM_OPS,
1291 },
1292 .probe = bcm_iproc_i2c_probe,
1293 .remove = bcm_iproc_i2c_remove,
1294 };
1295 module_platform_driver(bcm_iproc_i2c_driver);
1296
1297 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1298 MODULE_DESCRIPTION("Broadcom iProc I2C Driver");
1299 MODULE_LICENSE("GPL v2");
1300