1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 <mdsxyz123@yahoo.com>
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
7 Copyright (C) 2010 Intel Corporation,
8 David Woodhouse <dwmw2@infradead.org>
9
10 */
11
12 /*
13 * Supports the following Intel I/O Controller Hubs (ICH):
14 *
15 * I/O Block I2C
16 * region SMBus Block proc. block
17 * Chip name PCI ID size PEC buffer call read
18 * ---------------------------------------------------------------------------
19 * 82801AA (ICH) 0x2413 16 no no no no
20 * 82801AB (ICH0) 0x2423 16 no no no no
21 * 82801BA (ICH2) 0x2443 16 no no no no
22 * 82801CA (ICH3) 0x2483 32 soft no no no
23 * 82801DB (ICH4) 0x24c3 32 hard yes no no
24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
25 * 6300ESB 0x25a4 32 hard yes yes yes
26 * 82801F (ICH6) 0x266a 32 hard yes yes yes
27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
28 * 82801G (ICH7) 0x27da 32 hard yes yes yes
29 * 82801H (ICH8) 0x283e 32 hard yes yes yes
30 * 82801I (ICH9) 0x2930 32 hard yes yes yes
31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
32 * ICH10 0x3a30 32 hard yes yes yes
33 * ICH10 0x3a60 32 hard yes yes yes
34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
53 * Braswell (SOC) 0x2292 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
56 * DNV (SOC) 0x19df 32 hard yes yes yes
57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes
58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes
59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes
60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes
63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes
64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes
65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes
66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes
67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes
68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes
69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes
70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes
71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes
72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes
73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes
74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes
75 * Alder Lake-P (PCH) 0x51a3 32 hard yes yes yes
76 * Alder Lake-M (PCH) 0x54a3 32 hard yes yes yes
77 *
78 * Features supported by this driver:
79 * Software PEC no
80 * Hardware PEC yes
81 * Block buffer yes
82 * Block process call transaction yes
83 * I2C block read transaction yes (doesn't use the block buffer)
84 * Slave mode no
85 * SMBus Host Notify yes
86 * Interrupt processing yes
87 *
88 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
89 */
90
91 #define DRV_NAME "i801_smbus"
92
93 #include <linux/interrupt.h>
94 #include <linux/module.h>
95 #include <linux/pci.h>
96 #include <linux/kernel.h>
97 #include <linux/stddef.h>
98 #include <linux/delay.h>
99 #include <linux/ioport.h>
100 #include <linux/init.h>
101 #include <linux/i2c.h>
102 #include <linux/i2c-smbus.h>
103 #include <linux/acpi.h>
104 #include <linux/io.h>
105 #include <linux/dmi.h>
106 #include <linux/slab.h>
107 #include <linux/string.h>
108 #include <linux/completion.h>
109 #include <linux/err.h>
110 #include <linux/platform_device.h>
111 #include <linux/platform_data/itco_wdt.h>
112 #include <linux/pm_runtime.h>
113 #include <linux/mutex.h>
114
115 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
116 #include <linux/gpio/machine.h>
117 #include <linux/platform_data/i2c-mux-gpio.h>
118 #endif
119
120 /* I801 SMBus address offsets */
121 #define SMBHSTSTS(p) (0 + (p)->smba)
122 #define SMBHSTCNT(p) (2 + (p)->smba)
123 #define SMBHSTCMD(p) (3 + (p)->smba)
124 #define SMBHSTADD(p) (4 + (p)->smba)
125 #define SMBHSTDAT0(p) (5 + (p)->smba)
126 #define SMBHSTDAT1(p) (6 + (p)->smba)
127 #define SMBBLKDAT(p) (7 + (p)->smba)
128 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
129 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
130 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
131 #define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */
132 #define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */
133 #define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */
134
135 /* PCI Address Constants */
136 #define SMBBAR 4
137 #define SMBHSTCFG 0x040
138 #define TCOBASE 0x050
139 #define TCOCTL 0x054
140
141 #define SBREG_BAR 0x10
142 #define SBREG_SMBCTRL 0xc6000c
143 #define SBREG_SMBCTRL_DNV 0xcf000c
144
145 /* Host configuration bits for SMBHSTCFG */
146 #define SMBHSTCFG_HST_EN BIT(0)
147 #define SMBHSTCFG_SMB_SMI_EN BIT(1)
148 #define SMBHSTCFG_I2C_EN BIT(2)
149 #define SMBHSTCFG_SPD_WD BIT(4)
150
151 /* TCO configuration bits for TCOCTL */
152 #define TCOCTL_EN BIT(8)
153
154 /* Auxiliary status register bits, ICH4+ only */
155 #define SMBAUXSTS_CRCE BIT(0)
156 #define SMBAUXSTS_STCO BIT(1)
157
158 /* Auxiliary control register bits, ICH4+ only */
159 #define SMBAUXCTL_CRC BIT(0)
160 #define SMBAUXCTL_E32B BIT(1)
161
162 /* I801 command constants */
163 #define I801_QUICK 0x00
164 #define I801_BYTE 0x04
165 #define I801_BYTE_DATA 0x08
166 #define I801_WORD_DATA 0x0C
167 #define I801_PROC_CALL 0x10 /* unimplemented */
168 #define I801_BLOCK_DATA 0x14
169 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
170 #define I801_BLOCK_PROC_CALL 0x1C
171
172 /* I801 Host Control register bits */
173 #define SMBHSTCNT_INTREN BIT(0)
174 #define SMBHSTCNT_KILL BIT(1)
175 #define SMBHSTCNT_LAST_BYTE BIT(5)
176 #define SMBHSTCNT_START BIT(6)
177 #define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */
178
179 /* I801 Hosts Status register bits */
180 #define SMBHSTSTS_BYTE_DONE BIT(7)
181 #define SMBHSTSTS_INUSE_STS BIT(6)
182 #define SMBHSTSTS_SMBALERT_STS BIT(5)
183 #define SMBHSTSTS_FAILED BIT(4)
184 #define SMBHSTSTS_BUS_ERR BIT(3)
185 #define SMBHSTSTS_DEV_ERR BIT(2)
186 #define SMBHSTSTS_INTR BIT(1)
187 #define SMBHSTSTS_HOST_BUSY BIT(0)
188
189 /* Host Notify Status register bits */
190 #define SMBSLVSTS_HST_NTFY_STS BIT(0)
191
192 /* Host Notify Command register bits */
193 #define SMBSLVCMD_HST_NTFY_INTREN BIT(0)
194
195 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
196 SMBHSTSTS_DEV_ERR)
197
198 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
199 STATUS_ERROR_FLAGS)
200
201 /* Older devices have their ID defined in <linux/pci_ids.h> */
202 #define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3
203 #define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3
204 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
205 #define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df
206 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df
207 #define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9
208 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
209 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
210 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
211 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
212 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
213 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
214 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
215 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
216 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
217 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
218 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
219 #define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4
220 #define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3
221 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
222 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3
223 #define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23
224 #define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3
225 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS 0x51a3
226 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS 0x54a3
227 #define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4
228 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3
229 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
230 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
231 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
232 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
233 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
234 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
235 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
236 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
237 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
238 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3
239 #define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3
240 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
241 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3
242 #define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223
243 #define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3
244 #define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323
245 #define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3
246
247 struct i801_mux_config {
248 char *gpio_chip;
249 unsigned values[3];
250 int n_values;
251 unsigned classes[3];
252 unsigned gpios[2]; /* Relative to gpio_chip->base */
253 int n_gpios;
254 };
255
256 struct i801_priv {
257 struct i2c_adapter adapter;
258 unsigned long smba;
259 unsigned char original_hstcfg;
260 unsigned char original_slvcmd;
261 struct pci_dev *pci_dev;
262 unsigned int features;
263
264 /* isr processing */
265 struct completion done;
266 u8 status;
267
268 /* Command state used by isr for byte-by-byte block transactions */
269 u8 cmd;
270 bool is_read;
271 int count;
272 int len;
273 u8 *data;
274
275 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
276 const struct i801_mux_config *mux_drvdata;
277 struct platform_device *mux_pdev;
278 struct gpiod_lookup_table *lookup;
279 #endif
280 struct platform_device *tco_pdev;
281
282 /*
283 * If set to true the host controller registers are reserved for
284 * ACPI AML use. Protected by acpi_lock.
285 */
286 bool acpi_reserved;
287 struct mutex acpi_lock;
288 };
289
290 #define FEATURE_SMBUS_PEC BIT(0)
291 #define FEATURE_BLOCK_BUFFER BIT(1)
292 #define FEATURE_BLOCK_PROC BIT(2)
293 #define FEATURE_I2C_BLOCK_READ BIT(3)
294 #define FEATURE_IRQ BIT(4)
295 #define FEATURE_HOST_NOTIFY BIT(5)
296 /* Not really a feature, but it's convenient to handle it as such */
297 #define FEATURE_IDF BIT(15)
298 #define FEATURE_TCO_SPT BIT(16)
299 #define FEATURE_TCO_CNL BIT(17)
300
301 static const char *i801_feature_names[] = {
302 "SMBus PEC",
303 "Block buffer",
304 "Block process call",
305 "I2C block read",
306 "Interrupt",
307 "SMBus Host Notify",
308 };
309
310 static unsigned int disable_features;
311 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
312 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
313 "\t\t 0x01 disable SMBus PEC\n"
314 "\t\t 0x02 disable the block buffer\n"
315 "\t\t 0x08 disable the I2C block read functionality\n"
316 "\t\t 0x10 don't use interrupts\n"
317 "\t\t 0x20 disable SMBus Host Notify ");
318
319 /* Make sure the SMBus host is ready to start transmitting.
320 Return 0 if it is, -EBUSY if it is not. */
i801_check_pre(struct i801_priv * priv)321 static int i801_check_pre(struct i801_priv *priv)
322 {
323 int status;
324
325 status = inb_p(SMBHSTSTS(priv));
326 if (status & SMBHSTSTS_HOST_BUSY) {
327 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
328 return -EBUSY;
329 }
330
331 status &= STATUS_FLAGS;
332 if (status) {
333 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
334 status);
335 outb_p(status, SMBHSTSTS(priv));
336 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
337 if (status) {
338 dev_err(&priv->pci_dev->dev,
339 "Failed clearing status flags (%02x)\n",
340 status);
341 return -EBUSY;
342 }
343 }
344
345 /*
346 * Clear CRC status if needed.
347 * During normal operation, i801_check_post() takes care
348 * of it after every operation. We do it here only in case
349 * the hardware was already in this state when the driver
350 * started.
351 */
352 if (priv->features & FEATURE_SMBUS_PEC) {
353 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
354 if (status) {
355 dev_dbg(&priv->pci_dev->dev,
356 "Clearing aux status flags (%02x)\n", status);
357 outb_p(status, SMBAUXSTS(priv));
358 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
359 if (status) {
360 dev_err(&priv->pci_dev->dev,
361 "Failed clearing aux status flags (%02x)\n",
362 status);
363 return -EBUSY;
364 }
365 }
366 }
367
368 return 0;
369 }
370
371 /*
372 * Convert the status register to an error code, and clear it.
373 * Note that status only contains the bits we want to clear, not the
374 * actual register value.
375 */
i801_check_post(struct i801_priv * priv,int status)376 static int i801_check_post(struct i801_priv *priv, int status)
377 {
378 int result = 0;
379
380 /*
381 * If the SMBus is still busy, we give up
382 * Note: This timeout condition only happens when using polling
383 * transactions. For interrupt operation, NAK/timeout is indicated by
384 * DEV_ERR.
385 */
386 if (unlikely(status < 0)) {
387 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
388 /* try to stop the current command */
389 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
390 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
391 usleep_range(1000, 2000);
392 outb_p(0, SMBHSTCNT(priv));
393
394 /* Check if it worked */
395 status = inb_p(SMBHSTSTS(priv));
396 if ((status & SMBHSTSTS_HOST_BUSY) ||
397 !(status & SMBHSTSTS_FAILED))
398 dev_err(&priv->pci_dev->dev,
399 "Failed terminating the transaction\n");
400 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
401 return -ETIMEDOUT;
402 }
403
404 if (status & SMBHSTSTS_FAILED) {
405 result = -EIO;
406 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
407 }
408 if (status & SMBHSTSTS_DEV_ERR) {
409 /*
410 * This may be a PEC error, check and clear it.
411 *
412 * AUXSTS is handled differently from HSTSTS.
413 * For HSTSTS, i801_isr() or i801_wait_intr()
414 * has already cleared the error bits in hardware,
415 * and we are passed a copy of the original value
416 * in "status".
417 * For AUXSTS, the hardware register is left
418 * for us to handle here.
419 * This is asymmetric, slightly iffy, but safe,
420 * since all this code is serialized and the CRCE
421 * bit is harmless as long as it's cleared before
422 * the next operation.
423 */
424 if ((priv->features & FEATURE_SMBUS_PEC) &&
425 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
426 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
427 result = -EBADMSG;
428 dev_dbg(&priv->pci_dev->dev, "PEC error\n");
429 } else {
430 result = -ENXIO;
431 dev_dbg(&priv->pci_dev->dev, "No response\n");
432 }
433 }
434 if (status & SMBHSTSTS_BUS_ERR) {
435 result = -EAGAIN;
436 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
437 }
438
439 /* Clear status flags except BYTE_DONE, to be cleared by caller */
440 outb_p(status, SMBHSTSTS(priv));
441
442 return result;
443 }
444
445 /* Wait for BUSY being cleared and either INTR or an error flag being set */
i801_wait_intr(struct i801_priv * priv)446 static int i801_wait_intr(struct i801_priv *priv)
447 {
448 unsigned long timeout = jiffies + priv->adapter.timeout;
449 int status, busy;
450
451 do {
452 usleep_range(250, 500);
453 status = inb_p(SMBHSTSTS(priv));
454 busy = status & SMBHSTSTS_HOST_BUSY;
455 status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
456 if (!busy && status)
457 return status;
458 } while (time_is_after_eq_jiffies(timeout));
459
460 return -ETIMEDOUT;
461 }
462
463 /* Wait for either BYTE_DONE or an error flag being set */
i801_wait_byte_done(struct i801_priv * priv)464 static int i801_wait_byte_done(struct i801_priv *priv)
465 {
466 unsigned long timeout = jiffies + priv->adapter.timeout;
467 int status;
468
469 do {
470 usleep_range(250, 500);
471 status = inb_p(SMBHSTSTS(priv));
472 if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
473 return status & STATUS_ERROR_FLAGS;
474 } while (time_is_after_eq_jiffies(timeout));
475
476 return -ETIMEDOUT;
477 }
478
i801_transaction(struct i801_priv * priv,int xact)479 static int i801_transaction(struct i801_priv *priv, int xact)
480 {
481 int status;
482 unsigned long result;
483 const struct i2c_adapter *adap = &priv->adapter;
484
485 status = i801_check_pre(priv);
486 if (status < 0)
487 return status;
488
489 if (priv->features & FEATURE_IRQ) {
490 reinit_completion(&priv->done);
491 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
492 SMBHSTCNT(priv));
493 result = wait_for_completion_timeout(&priv->done, adap->timeout);
494 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
495 }
496
497 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
498 * SMBSCMD are passed in xact */
499 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
500
501 status = i801_wait_intr(priv);
502 return i801_check_post(priv, status);
503 }
504
i801_block_transaction_by_block(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)505 static int i801_block_transaction_by_block(struct i801_priv *priv,
506 union i2c_smbus_data *data,
507 char read_write, int command)
508 {
509 int i, len, status, xact;
510
511 switch (command) {
512 case I2C_SMBUS_BLOCK_PROC_CALL:
513 xact = I801_BLOCK_PROC_CALL;
514 break;
515 case I2C_SMBUS_BLOCK_DATA:
516 xact = I801_BLOCK_DATA;
517 break;
518 default:
519 return -EOPNOTSUPP;
520 }
521
522 /* Set block buffer mode */
523 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
524
525 if (read_write == I2C_SMBUS_WRITE) {
526 len = data->block[0];
527 outb_p(len, SMBHSTDAT0(priv));
528 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
529 for (i = 0; i < len; i++)
530 outb_p(data->block[i+1], SMBBLKDAT(priv));
531 }
532
533 status = i801_transaction(priv, xact);
534 if (status)
535 return status;
536
537 if (read_write == I2C_SMBUS_READ ||
538 command == I2C_SMBUS_BLOCK_PROC_CALL) {
539 len = inb_p(SMBHSTDAT0(priv));
540 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
541 return -EPROTO;
542
543 data->block[0] = len;
544 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
545 for (i = 0; i < len; i++)
546 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
547 }
548 return 0;
549 }
550
i801_isr_byte_done(struct i801_priv * priv)551 static void i801_isr_byte_done(struct i801_priv *priv)
552 {
553 if (priv->is_read) {
554 /* For SMBus block reads, length is received with first byte */
555 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
556 (priv->count == 0)) {
557 priv->len = inb_p(SMBHSTDAT0(priv));
558 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
559 dev_err(&priv->pci_dev->dev,
560 "Illegal SMBus block read size %d\n",
561 priv->len);
562 /* FIXME: Recover */
563 priv->len = I2C_SMBUS_BLOCK_MAX;
564 }
565 priv->data[-1] = priv->len;
566 }
567
568 /* Read next byte */
569 if (priv->count < priv->len)
570 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
571 else
572 dev_dbg(&priv->pci_dev->dev,
573 "Discarding extra byte on block read\n");
574
575 /* Set LAST_BYTE for last byte of read transaction */
576 if (priv->count == priv->len - 1)
577 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
578 SMBHSTCNT(priv));
579 } else if (priv->count < priv->len - 1) {
580 /* Write next byte, except for IRQ after last byte */
581 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
582 }
583
584 /* Clear BYTE_DONE to continue with next byte */
585 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
586 }
587
i801_host_notify_isr(struct i801_priv * priv)588 static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
589 {
590 unsigned short addr;
591
592 addr = inb_p(SMBNTFDADD(priv)) >> 1;
593
594 /*
595 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
596 * always returns 0. Our current implementation doesn't provide
597 * data, so we just ignore it.
598 */
599 i2c_handle_smbus_host_notify(&priv->adapter, addr);
600
601 /* clear Host Notify bit and return */
602 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
603 return IRQ_HANDLED;
604 }
605
606 /*
607 * There are three kinds of interrupts:
608 *
609 * 1) i801 signals transaction completion with one of these interrupts:
610 * INTR - Success
611 * DEV_ERR - Invalid command, NAK or communication timeout
612 * BUS_ERR - SMI# transaction collision
613 * FAILED - transaction was canceled due to a KILL request
614 * When any of these occur, update ->status and signal completion.
615 * ->status must be cleared before kicking off the next transaction.
616 *
617 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
618 * occurs for each byte of a byte-by-byte to prepare the next byte.
619 *
620 * 3) Host Notify interrupts
621 */
i801_isr(int irq,void * dev_id)622 static irqreturn_t i801_isr(int irq, void *dev_id)
623 {
624 struct i801_priv *priv = dev_id;
625 u16 pcists;
626 u8 status;
627
628 /* Confirm this is our interrupt */
629 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
630 if (!(pcists & PCI_STATUS_INTERRUPT))
631 return IRQ_NONE;
632
633 if (priv->features & FEATURE_HOST_NOTIFY) {
634 status = inb_p(SMBSLVSTS(priv));
635 if (status & SMBSLVSTS_HST_NTFY_STS)
636 return i801_host_notify_isr(priv);
637 }
638
639 status = inb_p(SMBHSTSTS(priv));
640 if (status & SMBHSTSTS_BYTE_DONE)
641 i801_isr_byte_done(priv);
642
643 /*
644 * Clear irq sources and report transaction result.
645 * ->status must be cleared before the next transaction is started.
646 */
647 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
648 if (status) {
649 outb_p(status, SMBHSTSTS(priv));
650 priv->status = status;
651 complete(&priv->done);
652 }
653
654 return IRQ_HANDLED;
655 }
656
657 /*
658 * For "byte-by-byte" block transactions:
659 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
660 * I2C read uses cmd=I801_I2C_BLOCK_DATA
661 */
i801_block_transaction_byte_by_byte(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)662 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
663 union i2c_smbus_data *data,
664 char read_write, int command)
665 {
666 int i, len;
667 int smbcmd;
668 int status;
669 unsigned long result;
670 const struct i2c_adapter *adap = &priv->adapter;
671
672 if (command == I2C_SMBUS_BLOCK_PROC_CALL)
673 return -EOPNOTSUPP;
674
675 status = i801_check_pre(priv);
676 if (status < 0)
677 return status;
678
679 len = data->block[0];
680
681 if (read_write == I2C_SMBUS_WRITE) {
682 outb_p(len, SMBHSTDAT0(priv));
683 outb_p(data->block[1], SMBBLKDAT(priv));
684 }
685
686 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
687 read_write == I2C_SMBUS_READ)
688 smbcmd = I801_I2C_BLOCK_DATA;
689 else
690 smbcmd = I801_BLOCK_DATA;
691
692 if (priv->features & FEATURE_IRQ) {
693 priv->is_read = (read_write == I2C_SMBUS_READ);
694 if (len == 1 && priv->is_read)
695 smbcmd |= SMBHSTCNT_LAST_BYTE;
696 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
697 priv->len = len;
698 priv->count = 0;
699 priv->data = &data->block[1];
700
701 reinit_completion(&priv->done);
702 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
703 result = wait_for_completion_timeout(&priv->done, adap->timeout);
704 return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
705 }
706
707 if (len == 1 && read_write == I2C_SMBUS_READ)
708 smbcmd |= SMBHSTCNT_LAST_BYTE;
709 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv));
710
711 for (i = 1; i <= len; i++) {
712 status = i801_wait_byte_done(priv);
713 if (status)
714 goto exit;
715
716 if (i == 1 && read_write == I2C_SMBUS_READ
717 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
718 len = inb_p(SMBHSTDAT0(priv));
719 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
720 dev_err(&priv->pci_dev->dev,
721 "Illegal SMBus block read size %d\n",
722 len);
723 /* Recover */
724 while (inb_p(SMBHSTSTS(priv)) &
725 SMBHSTSTS_HOST_BUSY)
726 outb_p(SMBHSTSTS_BYTE_DONE,
727 SMBHSTSTS(priv));
728 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
729 return -EPROTO;
730 }
731 data->block[0] = len;
732 }
733
734 if (read_write == I2C_SMBUS_READ) {
735 data->block[i] = inb_p(SMBBLKDAT(priv));
736 if (i == len - 1)
737 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv));
738 }
739
740 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
741 outb_p(data->block[i+1], SMBBLKDAT(priv));
742
743 /* signals SMBBLKDAT ready */
744 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
745 }
746
747 status = i801_wait_intr(priv);
748 exit:
749 return i801_check_post(priv, status);
750 }
751
752 /* Block transaction function */
i801_block_transaction(struct i801_priv * priv,union i2c_smbus_data * data,char read_write,int command)753 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
754 char read_write, int command)
755 {
756 int result = 0;
757 unsigned char hostc;
758
759 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA)
760 data->block[0] = I2C_SMBUS_BLOCK_MAX;
761 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
762 return -EPROTO;
763
764 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
765 if (read_write == I2C_SMBUS_WRITE) {
766 /* set I2C_EN bit in configuration register */
767 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
768 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
769 hostc | SMBHSTCFG_I2C_EN);
770 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
771 dev_err(&priv->pci_dev->dev,
772 "I2C block read is unsupported!\n");
773 return -EOPNOTSUPP;
774 }
775 }
776
777 /* Experience has shown that the block buffer can only be used for
778 SMBus (not I2C) block transactions, even though the datasheet
779 doesn't mention this limitation. */
780 if ((priv->features & FEATURE_BLOCK_BUFFER) &&
781 command != I2C_SMBUS_I2C_BLOCK_DATA)
782 result = i801_block_transaction_by_block(priv, data,
783 read_write,
784 command);
785 else
786 result = i801_block_transaction_byte_by_byte(priv, data,
787 read_write,
788 command);
789
790 if (command == I2C_SMBUS_I2C_BLOCK_DATA
791 && read_write == I2C_SMBUS_WRITE) {
792 /* restore saved configuration register value */
793 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
794 }
795 return result;
796 }
797
798 /* Return negative errno on error. */
i801_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)799 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
800 unsigned short flags, char read_write, u8 command,
801 int size, union i2c_smbus_data *data)
802 {
803 int hwpec;
804 int block = 0;
805 int ret = 0, xact = 0;
806 struct i801_priv *priv = i2c_get_adapdata(adap);
807
808 mutex_lock(&priv->acpi_lock);
809 if (priv->acpi_reserved) {
810 mutex_unlock(&priv->acpi_lock);
811 return -EBUSY;
812 }
813
814 pm_runtime_get_sync(&priv->pci_dev->dev);
815
816 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
817 && size != I2C_SMBUS_QUICK
818 && size != I2C_SMBUS_I2C_BLOCK_DATA;
819
820 switch (size) {
821 case I2C_SMBUS_QUICK:
822 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
823 SMBHSTADD(priv));
824 xact = I801_QUICK;
825 break;
826 case I2C_SMBUS_BYTE:
827 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
828 SMBHSTADD(priv));
829 if (read_write == I2C_SMBUS_WRITE)
830 outb_p(command, SMBHSTCMD(priv));
831 xact = I801_BYTE;
832 break;
833 case I2C_SMBUS_BYTE_DATA:
834 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
835 SMBHSTADD(priv));
836 outb_p(command, SMBHSTCMD(priv));
837 if (read_write == I2C_SMBUS_WRITE)
838 outb_p(data->byte, SMBHSTDAT0(priv));
839 xact = I801_BYTE_DATA;
840 break;
841 case I2C_SMBUS_WORD_DATA:
842 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
843 SMBHSTADD(priv));
844 outb_p(command, SMBHSTCMD(priv));
845 if (read_write == I2C_SMBUS_WRITE) {
846 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
847 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
848 }
849 xact = I801_WORD_DATA;
850 break;
851 case I2C_SMBUS_BLOCK_DATA:
852 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
853 SMBHSTADD(priv));
854 outb_p(command, SMBHSTCMD(priv));
855 block = 1;
856 break;
857 case I2C_SMBUS_I2C_BLOCK_DATA:
858 /*
859 * NB: page 240 of ICH5 datasheet shows that the R/#W
860 * bit should be cleared here, even when reading.
861 * However if SPD Write Disable is set (Lynx Point and later),
862 * the read will fail if we don't set the R/#W bit.
863 */
864 outb_p(((addr & 0x7f) << 1) |
865 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
866 (read_write & 0x01) : 0),
867 SMBHSTADD(priv));
868 if (read_write == I2C_SMBUS_READ) {
869 /* NB: page 240 of ICH5 datasheet also shows
870 * that DATA1 is the cmd field when reading */
871 outb_p(command, SMBHSTDAT1(priv));
872 } else
873 outb_p(command, SMBHSTCMD(priv));
874 block = 1;
875 break;
876 case I2C_SMBUS_BLOCK_PROC_CALL:
877 /*
878 * Bit 0 of the slave address register always indicate a write
879 * command.
880 */
881 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
882 outb_p(command, SMBHSTCMD(priv));
883 block = 1;
884 break;
885 default:
886 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
887 size);
888 ret = -EOPNOTSUPP;
889 goto out;
890 }
891
892 if (hwpec) /* enable/disable hardware PEC */
893 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
894 else
895 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
896 SMBAUXCTL(priv));
897
898 if (block)
899 ret = i801_block_transaction(priv, data, read_write, size);
900 else
901 ret = i801_transaction(priv, xact);
902
903 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
904 time, so we forcibly disable it after every transaction. Turn off
905 E32B for the same reason. */
906 if (hwpec || block)
907 outb_p(inb_p(SMBAUXCTL(priv)) &
908 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
909
910 if (block)
911 goto out;
912 if (ret)
913 goto out;
914 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
915 goto out;
916
917 switch (xact & 0x7f) {
918 case I801_BYTE: /* Result put in SMBHSTDAT0 */
919 case I801_BYTE_DATA:
920 data->byte = inb_p(SMBHSTDAT0(priv));
921 break;
922 case I801_WORD_DATA:
923 data->word = inb_p(SMBHSTDAT0(priv)) +
924 (inb_p(SMBHSTDAT1(priv)) << 8);
925 break;
926 }
927
928 out:
929 /* Unlock the SMBus device for use by BIOS/ACPI */
930 outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv));
931
932 pm_runtime_mark_last_busy(&priv->pci_dev->dev);
933 pm_runtime_put_autosuspend(&priv->pci_dev->dev);
934 mutex_unlock(&priv->acpi_lock);
935 return ret;
936 }
937
938
i801_func(struct i2c_adapter * adapter)939 static u32 i801_func(struct i2c_adapter *adapter)
940 {
941 struct i801_priv *priv = i2c_get_adapdata(adapter);
942
943 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
944 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
945 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
946 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
947 ((priv->features & FEATURE_BLOCK_PROC) ?
948 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
949 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
950 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
951 ((priv->features & FEATURE_HOST_NOTIFY) ?
952 I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
953 }
954
i801_enable_host_notify(struct i2c_adapter * adapter)955 static void i801_enable_host_notify(struct i2c_adapter *adapter)
956 {
957 struct i801_priv *priv = i2c_get_adapdata(adapter);
958
959 if (!(priv->features & FEATURE_HOST_NOTIFY))
960 return;
961
962 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
963 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
964 SMBSLVCMD(priv));
965
966 /* clear Host Notify bit to allow a new notification */
967 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
968 }
969
i801_disable_host_notify(struct i801_priv * priv)970 static void i801_disable_host_notify(struct i801_priv *priv)
971 {
972 if (!(priv->features & FEATURE_HOST_NOTIFY))
973 return;
974
975 outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
976 }
977
978 static const struct i2c_algorithm smbus_algorithm = {
979 .smbus_xfer = i801_access,
980 .functionality = i801_func,
981 };
982
983 static const struct pci_device_id i801_ids[] = {
984 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
985 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
986 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
987 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
988 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
989 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
990 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
991 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
992 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
993 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
994 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
995 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
996 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
997 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
998 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
999 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1000 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1001 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1002 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1003 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1005 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1006 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1007 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1008 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1009 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1010 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1011 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1012 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1013 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1014 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1015 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1016 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1017 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1018 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) },
1042 { 0, }
1043 };
1044
1045 MODULE_DEVICE_TABLE(pci, i801_ids);
1046
1047 #if defined CONFIG_X86 && defined CONFIG_DMI
1048 static unsigned char apanel_addr;
1049
1050 /* Scan the system ROM for the signature "FJKEYINF" */
bios_signature(const void __iomem * bios)1051 static __init const void __iomem *bios_signature(const void __iomem *bios)
1052 {
1053 ssize_t offset;
1054 const unsigned char signature[] = "FJKEYINF";
1055
1056 for (offset = 0; offset < 0x10000; offset += 0x10) {
1057 if (check_signature(bios + offset, signature,
1058 sizeof(signature)-1))
1059 return bios + offset;
1060 }
1061 return NULL;
1062 }
1063
input_apanel_init(void)1064 static void __init input_apanel_init(void)
1065 {
1066 void __iomem *bios;
1067 const void __iomem *p;
1068
1069 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1070 p = bios_signature(bios);
1071 if (p) {
1072 /* just use the first address */
1073 apanel_addr = readb(p + 8 + 3) >> 1;
1074 }
1075 iounmap(bios);
1076 }
1077
1078 struct dmi_onboard_device_info {
1079 const char *name;
1080 u8 type;
1081 unsigned short i2c_addr;
1082 const char *i2c_type;
1083 };
1084
1085 static const struct dmi_onboard_device_info dmi_devices[] = {
1086 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1087 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1088 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1089 };
1090
dmi_check_onboard_device(u8 type,const char * name,struct i2c_adapter * adap)1091 static void dmi_check_onboard_device(u8 type, const char *name,
1092 struct i2c_adapter *adap)
1093 {
1094 int i;
1095 struct i2c_board_info info;
1096
1097 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1098 /* & ~0x80, ignore enabled/disabled bit */
1099 if ((type & ~0x80) != dmi_devices[i].type)
1100 continue;
1101 if (strcasecmp(name, dmi_devices[i].name))
1102 continue;
1103
1104 memset(&info, 0, sizeof(struct i2c_board_info));
1105 info.addr = dmi_devices[i].i2c_addr;
1106 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1107 i2c_new_client_device(adap, &info);
1108 break;
1109 }
1110 }
1111
1112 /* We use our own function to check for onboard devices instead of
1113 dmi_find_device() as some buggy BIOS's have the devices we are interested
1114 in marked as disabled */
dmi_check_onboard_devices(const struct dmi_header * dm,void * adap)1115 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1116 {
1117 int i, count;
1118
1119 if (dm->type != 10)
1120 return;
1121
1122 count = (dm->length - sizeof(struct dmi_header)) / 2;
1123 for (i = 0; i < count; i++) {
1124 const u8 *d = (char *)(dm + 1) + (i * 2);
1125 const char *name = ((char *) dm) + dm->length;
1126 u8 type = d[0];
1127 u8 s = d[1];
1128
1129 if (!s)
1130 continue;
1131 s--;
1132 while (s > 0 && name[0]) {
1133 name += strlen(name) + 1;
1134 s--;
1135 }
1136 if (name[0] == 0) /* Bogus string reference */
1137 continue;
1138
1139 dmi_check_onboard_device(type, name, adap);
1140 }
1141 }
1142
1143 /* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1144 static const char *const acpi_smo8800_ids[] = {
1145 "SMO8800",
1146 "SMO8801",
1147 "SMO8810",
1148 "SMO8811",
1149 "SMO8820",
1150 "SMO8821",
1151 "SMO8830",
1152 "SMO8831",
1153 };
1154
check_acpi_smo88xx_device(acpi_handle obj_handle,u32 nesting_level,void * context,void ** return_value)1155 static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1156 u32 nesting_level,
1157 void *context,
1158 void **return_value)
1159 {
1160 struct acpi_device_info *info;
1161 acpi_status status;
1162 char *hid;
1163 int i;
1164
1165 status = acpi_get_object_info(obj_handle, &info);
1166 if (ACPI_FAILURE(status))
1167 return AE_OK;
1168
1169 if (!(info->valid & ACPI_VALID_HID))
1170 goto smo88xx_not_found;
1171
1172 hid = info->hardware_id.string;
1173 if (!hid)
1174 goto smo88xx_not_found;
1175
1176 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1177 if (i < 0)
1178 goto smo88xx_not_found;
1179
1180 kfree(info);
1181
1182 *((bool *)return_value) = true;
1183 return AE_CTRL_TERMINATE;
1184
1185 smo88xx_not_found:
1186 kfree(info);
1187 return AE_OK;
1188 }
1189
is_dell_system_with_lis3lv02d(void)1190 static bool is_dell_system_with_lis3lv02d(void)
1191 {
1192 bool found;
1193 const char *vendor;
1194
1195 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1196 if (!vendor || strcmp(vendor, "Dell Inc."))
1197 return false;
1198
1199 /*
1200 * Check that ACPI device SMO88xx is present and is functioning.
1201 * Function acpi_get_devices() already filters all ACPI devices
1202 * which are not present or are not functioning.
1203 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1204 * accelerometer but unfortunately ACPI does not provide any other
1205 * information (like I2C address).
1206 */
1207 found = false;
1208 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1209 (void **)&found);
1210
1211 return found;
1212 }
1213
1214 /*
1215 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1216 * so it is needed to define mapping table based on DMI product names.
1217 */
1218 static const struct {
1219 const char *dmi_product_name;
1220 unsigned short i2c_addr;
1221 } dell_lis3lv02d_devices[] = {
1222 /*
1223 * Dell platform team told us that these Latitude devices have
1224 * ST microelectronics accelerometer at I2C address 0x29.
1225 */
1226 { "Latitude E5250", 0x29 },
1227 { "Latitude E5450", 0x29 },
1228 { "Latitude E5550", 0x29 },
1229 { "Latitude E6440", 0x29 },
1230 { "Latitude E6440 ATG", 0x29 },
1231 { "Latitude E6540", 0x29 },
1232 /*
1233 * Additional individual entries were added after verification.
1234 */
1235 { "Latitude 5480", 0x29 },
1236 { "Vostro V131", 0x1d },
1237 { "Vostro 5568", 0x29 },
1238 };
1239
register_dell_lis3lv02d_i2c_device(struct i801_priv * priv)1240 static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1241 {
1242 struct i2c_board_info info;
1243 const char *dmi_product_name;
1244 int i;
1245
1246 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1247 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1248 if (strcmp(dmi_product_name,
1249 dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1250 break;
1251 }
1252
1253 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1254 dev_warn(&priv->pci_dev->dev,
1255 "Accelerometer lis3lv02d is present on SMBus but its"
1256 " address is unknown, skipping registration\n");
1257 return;
1258 }
1259
1260 memset(&info, 0, sizeof(struct i2c_board_info));
1261 info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1262 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1263 i2c_new_client_device(&priv->adapter, &info);
1264 }
1265
1266 /* Register optional slaves */
i801_probe_optional_slaves(struct i801_priv * priv)1267 static void i801_probe_optional_slaves(struct i801_priv *priv)
1268 {
1269 /* Only register slaves on main SMBus channel */
1270 if (priv->features & FEATURE_IDF)
1271 return;
1272
1273 if (apanel_addr) {
1274 struct i2c_board_info info = {
1275 .addr = apanel_addr,
1276 .type = "fujitsu_apanel",
1277 };
1278
1279 i2c_new_client_device(&priv->adapter, &info);
1280 }
1281
1282 if (dmi_name_in_vendors("FUJITSU"))
1283 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1284
1285 if (is_dell_system_with_lis3lv02d())
1286 register_dell_lis3lv02d_i2c_device(priv);
1287
1288 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1289 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1290 if (!priv->mux_drvdata)
1291 #endif
1292 i2c_register_spd(&priv->adapter);
1293 }
1294 #else
input_apanel_init(void)1295 static void __init input_apanel_init(void) {}
i801_probe_optional_slaves(struct i801_priv * priv)1296 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1297 #endif /* CONFIG_X86 && CONFIG_DMI */
1298
1299 #if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1300 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1301 .gpio_chip = "gpio_ich",
1302 .values = { 0x02, 0x03 },
1303 .n_values = 2,
1304 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1305 .gpios = { 52, 53 },
1306 .n_gpios = 2,
1307 };
1308
1309 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1310 .gpio_chip = "gpio_ich",
1311 .values = { 0x02, 0x03, 0x01 },
1312 .n_values = 3,
1313 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1314 .gpios = { 52, 53 },
1315 .n_gpios = 2,
1316 };
1317
1318 static const struct dmi_system_id mux_dmi_table[] = {
1319 {
1320 .matches = {
1321 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1322 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1323 },
1324 .driver_data = &i801_mux_config_asus_z8_d12,
1325 },
1326 {
1327 .matches = {
1328 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1329 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1330 },
1331 .driver_data = &i801_mux_config_asus_z8_d12,
1332 },
1333 {
1334 .matches = {
1335 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1336 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1337 },
1338 .driver_data = &i801_mux_config_asus_z8_d12,
1339 },
1340 {
1341 .matches = {
1342 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1343 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1344 },
1345 .driver_data = &i801_mux_config_asus_z8_d12,
1346 },
1347 {
1348 .matches = {
1349 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1350 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1351 },
1352 .driver_data = &i801_mux_config_asus_z8_d12,
1353 },
1354 {
1355 .matches = {
1356 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1357 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1358 },
1359 .driver_data = &i801_mux_config_asus_z8_d12,
1360 },
1361 {
1362 .matches = {
1363 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1364 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1365 },
1366 .driver_data = &i801_mux_config_asus_z8_d18,
1367 },
1368 {
1369 .matches = {
1370 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1371 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1372 },
1373 .driver_data = &i801_mux_config_asus_z8_d18,
1374 },
1375 {
1376 .matches = {
1377 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1378 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1379 },
1380 .driver_data = &i801_mux_config_asus_z8_d12,
1381 },
1382 { }
1383 };
1384
1385 /* Setup multiplexing if needed */
i801_add_mux(struct i801_priv * priv)1386 static int i801_add_mux(struct i801_priv *priv)
1387 {
1388 struct device *dev = &priv->adapter.dev;
1389 const struct i801_mux_config *mux_config;
1390 struct i2c_mux_gpio_platform_data gpio_data;
1391 struct gpiod_lookup_table *lookup;
1392 int i;
1393
1394 if (!priv->mux_drvdata)
1395 return 0;
1396 mux_config = priv->mux_drvdata;
1397
1398 /* Prepare the platform data */
1399 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1400 gpio_data.parent = priv->adapter.nr;
1401 gpio_data.values = mux_config->values;
1402 gpio_data.n_values = mux_config->n_values;
1403 gpio_data.classes = mux_config->classes;
1404 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1405
1406 /* Register GPIO descriptor lookup table */
1407 lookup = devm_kzalloc(dev,
1408 struct_size(lookup, table, mux_config->n_gpios + 1),
1409 GFP_KERNEL);
1410 if (!lookup)
1411 return -ENOMEM;
1412 lookup->dev_id = "i2c-mux-gpio";
1413 for (i = 0; i < mux_config->n_gpios; i++) {
1414 lookup->table[i] = (struct gpiod_lookup)
1415 GPIO_LOOKUP(mux_config->gpio_chip,
1416 mux_config->gpios[i], "mux", 0);
1417 }
1418 gpiod_add_lookup_table(lookup);
1419 priv->lookup = lookup;
1420
1421 /*
1422 * Register the mux device, we use PLATFORM_DEVID_NONE here
1423 * because since we are referring to the GPIO chip by name we are
1424 * anyways in deep trouble if there is more than one of these
1425 * devices, and there should likely only be one platform controller
1426 * hub.
1427 */
1428 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1429 PLATFORM_DEVID_NONE, &gpio_data,
1430 sizeof(struct i2c_mux_gpio_platform_data));
1431 if (IS_ERR(priv->mux_pdev)) {
1432 gpiod_remove_lookup_table(lookup);
1433 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1434 }
1435
1436 return PTR_ERR_OR_ZERO(priv->mux_pdev);
1437 }
1438
i801_del_mux(struct i801_priv * priv)1439 static void i801_del_mux(struct i801_priv *priv)
1440 {
1441 platform_device_unregister(priv->mux_pdev);
1442 gpiod_remove_lookup_table(priv->lookup);
1443 }
1444
i801_get_adapter_class(struct i801_priv * priv)1445 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1446 {
1447 const struct dmi_system_id *id;
1448 const struct i801_mux_config *mux_config;
1449 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1450 int i;
1451
1452 id = dmi_first_match(mux_dmi_table);
1453 if (id) {
1454 /* Remove branch classes from trunk */
1455 mux_config = id->driver_data;
1456 for (i = 0; i < mux_config->n_values; i++)
1457 class &= ~mux_config->classes[i];
1458
1459 /* Remember for later */
1460 priv->mux_drvdata = mux_config;
1461 }
1462
1463 return class;
1464 }
1465 #else
i801_add_mux(struct i801_priv * priv)1466 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
i801_del_mux(struct i801_priv * priv)1467 static inline void i801_del_mux(struct i801_priv *priv) { }
1468
i801_get_adapter_class(struct i801_priv * priv)1469 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1470 {
1471 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1472 }
1473 #endif
1474
1475 static const struct itco_wdt_platform_data spt_tco_platform_data = {
1476 .name = "Intel PCH",
1477 .version = 4,
1478 };
1479
1480 static struct platform_device *
i801_add_tco_spt(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1481 i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1482 struct resource *tco_res)
1483 {
1484 struct resource *res;
1485 unsigned int devfn;
1486 u64 base64_addr;
1487 u32 base_addr;
1488 u8 hidden;
1489
1490 /*
1491 * We must access the NO_REBOOT bit over the Primary to Sideband
1492 * bridge (P2SB). The BIOS prevents the P2SB device from being
1493 * enumerated by the PCI subsystem, so we need to unhide/hide it
1494 * to lookup the P2SB BAR.
1495 */
1496 pci_lock_rescan_remove();
1497
1498 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1499
1500 /* Unhide the P2SB device, if it is hidden */
1501 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1502 if (hidden)
1503 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1504
1505 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1506 base64_addr = base_addr & 0xfffffff0;
1507
1508 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1509 base64_addr |= (u64)base_addr << 32;
1510
1511 /* Hide the P2SB device, if it was hidden before */
1512 if (hidden)
1513 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1514 pci_unlock_rescan_remove();
1515
1516 res = &tco_res[1];
1517 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1518 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1519 else
1520 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1521
1522 res->end = res->start + 3;
1523 res->flags = IORESOURCE_MEM;
1524
1525 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1526 tco_res, 2, &spt_tco_platform_data,
1527 sizeof(spt_tco_platform_data));
1528 }
1529
1530 static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1531 .name = "Intel PCH",
1532 .version = 6,
1533 };
1534
1535 static struct platform_device *
i801_add_tco_cnl(struct i801_priv * priv,struct pci_dev * pci_dev,struct resource * tco_res)1536 i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1537 struct resource *tco_res)
1538 {
1539 return platform_device_register_resndata(&pci_dev->dev,
1540 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1541 sizeof(cnl_tco_platform_data));
1542 }
1543
i801_add_tco(struct i801_priv * priv)1544 static void i801_add_tco(struct i801_priv *priv)
1545 {
1546 struct pci_dev *pci_dev = priv->pci_dev;
1547 struct resource tco_res[2], *res;
1548 u32 tco_base, tco_ctl;
1549
1550 /* If we have ACPI based watchdog use that instead */
1551 if (acpi_has_watchdog())
1552 return;
1553
1554 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1555 return;
1556
1557 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1558 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1559 if (!(tco_ctl & TCOCTL_EN))
1560 return;
1561
1562 memset(tco_res, 0, sizeof(tco_res));
1563 /*
1564 * Always populate the main iTCO IO resource here. The second entry
1565 * for NO_REBOOT MMIO is filled by the SPT specific function.
1566 */
1567 res = &tco_res[0];
1568 res->start = tco_base & ~1;
1569 res->end = res->start + 32 - 1;
1570 res->flags = IORESOURCE_IO;
1571
1572 if (priv->features & FEATURE_TCO_CNL)
1573 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1574 else
1575 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1576
1577 if (IS_ERR(priv->tco_pdev))
1578 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1579 }
1580
1581 #ifdef CONFIG_ACPI
i801_acpi_is_smbus_ioport(const struct i801_priv * priv,acpi_physical_address address)1582 static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1583 acpi_physical_address address)
1584 {
1585 return address >= priv->smba &&
1586 address <= pci_resource_end(priv->pci_dev, SMBBAR);
1587 }
1588
1589 static acpi_status
i801_acpi_io_handler(u32 function,acpi_physical_address address,u32 bits,u64 * value,void * handler_context,void * region_context)1590 i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1591 u64 *value, void *handler_context, void *region_context)
1592 {
1593 struct i801_priv *priv = handler_context;
1594 struct pci_dev *pdev = priv->pci_dev;
1595 acpi_status status;
1596
1597 /*
1598 * Once BIOS AML code touches the OpRegion we warn and inhibit any
1599 * further access from the driver itself. This device is now owned
1600 * by the system firmware.
1601 */
1602 mutex_lock(&priv->acpi_lock);
1603
1604 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1605 priv->acpi_reserved = true;
1606
1607 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1608 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1609
1610 /*
1611 * BIOS is accessing the host controller so prevent it from
1612 * suspending automatically from now on.
1613 */
1614 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1615 }
1616
1617 if ((function & ACPI_IO_MASK) == ACPI_READ)
1618 status = acpi_os_read_port(address, (u32 *)value, bits);
1619 else
1620 status = acpi_os_write_port(address, (u32)*value, bits);
1621
1622 mutex_unlock(&priv->acpi_lock);
1623
1624 return status;
1625 }
1626
i801_acpi_probe(struct i801_priv * priv)1627 static int i801_acpi_probe(struct i801_priv *priv)
1628 {
1629 struct acpi_device *adev;
1630 acpi_status status;
1631
1632 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1633 if (adev) {
1634 status = acpi_install_address_space_handler(adev->handle,
1635 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1636 NULL, priv);
1637 if (ACPI_SUCCESS(status))
1638 return 0;
1639 }
1640
1641 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1642 }
1643
i801_acpi_remove(struct i801_priv * priv)1644 static void i801_acpi_remove(struct i801_priv *priv)
1645 {
1646 struct acpi_device *adev;
1647
1648 adev = ACPI_COMPANION(&priv->pci_dev->dev);
1649 if (!adev)
1650 return;
1651
1652 acpi_remove_address_space_handler(adev->handle,
1653 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1654 }
1655 #else
i801_acpi_probe(struct i801_priv * priv)1656 static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
i801_acpi_remove(struct i801_priv * priv)1657 static inline void i801_acpi_remove(struct i801_priv *priv) { }
1658 #endif
1659
i801_setup_hstcfg(struct i801_priv * priv)1660 static void i801_setup_hstcfg(struct i801_priv *priv)
1661 {
1662 unsigned char hstcfg = priv->original_hstcfg;
1663
1664 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1665 hstcfg &= ~SMBHSTCNT_PEC_EN; /* Disable software PEC */
1666 hstcfg |= SMBHSTCFG_HST_EN;
1667 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1668 }
1669
i801_probe(struct pci_dev * dev,const struct pci_device_id * id)1670 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1671 {
1672 int err, i;
1673 struct i801_priv *priv;
1674
1675 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1676 if (!priv)
1677 return -ENOMEM;
1678
1679 i2c_set_adapdata(&priv->adapter, priv);
1680 priv->adapter.owner = THIS_MODULE;
1681 priv->adapter.class = i801_get_adapter_class(priv);
1682 priv->adapter.algo = &smbus_algorithm;
1683 priv->adapter.dev.parent = &dev->dev;
1684 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1685 priv->adapter.retries = 3;
1686 mutex_init(&priv->acpi_lock);
1687
1688 priv->pci_dev = dev;
1689 switch (dev->device) {
1690 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1691 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1692 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1693 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1694 case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1695 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1696 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1697 priv->features |= FEATURE_BLOCK_PROC;
1698 priv->features |= FEATURE_I2C_BLOCK_READ;
1699 priv->features |= FEATURE_IRQ;
1700 priv->features |= FEATURE_SMBUS_PEC;
1701 priv->features |= FEATURE_BLOCK_BUFFER;
1702 priv->features |= FEATURE_TCO_SPT;
1703 priv->features |= FEATURE_HOST_NOTIFY;
1704 break;
1705
1706 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1707 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1708 case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1709 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1710 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1711 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1712 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1713 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1714 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1715 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1716 case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1717 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1718 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS:
1719 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS:
1720 priv->features |= FEATURE_BLOCK_PROC;
1721 priv->features |= FEATURE_I2C_BLOCK_READ;
1722 priv->features |= FEATURE_IRQ;
1723 priv->features |= FEATURE_SMBUS_PEC;
1724 priv->features |= FEATURE_BLOCK_BUFFER;
1725 priv->features |= FEATURE_TCO_CNL;
1726 priv->features |= FEATURE_HOST_NOTIFY;
1727 break;
1728
1729 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1730 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1731 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1732 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1733 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1734 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1735 priv->features |= FEATURE_IDF;
1736 fallthrough;
1737 default:
1738 priv->features |= FEATURE_BLOCK_PROC;
1739 priv->features |= FEATURE_I2C_BLOCK_READ;
1740 priv->features |= FEATURE_IRQ;
1741 fallthrough;
1742 case PCI_DEVICE_ID_INTEL_82801DB_3:
1743 priv->features |= FEATURE_SMBUS_PEC;
1744 priv->features |= FEATURE_BLOCK_BUFFER;
1745 fallthrough;
1746 case PCI_DEVICE_ID_INTEL_82801CA_3:
1747 priv->features |= FEATURE_HOST_NOTIFY;
1748 fallthrough;
1749 case PCI_DEVICE_ID_INTEL_82801BA_2:
1750 case PCI_DEVICE_ID_INTEL_82801AB_3:
1751 case PCI_DEVICE_ID_INTEL_82801AA_3:
1752 break;
1753 }
1754
1755 /* Disable features on user request */
1756 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1757 if (priv->features & disable_features & (1 << i))
1758 dev_notice(&dev->dev, "%s disabled by user\n",
1759 i801_feature_names[i]);
1760 }
1761 priv->features &= ~disable_features;
1762
1763 err = pcim_enable_device(dev);
1764 if (err) {
1765 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1766 err);
1767 return err;
1768 }
1769 pcim_pin_device(dev);
1770
1771 /* Determine the address of the SMBus area */
1772 priv->smba = pci_resource_start(dev, SMBBAR);
1773 if (!priv->smba) {
1774 dev_err(&dev->dev,
1775 "SMBus base address uninitialized, upgrade BIOS\n");
1776 return -ENODEV;
1777 }
1778
1779 if (i801_acpi_probe(priv))
1780 return -ENODEV;
1781
1782 err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1783 if (err) {
1784 dev_err(&dev->dev,
1785 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1786 priv->smba,
1787 (unsigned long long)pci_resource_end(dev, SMBBAR));
1788 i801_acpi_remove(priv);
1789 return err;
1790 }
1791
1792 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1793 i801_setup_hstcfg(priv);
1794 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1795 dev_info(&dev->dev, "Enabling SMBus device\n");
1796
1797 if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1798 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1799 /* Disable SMBus interrupt feature if SMBus using SMI# */
1800 priv->features &= ~FEATURE_IRQ;
1801 }
1802 if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1803 dev_info(&dev->dev, "SPD Write Disable is set\n");
1804
1805 /* Clear special mode bits */
1806 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1807 outb_p(inb_p(SMBAUXCTL(priv)) &
1808 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1809
1810 /* Remember original Host Notify setting */
1811 if (priv->features & FEATURE_HOST_NOTIFY)
1812 priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1813
1814 /* Default timeout in interrupt mode: 200 ms */
1815 priv->adapter.timeout = HZ / 5;
1816
1817 if (dev->irq == IRQ_NOTCONNECTED)
1818 priv->features &= ~FEATURE_IRQ;
1819
1820 if (priv->features & FEATURE_IRQ) {
1821 u16 pcictl, pcists;
1822
1823 /* Complain if an interrupt is already pending */
1824 pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1825 if (pcists & PCI_STATUS_INTERRUPT)
1826 dev_warn(&dev->dev, "An interrupt is pending!\n");
1827
1828 /* Check if interrupts have been disabled */
1829 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pcictl);
1830 if (pcictl & PCI_COMMAND_INTX_DISABLE) {
1831 dev_info(&dev->dev, "Interrupts are disabled\n");
1832 priv->features &= ~FEATURE_IRQ;
1833 }
1834 }
1835
1836 if (priv->features & FEATURE_IRQ) {
1837 init_completion(&priv->done);
1838
1839 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1840 IRQF_SHARED, DRV_NAME, priv);
1841 if (err) {
1842 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1843 dev->irq, err);
1844 priv->features &= ~FEATURE_IRQ;
1845 }
1846 }
1847 dev_info(&dev->dev, "SMBus using %s\n",
1848 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1849
1850 i801_add_tco(priv);
1851
1852 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1853 "SMBus I801 adapter at %04lx", priv->smba);
1854 err = i2c_add_adapter(&priv->adapter);
1855 if (err) {
1856 platform_device_unregister(priv->tco_pdev);
1857 i801_acpi_remove(priv);
1858 return err;
1859 }
1860
1861 i801_enable_host_notify(&priv->adapter);
1862
1863 i801_probe_optional_slaves(priv);
1864 /* We ignore errors - multiplexing is optional */
1865 i801_add_mux(priv);
1866
1867 pci_set_drvdata(dev, priv);
1868
1869 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1870 pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1871 pm_runtime_use_autosuspend(&dev->dev);
1872 pm_runtime_put_autosuspend(&dev->dev);
1873 pm_runtime_allow(&dev->dev);
1874
1875 return 0;
1876 }
1877
i801_remove(struct pci_dev * dev)1878 static void i801_remove(struct pci_dev *dev)
1879 {
1880 struct i801_priv *priv = pci_get_drvdata(dev);
1881
1882 pm_runtime_forbid(&dev->dev);
1883 pm_runtime_get_noresume(&dev->dev);
1884
1885 i801_disable_host_notify(priv);
1886 i801_del_mux(priv);
1887 i2c_del_adapter(&priv->adapter);
1888 i801_acpi_remove(priv);
1889 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1890
1891 platform_device_unregister(priv->tco_pdev);
1892
1893 /*
1894 * do not call pci_disable_device(dev) since it can cause hard hangs on
1895 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1896 */
1897 }
1898
i801_shutdown(struct pci_dev * dev)1899 static void i801_shutdown(struct pci_dev *dev)
1900 {
1901 struct i801_priv *priv = pci_get_drvdata(dev);
1902
1903 /* Restore config registers to avoid hard hang on some systems */
1904 i801_disable_host_notify(priv);
1905 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1906 }
1907
1908 #ifdef CONFIG_PM_SLEEP
i801_suspend(struct device * dev)1909 static int i801_suspend(struct device *dev)
1910 {
1911 struct i801_priv *priv = dev_get_drvdata(dev);
1912
1913 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1914 return 0;
1915 }
1916
i801_resume(struct device * dev)1917 static int i801_resume(struct device *dev)
1918 {
1919 struct i801_priv *priv = dev_get_drvdata(dev);
1920
1921 i801_setup_hstcfg(priv);
1922 i801_enable_host_notify(&priv->adapter);
1923
1924 return 0;
1925 }
1926 #endif
1927
1928 static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1929
1930 static struct pci_driver i801_driver = {
1931 .name = DRV_NAME,
1932 .id_table = i801_ids,
1933 .probe = i801_probe,
1934 .remove = i801_remove,
1935 .shutdown = i801_shutdown,
1936 .driver = {
1937 .pm = &i801_pm_ops,
1938 },
1939 };
1940
i2c_i801_init(void)1941 static int __init i2c_i801_init(void)
1942 {
1943 if (dmi_name_in_vendors("FUJITSU"))
1944 input_apanel_init();
1945 return pci_register_driver(&i801_driver);
1946 }
1947
i2c_i801_exit(void)1948 static void __exit i2c_i801_exit(void)
1949 {
1950 pci_unregister_driver(&i801_driver);
1951 }
1952
1953 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1954 MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1955 MODULE_DESCRIPTION("I801 SMBus driver");
1956 MODULE_LICENSE("GPL");
1957
1958 module_init(i2c_i801_init);
1959 module_exit(i2c_i801_exit);
1960