1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2002 Motorola GSG-China
4 *
5 * Author:
6 * Darius Augulis, Teltonika Inc.
7 *
8 * Desc.:
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
11 *
12 * Derived from Motorola GSG China I2C example driver
13 *
14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
16 * Copyright (C) 2007 RightHand Technologies, Inc.
17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
18 *
19 * Copyright 2013 Freescale Semiconductor, Inc.
20 * Copyright 2020 NXP
21 *
22 */
23
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/completion.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dmapool.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/i2c.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iopoll.h>
39 #include <linux/kernel.h>
40 #include <linux/spinlock.h>
41 #include <linux/hrtimer.h>
42 #include <linux/module.h>
43 #include <linux/of.h>
44 #include <linux/of_device.h>
45 #include <linux/of_dma.h>
46 #include <linux/pinctrl/consumer.h>
47 #include <linux/platform_data/i2c-imx.h>
48 #include <linux/platform_device.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/sched.h>
51 #include <linux/slab.h>
52
53 /* This will be the driver name the kernel reports */
54 #define DRIVER_NAME "imx-i2c"
55
56 #define I2C_IMX_CHECK_DELAY 30000 /* Time to check for bus idle, in NS */
57
58 /*
59 * Enable DMA if transfer byte size is bigger than this threshold.
60 * As the hardware request, it must bigger than 4 bytes.\
61 * I have set '16' here, maybe it's not the best but I think it's
62 * the appropriate.
63 */
64 #define DMA_THRESHOLD 16
65 #define DMA_TIMEOUT 1000
66
67 /* IMX I2C registers:
68 * the I2C register offset is different between SoCs,
69 * to provid support for all these chips, split the
70 * register offset into a fixed base address and a
71 * variable shift value, then the full register offset
72 * will be calculated by
73 * reg_off = ( reg_base_addr << reg_shift)
74 */
75 #define IMX_I2C_IADR 0x00 /* i2c slave address */
76 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
77 #define IMX_I2C_I2CR 0x02 /* i2c control */
78 #define IMX_I2C_I2SR 0x03 /* i2c status */
79 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
80
81 /*
82 * All of the layerscape series SoCs support IBIC register.
83 */
84 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
85
86 #define IMX_I2C_REGSHIFT 2
87 #define VF610_I2C_REGSHIFT 0
88
89 /* Bits of IMX I2C registers */
90 #define I2SR_RXAK 0x01
91 #define I2SR_IIF 0x02
92 #define I2SR_SRW 0x04
93 #define I2SR_IAL 0x10
94 #define I2SR_IBB 0x20
95 #define I2SR_IAAS 0x40
96 #define I2SR_ICF 0x80
97 #define I2CR_DMAEN 0x02
98 #define I2CR_RSTA 0x04
99 #define I2CR_TXAK 0x08
100 #define I2CR_MTX 0x10
101 #define I2CR_MSTA 0x20
102 #define I2CR_IIEN 0x40
103 #define I2CR_IEN 0x80
104 #define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
105
106 /* register bits different operating codes definition:
107 * 1) I2SR: Interrupt flags clear operation differ between SoCs:
108 * - write zero to clear(w0c) INT flag on i.MX,
109 * - but write one to clear(w1c) INT flag on Vybrid.
110 * 2) I2CR: I2C module enable operation also differ between SoCs:
111 * - set I2CR_IEN bit enable the module on i.MX,
112 * - but clear I2CR_IEN bit enable the module on Vybrid.
113 */
114 #define I2SR_CLR_OPCODE_W0C 0x0
115 #define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF)
116 #define I2CR_IEN_OPCODE_0 0x0
117 #define I2CR_IEN_OPCODE_1 I2CR_IEN
118
119 #define I2C_PM_TIMEOUT 10 /* ms */
120
121 /*
122 * sorted list of clock divider, register value pairs
123 * taken from table 26-5, p.26-9, Freescale i.MX
124 * Integrated Portable System Processor Reference Manual
125 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
126 *
127 * Duplicated divider values removed from list
128 */
129 struct imx_i2c_clk_pair {
130 u16 div;
131 u16 val;
132 };
133
134 static struct imx_i2c_clk_pair imx_i2c_clk_div[] = {
135 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
136 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
137 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
138 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
139 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
140 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
141 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
142 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
143 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
144 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
145 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
146 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
147 { 3072, 0x1E }, { 3840, 0x1F }
148 };
149
150 /* Vybrid VF610 clock divider, register value pairs */
151 static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = {
152 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
153 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
154 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
155 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
156 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
157 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
158 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
159 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
160 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
161 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
162 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
163 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
164 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
165 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
166 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
167 };
168
169 enum imx_i2c_type {
170 IMX1_I2C,
171 IMX21_I2C,
172 VF610_I2C,
173 };
174
175 struct imx_i2c_hwdata {
176 enum imx_i2c_type devtype;
177 unsigned int regshift;
178 struct imx_i2c_clk_pair *clk_div;
179 unsigned int ndivs;
180 unsigned int i2sr_clr_opcode;
181 unsigned int i2cr_ien_opcode;
182 };
183
184 struct imx_i2c_dma {
185 struct dma_chan *chan_tx;
186 struct dma_chan *chan_rx;
187 struct dma_chan *chan_using;
188 struct completion cmd_complete;
189 dma_addr_t dma_buf;
190 unsigned int dma_len;
191 enum dma_transfer_direction dma_transfer_dir;
192 enum dma_data_direction dma_data_dir;
193 };
194
195 struct imx_i2c_struct {
196 struct i2c_adapter adapter;
197 struct clk *clk;
198 struct notifier_block clk_change_nb;
199 void __iomem *base;
200 wait_queue_head_t queue;
201 unsigned long i2csr;
202 unsigned int disable_delay;
203 int stopped;
204 unsigned int ifdr; /* IMX_I2C_IFDR */
205 unsigned int cur_clk;
206 unsigned int bitrate;
207 const struct imx_i2c_hwdata *hwdata;
208 struct i2c_bus_recovery_info rinfo;
209
210 struct pinctrl *pinctrl;
211 struct pinctrl_state *pinctrl_pins_default;
212 struct pinctrl_state *pinctrl_pins_gpio;
213
214 struct imx_i2c_dma *dma;
215 struct i2c_client *slave;
216 enum i2c_slave_event last_slave_event;
217
218 /* For checking slave events. */
219 spinlock_t slave_lock;
220 struct hrtimer slave_timer;
221 };
222
223 static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
224 .devtype = IMX1_I2C,
225 .regshift = IMX_I2C_REGSHIFT,
226 .clk_div = imx_i2c_clk_div,
227 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
228 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
229 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
230
231 };
232
233 static const struct imx_i2c_hwdata imx21_i2c_hwdata = {
234 .devtype = IMX21_I2C,
235 .regshift = IMX_I2C_REGSHIFT,
236 .clk_div = imx_i2c_clk_div,
237 .ndivs = ARRAY_SIZE(imx_i2c_clk_div),
238 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C,
239 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1,
240
241 };
242
243 static struct imx_i2c_hwdata vf610_i2c_hwdata = {
244 .devtype = VF610_I2C,
245 .regshift = VF610_I2C_REGSHIFT,
246 .clk_div = vf610_i2c_clk_div,
247 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div),
248 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C,
249 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0,
250
251 };
252
253 static const struct platform_device_id imx_i2c_devtype[] = {
254 {
255 .name = "imx1-i2c",
256 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata,
257 }, {
258 .name = "imx21-i2c",
259 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata,
260 }, {
261 /* sentinel */
262 }
263 };
264 MODULE_DEVICE_TABLE(platform, imx_i2c_devtype);
265
266 static const struct of_device_id i2c_imx_dt_ids[] = {
267 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
268 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
269 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
270 { /* sentinel */ }
271 };
272 MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
273
274 static const struct acpi_device_id i2c_imx_acpi_ids[] = {
275 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata},
276 { }
277 };
278 MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids);
279
is_imx1_i2c(struct imx_i2c_struct * i2c_imx)280 static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
281 {
282 return i2c_imx->hwdata->devtype == IMX1_I2C;
283 }
284
is_vf610_i2c(struct imx_i2c_struct * i2c_imx)285 static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
286 {
287 return i2c_imx->hwdata->devtype == VF610_I2C;
288 }
289
imx_i2c_write_reg(unsigned int val,struct imx_i2c_struct * i2c_imx,unsigned int reg)290 static inline void imx_i2c_write_reg(unsigned int val,
291 struct imx_i2c_struct *i2c_imx, unsigned int reg)
292 {
293 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
294 }
295
imx_i2c_read_reg(struct imx_i2c_struct * i2c_imx,unsigned int reg)296 static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
297 unsigned int reg)
298 {
299 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
300 }
301
i2c_imx_clear_irq(struct imx_i2c_struct * i2c_imx,unsigned int bits)302 static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
303 {
304 unsigned int temp;
305
306 /*
307 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to
308 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
309 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
310 */
311 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
312 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
313 }
314
315 /* Set up i2c controller register and i2c status register to default value. */
i2c_imx_reset_regs(struct imx_i2c_struct * i2c_imx)316 static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
317 {
318 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
319 i2c_imx, IMX_I2C_I2CR);
320 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
321 }
322
323 /* Functions for DMA support */
i2c_imx_dma_request(struct imx_i2c_struct * i2c_imx,dma_addr_t phy_addr)324 static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
325 dma_addr_t phy_addr)
326 {
327 struct imx_i2c_dma *dma;
328 struct dma_slave_config dma_sconfig;
329 struct device *dev = &i2c_imx->adapter.dev;
330 int ret;
331
332 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
333 if (!dma)
334 return;
335
336 dma->chan_tx = dma_request_chan(dev, "tx");
337 if (IS_ERR(dma->chan_tx)) {
338 ret = PTR_ERR(dma->chan_tx);
339 if (ret != -ENODEV && ret != -EPROBE_DEFER)
340 dev_err(dev, "can't request DMA tx channel (%d)\n", ret);
341 goto fail_al;
342 }
343
344 dma_sconfig.dst_addr = phy_addr +
345 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
346 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
347 dma_sconfig.dst_maxburst = 1;
348 dma_sconfig.direction = DMA_MEM_TO_DEV;
349 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
350 if (ret < 0) {
351 dev_err(dev, "can't configure tx channel (%d)\n", ret);
352 goto fail_tx;
353 }
354
355 dma->chan_rx = dma_request_chan(dev, "rx");
356 if (IS_ERR(dma->chan_rx)) {
357 ret = PTR_ERR(dma->chan_rx);
358 if (ret != -ENODEV && ret != -EPROBE_DEFER)
359 dev_err(dev, "can't request DMA rx channel (%d)\n", ret);
360 goto fail_tx;
361 }
362
363 dma_sconfig.src_addr = phy_addr +
364 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
365 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
366 dma_sconfig.src_maxburst = 1;
367 dma_sconfig.direction = DMA_DEV_TO_MEM;
368 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
369 if (ret < 0) {
370 dev_err(dev, "can't configure rx channel (%d)\n", ret);
371 goto fail_rx;
372 }
373
374 i2c_imx->dma = dma;
375 init_completion(&dma->cmd_complete);
376 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
377 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
378
379 return;
380
381 fail_rx:
382 dma_release_channel(dma->chan_rx);
383 fail_tx:
384 dma_release_channel(dma->chan_tx);
385 fail_al:
386 devm_kfree(dev, dma);
387 }
388
i2c_imx_dma_callback(void * arg)389 static void i2c_imx_dma_callback(void *arg)
390 {
391 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
392 struct imx_i2c_dma *dma = i2c_imx->dma;
393
394 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
395 dma->dma_len, dma->dma_data_dir);
396 complete(&dma->cmd_complete);
397 }
398
i2c_imx_dma_xfer(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)399 static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
400 struct i2c_msg *msgs)
401 {
402 struct imx_i2c_dma *dma = i2c_imx->dma;
403 struct dma_async_tx_descriptor *txdesc;
404 struct device *dev = &i2c_imx->adapter.dev;
405 struct device *chan_dev = dma->chan_using->device->dev;
406
407 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
408 dma->dma_len, dma->dma_data_dir);
409 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
410 dev_err(dev, "DMA mapping failed\n");
411 goto err_map;
412 }
413
414 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
415 dma->dma_len, dma->dma_transfer_dir,
416 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
417 if (!txdesc) {
418 dev_err(dev, "Not able to get desc for DMA xfer\n");
419 goto err_desc;
420 }
421
422 reinit_completion(&dma->cmd_complete);
423 txdesc->callback = i2c_imx_dma_callback;
424 txdesc->callback_param = i2c_imx;
425 if (dma_submit_error(dmaengine_submit(txdesc))) {
426 dev_err(dev, "DMA submit failed\n");
427 goto err_submit;
428 }
429
430 dma_async_issue_pending(dma->chan_using);
431 return 0;
432
433 err_submit:
434 dmaengine_terminate_sync(dma->chan_using);
435 err_desc:
436 dma_unmap_single(chan_dev, dma->dma_buf,
437 dma->dma_len, dma->dma_data_dir);
438 err_map:
439 return -EINVAL;
440 }
441
i2c_imx_dma_free(struct imx_i2c_struct * i2c_imx)442 static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
443 {
444 struct imx_i2c_dma *dma = i2c_imx->dma;
445
446 dma->dma_buf = 0;
447 dma->dma_len = 0;
448
449 dma_release_channel(dma->chan_tx);
450 dma->chan_tx = NULL;
451
452 dma_release_channel(dma->chan_rx);
453 dma->chan_rx = NULL;
454
455 dma->chan_using = NULL;
456 }
457
i2c_imx_bus_busy(struct imx_i2c_struct * i2c_imx,int for_busy,bool atomic)458 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
459 {
460 unsigned long orig_jiffies = jiffies;
461 unsigned int temp;
462
463 while (1) {
464 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
465
466 /* check for arbitration lost */
467 if (temp & I2SR_IAL) {
468 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
469 return -EAGAIN;
470 }
471
472 if (for_busy && (temp & I2SR_IBB)) {
473 i2c_imx->stopped = 0;
474 break;
475 }
476 if (!for_busy && !(temp & I2SR_IBB)) {
477 i2c_imx->stopped = 1;
478 break;
479 }
480 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) {
481 dev_dbg(&i2c_imx->adapter.dev,
482 "<%s> I2C bus is busy\n", __func__);
483 return -ETIMEDOUT;
484 }
485 if (atomic)
486 udelay(100);
487 else
488 schedule();
489 }
490
491 return 0;
492 }
493
i2c_imx_trx_complete(struct imx_i2c_struct * i2c_imx,bool atomic)494 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic)
495 {
496 if (atomic) {
497 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
498 unsigned int regval;
499
500 /*
501 * The formula for the poll timeout is documented in the RM
502 * Rev.5 on page 1878:
503 * T_min = 10/F_scl
504 * Set the value hard as it is done for the non-atomic use-case.
505 * Use 10 kHz for the calculation since this is the minimum
506 * allowed SMBus frequency. Also add an offset of 100us since it
507 * turned out that the I2SR_IIF bit isn't set correctly within
508 * the minimum timeout in polling mode.
509 */
510 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100);
511 i2c_imx->i2csr = regval;
512 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
513 } else {
514 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
515 }
516
517 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
518 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
519 return -ETIMEDOUT;
520 }
521
522 /* check for arbitration lost */
523 if (i2c_imx->i2csr & I2SR_IAL) {
524 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
525 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
526
527 i2c_imx->i2csr = 0;
528 return -EAGAIN;
529 }
530
531 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
532 i2c_imx->i2csr = 0;
533 return 0;
534 }
535
i2c_imx_acked(struct imx_i2c_struct * i2c_imx)536 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
537 {
538 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) {
539 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
540 return -ENXIO; /* No ACK */
541 }
542
543 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
544 return 0;
545 }
546
i2c_imx_set_clk(struct imx_i2c_struct * i2c_imx,unsigned int i2c_clk_rate)547 static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
548 unsigned int i2c_clk_rate)
549 {
550 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
551 unsigned int div;
552 int i;
553
554 /* Divider value calculation */
555 if (i2c_imx->cur_clk == i2c_clk_rate)
556 return;
557
558 i2c_imx->cur_clk = i2c_clk_rate;
559
560 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
561 if (div < i2c_clk_div[0].div)
562 i = 0;
563 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
564 i = i2c_imx->hwdata->ndivs - 1;
565 else
566 for (i = 0; i2c_clk_div[i].div < div; i++)
567 ;
568
569 /* Store divider value */
570 i2c_imx->ifdr = i2c_clk_div[i].val;
571
572 /*
573 * There dummy delay is calculated.
574 * It should be about one I2C clock period long.
575 * This delay is used in I2C bus disable function
576 * to fix chip hardware bug.
577 */
578 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
579 i2c_clk_rate / 2);
580
581 #ifdef CONFIG_I2C_DEBUG_BUS
582 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
583 i2c_clk_rate, div);
584 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
585 i2c_clk_div[i].val, i2c_clk_div[i].div);
586 #endif
587 }
588
i2c_imx_clk_notifier_call(struct notifier_block * nb,unsigned long action,void * data)589 static int i2c_imx_clk_notifier_call(struct notifier_block *nb,
590 unsigned long action, void *data)
591 {
592 struct clk_notifier_data *ndata = data;
593 struct imx_i2c_struct *i2c_imx = container_of(nb,
594 struct imx_i2c_struct,
595 clk_change_nb);
596
597 if (action & POST_RATE_CHANGE)
598 i2c_imx_set_clk(i2c_imx, ndata->new_rate);
599
600 return NOTIFY_OK;
601 }
602
i2c_imx_start(struct imx_i2c_struct * i2c_imx,bool atomic)603 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic)
604 {
605 unsigned int temp = 0;
606 int result;
607
608 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
609 /* Enable I2C controller */
610 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
611 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
612
613 /* Wait controller to be stable */
614 if (atomic)
615 udelay(50);
616 else
617 usleep_range(50, 150);
618
619 /* Start I2C transaction */
620 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
621 temp |= I2CR_MSTA;
622 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
623 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
624 if (result)
625 return result;
626
627 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
628 if (atomic)
629 temp &= ~I2CR_IIEN; /* Disable interrupt */
630
631 temp &= ~I2CR_DMAEN;
632 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
633 return result;
634 }
635
i2c_imx_stop(struct imx_i2c_struct * i2c_imx,bool atomic)636 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
637 {
638 unsigned int temp = 0;
639
640 if (!i2c_imx->stopped) {
641 /* Stop I2C transaction */
642 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
643 if (!(temp & I2CR_MSTA))
644 i2c_imx->stopped = 1;
645 temp &= ~(I2CR_MSTA | I2CR_MTX);
646 if (i2c_imx->dma)
647 temp &= ~I2CR_DMAEN;
648 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
649 }
650 if (is_imx1_i2c(i2c_imx)) {
651 /*
652 * This delay caused by an i.MXL hardware bug.
653 * If no (or too short) delay, no "STOP" bit will be generated.
654 */
655 udelay(i2c_imx->disable_delay);
656 }
657
658 if (!i2c_imx->stopped)
659 i2c_imx_bus_busy(i2c_imx, 0, atomic);
660
661 /* Disable I2C controller */
662 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
663 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
664 }
665
666 /*
667 * Enable bus idle interrupts
668 * Note: IBIC register will be cleared after disabled i2c module.
669 * All of layerscape series SoCs support IBIC register.
670 */
i2c_imx_enable_bus_idle(struct imx_i2c_struct * i2c_imx)671 static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
672 {
673 if (is_vf610_i2c(i2c_imx)) {
674 unsigned int temp;
675
676 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
677 temp |= IBIC_BIIE;
678 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
679 }
680 }
681
i2c_imx_slave_event(struct imx_i2c_struct * i2c_imx,enum i2c_slave_event event,u8 * val)682 static void i2c_imx_slave_event(struct imx_i2c_struct *i2c_imx,
683 enum i2c_slave_event event, u8 *val)
684 {
685 i2c_slave_event(i2c_imx->slave, event, val);
686 i2c_imx->last_slave_event = event;
687 }
688
i2c_imx_slave_finish_op(struct imx_i2c_struct * i2c_imx)689 static void i2c_imx_slave_finish_op(struct imx_i2c_struct *i2c_imx)
690 {
691 u8 val = 0;
692
693 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
694 switch (i2c_imx->last_slave_event) {
695 case I2C_SLAVE_READ_REQUESTED:
696 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_READ_PROCESSED,
697 &val);
698 break;
699
700 case I2C_SLAVE_WRITE_REQUESTED:
701 case I2C_SLAVE_READ_PROCESSED:
702 case I2C_SLAVE_WRITE_RECEIVED:
703 i2c_imx_slave_event(i2c_imx, I2C_SLAVE_STOP, &val);
704 break;
705
706 case I2C_SLAVE_STOP:
707 break;
708 }
709 }
710 }
711
712 /* Returns true if the timer should be restarted, false if not. */
i2c_imx_slave_handle(struct imx_i2c_struct * i2c_imx,unsigned int status,unsigned int ctl)713 static irqreturn_t i2c_imx_slave_handle(struct imx_i2c_struct *i2c_imx,
714 unsigned int status, unsigned int ctl)
715 {
716 u8 value = 0;
717
718 if (status & I2SR_IAL) { /* Arbitration lost */
719 i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
720 if (!(status & I2SR_IAAS))
721 return IRQ_HANDLED;
722 }
723
724 if (!(status & I2SR_IBB)) {
725 /* No master on the bus, that could mean a stop condition. */
726 i2c_imx_slave_finish_op(i2c_imx);
727 return IRQ_HANDLED;
728 }
729
730 if (!(status & I2SR_ICF))
731 /* Data transfer still in progress, ignore this. */
732 goto out;
733
734 if (status & I2SR_IAAS) { /* Addressed as a slave */
735 i2c_imx_slave_finish_op(i2c_imx);
736 if (status & I2SR_SRW) { /* Master wants to read from us*/
737 dev_dbg(&i2c_imx->adapter.dev, "read requested");
738 i2c_imx_slave_event(i2c_imx,
739 I2C_SLAVE_READ_REQUESTED, &value);
740
741 /* Slave transmit */
742 ctl |= I2CR_MTX;
743 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
744
745 /* Send data */
746 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
747 } else { /* Master wants to write to us */
748 dev_dbg(&i2c_imx->adapter.dev, "write requested");
749 i2c_imx_slave_event(i2c_imx,
750 I2C_SLAVE_WRITE_REQUESTED, &value);
751
752 /* Slave receive */
753 ctl &= ~I2CR_MTX;
754 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
755 /* Dummy read */
756 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
757 }
758 } else if (!(ctl & I2CR_MTX)) { /* Receive mode */
759 value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
760 i2c_imx_slave_event(i2c_imx,
761 I2C_SLAVE_WRITE_RECEIVED, &value);
762 } else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
763 ctl |= I2CR_MTX;
764 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
765
766 i2c_imx_slave_event(i2c_imx,
767 I2C_SLAVE_READ_PROCESSED, &value);
768
769 imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
770 } else { /* Transmit mode received NAK, operation is done */
771 ctl &= ~I2CR_MTX;
772 imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
773 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
774
775 /* flag the last byte as processed */
776 i2c_imx_slave_event(i2c_imx,
777 I2C_SLAVE_READ_PROCESSED, &value);
778
779 i2c_imx_slave_finish_op(i2c_imx);
780 return IRQ_HANDLED;
781 }
782
783 out:
784 /*
785 * No need to check the return value here. If it returns 0 or
786 * 1, then everything is fine. If it returns -1, then the
787 * timer is running in the handler. This will still work,
788 * though it may be redone (or already have been done) by the
789 * timer function.
790 */
791 hrtimer_try_to_cancel(&i2c_imx->slave_timer);
792 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
793 hrtimer_restart(&i2c_imx->slave_timer);
794 return IRQ_HANDLED;
795 }
796
i2c_imx_slave_timeout(struct hrtimer * t)797 static enum hrtimer_restart i2c_imx_slave_timeout(struct hrtimer *t)
798 {
799 struct imx_i2c_struct *i2c_imx = container_of(t, struct imx_i2c_struct,
800 slave_timer);
801 unsigned int ctl, status;
802 unsigned long flags;
803
804 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
805 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
806 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
807 i2c_imx_slave_handle(i2c_imx, status, ctl);
808 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
809 return HRTIMER_NORESTART;
810 }
811
i2c_imx_slave_init(struct imx_i2c_struct * i2c_imx)812 static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
813 {
814 int temp;
815
816 /* Set slave addr. */
817 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
818
819 i2c_imx_reset_regs(i2c_imx);
820
821 /* Enable module */
822 temp = i2c_imx->hwdata->i2cr_ien_opcode;
823 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
824
825 /* Enable interrupt from i2c module */
826 temp |= I2CR_IIEN;
827 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
828
829 i2c_imx_enable_bus_idle(i2c_imx);
830 }
831
i2c_imx_reg_slave(struct i2c_client * client)832 static int i2c_imx_reg_slave(struct i2c_client *client)
833 {
834 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
835 int ret;
836
837 if (i2c_imx->slave)
838 return -EBUSY;
839
840 i2c_imx->slave = client;
841 i2c_imx->last_slave_event = I2C_SLAVE_STOP;
842
843 /* Resume */
844 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
845 if (ret < 0) {
846 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
847 return ret;
848 }
849
850 i2c_imx_slave_init(i2c_imx);
851
852 return 0;
853 }
854
i2c_imx_unreg_slave(struct i2c_client * client)855 static int i2c_imx_unreg_slave(struct i2c_client *client)
856 {
857 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
858 int ret;
859
860 if (!i2c_imx->slave)
861 return -EINVAL;
862
863 /* Reset slave address. */
864 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
865
866 i2c_imx_reset_regs(i2c_imx);
867
868 i2c_imx->slave = NULL;
869
870 /* Suspend */
871 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
872 if (ret < 0)
873 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
874
875 return ret;
876 }
877
i2c_imx_master_isr(struct imx_i2c_struct * i2c_imx,unsigned int status)878 static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
879 {
880 /* save status register */
881 i2c_imx->i2csr = status;
882 wake_up(&i2c_imx->queue);
883
884 return IRQ_HANDLED;
885 }
886
i2c_imx_isr(int irq,void * dev_id)887 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
888 {
889 struct imx_i2c_struct *i2c_imx = dev_id;
890 unsigned int ctl, status;
891 unsigned long flags;
892
893 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
894 status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
895 ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
896
897 if (status & I2SR_IIF) {
898 i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
899 if (i2c_imx->slave) {
900 if (!(ctl & I2CR_MSTA)) {
901 irqreturn_t ret;
902
903 ret = i2c_imx_slave_handle(i2c_imx,
904 status, ctl);
905 spin_unlock_irqrestore(&i2c_imx->slave_lock,
906 flags);
907 return ret;
908 }
909 i2c_imx_slave_finish_op(i2c_imx);
910 }
911 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
912 return i2c_imx_master_isr(i2c_imx, status);
913 }
914 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
915
916 return IRQ_NONE;
917 }
918
i2c_imx_dma_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs)919 static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
920 struct i2c_msg *msgs)
921 {
922 int result;
923 unsigned long time_left;
924 unsigned int temp = 0;
925 unsigned long orig_jiffies = jiffies;
926 struct imx_i2c_dma *dma = i2c_imx->dma;
927 struct device *dev = &i2c_imx->adapter.dev;
928
929 dma->chan_using = dma->chan_tx;
930 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
931 dma->dma_data_dir = DMA_TO_DEVICE;
932 dma->dma_len = msgs->len - 1;
933 result = i2c_imx_dma_xfer(i2c_imx, msgs);
934 if (result)
935 return result;
936
937 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
938 temp |= I2CR_DMAEN;
939 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
940
941 /*
942 * Write slave address.
943 * The first byte must be transmitted by the CPU.
944 */
945 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
946 time_left = wait_for_completion_timeout(
947 &i2c_imx->dma->cmd_complete,
948 msecs_to_jiffies(DMA_TIMEOUT));
949 if (time_left == 0) {
950 dmaengine_terminate_sync(dma->chan_using);
951 return -ETIMEDOUT;
952 }
953
954 /* Waiting for transfer complete. */
955 while (1) {
956 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
957 if (temp & I2SR_ICF)
958 break;
959 if (time_after(jiffies, orig_jiffies +
960 msecs_to_jiffies(DMA_TIMEOUT))) {
961 dev_dbg(dev, "<%s> Timeout\n", __func__);
962 return -ETIMEDOUT;
963 }
964 schedule();
965 }
966
967 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
968 temp &= ~I2CR_DMAEN;
969 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
970
971 /* The last data byte must be transferred by the CPU. */
972 imx_i2c_write_reg(msgs->buf[msgs->len-1],
973 i2c_imx, IMX_I2C_I2DR);
974 result = i2c_imx_trx_complete(i2c_imx, false);
975 if (result)
976 return result;
977
978 return i2c_imx_acked(i2c_imx);
979 }
980
i2c_imx_dma_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg)981 static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
982 struct i2c_msg *msgs, bool is_lastmsg)
983 {
984 int result;
985 unsigned long time_left;
986 unsigned int temp;
987 unsigned long orig_jiffies = jiffies;
988 struct imx_i2c_dma *dma = i2c_imx->dma;
989 struct device *dev = &i2c_imx->adapter.dev;
990
991
992 dma->chan_using = dma->chan_rx;
993 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
994 dma->dma_data_dir = DMA_FROM_DEVICE;
995 /* The last two data bytes must be transferred by the CPU. */
996 dma->dma_len = msgs->len - 2;
997 result = i2c_imx_dma_xfer(i2c_imx, msgs);
998 if (result)
999 return result;
1000
1001 time_left = wait_for_completion_timeout(
1002 &i2c_imx->dma->cmd_complete,
1003 msecs_to_jiffies(DMA_TIMEOUT));
1004 if (time_left == 0) {
1005 dmaengine_terminate_sync(dma->chan_using);
1006 return -ETIMEDOUT;
1007 }
1008
1009 /* waiting for transfer complete. */
1010 while (1) {
1011 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1012 if (temp & I2SR_ICF)
1013 break;
1014 if (time_after(jiffies, orig_jiffies +
1015 msecs_to_jiffies(DMA_TIMEOUT))) {
1016 dev_dbg(dev, "<%s> Timeout\n", __func__);
1017 return -ETIMEDOUT;
1018 }
1019 schedule();
1020 }
1021
1022 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1023 temp &= ~I2CR_DMAEN;
1024 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1025
1026 /* read n-1 byte data */
1027 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1028 temp |= I2CR_TXAK;
1029 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1030
1031 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1032 /* read n byte data */
1033 result = i2c_imx_trx_complete(i2c_imx, false);
1034 if (result)
1035 return result;
1036
1037 if (is_lastmsg) {
1038 /*
1039 * It must generate STOP before read I2DR to prevent
1040 * controller from generating another clock cycle
1041 */
1042 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
1043 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1044 if (!(temp & I2CR_MSTA))
1045 i2c_imx->stopped = 1;
1046 temp &= ~(I2CR_MSTA | I2CR_MTX);
1047 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1048 if (!i2c_imx->stopped)
1049 i2c_imx_bus_busy(i2c_imx, 0, false);
1050 } else {
1051 /*
1052 * For i2c master receiver repeat restart operation like:
1053 * read -> repeat MSTA -> read/write
1054 * The controller must set MTX before read the last byte in
1055 * the first read operation, otherwise the first read cost
1056 * one extra clock cycle.
1057 */
1058 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1059 temp |= I2CR_MTX;
1060 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1061 }
1062 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1063
1064 return 0;
1065 }
1066
i2c_imx_write(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool atomic)1067 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1068 bool atomic)
1069 {
1070 int i, result;
1071
1072 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1073 __func__, i2c_8bit_addr_from_msg(msgs));
1074
1075 /* write slave address */
1076 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1077 result = i2c_imx_trx_complete(i2c_imx, atomic);
1078 if (result)
1079 return result;
1080 result = i2c_imx_acked(i2c_imx);
1081 if (result)
1082 return result;
1083 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1084
1085 /* write data */
1086 for (i = 0; i < msgs->len; i++) {
1087 dev_dbg(&i2c_imx->adapter.dev,
1088 "<%s> write byte: B%d=0x%X\n",
1089 __func__, i, msgs->buf[i]);
1090 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1091 result = i2c_imx_trx_complete(i2c_imx, atomic);
1092 if (result)
1093 return result;
1094 result = i2c_imx_acked(i2c_imx);
1095 if (result)
1096 return result;
1097 }
1098 return 0;
1099 }
1100
i2c_imx_read(struct imx_i2c_struct * i2c_imx,struct i2c_msg * msgs,bool is_lastmsg,bool atomic)1101 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs,
1102 bool is_lastmsg, bool atomic)
1103 {
1104 int i, result;
1105 unsigned int temp;
1106 int block_data = msgs->flags & I2C_M_RECV_LEN;
1107 int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE &&
1108 msgs->len >= DMA_THRESHOLD && !block_data;
1109
1110 dev_dbg(&i2c_imx->adapter.dev,
1111 "<%s> write slave address: addr=0x%x\n",
1112 __func__, i2c_8bit_addr_from_msg(msgs));
1113
1114 /* write slave address */
1115 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR);
1116 result = i2c_imx_trx_complete(i2c_imx, atomic);
1117 if (result)
1118 return result;
1119 result = i2c_imx_acked(i2c_imx);
1120 if (result)
1121 return result;
1122
1123 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1124
1125 /* setup bus to read data */
1126 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1127 temp &= ~I2CR_MTX;
1128
1129 /*
1130 * Reset the I2CR_TXAK flag initially for SMBus block read since the
1131 * length is unknown
1132 */
1133 if ((msgs->len - 1) || block_data)
1134 temp &= ~I2CR_TXAK;
1135 if (use_dma)
1136 temp |= I2CR_DMAEN;
1137 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1138 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */
1139
1140 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1141
1142 if (use_dma)
1143 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
1144
1145 /* read data */
1146 for (i = 0; i < msgs->len; i++) {
1147 u8 len = 0;
1148
1149 result = i2c_imx_trx_complete(i2c_imx, atomic);
1150 if (result)
1151 return result;
1152 /*
1153 * First byte is the length of remaining packet
1154 * in the SMBus block data read. Add it to
1155 * msgs->len.
1156 */
1157 if ((!i) && block_data) {
1158 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1159 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX))
1160 return -EPROTO;
1161 dev_dbg(&i2c_imx->adapter.dev,
1162 "<%s> read length: 0x%X\n",
1163 __func__, len);
1164 msgs->len += len;
1165 }
1166 if (i == (msgs->len - 1)) {
1167 if (is_lastmsg) {
1168 /*
1169 * It must generate STOP before read I2DR to prevent
1170 * controller from generating another clock cycle
1171 */
1172 dev_dbg(&i2c_imx->adapter.dev,
1173 "<%s> clear MSTA\n", __func__);
1174 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1175 if (!(temp & I2CR_MSTA))
1176 i2c_imx->stopped = 1;
1177 temp &= ~(I2CR_MSTA | I2CR_MTX);
1178 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1179 if (!i2c_imx->stopped)
1180 i2c_imx_bus_busy(i2c_imx, 0, atomic);
1181 } else {
1182 /*
1183 * For i2c master receiver repeat restart operation like:
1184 * read -> repeat MSTA -> read/write
1185 * The controller must set MTX before read the last byte in
1186 * the first read operation, otherwise the first read cost
1187 * one extra clock cycle.
1188 */
1189 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1190 temp |= I2CR_MTX;
1191 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1192 }
1193 } else if (i == (msgs->len - 2)) {
1194 dev_dbg(&i2c_imx->adapter.dev,
1195 "<%s> set TXAK\n", __func__);
1196 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1197 temp |= I2CR_TXAK;
1198 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1199 }
1200 if ((!i) && block_data)
1201 msgs->buf[0] = len;
1202 else
1203 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1204 dev_dbg(&i2c_imx->adapter.dev,
1205 "<%s> read byte: B%d=0x%X\n",
1206 __func__, i, msgs->buf[i]);
1207 }
1208 return 0;
1209 }
1210
i2c_imx_xfer_common(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,bool atomic)1211 static int i2c_imx_xfer_common(struct i2c_adapter *adapter,
1212 struct i2c_msg *msgs, int num, bool atomic)
1213 {
1214 unsigned int i, temp;
1215 int result;
1216 bool is_lastmsg = false;
1217 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1218
1219 /* Start I2C transfer */
1220 result = i2c_imx_start(i2c_imx, atomic);
1221 if (result) {
1222 /*
1223 * Bus recovery uses gpiod_get_value_cansleep() which is not
1224 * allowed within atomic context.
1225 */
1226 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1227 i2c_recover_bus(&i2c_imx->adapter);
1228 result = i2c_imx_start(i2c_imx, atomic);
1229 }
1230 }
1231
1232 if (result)
1233 goto fail0;
1234
1235 /* read/write data */
1236 for (i = 0; i < num; i++) {
1237 if (i == num - 1)
1238 is_lastmsg = true;
1239
1240 if (i) {
1241 dev_dbg(&i2c_imx->adapter.dev,
1242 "<%s> repeated start\n", __func__);
1243 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1244 temp |= I2CR_RSTA;
1245 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
1246 result = i2c_imx_bus_busy(i2c_imx, 1, atomic);
1247 if (result)
1248 goto fail0;
1249 }
1250 dev_dbg(&i2c_imx->adapter.dev,
1251 "<%s> transfer message: %d\n", __func__, i);
1252 /* write/read data */
1253 #ifdef CONFIG_I2C_DEBUG_BUS
1254 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
1255 dev_dbg(&i2c_imx->adapter.dev,
1256 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n",
1257 __func__,
1258 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
1259 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
1260 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
1261 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
1262 dev_dbg(&i2c_imx->adapter.dev,
1263 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n",
1264 __func__,
1265 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
1266 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
1267 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
1268 (temp & I2SR_RXAK ? 1 : 0));
1269 #endif
1270 if (msgs[i].flags & I2C_M_RD) {
1271 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic);
1272 } else {
1273 if (!atomic &&
1274 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1275 msgs[i].flags & I2C_M_DMA_SAFE)
1276 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
1277 else
1278 result = i2c_imx_write(i2c_imx, &msgs[i], atomic);
1279 }
1280 if (result)
1281 goto fail0;
1282 }
1283
1284 fail0:
1285 /* Stop I2C transfer */
1286 i2c_imx_stop(i2c_imx, atomic);
1287
1288 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1289 (result < 0) ? "error" : "success msg",
1290 (result < 0) ? result : num);
1291 /* After data is transferred, switch to slave mode(as a receiver) */
1292 if (i2c_imx->slave)
1293 i2c_imx_slave_init(i2c_imx);
1294
1295 return (result < 0) ? result : num;
1296 }
1297
i2c_imx_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1298 static int i2c_imx_xfer(struct i2c_adapter *adapter,
1299 struct i2c_msg *msgs, int num)
1300 {
1301 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1302 int result;
1303
1304 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1305 if (result < 0)
1306 return result;
1307
1308 result = i2c_imx_xfer_common(adapter, msgs, num, false);
1309
1310 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1311 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1312
1313 return result;
1314 }
1315
i2c_imx_xfer_atomic(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)1316 static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter,
1317 struct i2c_msg *msgs, int num)
1318 {
1319 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
1320 int result;
1321
1322 result = clk_enable(i2c_imx->clk);
1323 if (result)
1324 return result;
1325
1326 result = i2c_imx_xfer_common(adapter, msgs, num, true);
1327
1328 clk_disable(i2c_imx->clk);
1329
1330 return result;
1331 }
1332
i2c_imx_prepare_recovery(struct i2c_adapter * adap)1333 static void i2c_imx_prepare_recovery(struct i2c_adapter *adap)
1334 {
1335 struct imx_i2c_struct *i2c_imx;
1336
1337 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1338
1339 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio);
1340 }
1341
i2c_imx_unprepare_recovery(struct i2c_adapter * adap)1342 static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap)
1343 {
1344 struct imx_i2c_struct *i2c_imx;
1345
1346 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter);
1347
1348 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default);
1349 }
1350
1351 /*
1352 * We switch SCL and SDA to their GPIO function and do some bitbanging
1353 * for bus recovery. These alternative pinmux settings can be
1354 * described in the device tree by a separate pinctrl state "gpio". If
1355 * this is missing this is not a big problem, the only implication is
1356 * that we can't do bus recovery.
1357 */
i2c_imx_init_recovery_info(struct imx_i2c_struct * i2c_imx,struct platform_device * pdev)1358 static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx,
1359 struct platform_device *pdev)
1360 {
1361 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo;
1362
1363 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev);
1364 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) {
1365 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n");
1366 return PTR_ERR(i2c_imx->pinctrl);
1367 }
1368
1369 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl,
1370 PINCTRL_STATE_DEFAULT);
1371 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl,
1372 "gpio");
1373 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN);
1374 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN);
1375
1376 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER ||
1377 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) {
1378 return -EPROBE_DEFER;
1379 } else if (IS_ERR(rinfo->sda_gpiod) ||
1380 IS_ERR(rinfo->scl_gpiod) ||
1381 IS_ERR(i2c_imx->pinctrl_pins_default) ||
1382 IS_ERR(i2c_imx->pinctrl_pins_gpio)) {
1383 dev_dbg(&pdev->dev, "recovery information incomplete\n");
1384 return 0;
1385 }
1386
1387 dev_dbg(&pdev->dev, "using scl%s for recovery\n",
1388 rinfo->sda_gpiod ? ",sda" : "");
1389
1390 rinfo->prepare_recovery = i2c_imx_prepare_recovery;
1391 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery;
1392 rinfo->recover_bus = i2c_generic_scl_recovery;
1393 i2c_imx->adapter.bus_recovery_info = rinfo;
1394
1395 return 0;
1396 }
1397
i2c_imx_func(struct i2c_adapter * adapter)1398 static u32 i2c_imx_func(struct i2c_adapter *adapter)
1399 {
1400 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
1401 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1402 }
1403
1404 static const struct i2c_algorithm i2c_imx_algo = {
1405 .master_xfer = i2c_imx_xfer,
1406 .master_xfer_atomic = i2c_imx_xfer_atomic,
1407 .functionality = i2c_imx_func,
1408 .reg_slave = i2c_imx_reg_slave,
1409 .unreg_slave = i2c_imx_unreg_slave,
1410 };
1411
i2c_imx_probe(struct platform_device * pdev)1412 static int i2c_imx_probe(struct platform_device *pdev)
1413 {
1414 struct imx_i2c_struct *i2c_imx;
1415 struct resource *res;
1416 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1417 void __iomem *base;
1418 int irq, ret;
1419 dma_addr_t phy_addr;
1420 const struct imx_i2c_hwdata *match;
1421
1422 irq = platform_get_irq(pdev, 0);
1423 if (irq < 0)
1424 return irq;
1425
1426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1427 base = devm_ioremap_resource(&pdev->dev, res);
1428 if (IS_ERR(base))
1429 return PTR_ERR(base);
1430
1431 phy_addr = (dma_addr_t)res->start;
1432 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1433 if (!i2c_imx)
1434 return -ENOMEM;
1435
1436 spin_lock_init(&i2c_imx->slave_lock);
1437 hrtimer_init(&i2c_imx->slave_timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
1438 i2c_imx->slave_timer.function = i2c_imx_slave_timeout;
1439
1440 match = device_get_match_data(&pdev->dev);
1441 if (match)
1442 i2c_imx->hwdata = match;
1443 else
1444 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1445 platform_get_device_id(pdev)->driver_data;
1446
1447 /* Setup i2c_imx driver structure */
1448 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1449 i2c_imx->adapter.owner = THIS_MODULE;
1450 i2c_imx->adapter.algo = &i2c_imx_algo;
1451 i2c_imx->adapter.dev.parent = &pdev->dev;
1452 i2c_imx->adapter.nr = pdev->id;
1453 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1454 i2c_imx->base = base;
1455 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1456
1457 /* Get I2C clock */
1458 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
1459 if (IS_ERR(i2c_imx->clk))
1460 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1461 "can't get I2C clock\n");
1462
1463 ret = clk_prepare_enable(i2c_imx->clk);
1464 if (ret) {
1465 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret);
1466 return ret;
1467 }
1468
1469 /* Init queue */
1470 init_waitqueue_head(&i2c_imx->queue);
1471
1472 /* Set up adapter data */
1473 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1474
1475 /* Set up platform driver data */
1476 platform_set_drvdata(pdev, i2c_imx);
1477
1478 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1479 pm_runtime_use_autosuspend(&pdev->dev);
1480 pm_runtime_set_active(&pdev->dev);
1481 pm_runtime_enable(&pdev->dev);
1482
1483 ret = pm_runtime_get_sync(&pdev->dev);
1484 if (ret < 0)
1485 goto rpm_disable;
1486
1487 /* Request IRQ */
1488 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED,
1489 pdev->name, i2c_imx);
1490 if (ret) {
1491 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1492 goto rpm_disable;
1493 }
1494
1495 /* Set up clock divider */
1496 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1497 ret = of_property_read_u32(pdev->dev.of_node,
1498 "clock-frequency", &i2c_imx->bitrate);
1499 if (ret < 0 && pdata && pdata->bitrate)
1500 i2c_imx->bitrate = pdata->bitrate;
1501 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1502 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1503 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1504
1505 i2c_imx_reset_regs(i2c_imx);
1506
1507 /* Init optional bus recovery function */
1508 ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
1509 /* Give it another chance if pinctrl used is not ready yet */
1510 if (ret == -EPROBE_DEFER)
1511 goto clk_notifier_unregister;
1512
1513 /* Add I2C adapter */
1514 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1515 if (ret < 0)
1516 goto clk_notifier_unregister;
1517
1518 pm_runtime_mark_last_busy(&pdev->dev);
1519 pm_runtime_put_autosuspend(&pdev->dev);
1520
1521 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1522 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1523 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1524 i2c_imx->adapter.name);
1525 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1526
1527 /* Init DMA config if supported */
1528 i2c_imx_dma_request(i2c_imx, phy_addr);
1529
1530 return 0; /* Return OK */
1531
1532 clk_notifier_unregister:
1533 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1534 free_irq(irq, i2c_imx);
1535 rpm_disable:
1536 pm_runtime_put_noidle(&pdev->dev);
1537 pm_runtime_disable(&pdev->dev);
1538 pm_runtime_set_suspended(&pdev->dev);
1539 pm_runtime_dont_use_autosuspend(&pdev->dev);
1540 clk_disable_unprepare(i2c_imx->clk);
1541 return ret;
1542 }
1543
i2c_imx_remove(struct platform_device * pdev)1544 static int i2c_imx_remove(struct platform_device *pdev)
1545 {
1546 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
1547 int irq, ret;
1548
1549 ret = pm_runtime_get_sync(&pdev->dev);
1550
1551 hrtimer_cancel(&i2c_imx->slave_timer);
1552
1553 /* remove adapter */
1554 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1555 i2c_del_adapter(&i2c_imx->adapter);
1556
1557 if (i2c_imx->dma)
1558 i2c_imx_dma_free(i2c_imx);
1559
1560 if (ret >= 0) {
1561 /* setup chip registers to defaults */
1562 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
1563 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
1564 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR);
1565 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR);
1566 clk_disable(i2c_imx->clk);
1567 }
1568
1569 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1570 irq = platform_get_irq(pdev, 0);
1571 if (irq >= 0)
1572 free_irq(irq, i2c_imx);
1573
1574 clk_unprepare(i2c_imx->clk);
1575
1576 pm_runtime_put_noidle(&pdev->dev);
1577 pm_runtime_disable(&pdev->dev);
1578
1579 return 0;
1580 }
1581
i2c_imx_runtime_suspend(struct device * dev)1582 static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev)
1583 {
1584 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1585
1586 clk_disable(i2c_imx->clk);
1587
1588 return 0;
1589 }
1590
i2c_imx_runtime_resume(struct device * dev)1591 static int __maybe_unused i2c_imx_runtime_resume(struct device *dev)
1592 {
1593 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev);
1594 int ret;
1595
1596 ret = clk_enable(i2c_imx->clk);
1597 if (ret)
1598 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1599
1600 return ret;
1601 }
1602
1603 static const struct dev_pm_ops i2c_imx_pm_ops = {
1604 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend,
1605 i2c_imx_runtime_resume, NULL)
1606 };
1607
1608 static struct platform_driver i2c_imx_driver = {
1609 .probe = i2c_imx_probe,
1610 .remove = i2c_imx_remove,
1611 .driver = {
1612 .name = DRIVER_NAME,
1613 .pm = &i2c_imx_pm_ops,
1614 .of_match_table = i2c_imx_dt_ids,
1615 .acpi_match_table = i2c_imx_acpi_ids,
1616 },
1617 .id_table = imx_i2c_devtype,
1618 };
1619
i2c_adap_imx_init(void)1620 static int __init i2c_adap_imx_init(void)
1621 {
1622 return platform_driver_register(&i2c_imx_driver);
1623 }
1624 subsys_initcall(i2c_adap_imx_init);
1625
i2c_adap_imx_exit(void)1626 static void __exit i2c_adap_imx_exit(void)
1627 {
1628 platform_driver_unregister(&i2c_imx_driver);
1629 }
1630 module_exit(i2c_adap_imx_exit);
1631
1632 MODULE_LICENSE("GPL");
1633 MODULE_AUTHOR("Darius Augulis");
1634 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
1635 MODULE_ALIAS("platform:" DRIVER_NAME);
1636