1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/spi/spi.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/adc/ad_sigma_delta.h>
23 #include <linux/iio/sysfs.h>
24
25 /* AD7124 registers */
26 #define AD7124_COMMS 0x00
27 #define AD7124_STATUS 0x00
28 #define AD7124_ADC_CONTROL 0x01
29 #define AD7124_DATA 0x02
30 #define AD7124_IO_CONTROL_1 0x03
31 #define AD7124_IO_CONTROL_2 0x04
32 #define AD7124_ID 0x05
33 #define AD7124_ERROR 0x06
34 #define AD7124_ERROR_EN 0x07
35 #define AD7124_MCLK_COUNT 0x08
36 #define AD7124_CHANNEL(x) (0x09 + (x))
37 #define AD7124_CONFIG(x) (0x19 + (x))
38 #define AD7124_FILTER(x) (0x21 + (x))
39 #define AD7124_OFFSET(x) (0x29 + (x))
40 #define AD7124_GAIN(x) (0x31 + (x))
41
42 /* AD7124_STATUS */
43 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
44
45 /* AD7124_ADC_CONTROL */
46 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
47 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
48 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
49 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
50 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
51 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
52
53 /* AD7124 ID */
54 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
55 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
56 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
57 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
58
59 #define CHIPID_AD7124_4 0x0
60 #define CHIPID_AD7124_8 0x1
61
62 /* AD7124_CHANNEL_X */
63 #define AD7124_CHANNEL_EN_MSK BIT(15)
64 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
65 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
66 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
67 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
68 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
69 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
70 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
71
72 /* AD7124_CONFIG_X */
73 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
74 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
75 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
76 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
77 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
78 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
79 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
80 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
81
82 /* AD7124_FILTER_X */
83 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
84 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
85 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
86 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
87
88 #define AD7124_SINC3_FILTER 2
89 #define AD7124_SINC4_FILTER 0
90
91 #define AD7124_CONF_ADDR_OFFSET 20
92 #define AD7124_MAX_CONFIGS 8
93 #define AD7124_MAX_CHANNELS 16
94
95 enum ad7124_ids {
96 ID_AD7124_4,
97 ID_AD7124_8,
98 };
99
100 enum ad7124_ref_sel {
101 AD7124_REFIN1,
102 AD7124_REFIN2,
103 AD7124_INT_REF,
104 AD7124_AVDD_REF,
105 };
106
107 enum ad7124_power_mode {
108 AD7124_LOW_POWER,
109 AD7124_MID_POWER,
110 AD7124_FULL_POWER,
111 };
112
113 static const unsigned int ad7124_gain[8] = {
114 1, 2, 4, 8, 16, 32, 64, 128
115 };
116
117 static const unsigned int ad7124_reg_size[] = {
118 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
119 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
120 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
121 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
122 3, 3, 3, 3, 3
123 };
124
125 static const int ad7124_master_clk_freq_hz[3] = {
126 [AD7124_LOW_POWER] = 76800,
127 [AD7124_MID_POWER] = 153600,
128 [AD7124_FULL_POWER] = 614400,
129 };
130
131 static const char * const ad7124_ref_names[] = {
132 [AD7124_REFIN1] = "refin1",
133 [AD7124_REFIN2] = "refin2",
134 [AD7124_INT_REF] = "int",
135 [AD7124_AVDD_REF] = "avdd",
136 };
137
138 struct ad7124_chip_info {
139 const char *name;
140 unsigned int chip_id;
141 unsigned int num_inputs;
142 };
143
144 struct ad7124_channel_config {
145 bool live;
146 unsigned int cfg_slot;
147 enum ad7124_ref_sel refsel;
148 bool bipolar;
149 bool buf_positive;
150 bool buf_negative;
151 unsigned int vref_mv;
152 unsigned int pga_bits;
153 unsigned int odr;
154 unsigned int odr_sel_bits;
155 unsigned int filter_type;
156 };
157
158 struct ad7124_channel {
159 unsigned int nr;
160 struct ad7124_channel_config cfg;
161 unsigned int ain;
162 unsigned int slot;
163 };
164
165 struct ad7124_state {
166 const struct ad7124_chip_info *chip_info;
167 struct ad_sigma_delta sd;
168 struct ad7124_channel *channels;
169 struct regulator *vref[4];
170 struct clk *mclk;
171 unsigned int adc_control;
172 unsigned int num_channels;
173 struct mutex cfgs_lock; /* lock for configs access */
174 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
175 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
176 };
177
178 static const struct iio_chan_spec ad7124_channel_template = {
179 .type = IIO_VOLTAGE,
180 .indexed = 1,
181 .differential = 1,
182 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
183 BIT(IIO_CHAN_INFO_SCALE) |
184 BIT(IIO_CHAN_INFO_OFFSET) |
185 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
186 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
187 .scan_type = {
188 .sign = 'u',
189 .realbits = 24,
190 .storagebits = 32,
191 .endianness = IIO_BE,
192 },
193 };
194
195 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
196 [ID_AD7124_4] = {
197 .name = "ad7124-4",
198 .chip_id = CHIPID_AD7124_4,
199 .num_inputs = 8,
200 },
201 [ID_AD7124_8] = {
202 .name = "ad7124-8",
203 .chip_id = CHIPID_AD7124_8,
204 .num_inputs = 16,
205 },
206 };
207
ad7124_find_closest_match(const int * array,unsigned int size,int val)208 static int ad7124_find_closest_match(const int *array,
209 unsigned int size, int val)
210 {
211 int i, idx;
212 unsigned int diff_new, diff_old;
213
214 diff_old = U32_MAX;
215 idx = 0;
216
217 for (i = 0; i < size; i++) {
218 diff_new = abs(val - array[i]);
219 if (diff_new < diff_old) {
220 diff_old = diff_new;
221 idx = i;
222 }
223 }
224
225 return idx;
226 }
227
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)228 static int ad7124_spi_write_mask(struct ad7124_state *st,
229 unsigned int addr,
230 unsigned long mask,
231 unsigned int val,
232 unsigned int bytes)
233 {
234 unsigned int readval;
235 int ret;
236
237 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
238 if (ret < 0)
239 return ret;
240
241 readval &= ~mask;
242 readval |= val;
243
244 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
245 }
246
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)247 static int ad7124_set_mode(struct ad_sigma_delta *sd,
248 enum ad_sigma_delta_mode mode)
249 {
250 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
251
252 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
253 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
254
255 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
256 }
257
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel,unsigned int odr)258 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
259 {
260 unsigned int fclk, odr_sel_bits;
261
262 fclk = clk_get_rate(st->mclk);
263 /*
264 * FS[10:0] = fCLK / (fADC x 32) where:
265 * fADC is the output data rate
266 * fCLK is the master clock frequency
267 * FS[10:0] are the bits in the filter register
268 * FS[10:0] can have a value from 1 to 2047
269 */
270 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
271 if (odr_sel_bits < 1)
272 odr_sel_bits = 1;
273 else if (odr_sel_bits > 2047)
274 odr_sel_bits = 2047;
275
276 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
277 st->channels[channel].cfg.live = false;
278
279 /* fADC = fCLK / (FS[10:0] x 32) */
280 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
281 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
282 }
283
ad7124_get_3db_filter_freq(struct ad7124_state * st,unsigned int channel)284 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
285 unsigned int channel)
286 {
287 unsigned int fadc;
288
289 fadc = st->channels[channel].cfg.odr;
290
291 switch (st->channels[channel].cfg.filter_type) {
292 case AD7124_SINC3_FILTER:
293 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
294 case AD7124_SINC4_FILTER:
295 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
296 default:
297 return -EINVAL;
298 }
299 }
300
ad7124_set_3db_filter_freq(struct ad7124_state * st,unsigned int channel,unsigned int freq)301 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
302 unsigned int freq)
303 {
304 unsigned int sinc4_3db_odr;
305 unsigned int sinc3_3db_odr;
306 unsigned int new_filter;
307 unsigned int new_odr;
308
309 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
310 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
311
312 if (sinc4_3db_odr > sinc3_3db_odr) {
313 new_filter = AD7124_SINC3_FILTER;
314 new_odr = sinc4_3db_odr;
315 } else {
316 new_filter = AD7124_SINC4_FILTER;
317 new_odr = sinc3_3db_odr;
318 }
319
320 if (new_odr != st->channels[channel].cfg.odr)
321 st->channels[channel].cfg.live = false;
322
323 st->channels[channel].cfg.filter_type = new_filter;
324 st->channels[channel].cfg.odr = new_odr;
325 }
326
ad7124_find_similar_live_cfg(struct ad7124_state * st,struct ad7124_channel_config * cfg)327 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
328 struct ad7124_channel_config *cfg)
329 {
330 struct ad7124_channel_config *cfg_aux;
331 ptrdiff_t cmp_size;
332 int i;
333
334 cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
335 for (i = 0; i < st->num_channels; i++) {
336 cfg_aux = &st->channels[i].cfg;
337
338 if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
339 return cfg_aux;
340 }
341
342 return NULL;
343 }
344
ad7124_find_free_config_slot(struct ad7124_state * st)345 static int ad7124_find_free_config_slot(struct ad7124_state *st)
346 {
347 unsigned int free_cfg_slot;
348
349 free_cfg_slot = find_next_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS, 0);
350 if (free_cfg_slot == AD7124_MAX_CONFIGS)
351 return -1;
352
353 return free_cfg_slot;
354 }
355
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)356 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
357 {
358 unsigned int refsel = cfg->refsel;
359
360 switch (refsel) {
361 case AD7124_REFIN1:
362 case AD7124_REFIN2:
363 case AD7124_AVDD_REF:
364 if (IS_ERR(st->vref[refsel])) {
365 dev_err(&st->sd.spi->dev,
366 "Error, trying to use external voltage reference without a %s regulator.\n",
367 ad7124_ref_names[refsel]);
368 return PTR_ERR(st->vref[refsel]);
369 }
370 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
371 /* Conversion from uV to mV */
372 cfg->vref_mv /= 1000;
373 return 0;
374 case AD7124_INT_REF:
375 cfg->vref_mv = 2500;
376 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
377 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
378 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
379 2, st->adc_control);
380 default:
381 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
382 return -EINVAL;
383 }
384 }
385
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)386 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
387 unsigned int cfg_slot)
388 {
389 unsigned int tmp;
390 unsigned int val;
391 int ret;
392
393 cfg->cfg_slot = cfg_slot;
394
395 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
396 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
397 AD7124_CONFIG_IN_BUFF(tmp);
398 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
399 if (ret < 0)
400 return ret;
401
402 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
403 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
404 tmp, 3);
405 if (ret < 0)
406 return ret;
407
408 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
409 AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
410 if (ret < 0)
411 return ret;
412
413 return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
414 AD7124_CONFIG_PGA(cfg->pga_bits), 2);
415 }
416
ad7124_pop_config(struct ad7124_state * st)417 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
418 {
419 struct ad7124_channel_config *lru_cfg;
420 struct ad7124_channel_config *cfg;
421 int ret;
422 int i;
423
424 /*
425 * Pop least recently used config from the fifo
426 * in order to make room for the new one
427 */
428 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
429 if (ret <= 0)
430 return NULL;
431
432 lru_cfg->live = false;
433
434 /* mark slot as free */
435 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
436
437 /* invalidate all other configs that pointed to this one */
438 for (i = 0; i < st->num_channels; i++) {
439 cfg = &st->channels[i].cfg;
440
441 if (cfg->cfg_slot == lru_cfg->cfg_slot)
442 cfg->live = false;
443 }
444
445 return lru_cfg;
446 }
447
ad7124_push_config(struct ad7124_state * st,struct ad7124_channel_config * cfg)448 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
449 {
450 struct ad7124_channel_config *lru_cfg;
451 int free_cfg_slot;
452
453 free_cfg_slot = ad7124_find_free_config_slot(st);
454 if (free_cfg_slot >= 0) {
455 /* push the new config in configs queue */
456 kfifo_put(&st->live_cfgs_fifo, cfg);
457 } else {
458 /* pop one config to make room for the new one */
459 lru_cfg = ad7124_pop_config(st);
460 if (!lru_cfg)
461 return -EINVAL;
462
463 /* push the new config in configs queue */
464 free_cfg_slot = lru_cfg->cfg_slot;
465 kfifo_put(&st->live_cfgs_fifo, cfg);
466 }
467
468 /* mark slot as used */
469 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
470
471 return ad7124_write_config(st, cfg, free_cfg_slot);
472 }
473
ad7124_enable_channel(struct ad7124_state * st,struct ad7124_channel * ch)474 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
475 {
476 ch->cfg.live = true;
477 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
478 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
479 }
480
ad7124_prepare_read(struct ad7124_state * st,int address)481 static int ad7124_prepare_read(struct ad7124_state *st, int address)
482 {
483 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
484 struct ad7124_channel_config *live_cfg;
485
486 /*
487 * Before doing any reads assign the channel a configuration.
488 * Check if channel's config is on the device
489 */
490 if (!cfg->live) {
491 /* check if config matches another one */
492 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
493 if (!live_cfg)
494 ad7124_push_config(st, cfg);
495 else
496 cfg->cfg_slot = live_cfg->cfg_slot;
497 }
498
499 /* point channel to the config slot and enable */
500 return ad7124_enable_channel(st, &st->channels[address]);
501 }
502
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)503 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
504 {
505 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
506 int ret;
507
508 mutex_lock(&st->cfgs_lock);
509 ret = ad7124_prepare_read(st, channel);
510 mutex_unlock(&st->cfgs_lock);
511
512 return ret;
513 }
514
515 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
516 .set_channel = ad7124_set_channel,
517 .set_mode = ad7124_set_mode,
518 .has_registers = true,
519 .addr_shift = 0,
520 .read_mask = BIT(6),
521 .data_reg = AD7124_DATA,
522 .irq_flags = IRQF_TRIGGER_FALLING
523 };
524
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)525 static int ad7124_read_raw(struct iio_dev *indio_dev,
526 struct iio_chan_spec const *chan,
527 int *val, int *val2, long info)
528 {
529 struct ad7124_state *st = iio_priv(indio_dev);
530 int idx, ret;
531
532 switch (info) {
533 case IIO_CHAN_INFO_RAW:
534 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
535 if (ret < 0)
536 return ret;
537
538 /* After the conversion is performed, disable the channel */
539 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
540 st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
541 if (ret < 0)
542 return ret;
543
544 return IIO_VAL_INT;
545 case IIO_CHAN_INFO_SCALE:
546 mutex_lock(&st->cfgs_lock);
547
548 idx = st->channels[chan->address].cfg.pga_bits;
549 *val = st->channels[chan->address].cfg.vref_mv;
550 if (st->channels[chan->address].cfg.bipolar)
551 *val2 = chan->scan_type.realbits - 1 + idx;
552 else
553 *val2 = chan->scan_type.realbits + idx;
554
555 mutex_unlock(&st->cfgs_lock);
556 return IIO_VAL_FRACTIONAL_LOG2;
557 case IIO_CHAN_INFO_OFFSET:
558 mutex_lock(&st->cfgs_lock);
559 if (st->channels[chan->address].cfg.bipolar)
560 *val = -(1 << (chan->scan_type.realbits - 1));
561 else
562 *val = 0;
563
564 mutex_unlock(&st->cfgs_lock);
565 return IIO_VAL_INT;
566 case IIO_CHAN_INFO_SAMP_FREQ:
567 mutex_lock(&st->cfgs_lock);
568 *val = st->channels[chan->address].cfg.odr;
569 mutex_unlock(&st->cfgs_lock);
570
571 return IIO_VAL_INT;
572 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
573 mutex_lock(&st->cfgs_lock);
574 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
575 mutex_unlock(&st->cfgs_lock);
576
577 return IIO_VAL_INT;
578 default:
579 return -EINVAL;
580 }
581 }
582
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)583 static int ad7124_write_raw(struct iio_dev *indio_dev,
584 struct iio_chan_spec const *chan,
585 int val, int val2, long info)
586 {
587 struct ad7124_state *st = iio_priv(indio_dev);
588 unsigned int res, gain, full_scale, vref;
589 int ret = 0;
590
591 mutex_lock(&st->cfgs_lock);
592
593 switch (info) {
594 case IIO_CHAN_INFO_SAMP_FREQ:
595 if (val2 != 0) {
596 ret = -EINVAL;
597 break;
598 }
599
600 ad7124_set_channel_odr(st, chan->address, val);
601 break;
602 case IIO_CHAN_INFO_SCALE:
603 if (val != 0) {
604 ret = -EINVAL;
605 break;
606 }
607
608 if (st->channels[chan->address].cfg.bipolar)
609 full_scale = 1 << (chan->scan_type.realbits - 1);
610 else
611 full_scale = 1 << chan->scan_type.realbits;
612
613 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
614 res = DIV_ROUND_CLOSEST(vref, full_scale);
615 gain = DIV_ROUND_CLOSEST(res, val2);
616 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
617
618 if (st->channels[chan->address].cfg.pga_bits != res)
619 st->channels[chan->address].cfg.live = false;
620
621 st->channels[chan->address].cfg.pga_bits = res;
622 break;
623 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
624 if (val2 != 0) {
625 ret = -EINVAL;
626 break;
627 }
628
629 ad7124_set_3db_filter_freq(st, chan->address, val);
630 break;
631 default:
632 ret = -EINVAL;
633 }
634
635 mutex_unlock(&st->cfgs_lock);
636 return ret;
637 }
638
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)639 static int ad7124_reg_access(struct iio_dev *indio_dev,
640 unsigned int reg,
641 unsigned int writeval,
642 unsigned int *readval)
643 {
644 struct ad7124_state *st = iio_priv(indio_dev);
645 int ret;
646
647 if (reg >= ARRAY_SIZE(ad7124_reg_size))
648 return -EINVAL;
649
650 if (readval)
651 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
652 readval);
653 else
654 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
655 writeval);
656
657 return ret;
658 }
659
660 static IIO_CONST_ATTR(in_voltage_scale_available,
661 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
662
663 static struct attribute *ad7124_attributes[] = {
664 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
665 NULL,
666 };
667
668 static const struct attribute_group ad7124_attrs_group = {
669 .attrs = ad7124_attributes,
670 };
671
672 static const struct iio_info ad7124_info = {
673 .read_raw = ad7124_read_raw,
674 .write_raw = ad7124_write_raw,
675 .debugfs_reg_access = &ad7124_reg_access,
676 .validate_trigger = ad_sd_validate_trigger,
677 .attrs = &ad7124_attrs_group,
678 };
679
ad7124_soft_reset(struct ad7124_state * st)680 static int ad7124_soft_reset(struct ad7124_state *st)
681 {
682 unsigned int readval, timeout;
683 int ret;
684
685 ret = ad_sd_reset(&st->sd, 64);
686 if (ret < 0)
687 return ret;
688
689 timeout = 100;
690 do {
691 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
692 if (ret < 0)
693 return ret;
694
695 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
696 return 0;
697
698 /* The AD7124 requires typically 2ms to power up and settle */
699 usleep_range(100, 2000);
700 } while (--timeout);
701
702 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
703
704 return -EIO;
705 }
706
ad7124_check_chip_id(struct ad7124_state * st)707 static int ad7124_check_chip_id(struct ad7124_state *st)
708 {
709 unsigned int readval, chip_id, silicon_rev;
710 int ret;
711
712 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
713 if (ret < 0)
714 return ret;
715
716 chip_id = AD7124_DEVICE_ID_GET(readval);
717 silicon_rev = AD7124_SILICON_REV_GET(readval);
718
719 if (chip_id != st->chip_info->chip_id) {
720 dev_err(&st->sd.spi->dev,
721 "Chip ID mismatch: expected %u, got %u\n",
722 st->chip_info->chip_id, chip_id);
723 return -ENODEV;
724 }
725
726 if (silicon_rev == 0) {
727 dev_err(&st->sd.spi->dev,
728 "Silicon revision empty. Chip may not be present\n");
729 return -ENODEV;
730 }
731
732 return 0;
733 }
734
ad7124_of_parse_channel_config(struct iio_dev * indio_dev,struct device_node * np)735 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
736 struct device_node *np)
737 {
738 struct ad7124_state *st = iio_priv(indio_dev);
739 struct ad7124_channel_config *cfg;
740 struct ad7124_channel *channels;
741 struct device_node *child;
742 struct iio_chan_spec *chan;
743 unsigned int ain[2], channel = 0, tmp;
744 int ret;
745
746 st->num_channels = of_get_available_child_count(np);
747 if (!st->num_channels) {
748 dev_err(indio_dev->dev.parent, "no channel children\n");
749 return -ENODEV;
750 }
751
752 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
753 sizeof(*chan), GFP_KERNEL);
754 if (!chan)
755 return -ENOMEM;
756
757 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
758 GFP_KERNEL);
759 if (!channels)
760 return -ENOMEM;
761
762 indio_dev->channels = chan;
763 indio_dev->num_channels = st->num_channels;
764 st->channels = channels;
765
766 for_each_available_child_of_node(np, child) {
767 cfg = &st->channels[channel].cfg;
768
769 ret = of_property_read_u32(child, "reg", &channel);
770 if (ret)
771 goto err;
772
773 if (channel >= indio_dev->num_channels) {
774 dev_err(indio_dev->dev.parent,
775 "Channel index >= number of channels\n");
776 ret = -EINVAL;
777 goto err;
778 }
779
780 ret = of_property_read_u32_array(child, "diff-channels",
781 ain, 2);
782 if (ret)
783 goto err;
784
785 st->channels[channel].nr = channel;
786 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
787 AD7124_CHANNEL_AINM(ain[1]);
788
789 cfg->bipolar = of_property_read_bool(child, "bipolar");
790
791 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
792 if (ret)
793 cfg->refsel = AD7124_INT_REF;
794 else
795 cfg->refsel = tmp;
796
797 cfg->buf_positive = of_property_read_bool(child, "adi,buffered-positive");
798 cfg->buf_negative = of_property_read_bool(child, "adi,buffered-negative");
799
800 chan[channel] = ad7124_channel_template;
801 chan[channel].address = channel;
802 chan[channel].scan_index = channel;
803 chan[channel].channel = ain[0];
804 chan[channel].channel2 = ain[1];
805 }
806
807 return 0;
808 err:
809 of_node_put(child);
810
811 return ret;
812 }
813
ad7124_setup(struct ad7124_state * st)814 static int ad7124_setup(struct ad7124_state *st)
815 {
816 unsigned int fclk, power_mode;
817 int i, ret;
818
819 fclk = clk_get_rate(st->mclk);
820 if (!fclk)
821 return -EINVAL;
822
823 /* The power mode changes the master clock frequency */
824 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
825 ARRAY_SIZE(ad7124_master_clk_freq_hz),
826 fclk);
827 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
828 ret = clk_set_rate(st->mclk, fclk);
829 if (ret)
830 return ret;
831 }
832
833 /* Set the power mode */
834 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
835 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
836 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
837 if (ret < 0)
838 return ret;
839
840 mutex_init(&st->cfgs_lock);
841 INIT_KFIFO(st->live_cfgs_fifo);
842 for (i = 0; i < st->num_channels; i++) {
843
844 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
845 if (ret < 0)
846 return ret;
847
848 /*
849 * 9.38 SPS is the minimum output data rate supported
850 * regardless of the selected power mode. Round it up to 10 and
851 * set all channels to this default value.
852 */
853 ad7124_set_channel_odr(st, i, 10);
854 }
855
856 return ret;
857 }
858
ad7124_reg_disable(void * r)859 static void ad7124_reg_disable(void *r)
860 {
861 regulator_disable(r);
862 }
863
ad7124_clk_disable(void * c)864 static void ad7124_clk_disable(void *c)
865 {
866 clk_disable_unprepare(c);
867 }
868
ad7124_probe(struct spi_device * spi)869 static int ad7124_probe(struct spi_device *spi)
870 {
871 const struct ad7124_chip_info *info;
872 struct ad7124_state *st;
873 struct iio_dev *indio_dev;
874 int i, ret;
875
876 info = of_device_get_match_data(&spi->dev);
877 if (!info)
878 return -ENODEV;
879
880 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
881 if (!indio_dev)
882 return -ENOMEM;
883
884 st = iio_priv(indio_dev);
885
886 st->chip_info = info;
887
888 ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
889
890 indio_dev->name = st->chip_info->name;
891 indio_dev->modes = INDIO_DIRECT_MODE;
892 indio_dev->info = &ad7124_info;
893
894 ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
895 if (ret < 0)
896 return ret;
897
898 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
899 if (i == AD7124_INT_REF)
900 continue;
901
902 st->vref[i] = devm_regulator_get_optional(&spi->dev,
903 ad7124_ref_names[i]);
904 if (PTR_ERR(st->vref[i]) == -ENODEV)
905 continue;
906 else if (IS_ERR(st->vref[i]))
907 return PTR_ERR(st->vref[i]);
908
909 ret = regulator_enable(st->vref[i]);
910 if (ret)
911 return ret;
912
913 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
914 st->vref[i]);
915 if (ret)
916 return ret;
917 }
918
919 st->mclk = devm_clk_get(&spi->dev, "mclk");
920 if (IS_ERR(st->mclk))
921 return PTR_ERR(st->mclk);
922
923 ret = clk_prepare_enable(st->mclk);
924 if (ret < 0)
925 return ret;
926
927 ret = devm_add_action_or_reset(&spi->dev, ad7124_clk_disable, st->mclk);
928 if (ret)
929 return ret;
930
931 ret = ad7124_soft_reset(st);
932 if (ret < 0)
933 return ret;
934
935 ret = ad7124_check_chip_id(st);
936 if (ret)
937 return ret;
938
939 ret = ad7124_setup(st);
940 if (ret < 0)
941 return ret;
942
943 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
944 if (ret < 0)
945 return ret;
946
947 return devm_iio_device_register(&spi->dev, indio_dev);
948
949 }
950
951 static const struct of_device_id ad7124_of_match[] = {
952 { .compatible = "adi,ad7124-4",
953 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
954 { .compatible = "adi,ad7124-8",
955 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
956 { },
957 };
958 MODULE_DEVICE_TABLE(of, ad7124_of_match);
959
960 static struct spi_driver ad71124_driver = {
961 .driver = {
962 .name = "ad7124",
963 .of_match_table = ad7124_of_match,
964 },
965 .probe = ad7124_probe,
966 };
967 module_spi_driver(ad71124_driver);
968
969 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
970 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
971 MODULE_LICENSE("GPL");
972