1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
6 * Copyright 2012 CS Systemes d'Information
7 */
8
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25
26 #define AD7923_WRITE_CR BIT(11) /* write control register */
27 #define AD7923_RANGE BIT(1) /* range to REFin */
28 #define AD7923_CODING BIT(0) /* coding is straight binary */
29 #define AD7923_PM_MODE_AS (1) /* auto shutdown */
30 #define AD7923_PM_MODE_FS (2) /* full shutdown */
31 #define AD7923_PM_MODE_OPS (3) /* normal operation */
32 #define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
33 #define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
34 #define AD7923_SEQUENCE_ON (3) /* continuous sequence */
35
36
37 #define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */
38 #define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
39 #define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
40 + (((sequence) & 2) << 9))
41 /* write sequence fonction */
42 /* left shift for CR : bit 11 transmit in first */
43 #define AD7923_SHIFT_REGISTER 4
44
45 /* val = value, dec = left shift, bits = number of bits of the mask */
46 #define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
47
48 struct ad7923_state {
49 struct spi_device *spi;
50 struct spi_transfer ring_xfer[5];
51 struct spi_transfer scan_single_xfer[2];
52 struct spi_message ring_msg;
53 struct spi_message scan_single_msg;
54
55 struct regulator *reg;
56
57 unsigned int settings;
58
59 /*
60 * DMA (thus cache coherency maintenance) requires the
61 * transfer buffers to live in their own cache lines.
62 * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
63 * Length = 8 channels + 4 extra for 8 byte timestamp
64 */
65 __be16 rx_buf[12] ____cacheline_aligned;
66 __be16 tx_buf[4];
67 };
68
69 struct ad7923_chip_info {
70 const struct iio_chan_spec *channels;
71 unsigned int num_channels;
72 };
73
74 enum ad7923_id {
75 AD7904,
76 AD7914,
77 AD7924,
78 AD7908,
79 AD7918,
80 AD7928
81 };
82
83 #define AD7923_V_CHAN(index, bits) \
84 { \
85 .type = IIO_VOLTAGE, \
86 .indexed = 1, \
87 .channel = index, \
88 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
89 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
90 .address = index, \
91 .scan_index = index, \
92 .scan_type = { \
93 .sign = 'u', \
94 .realbits = (bits), \
95 .storagebits = 16, \
96 .shift = 12 - (bits), \
97 .endianness = IIO_BE, \
98 }, \
99 }
100
101 #define DECLARE_AD7923_CHANNELS(name, bits) \
102 const struct iio_chan_spec name ## _channels[] = { \
103 AD7923_V_CHAN(0, bits), \
104 AD7923_V_CHAN(1, bits), \
105 AD7923_V_CHAN(2, bits), \
106 AD7923_V_CHAN(3, bits), \
107 IIO_CHAN_SOFT_TIMESTAMP(4), \
108 }
109
110 #define DECLARE_AD7908_CHANNELS(name, bits) \
111 const struct iio_chan_spec name ## _channels[] = { \
112 AD7923_V_CHAN(0, bits), \
113 AD7923_V_CHAN(1, bits), \
114 AD7923_V_CHAN(2, bits), \
115 AD7923_V_CHAN(3, bits), \
116 AD7923_V_CHAN(4, bits), \
117 AD7923_V_CHAN(5, bits), \
118 AD7923_V_CHAN(6, bits), \
119 AD7923_V_CHAN(7, bits), \
120 IIO_CHAN_SOFT_TIMESTAMP(8), \
121 }
122
123 static DECLARE_AD7923_CHANNELS(ad7904, 8);
124 static DECLARE_AD7923_CHANNELS(ad7914, 10);
125 static DECLARE_AD7923_CHANNELS(ad7924, 12);
126 static DECLARE_AD7908_CHANNELS(ad7908, 8);
127 static DECLARE_AD7908_CHANNELS(ad7918, 10);
128 static DECLARE_AD7908_CHANNELS(ad7928, 12);
129
130 static const struct ad7923_chip_info ad7923_chip_info[] = {
131 [AD7904] = {
132 .channels = ad7904_channels,
133 .num_channels = ARRAY_SIZE(ad7904_channels),
134 },
135 [AD7914] = {
136 .channels = ad7914_channels,
137 .num_channels = ARRAY_SIZE(ad7914_channels),
138 },
139 [AD7924] = {
140 .channels = ad7924_channels,
141 .num_channels = ARRAY_SIZE(ad7924_channels),
142 },
143 [AD7908] = {
144 .channels = ad7908_channels,
145 .num_channels = ARRAY_SIZE(ad7908_channels),
146 },
147 [AD7918] = {
148 .channels = ad7918_channels,
149 .num_channels = ARRAY_SIZE(ad7918_channels),
150 },
151 [AD7928] = {
152 .channels = ad7928_channels,
153 .num_channels = ARRAY_SIZE(ad7928_channels),
154 },
155 };
156
157 /*
158 * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
159 */
ad7923_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)160 static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
161 const unsigned long *active_scan_mask)
162 {
163 struct ad7923_state *st = iio_priv(indio_dev);
164 int i, cmd, len;
165
166 len = 0;
167 /*
168 * For this driver the last channel is always the software timestamp so
169 * skip that one.
170 */
171 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
172 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
173 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
174 st->settings;
175 cmd <<= AD7923_SHIFT_REGISTER;
176 st->tx_buf[len++] = cpu_to_be16(cmd);
177 }
178 /* build spi ring message */
179 st->ring_xfer[0].tx_buf = &st->tx_buf[0];
180 st->ring_xfer[0].len = len;
181 st->ring_xfer[0].cs_change = 1;
182
183 spi_message_init(&st->ring_msg);
184 spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
185
186 for (i = 0; i < len; i++) {
187 st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
188 st->ring_xfer[i + 1].len = 2;
189 st->ring_xfer[i + 1].cs_change = 1;
190 spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
191 }
192 /* make sure last transfer cs_change is not set */
193 st->ring_xfer[i + 1].cs_change = 0;
194
195 return 0;
196 }
197
ad7923_trigger_handler(int irq,void * p)198 static irqreturn_t ad7923_trigger_handler(int irq, void *p)
199 {
200 struct iio_poll_func *pf = p;
201 struct iio_dev *indio_dev = pf->indio_dev;
202 struct ad7923_state *st = iio_priv(indio_dev);
203 int b_sent;
204
205 b_sent = spi_sync(st->spi, &st->ring_msg);
206 if (b_sent)
207 goto done;
208
209 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
210 iio_get_time_ns(indio_dev));
211
212 done:
213 iio_trigger_notify_done(indio_dev->trig);
214
215 return IRQ_HANDLED;
216 }
217
ad7923_scan_direct(struct ad7923_state * st,unsigned int ch)218 static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
219 {
220 int ret, cmd;
221
222 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
223 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
224 st->settings;
225 cmd <<= AD7923_SHIFT_REGISTER;
226 st->tx_buf[0] = cpu_to_be16(cmd);
227
228 ret = spi_sync(st->spi, &st->scan_single_msg);
229 if (ret)
230 return ret;
231
232 return be16_to_cpu(st->rx_buf[0]);
233 }
234
ad7923_get_range(struct ad7923_state * st)235 static int ad7923_get_range(struct ad7923_state *st)
236 {
237 int vref;
238
239 vref = regulator_get_voltage(st->reg);
240 if (vref < 0)
241 return vref;
242
243 vref /= 1000;
244
245 if (!(st->settings & AD7923_RANGE))
246 vref *= 2;
247
248 return vref;
249 }
250
ad7923_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)251 static int ad7923_read_raw(struct iio_dev *indio_dev,
252 struct iio_chan_spec const *chan,
253 int *val,
254 int *val2,
255 long m)
256 {
257 int ret;
258 struct ad7923_state *st = iio_priv(indio_dev);
259
260 switch (m) {
261 case IIO_CHAN_INFO_RAW:
262 ret = iio_device_claim_direct_mode(indio_dev);
263 if (ret)
264 return ret;
265 ret = ad7923_scan_direct(st, chan->address);
266 iio_device_release_direct_mode(indio_dev);
267
268 if (ret < 0)
269 return ret;
270
271 if (chan->address == EXTRACT(ret, 12, 4))
272 *val = EXTRACT(ret, chan->scan_type.shift,
273 chan->scan_type.realbits);
274 else
275 return -EIO;
276
277 return IIO_VAL_INT;
278 case IIO_CHAN_INFO_SCALE:
279 ret = ad7923_get_range(st);
280 if (ret < 0)
281 return ret;
282 *val = ret;
283 *val2 = chan->scan_type.realbits;
284 return IIO_VAL_FRACTIONAL_LOG2;
285 }
286 return -EINVAL;
287 }
288
289 static const struct iio_info ad7923_info = {
290 .read_raw = &ad7923_read_raw,
291 .update_scan_mode = ad7923_update_scan_mode,
292 };
293
ad7923_regulator_disable(void * data)294 static void ad7923_regulator_disable(void *data)
295 {
296 struct ad7923_state *st = data;
297
298 regulator_disable(st->reg);
299 }
300
ad7923_probe(struct spi_device * spi)301 static int ad7923_probe(struct spi_device *spi)
302 {
303 struct ad7923_state *st;
304 struct iio_dev *indio_dev;
305 const struct ad7923_chip_info *info;
306 int ret;
307
308 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
309 if (!indio_dev)
310 return -ENOMEM;
311
312 st = iio_priv(indio_dev);
313
314 st->spi = spi;
315 st->settings = AD7923_CODING | AD7923_RANGE |
316 AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
317
318 info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
319
320 indio_dev->name = spi_get_device_id(spi)->name;
321 indio_dev->modes = INDIO_DIRECT_MODE;
322 indio_dev->channels = info->channels;
323 indio_dev->num_channels = info->num_channels;
324 indio_dev->info = &ad7923_info;
325
326 /* Setup default message */
327
328 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
329 st->scan_single_xfer[0].len = 2;
330 st->scan_single_xfer[0].cs_change = 1;
331 st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
332 st->scan_single_xfer[1].len = 2;
333
334 spi_message_init(&st->scan_single_msg);
335 spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
336 spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
337
338 st->reg = devm_regulator_get(&spi->dev, "refin");
339 if (IS_ERR(st->reg))
340 return PTR_ERR(st->reg);
341
342 ret = regulator_enable(st->reg);
343 if (ret)
344 return ret;
345
346 ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
347 if (ret)
348 return ret;
349
350 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
351 &ad7923_trigger_handler, NULL);
352 if (ret)
353 return ret;
354
355 return devm_iio_device_register(&spi->dev, indio_dev);
356 }
357
358 static const struct spi_device_id ad7923_id[] = {
359 {"ad7904", AD7904},
360 {"ad7914", AD7914},
361 {"ad7923", AD7924},
362 {"ad7924", AD7924},
363 {"ad7908", AD7908},
364 {"ad7918", AD7918},
365 {"ad7928", AD7928},
366 {}
367 };
368 MODULE_DEVICE_TABLE(spi, ad7923_id);
369
370 static const struct of_device_id ad7923_of_match[] = {
371 { .compatible = "adi,ad7904", },
372 { .compatible = "adi,ad7914", },
373 { .compatible = "adi,ad7923", },
374 { .compatible = "adi,ad7924", },
375 { .compatible = "adi,ad7908", },
376 { .compatible = "adi,ad7918", },
377 { .compatible = "adi,ad7928", },
378 { },
379 };
380 MODULE_DEVICE_TABLE(of, ad7923_of_match);
381
382 static struct spi_driver ad7923_driver = {
383 .driver = {
384 .name = "ad7923",
385 .of_match_table = ad7923_of_match,
386 },
387 .probe = ad7923_probe,
388 .id_table = ad7923_id,
389 };
390 module_spi_driver(ad7923_driver);
391
392 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
393 MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
394 MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
395 MODULE_LICENSE("GPL v2");
396