1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/completion.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/iio/adc/qcom-vadc-common.h>
11 #include <linux/iio/iio.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/log2.h>
15 #include <linux/math64.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/slab.h>
22
23 #include <dt-bindings/iio/qcom,spmi-vadc.h>
24
25 #define ADC5_USR_REVISION1 0x0
26 #define ADC5_USR_STATUS1 0x8
27 #define ADC5_USR_STATUS1_CONV_FAULT BIT(7)
28 #define ADC5_USR_STATUS1_REQ_STS BIT(1)
29 #define ADC5_USR_STATUS1_EOC BIT(0)
30 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3
31
32 #define ADC5_USR_STATUS2 0x9
33 #define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70
34 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5
35
36 #define ADC5_USR_IBAT_MEAS 0xf
37 #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0)
38
39 #define ADC5_USR_DIG_PARAM 0x42
40 #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6)
41 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6
42 #define ADC5_USR_DIG_PARAM_CAL_SEL 0x30
43 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4
44 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc
45 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2
46
47 #define ADC5_USR_FAST_AVG_CTL 0x43
48 #define ADC5_USR_FAST_AVG_CTL_EN BIT(7)
49 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7
50
51 #define ADC5_USR_CH_SEL_CTL 0x44
52
53 #define ADC5_USR_DELAY_CTL 0x45
54 #define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf
55
56 #define ADC5_USR_EN_CTL1 0x46
57 #define ADC5_USR_EN_CTL1_ADC_EN BIT(7)
58
59 #define ADC5_USR_CONV_REQ 0x47
60 #define ADC5_USR_CONV_REQ_REQ BIT(7)
61
62 #define ADC5_USR_DATA0 0x50
63
64 #define ADC5_USR_DATA1 0x51
65
66 #define ADC5_USR_IBAT_DATA0 0x52
67
68 #define ADC5_USR_IBAT_DATA1 0x53
69
70 #define ADC_CHANNEL_OFFSET 0x8
71 #define ADC_CHANNEL_MASK GENMASK(7, 0)
72
73 /*
74 * Conversion time varies based on the decimation, clock rate, fast average
75 * samples and measurements queued across different VADC peripherals.
76 * Set the timeout to a max of 100ms.
77 */
78 #define ADC5_CONV_TIME_MIN_US 263
79 #define ADC5_CONV_TIME_MAX_US 264
80 #define ADC5_CONV_TIME_RETRY 400
81 #define ADC5_CONV_TIMEOUT msecs_to_jiffies(100)
82
83 /* Digital version >= 5.3 supports hw_settle_2 */
84 #define ADC5_HW_SETTLE_DIFF_MINOR 3
85 #define ADC5_HW_SETTLE_DIFF_MAJOR 5
86
87 /* For PMIC7 */
88 #define ADC_APP_SID 0x40
89 #define ADC_APP_SID_MASK GENMASK(3, 0)
90 #define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
91
92 enum adc5_cal_method {
93 ADC5_NO_CAL = 0,
94 ADC5_RATIOMETRIC_CAL,
95 ADC5_ABSOLUTE_CAL
96 };
97
98 enum adc5_cal_val {
99 ADC5_TIMER_CAL = 0,
100 ADC5_NEW_CAL
101 };
102
103 /**
104 * struct adc5_channel_prop - ADC channel property.
105 * @channel: channel number, refer to the channel list.
106 * @cal_method: calibration method.
107 * @cal_val: calibration value
108 * @decimation: sampling rate supported for the channel.
109 * @sid: slave id of PMIC owning the channel, for PMIC7.
110 * @prescale: channel scaling performed on the input signal.
111 * @hw_settle_time: the time between AMUX being configured and the
112 * start of conversion.
113 * @avg_samples: ability to provide single result from the ADC
114 * that is an average of multiple measurements.
115 * @scale_fn_type: Represents the scaling function to convert voltage
116 * physical units desired by the client for the channel.
117 * @datasheet_name: Channel name used in device tree.
118 */
119 struct adc5_channel_prop {
120 unsigned int channel;
121 enum adc5_cal_method cal_method;
122 enum adc5_cal_val cal_val;
123 unsigned int decimation;
124 unsigned int sid;
125 unsigned int prescale;
126 unsigned int hw_settle_time;
127 unsigned int avg_samples;
128 enum vadc_scale_fn_type scale_fn_type;
129 const char *datasheet_name;
130 };
131
132 /**
133 * struct adc5_chip - ADC private structure.
134 * @regmap: SPMI ADC5 peripheral register map field.
135 * @dev: SPMI ADC5 device.
136 * @base: base address for the ADC peripheral.
137 * @nchannels: number of ADC channels.
138 * @chan_props: array of ADC channel properties.
139 * @iio_chans: array of IIO channels specification.
140 * @poll_eoc: use polling instead of interrupt.
141 * @complete: ADC result notification after interrupt is received.
142 * @lock: ADC lock for access to the peripheral.
143 * @data: software configuration data.
144 */
145 struct adc5_chip {
146 struct regmap *regmap;
147 struct device *dev;
148 u16 base;
149 unsigned int nchannels;
150 struct adc5_channel_prop *chan_props;
151 struct iio_chan_spec *iio_chans;
152 bool poll_eoc;
153 struct completion complete;
154 struct mutex lock;
155 const struct adc5_data *data;
156 };
157
adc5_read(struct adc5_chip * adc,u16 offset,u8 * data,int len)158 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
159 {
160 return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
161 }
162
adc5_write(struct adc5_chip * adc,u16 offset,u8 * data,int len)163 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
164 {
165 return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
166 }
167
adc5_masked_write(struct adc5_chip * adc,u16 offset,u8 mask,u8 val)168 static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
169 {
170 return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
171 }
172
adc5_read_voltage_data(struct adc5_chip * adc,u16 * data)173 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
174 {
175 int ret;
176 u8 rslt_lsb, rslt_msb;
177
178 ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
179 if (ret)
180 return ret;
181
182 ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
183 if (ret)
184 return ret;
185
186 *data = (rslt_msb << 8) | rslt_lsb;
187
188 if (*data == ADC5_USR_DATA_CHECK) {
189 dev_err(adc->dev, "Invalid data:0x%x\n", *data);
190 return -EINVAL;
191 }
192
193 dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
194
195 return 0;
196 }
197
adc5_poll_wait_eoc(struct adc5_chip * adc)198 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
199 {
200 unsigned int count, retry = ADC5_CONV_TIME_RETRY;
201 u8 status1;
202 int ret;
203
204 for (count = 0; count < retry; count++) {
205 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
206 sizeof(status1));
207 if (ret)
208 return ret;
209
210 status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
211 if (status1 == ADC5_USR_STATUS1_EOC)
212 return 0;
213
214 usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
215 }
216
217 return -ETIMEDOUT;
218 }
219
adc5_update_dig_param(struct adc5_chip * adc,struct adc5_channel_prop * prop,u8 * data)220 static void adc5_update_dig_param(struct adc5_chip *adc,
221 struct adc5_channel_prop *prop, u8 *data)
222 {
223 /* Update calibration value */
224 *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
225 *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
226
227 /* Update calibration select */
228 *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
229 *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
230
231 /* Update decimation ratio select */
232 *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
233 *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
234 }
235
adc5_configure(struct adc5_chip * adc,struct adc5_channel_prop * prop)236 static int adc5_configure(struct adc5_chip *adc,
237 struct adc5_channel_prop *prop)
238 {
239 int ret;
240 u8 buf[6];
241
242 /* Read registers 0x42 through 0x46 */
243 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
244 if (ret)
245 return ret;
246
247 /* Digital param selection */
248 adc5_update_dig_param(adc, prop, &buf[0]);
249
250 /* Update fast average sample value */
251 buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
252 buf[1] |= prop->avg_samples;
253
254 /* Select ADC channel */
255 buf[2] = prop->channel;
256
257 /* Select HW settle delay for channel */
258 buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
259 buf[3] |= prop->hw_settle_time;
260
261 /* Select ADC enable */
262 buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
263
264 /* Select CONV request */
265 buf[5] |= ADC5_USR_CONV_REQ_REQ;
266
267 if (!adc->poll_eoc)
268 reinit_completion(&adc->complete);
269
270 return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
271 }
272
adc7_configure(struct adc5_chip * adc,struct adc5_channel_prop * prop)273 static int adc7_configure(struct adc5_chip *adc,
274 struct adc5_channel_prop *prop)
275 {
276 int ret;
277 u8 conv_req = 0, buf[4];
278
279 ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
280 if (ret)
281 return ret;
282
283 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
284 if (ret)
285 return ret;
286
287 /* Digital param selection */
288 adc5_update_dig_param(adc, prop, &buf[0]);
289
290 /* Update fast average sample value */
291 buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
292 buf[1] |= prop->avg_samples;
293
294 /* Select ADC channel */
295 buf[2] = prop->channel;
296
297 /* Select HW settle delay for channel */
298 buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK;
299 buf[3] |= prop->hw_settle_time;
300
301 /* Select CONV request */
302 conv_req = ADC5_USR_CONV_REQ_REQ;
303
304 if (!adc->poll_eoc)
305 reinit_completion(&adc->complete);
306
307 ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
308 if (ret)
309 return ret;
310
311 return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
312 }
313
adc5_do_conversion(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct iio_chan_spec const * chan,u16 * data_volt,u16 * data_cur)314 static int adc5_do_conversion(struct adc5_chip *adc,
315 struct adc5_channel_prop *prop,
316 struct iio_chan_spec const *chan,
317 u16 *data_volt, u16 *data_cur)
318 {
319 int ret;
320
321 mutex_lock(&adc->lock);
322
323 ret = adc5_configure(adc, prop);
324 if (ret) {
325 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
326 goto unlock;
327 }
328
329 if (adc->poll_eoc) {
330 ret = adc5_poll_wait_eoc(adc);
331 if (ret) {
332 dev_err(adc->dev, "EOC bit not set\n");
333 goto unlock;
334 }
335 } else {
336 ret = wait_for_completion_timeout(&adc->complete,
337 ADC5_CONV_TIMEOUT);
338 if (!ret) {
339 dev_dbg(adc->dev, "Did not get completion timeout.\n");
340 ret = adc5_poll_wait_eoc(adc);
341 if (ret) {
342 dev_err(adc->dev, "EOC bit not set\n");
343 goto unlock;
344 }
345 }
346 }
347
348 ret = adc5_read_voltage_data(adc, data_volt);
349 unlock:
350 mutex_unlock(&adc->lock);
351
352 return ret;
353 }
354
adc7_do_conversion(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct iio_chan_spec const * chan,u16 * data_volt,u16 * data_cur)355 static int adc7_do_conversion(struct adc5_chip *adc,
356 struct adc5_channel_prop *prop,
357 struct iio_chan_spec const *chan,
358 u16 *data_volt, u16 *data_cur)
359 {
360 int ret;
361 u8 status;
362
363 mutex_lock(&adc->lock);
364
365 ret = adc7_configure(adc, prop);
366 if (ret) {
367 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
368 goto unlock;
369 }
370
371 /* No support for polling mode at present */
372 wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
373
374 ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
375 if (ret)
376 goto unlock;
377
378 if (status & ADC5_USR_STATUS1_CONV_FAULT) {
379 dev_err(adc->dev, "Unexpected conversion fault\n");
380 ret = -EIO;
381 goto unlock;
382 }
383
384 ret = adc5_read_voltage_data(adc, data_volt);
385
386 unlock:
387 mutex_unlock(&adc->lock);
388
389 return ret;
390 }
391
392 typedef int (*adc_do_conversion)(struct adc5_chip *adc,
393 struct adc5_channel_prop *prop,
394 struct iio_chan_spec const *chan,
395 u16 *data_volt, u16 *data_cur);
396
adc5_isr(int irq,void * dev_id)397 static irqreturn_t adc5_isr(int irq, void *dev_id)
398 {
399 struct adc5_chip *adc = dev_id;
400
401 complete(&adc->complete);
402
403 return IRQ_HANDLED;
404 }
405
adc5_of_xlate(struct iio_dev * indio_dev,const struct of_phandle_args * iiospec)406 static int adc5_of_xlate(struct iio_dev *indio_dev,
407 const struct of_phandle_args *iiospec)
408 {
409 struct adc5_chip *adc = iio_priv(indio_dev);
410 int i;
411
412 for (i = 0; i < adc->nchannels; i++)
413 if (adc->chan_props[i].channel == iiospec->args[0])
414 return i;
415
416 return -EINVAL;
417 }
418
adc7_of_xlate(struct iio_dev * indio_dev,const struct of_phandle_args * iiospec)419 static int adc7_of_xlate(struct iio_dev *indio_dev,
420 const struct of_phandle_args *iiospec)
421 {
422 struct adc5_chip *adc = iio_priv(indio_dev);
423 int i, v_channel;
424
425 for (i = 0; i < adc->nchannels; i++) {
426 v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
427 adc->chan_props[i].channel;
428 if (v_channel == iiospec->args[0])
429 return i;
430 }
431
432 return -EINVAL;
433 }
434
adc_read_raw_common(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask,adc_do_conversion do_conv)435 static int adc_read_raw_common(struct iio_dev *indio_dev,
436 struct iio_chan_spec const *chan, int *val, int *val2,
437 long mask, adc_do_conversion do_conv)
438 {
439 struct adc5_chip *adc = iio_priv(indio_dev);
440 struct adc5_channel_prop *prop;
441 u16 adc_code_volt, adc_code_cur;
442 int ret;
443
444 prop = &adc->chan_props[chan->address];
445
446 switch (mask) {
447 case IIO_CHAN_INFO_PROCESSED:
448 ret = do_conv(adc, prop, chan,
449 &adc_code_volt, &adc_code_cur);
450 if (ret)
451 return ret;
452
453 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
454 prop->prescale,
455 adc->data,
456 adc_code_volt, val);
457 if (ret)
458 return ret;
459
460 return IIO_VAL_INT;
461 default:
462 return -EINVAL;
463 }
464 }
465
adc5_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)466 static int adc5_read_raw(struct iio_dev *indio_dev,
467 struct iio_chan_spec const *chan, int *val, int *val2,
468 long mask)
469 {
470 return adc_read_raw_common(indio_dev, chan, val, val2,
471 mask, adc5_do_conversion);
472 }
473
adc7_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)474 static int adc7_read_raw(struct iio_dev *indio_dev,
475 struct iio_chan_spec const *chan, int *val, int *val2,
476 long mask)
477 {
478 return adc_read_raw_common(indio_dev, chan, val, val2,
479 mask, adc7_do_conversion);
480 }
481
482 static const struct iio_info adc5_info = {
483 .read_raw = adc5_read_raw,
484 .of_xlate = adc5_of_xlate,
485 };
486
487 static const struct iio_info adc7_info = {
488 .read_raw = adc7_read_raw,
489 .of_xlate = adc7_of_xlate,
490 };
491
492 struct adc5_channels {
493 const char *datasheet_name;
494 unsigned int prescale_index;
495 enum iio_chan_type type;
496 long info_mask;
497 enum vadc_scale_fn_type scale_fn_type;
498 };
499
500 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
501 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \
502 { \
503 .datasheet_name = _dname, \
504 .prescale_index = _pre, \
505 .type = _type, \
506 .info_mask = _mask, \
507 .scale_fn_type = _scale, \
508 }, \
509
510 #define ADC5_CHAN_TEMP(_dname, _pre, _scale) \
511 ADC5_CHAN(_dname, IIO_TEMP, \
512 BIT(IIO_CHAN_INFO_PROCESSED), \
513 _pre, _scale) \
514
515 #define ADC5_CHAN_VOLT(_dname, _pre, _scale) \
516 ADC5_CHAN(_dname, IIO_VOLTAGE, \
517 BIT(IIO_CHAN_INFO_PROCESSED), \
518 _pre, _scale) \
519
520 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
521 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
522 SCALE_HW_CALIB_DEFAULT)
523 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
524 SCALE_HW_CALIB_DEFAULT)
525 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
526 SCALE_HW_CALIB_DEFAULT)
527 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
528 SCALE_HW_CALIB_DEFAULT)
529 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
530 SCALE_HW_CALIB_PMIC_THERM)
531 [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
532 SCALE_HW_CALIB_DEFAULT)
533 [ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
534 SCALE_HW_CALIB_DEFAULT)
535 [ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0,
536 SCALE_HW_CALIB_PM5_CHG_TEMP)
537 /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
538 [ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 1,
539 SCALE_HW_CALIB_DEFAULT)
540 [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3,
541 SCALE_HW_CALIB_DEFAULT)
542 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
543 SCALE_HW_CALIB_XOTHERM)
544 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
545 SCALE_HW_CALIB_THERM_100K_PULLUP)
546 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
547 SCALE_HW_CALIB_THERM_100K_PULLUP)
548 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
549 SCALE_HW_CALIB_THERM_100K_PULLUP)
550 [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0,
551 SCALE_HW_CALIB_PM5_SMB_TEMP)
552 };
553
554 static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
555 [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
556 SCALE_HW_CALIB_DEFAULT)
557 [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
558 SCALE_HW_CALIB_DEFAULT)
559 [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
560 SCALE_HW_CALIB_DEFAULT)
561 [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
562 SCALE_HW_CALIB_DEFAULT)
563 [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
564 SCALE_HW_CALIB_PMIC_THERM_PM7)
565 [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
566 SCALE_HW_CALIB_THERM_100K_PU_PM7)
567 [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
568 SCALE_HW_CALIB_THERM_100K_PU_PM7)
569 [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
570 SCALE_HW_CALIB_THERM_100K_PU_PM7)
571 [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
572 SCALE_HW_CALIB_THERM_100K_PU_PM7)
573 [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
574 SCALE_HW_CALIB_THERM_100K_PU_PM7)
575 [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
576 SCALE_HW_CALIB_THERM_100K_PU_PM7)
577 [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
578 SCALE_HW_CALIB_THERM_100K_PU_PM7)
579 [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
580 SCALE_HW_CALIB_THERM_100K_PU_PM7)
581 [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
582 SCALE_HW_CALIB_THERM_100K_PU_PM7)
583 [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
584 SCALE_HW_CALIB_THERM_100K_PU_PM7)
585 };
586
587 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
588 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
589 SCALE_HW_CALIB_DEFAULT)
590 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
591 SCALE_HW_CALIB_DEFAULT)
592 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
593 SCALE_HW_CALIB_DEFAULT)
594 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
595 SCALE_HW_CALIB_DEFAULT)
596 [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1,
597 SCALE_HW_CALIB_DEFAULT)
598 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
599 SCALE_HW_CALIB_PMIC_THERM)
600 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
601 SCALE_HW_CALIB_THERM_100K_PULLUP)
602 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
603 SCALE_HW_CALIB_THERM_100K_PULLUP)
604 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
605 SCALE_HW_CALIB_THERM_100K_PULLUP)
606 [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
607 SCALE_HW_CALIB_THERM_100K_PULLUP)
608 [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
609 SCALE_HW_CALIB_THERM_100K_PULLUP)
610 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
611 SCALE_HW_CALIB_THERM_100K_PULLUP)
612 };
613
adc5_get_dt_channel_data(struct adc5_chip * adc,struct adc5_channel_prop * prop,struct device_node * node,const struct adc5_data * data)614 static int adc5_get_dt_channel_data(struct adc5_chip *adc,
615 struct adc5_channel_prop *prop,
616 struct device_node *node,
617 const struct adc5_data *data)
618 {
619 const char *name = node->name, *channel_name;
620 u32 chan, value, varr[2];
621 u32 sid = 0;
622 int ret;
623 struct device *dev = adc->dev;
624
625 ret = of_property_read_u32(node, "reg", &chan);
626 if (ret) {
627 dev_err(dev, "invalid channel number %s\n", name);
628 return ret;
629 }
630
631 /* Value read from "reg" is virtual channel number */
632
633 /* virtual channel number = sid << 8 | channel number */
634
635 if (adc->data->info == &adc7_info) {
636 sid = chan >> ADC_CHANNEL_OFFSET;
637 chan = chan & ADC_CHANNEL_MASK;
638 }
639
640 if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
641 !data->adc_chans[chan].datasheet_name) {
642 dev_err(dev, "%s invalid channel number %d\n", name, chan);
643 return -EINVAL;
644 }
645
646 /* the channel has DT description */
647 prop->channel = chan;
648 prop->sid = sid;
649
650 channel_name = of_get_property(node,
651 "label", NULL) ? : node->name;
652 if (!channel_name) {
653 dev_err(dev, "Invalid channel name\n");
654 return -EINVAL;
655 }
656 prop->datasheet_name = channel_name;
657
658 ret = of_property_read_u32(node, "qcom,decimation", &value);
659 if (!ret) {
660 ret = qcom_adc5_decimation_from_dt(value, data->decimation);
661 if (ret < 0) {
662 dev_err(dev, "%02x invalid decimation %d\n",
663 chan, value);
664 return ret;
665 }
666 prop->decimation = ret;
667 } else {
668 prop->decimation = ADC5_DECIMATION_DEFAULT;
669 }
670
671 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
672 if (!ret) {
673 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
674 if (ret < 0) {
675 dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
676 chan, varr[0], varr[1]);
677 return ret;
678 }
679 prop->prescale = ret;
680 } else {
681 prop->prescale =
682 adc->data->adc_chans[prop->channel].prescale_index;
683 }
684
685 ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
686 if (!ret) {
687 u8 dig_version[2];
688
689 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
690 sizeof(dig_version));
691 if (ret) {
692 dev_err(dev, "Invalid dig version read %d\n", ret);
693 return ret;
694 }
695
696 dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0],
697 dig_version[1]);
698 /* Digital controller >= 5.3 have hw_settle_2 option */
699 if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
700 dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
701 adc->data->info == &adc7_info)
702 ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_2);
703 else
704 ret = qcom_adc5_hw_settle_time_from_dt(value, data->hw_settle_1);
705
706 if (ret < 0) {
707 dev_err(dev, "%02x invalid hw-settle-time %d us\n",
708 chan, value);
709 return ret;
710 }
711 prop->hw_settle_time = ret;
712 } else {
713 prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
714 }
715
716 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
717 if (!ret) {
718 ret = qcom_adc5_avg_samples_from_dt(value);
719 if (ret < 0) {
720 dev_err(dev, "%02x invalid avg-samples %d\n",
721 chan, value);
722 return ret;
723 }
724 prop->avg_samples = ret;
725 } else {
726 prop->avg_samples = VADC_DEF_AVG_SAMPLES;
727 }
728
729 if (of_property_read_bool(node, "qcom,ratiometric"))
730 prop->cal_method = ADC5_RATIOMETRIC_CAL;
731 else
732 prop->cal_method = ADC5_ABSOLUTE_CAL;
733
734 /*
735 * Default to using timer calibration. Using a fresh calibration value
736 * for every conversion will increase the overall time for a request.
737 */
738 prop->cal_val = ADC5_TIMER_CAL;
739
740 dev_dbg(dev, "%02x name %s\n", chan, name);
741
742 return 0;
743 }
744
745 static const struct adc5_data adc5_data_pmic = {
746 .full_scale_code_volt = 0x70e4,
747 .full_scale_code_cur = 0x2710,
748 .adc_chans = adc5_chans_pmic,
749 .info = &adc5_info,
750 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
751 {250, 420, 840},
752 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
753 {15, 100, 200, 300, 400, 500, 600, 700,
754 800, 900, 1, 2, 4, 6, 8, 10},
755 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
756 {15, 100, 200, 300, 400, 500, 600, 700,
757 1, 2, 4, 8, 16, 32, 64, 128},
758 };
759
760 static const struct adc5_data adc7_data_pmic = {
761 .full_scale_code_volt = 0x70e4,
762 .adc_chans = adc7_chans_pmic,
763 .info = &adc7_info,
764 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
765 {85, 340, 1360},
766 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
767 {15, 100, 200, 300, 400, 500, 600, 700,
768 1000, 2000, 4000, 8000, 16000, 32000,
769 64000, 128000},
770 };
771
772 static const struct adc5_data adc5_data_pmic_rev2 = {
773 .full_scale_code_volt = 0x4000,
774 .full_scale_code_cur = 0x1800,
775 .adc_chans = adc5_chans_rev2,
776 .info = &adc5_info,
777 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
778 {256, 512, 1024},
779 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
780 {0, 100, 200, 300, 400, 500, 600, 700,
781 800, 900, 1, 2, 4, 6, 8, 10},
782 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
783 {15, 100, 200, 300, 400, 500, 600, 700,
784 1, 2, 4, 8, 16, 32, 64, 128},
785 };
786
787 static const struct of_device_id adc5_match_table[] = {
788 {
789 .compatible = "qcom,spmi-adc5",
790 .data = &adc5_data_pmic,
791 },
792 {
793 .compatible = "qcom,spmi-adc7",
794 .data = &adc7_data_pmic,
795 },
796 {
797 .compatible = "qcom,spmi-adc-rev2",
798 .data = &adc5_data_pmic_rev2,
799 },
800 { }
801 };
802 MODULE_DEVICE_TABLE(of, adc5_match_table);
803
adc5_get_dt_data(struct adc5_chip * adc,struct device_node * node)804 static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
805 {
806 const struct adc5_channels *adc_chan;
807 struct iio_chan_spec *iio_chan;
808 struct adc5_channel_prop prop, *chan_props;
809 struct device_node *child;
810 unsigned int index = 0;
811 int ret;
812
813 adc->nchannels = of_get_available_child_count(node);
814 if (!adc->nchannels)
815 return -EINVAL;
816
817 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
818 sizeof(*adc->iio_chans), GFP_KERNEL);
819 if (!adc->iio_chans)
820 return -ENOMEM;
821
822 adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
823 sizeof(*adc->chan_props), GFP_KERNEL);
824 if (!adc->chan_props)
825 return -ENOMEM;
826
827 chan_props = adc->chan_props;
828 iio_chan = adc->iio_chans;
829 adc->data = of_device_get_match_data(adc->dev);
830 if (!adc->data)
831 adc->data = &adc5_data_pmic;
832
833 for_each_available_child_of_node(node, child) {
834 ret = adc5_get_dt_channel_data(adc, &prop, child, adc->data);
835 if (ret) {
836 of_node_put(child);
837 return ret;
838 }
839
840 prop.scale_fn_type =
841 adc->data->adc_chans[prop.channel].scale_fn_type;
842 *chan_props = prop;
843 adc_chan = &adc->data->adc_chans[prop.channel];
844
845 iio_chan->channel = prop.channel;
846 iio_chan->datasheet_name = prop.datasheet_name;
847 iio_chan->extend_name = prop.datasheet_name;
848 iio_chan->info_mask_separate = adc_chan->info_mask;
849 iio_chan->type = adc_chan->type;
850 iio_chan->address = index;
851 iio_chan++;
852 chan_props++;
853 index++;
854 }
855
856 return 0;
857 }
858
adc5_probe(struct platform_device * pdev)859 static int adc5_probe(struct platform_device *pdev)
860 {
861 struct device_node *node = pdev->dev.of_node;
862 struct device *dev = &pdev->dev;
863 struct iio_dev *indio_dev;
864 struct adc5_chip *adc;
865 struct regmap *regmap;
866 int ret, irq_eoc;
867 u32 reg;
868
869 regmap = dev_get_regmap(dev->parent, NULL);
870 if (!regmap)
871 return -ENODEV;
872
873 ret = of_property_read_u32(node, "reg", ®);
874 if (ret < 0)
875 return ret;
876
877 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
878 if (!indio_dev)
879 return -ENOMEM;
880
881 adc = iio_priv(indio_dev);
882 adc->regmap = regmap;
883 adc->dev = dev;
884 adc->base = reg;
885
886 init_completion(&adc->complete);
887 mutex_init(&adc->lock);
888
889 ret = adc5_get_dt_data(adc, node);
890 if (ret) {
891 dev_err(dev, "adc get dt data failed\n");
892 return ret;
893 }
894
895 irq_eoc = platform_get_irq(pdev, 0);
896 if (irq_eoc < 0) {
897 if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
898 return irq_eoc;
899 adc->poll_eoc = true;
900 } else {
901 ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
902 "pm-adc5", adc);
903 if (ret)
904 return ret;
905 }
906
907 indio_dev->name = pdev->name;
908 indio_dev->modes = INDIO_DIRECT_MODE;
909 indio_dev->info = adc->data->info;
910 indio_dev->channels = adc->iio_chans;
911 indio_dev->num_channels = adc->nchannels;
912
913 return devm_iio_device_register(dev, indio_dev);
914 }
915
916 static struct platform_driver adc5_driver = {
917 .driver = {
918 .name = "qcom-spmi-adc5",
919 .of_match_table = adc5_match_table,
920 },
921 .probe = adc5_probe,
922 };
923 module_platform_driver(adc5_driver);
924
925 MODULE_ALIAS("platform:qcom-spmi-adc5");
926 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
927 MODULE_LICENSE("GPL v2");
928