1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Xilinx XADC driver
4 *
5 * Copyright 2013-2014 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 *
8 * Documentation for the parts can be found at:
9 * - XADC hardmacro: Xilinx UG480
10 * - ZYNQ XADC interface: Xilinx UG585
11 * - AXI XADC interface: Xilinx PG019
12 */
13
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/overflow.h>
23 #include <linux/platform_device.h>
24 #include <linux/slab.h>
25 #include <linux/sysfs.h>
26
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/events.h>
29 #include <linux/iio/iio.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/trigger.h>
32 #include <linux/iio/trigger_consumer.h>
33 #include <linux/iio/triggered_buffer.h>
34
35 #include "xilinx-xadc.h"
36
37 static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
38
39 /* ZYNQ register definitions */
40 #define XADC_ZYNQ_REG_CFG 0x00
41 #define XADC_ZYNQ_REG_INTSTS 0x04
42 #define XADC_ZYNQ_REG_INTMSK 0x08
43 #define XADC_ZYNQ_REG_STATUS 0x0c
44 #define XADC_ZYNQ_REG_CFIFO 0x10
45 #define XADC_ZYNQ_REG_DFIFO 0x14
46 #define XADC_ZYNQ_REG_CTL 0x18
47
48 #define XADC_ZYNQ_CFG_ENABLE BIT(31)
49 #define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
50 #define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
51 #define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
52 #define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
53 #define XADC_ZYNQ_CFG_WEDGE BIT(13)
54 #define XADC_ZYNQ_CFG_REDGE BIT(12)
55 #define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
56 #define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
57 #define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
58 #define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
59 #define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
60 #define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
61 #define XADC_ZYNQ_CFG_IGAP(x) (x)
62
63 #define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
64 #define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
65 #define XADC_ZYNQ_INT_ALARM_MASK 0xff
66 #define XADC_ZYNQ_INT_ALARM_OFFSET 0
67
68 #define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
69 #define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
70 #define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
71 #define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
72 #define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
73 #define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
74 #define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
75 #define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
76 #define XADC_ZYNQ_STATUS_OT BIT(7)
77 #define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
78
79 #define XADC_ZYNQ_CTL_RESET BIT(4)
80
81 #define XADC_ZYNQ_CMD_NOP 0x00
82 #define XADC_ZYNQ_CMD_READ 0x01
83 #define XADC_ZYNQ_CMD_WRITE 0x02
84
85 #define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
86
87 /* AXI register definitions */
88 #define XADC_AXI_REG_RESET 0x00
89 #define XADC_AXI_REG_STATUS 0x04
90 #define XADC_AXI_REG_ALARM_STATUS 0x08
91 #define XADC_AXI_REG_CONVST 0x0c
92 #define XADC_AXI_REG_XADC_RESET 0x10
93 #define XADC_AXI_REG_GIER 0x5c
94 #define XADC_AXI_REG_IPISR 0x60
95 #define XADC_AXI_REG_IPIER 0x68
96
97 /* 7 Series */
98 #define XADC_7S_AXI_ADC_REG_OFFSET 0x200
99
100 /* UltraScale */
101 #define XADC_US_AXI_ADC_REG_OFFSET 0x400
102
103 #define XADC_AXI_RESET_MAGIC 0xa
104 #define XADC_AXI_GIER_ENABLE BIT(31)
105
106 #define XADC_AXI_INT_EOS BIT(4)
107 #define XADC_AXI_INT_ALARM_MASK 0x3c0f
108
109 #define XADC_FLAGS_BUFFERED BIT(0)
110
111 /*
112 * The XADC hardware supports a samplerate of up to 1MSPS. Unfortunately it does
113 * not have a hardware FIFO. Which means an interrupt is generated for each
114 * conversion sequence. At 1MSPS sample rate the CPU in ZYNQ7000 is completely
115 * overloaded by the interrupts that it soft-lockups. For this reason the driver
116 * limits the maximum samplerate 150kSPS. At this rate the CPU is fairly busy,
117 * but still responsive.
118 */
119 #define XADC_MAX_SAMPLERATE 150000
120
xadc_write_reg(struct xadc * xadc,unsigned int reg,uint32_t val)121 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
122 uint32_t val)
123 {
124 writel(val, xadc->base + reg);
125 }
126
xadc_read_reg(struct xadc * xadc,unsigned int reg,uint32_t * val)127 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
128 uint32_t *val)
129 {
130 *val = readl(xadc->base + reg);
131 }
132
133 /*
134 * The ZYNQ interface uses two asynchronous FIFOs for communication with the
135 * XADC. Reads and writes to the XADC register are performed by submitting a
136 * request to the command FIFO (CFIFO), once the request has been completed the
137 * result can be read from the data FIFO (DFIFO). The method currently used in
138 * this driver is to submit the request for a read/write operation, then go to
139 * sleep and wait for an interrupt that signals that a response is available in
140 * the data FIFO.
141 */
142
xadc_zynq_write_fifo(struct xadc * xadc,uint32_t * cmd,unsigned int n)143 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
144 unsigned int n)
145 {
146 unsigned int i;
147
148 for (i = 0; i < n; i++)
149 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
150 }
151
xadc_zynq_drain_fifo(struct xadc * xadc)152 static void xadc_zynq_drain_fifo(struct xadc *xadc)
153 {
154 uint32_t status, tmp;
155
156 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
157
158 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
159 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
160 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
161 }
162 }
163
xadc_zynq_update_intmsk(struct xadc * xadc,unsigned int mask,unsigned int val)164 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
165 unsigned int val)
166 {
167 xadc->zynq_intmask &= ~mask;
168 xadc->zynq_intmask |= val;
169
170 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
171 xadc->zynq_intmask | xadc->zynq_masked_alarm);
172 }
173
xadc_zynq_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)174 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
175 uint16_t val)
176 {
177 uint32_t cmd[1];
178 uint32_t tmp;
179 int ret;
180
181 spin_lock_irq(&xadc->lock);
182 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
183 XADC_ZYNQ_INT_DFIFO_GTH);
184
185 reinit_completion(&xadc->completion);
186
187 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
188 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
189 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
190 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
191 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
192 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
193
194 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
195 spin_unlock_irq(&xadc->lock);
196
197 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
198 if (ret == 0)
199 ret = -EIO;
200 else
201 ret = 0;
202
203 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
204
205 return ret;
206 }
207
xadc_zynq_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)208 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
209 uint16_t *val)
210 {
211 uint32_t cmd[2];
212 uint32_t resp, tmp;
213 int ret;
214
215 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
216 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
217
218 spin_lock_irq(&xadc->lock);
219 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
220 XADC_ZYNQ_INT_DFIFO_GTH);
221 xadc_zynq_drain_fifo(xadc);
222 reinit_completion(&xadc->completion);
223
224 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
225 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
226 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
227 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
228 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
229
230 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
231 spin_unlock_irq(&xadc->lock);
232 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
233 if (ret == 0)
234 ret = -EIO;
235 if (ret < 0)
236 return ret;
237
238 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
239 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
240
241 *val = resp & 0xffff;
242
243 return 0;
244 }
245
xadc_zynq_transform_alarm(unsigned int alarm)246 static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
247 {
248 return ((alarm & 0x80) >> 4) |
249 ((alarm & 0x78) << 1) |
250 (alarm & 0x07);
251 }
252
253 /*
254 * The ZYNQ threshold interrupts are level sensitive. Since we can't make the
255 * threshold condition go way from within the interrupt handler, this means as
256 * soon as a threshold condition is present we would enter the interrupt handler
257 * again and again. To work around this we mask all active thresholds interrupts
258 * in the interrupt handler and start a timer. In this timer we poll the
259 * interrupt status and only if the interrupt is inactive we unmask it again.
260 */
xadc_zynq_unmask_worker(struct work_struct * work)261 static void xadc_zynq_unmask_worker(struct work_struct *work)
262 {
263 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
264 unsigned int misc_sts, unmask;
265
266 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
267
268 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
269
270 spin_lock_irq(&xadc->lock);
271
272 /* Clear those bits which are not active anymore */
273 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
274 xadc->zynq_masked_alarm &= misc_sts;
275
276 /* Also clear those which are masked out anyway */
277 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
278
279 /* Clear the interrupts before we unmask them */
280 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
281
282 xadc_zynq_update_intmsk(xadc, 0, 0);
283
284 spin_unlock_irq(&xadc->lock);
285
286 /* if still pending some alarm re-trigger the timer */
287 if (xadc->zynq_masked_alarm) {
288 schedule_delayed_work(&xadc->zynq_unmask_work,
289 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
290 }
291
292 }
293
xadc_zynq_interrupt_handler(int irq,void * devid)294 static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
295 {
296 struct iio_dev *indio_dev = devid;
297 struct xadc *xadc = iio_priv(indio_dev);
298 uint32_t status;
299
300 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
301
302 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
303
304 if (!status)
305 return IRQ_NONE;
306
307 spin_lock(&xadc->lock);
308
309 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
310
311 if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
312 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
313 XADC_ZYNQ_INT_DFIFO_GTH);
314 complete(&xadc->completion);
315 }
316
317 status &= XADC_ZYNQ_INT_ALARM_MASK;
318 if (status) {
319 xadc->zynq_masked_alarm |= status;
320 /*
321 * mask the current event interrupt,
322 * unmask it when the interrupt is no more active.
323 */
324 xadc_zynq_update_intmsk(xadc, 0, 0);
325
326 xadc_handle_events(indio_dev,
327 xadc_zynq_transform_alarm(status));
328
329 /* unmask the required interrupts in timer. */
330 schedule_delayed_work(&xadc->zynq_unmask_work,
331 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
332 }
333 spin_unlock(&xadc->lock);
334
335 return IRQ_HANDLED;
336 }
337
338 #define XADC_ZYNQ_TCK_RATE_MAX 50000000
339 #define XADC_ZYNQ_IGAP_DEFAULT 20
340 #define XADC_ZYNQ_PCAP_RATE_MAX 200000000
341
xadc_zynq_setup(struct platform_device * pdev,struct iio_dev * indio_dev,int irq)342 static int xadc_zynq_setup(struct platform_device *pdev,
343 struct iio_dev *indio_dev, int irq)
344 {
345 struct xadc *xadc = iio_priv(indio_dev);
346 unsigned long pcap_rate;
347 unsigned int tck_div;
348 unsigned int div;
349 unsigned int igap;
350 unsigned int tck_rate;
351 int ret;
352
353 /* TODO: Figure out how to make igap and tck_rate configurable */
354 igap = XADC_ZYNQ_IGAP_DEFAULT;
355 tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
356
357 xadc->zynq_intmask = ~0;
358
359 pcap_rate = clk_get_rate(xadc->clk);
360 if (!pcap_rate)
361 return -EINVAL;
362
363 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
364 ret = clk_set_rate(xadc->clk,
365 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
366 if (ret)
367 return ret;
368 }
369
370 if (tck_rate > pcap_rate / 2) {
371 div = 2;
372 } else {
373 div = pcap_rate / tck_rate;
374 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
375 div++;
376 }
377
378 if (div <= 3)
379 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
380 else if (div <= 7)
381 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
382 else if (div <= 15)
383 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
384 else
385 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
386
387 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
388 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
389 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
390 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
391 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
392 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
393 tck_div | XADC_ZYNQ_CFG_IGAP(igap));
394
395 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
396 ret = clk_set_rate(xadc->clk, pcap_rate);
397 if (ret)
398 return ret;
399 }
400
401 return 0;
402 }
403
xadc_zynq_get_dclk_rate(struct xadc * xadc)404 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
405 {
406 unsigned int div;
407 uint32_t val;
408
409 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
410
411 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
412 case XADC_ZYNQ_CFG_TCKRATE_DIV4:
413 div = 4;
414 break;
415 case XADC_ZYNQ_CFG_TCKRATE_DIV8:
416 div = 8;
417 break;
418 case XADC_ZYNQ_CFG_TCKRATE_DIV16:
419 div = 16;
420 break;
421 default:
422 div = 2;
423 break;
424 }
425
426 return clk_get_rate(xadc->clk) / div;
427 }
428
xadc_zynq_update_alarm(struct xadc * xadc,unsigned int alarm)429 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
430 {
431 unsigned long flags;
432 uint32_t status;
433
434 /* Move OT to bit 7 */
435 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
436
437 spin_lock_irqsave(&xadc->lock, flags);
438
439 /* Clear previous interrupts if any. */
440 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
441 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
442
443 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
444 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
445
446 spin_unlock_irqrestore(&xadc->lock, flags);
447 }
448
449 static const struct xadc_ops xadc_zynq_ops = {
450 .read = xadc_zynq_read_adc_reg,
451 .write = xadc_zynq_write_adc_reg,
452 .setup = xadc_zynq_setup,
453 .get_dclk_rate = xadc_zynq_get_dclk_rate,
454 .interrupt_handler = xadc_zynq_interrupt_handler,
455 .update_alarm = xadc_zynq_update_alarm,
456 .type = XADC_TYPE_S7,
457 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
458 .temp_scale = 503975,
459 .temp_offset = 273150,
460 };
461
462 static const unsigned int xadc_axi_reg_offsets[] = {
463 [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
464 [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
465 };
466
xadc_axi_read_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t * val)467 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
468 uint16_t *val)
469 {
470 uint32_t val32;
471
472 xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
473 &val32);
474 *val = val32 & 0xffff;
475
476 return 0;
477 }
478
xadc_axi_write_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t val)479 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
480 uint16_t val)
481 {
482 xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
483 val);
484
485 return 0;
486 }
487
xadc_axi_setup(struct platform_device * pdev,struct iio_dev * indio_dev,int irq)488 static int xadc_axi_setup(struct platform_device *pdev,
489 struct iio_dev *indio_dev, int irq)
490 {
491 struct xadc *xadc = iio_priv(indio_dev);
492
493 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
494 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
495
496 return 0;
497 }
498
xadc_axi_interrupt_handler(int irq,void * devid)499 static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
500 {
501 struct iio_dev *indio_dev = devid;
502 struct xadc *xadc = iio_priv(indio_dev);
503 uint32_t status, mask;
504 unsigned int events;
505
506 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
507 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
508 status &= mask;
509
510 if (!status)
511 return IRQ_NONE;
512
513 if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
514 iio_trigger_poll(xadc->trigger);
515
516 if (status & XADC_AXI_INT_ALARM_MASK) {
517 /*
518 * The order of the bits in the AXI-XADC status register does
519 * not match the order of the bits in the XADC alarm enable
520 * register. xadc_handle_events() expects the events to be in
521 * the same order as the XADC alarm enable register.
522 */
523 events = (status & 0x000e) >> 1;
524 events |= (status & 0x0001) << 3;
525 events |= (status & 0x3c00) >> 6;
526 xadc_handle_events(indio_dev, events);
527 }
528
529 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
530
531 return IRQ_HANDLED;
532 }
533
xadc_axi_update_alarm(struct xadc * xadc,unsigned int alarm)534 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
535 {
536 uint32_t val;
537 unsigned long flags;
538
539 /*
540 * The order of the bits in the AXI-XADC status register does not match
541 * the order of the bits in the XADC alarm enable register. We get
542 * passed the alarm mask in the same order as in the XADC alarm enable
543 * register.
544 */
545 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
546 ((alarm & 0xf0) << 6);
547
548 spin_lock_irqsave(&xadc->lock, flags);
549 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
550 val &= ~XADC_AXI_INT_ALARM_MASK;
551 val |= alarm;
552 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
553 spin_unlock_irqrestore(&xadc->lock, flags);
554 }
555
xadc_axi_get_dclk(struct xadc * xadc)556 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
557 {
558 return clk_get_rate(xadc->clk);
559 }
560
561 static const struct xadc_ops xadc_7s_axi_ops = {
562 .read = xadc_axi_read_adc_reg,
563 .write = xadc_axi_write_adc_reg,
564 .setup = xadc_axi_setup,
565 .get_dclk_rate = xadc_axi_get_dclk,
566 .update_alarm = xadc_axi_update_alarm,
567 .interrupt_handler = xadc_axi_interrupt_handler,
568 .flags = XADC_FLAGS_BUFFERED,
569 .type = XADC_TYPE_S7,
570 /* Temp in C = (val * 503.975) / 2**bits - 273.15 */
571 .temp_scale = 503975,
572 .temp_offset = 273150,
573 };
574
575 static const struct xadc_ops xadc_us_axi_ops = {
576 .read = xadc_axi_read_adc_reg,
577 .write = xadc_axi_write_adc_reg,
578 .setup = xadc_axi_setup,
579 .get_dclk_rate = xadc_axi_get_dclk,
580 .update_alarm = xadc_axi_update_alarm,
581 .interrupt_handler = xadc_axi_interrupt_handler,
582 .flags = XADC_FLAGS_BUFFERED,
583 .type = XADC_TYPE_US,
584 /**
585 * Values below are for UltraScale+ (SYSMONE4) using internal reference.
586 * See https://docs.xilinx.com/v/u/en-US/ug580-ultrascale-sysmon
587 */
588 .temp_scale = 509314,
589 .temp_offset = 280231,
590 };
591
_xadc_update_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t mask,uint16_t val)592 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
593 uint16_t mask, uint16_t val)
594 {
595 uint16_t tmp;
596 int ret;
597
598 ret = _xadc_read_adc_reg(xadc, reg, &tmp);
599 if (ret)
600 return ret;
601
602 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
603 }
604
xadc_update_adc_reg(struct xadc * xadc,unsigned int reg,uint16_t mask,uint16_t val)605 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
606 uint16_t mask, uint16_t val)
607 {
608 int ret;
609
610 mutex_lock(&xadc->mutex);
611 ret = _xadc_update_adc_reg(xadc, reg, mask, val);
612 mutex_unlock(&xadc->mutex);
613
614 return ret;
615 }
616
xadc_get_dclk_rate(struct xadc * xadc)617 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
618 {
619 return xadc->ops->get_dclk_rate(xadc);
620 }
621
xadc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * mask)622 static int xadc_update_scan_mode(struct iio_dev *indio_dev,
623 const unsigned long *mask)
624 {
625 struct xadc *xadc = iio_priv(indio_dev);
626 size_t new_size, n;
627 void *data;
628
629 n = bitmap_weight(mask, indio_dev->masklength);
630
631 if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))
632 return -ENOMEM;
633
634 data = devm_krealloc(indio_dev->dev.parent, xadc->data,
635 new_size, GFP_KERNEL);
636 if (!data)
637 return -ENOMEM;
638
639 memset(data, 0, new_size);
640 xadc->data = data;
641
642 return 0;
643 }
644
xadc_scan_index_to_channel(unsigned int scan_index)645 static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
646 {
647 switch (scan_index) {
648 case 5:
649 return XADC_REG_VCCPINT;
650 case 6:
651 return XADC_REG_VCCPAUX;
652 case 7:
653 return XADC_REG_VCCO_DDR;
654 case 8:
655 return XADC_REG_TEMP;
656 case 9:
657 return XADC_REG_VCCINT;
658 case 10:
659 return XADC_REG_VCCAUX;
660 case 11:
661 return XADC_REG_VPVN;
662 case 12:
663 return XADC_REG_VREFP;
664 case 13:
665 return XADC_REG_VREFN;
666 case 14:
667 return XADC_REG_VCCBRAM;
668 default:
669 return XADC_REG_VAUX(scan_index - 16);
670 }
671 }
672
xadc_trigger_handler(int irq,void * p)673 static irqreturn_t xadc_trigger_handler(int irq, void *p)
674 {
675 struct iio_poll_func *pf = p;
676 struct iio_dev *indio_dev = pf->indio_dev;
677 struct xadc *xadc = iio_priv(indio_dev);
678 unsigned int chan;
679 int i, j;
680
681 if (!xadc->data)
682 goto out;
683
684 j = 0;
685 for_each_set_bit(i, indio_dev->active_scan_mask,
686 indio_dev->masklength) {
687 chan = xadc_scan_index_to_channel(i);
688 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
689 j++;
690 }
691
692 iio_push_to_buffers(indio_dev, xadc->data);
693
694 out:
695 iio_trigger_notify_done(indio_dev->trig);
696
697 return IRQ_HANDLED;
698 }
699
xadc_trigger_set_state(struct iio_trigger * trigger,bool state)700 static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
701 {
702 struct xadc *xadc = iio_trigger_get_drvdata(trigger);
703 unsigned long flags;
704 unsigned int convst;
705 unsigned int val;
706 int ret = 0;
707
708 mutex_lock(&xadc->mutex);
709
710 if (state) {
711 /* Only one of the two triggers can be active at a time. */
712 if (xadc->trigger != NULL) {
713 ret = -EBUSY;
714 goto err_out;
715 } else {
716 xadc->trigger = trigger;
717 if (trigger == xadc->convst_trigger)
718 convst = XADC_CONF0_EC;
719 else
720 convst = 0;
721 }
722 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
723 convst);
724 if (ret)
725 goto err_out;
726 } else {
727 xadc->trigger = NULL;
728 }
729
730 spin_lock_irqsave(&xadc->lock, flags);
731 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
732 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
733 if (state)
734 val |= XADC_AXI_INT_EOS;
735 else
736 val &= ~XADC_AXI_INT_EOS;
737 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
738 spin_unlock_irqrestore(&xadc->lock, flags);
739
740 err_out:
741 mutex_unlock(&xadc->mutex);
742
743 return ret;
744 }
745
746 static const struct iio_trigger_ops xadc_trigger_ops = {
747 .set_trigger_state = &xadc_trigger_set_state,
748 };
749
xadc_alloc_trigger(struct iio_dev * indio_dev,const char * name)750 static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
751 const char *name)
752 {
753 struct device *dev = indio_dev->dev.parent;
754 struct iio_trigger *trig;
755 int ret;
756
757 trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
758 iio_device_id(indio_dev), name);
759 if (trig == NULL)
760 return ERR_PTR(-ENOMEM);
761
762 trig->ops = &xadc_trigger_ops;
763 iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
764
765 ret = devm_iio_trigger_register(dev, trig);
766 if (ret)
767 return ERR_PTR(ret);
768
769 return trig;
770 }
771
xadc_power_adc_b(struct xadc * xadc,unsigned int seq_mode)772 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
773 {
774 uint16_t val;
775
776 /*
777 * As per datasheet the power-down bits are don't care in the
778 * UltraScale, but as per reality setting the power-down bit for the
779 * non-existing ADC-B powers down the main ADC, so just return and don't
780 * do anything.
781 */
782 if (xadc->ops->type == XADC_TYPE_US)
783 return 0;
784
785 /* Powerdown the ADC-B when it is not needed. */
786 switch (seq_mode) {
787 case XADC_CONF1_SEQ_SIMULTANEOUS:
788 case XADC_CONF1_SEQ_INDEPENDENT:
789 val = 0;
790 break;
791 default:
792 val = XADC_CONF2_PD_ADC_B;
793 break;
794 }
795
796 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
797 val);
798 }
799
xadc_get_seq_mode(struct xadc * xadc,unsigned long scan_mode)800 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
801 {
802 unsigned int aux_scan_mode = scan_mode >> 16;
803
804 /* UltraScale has only one ADC and supports only continuous mode */
805 if (xadc->ops->type == XADC_TYPE_US)
806 return XADC_CONF1_SEQ_CONTINUOUS;
807
808 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
809 return XADC_CONF1_SEQ_SIMULTANEOUS;
810
811 if ((aux_scan_mode & 0xff00) == 0 ||
812 (aux_scan_mode & 0x00ff) == 0)
813 return XADC_CONF1_SEQ_CONTINUOUS;
814
815 return XADC_CONF1_SEQ_SIMULTANEOUS;
816 }
817
xadc_postdisable(struct iio_dev * indio_dev)818 static int xadc_postdisable(struct iio_dev *indio_dev)
819 {
820 struct xadc *xadc = iio_priv(indio_dev);
821 unsigned long scan_mask;
822 int ret;
823 int i;
824
825 scan_mask = 1; /* Run calibration as part of the sequence */
826 for (i = 0; i < indio_dev->num_channels; i++)
827 scan_mask |= BIT(indio_dev->channels[i].scan_index);
828
829 /* Enable all channels and calibration */
830 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
831 if (ret)
832 return ret;
833
834 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
835 if (ret)
836 return ret;
837
838 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
839 XADC_CONF1_SEQ_CONTINUOUS);
840 if (ret)
841 return ret;
842
843 return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
844 }
845
xadc_preenable(struct iio_dev * indio_dev)846 static int xadc_preenable(struct iio_dev *indio_dev)
847 {
848 struct xadc *xadc = iio_priv(indio_dev);
849 unsigned long scan_mask;
850 int seq_mode;
851 int ret;
852
853 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
854 XADC_CONF1_SEQ_DEFAULT);
855 if (ret)
856 goto err;
857
858 scan_mask = *indio_dev->active_scan_mask;
859 seq_mode = xadc_get_seq_mode(xadc, scan_mask);
860
861 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
862 if (ret)
863 goto err;
864
865 /*
866 * In simultaneous mode the upper and lower aux channels are samples at
867 * the same time. In this mode the upper 8 bits in the sequencer
868 * register are don't care and the lower 8 bits control two channels
869 * each. As such we must set the bit if either the channel in the lower
870 * group or the upper group is enabled.
871 */
872 if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
873 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
874
875 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
876 if (ret)
877 goto err;
878
879 ret = xadc_power_adc_b(xadc, seq_mode);
880 if (ret)
881 goto err;
882
883 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
884 seq_mode);
885 if (ret)
886 goto err;
887
888 return 0;
889 err:
890 xadc_postdisable(indio_dev);
891 return ret;
892 }
893
894 static const struct iio_buffer_setup_ops xadc_buffer_ops = {
895 .preenable = &xadc_preenable,
896 .postdisable = &xadc_postdisable,
897 };
898
xadc_read_samplerate(struct xadc * xadc)899 static int xadc_read_samplerate(struct xadc *xadc)
900 {
901 unsigned int div;
902 uint16_t val16;
903 int ret;
904
905 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
906 if (ret)
907 return ret;
908
909 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
910 if (div < 2)
911 div = 2;
912
913 return xadc_get_dclk_rate(xadc) / div / 26;
914 }
915
xadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)916 static int xadc_read_raw(struct iio_dev *indio_dev,
917 struct iio_chan_spec const *chan, int *val, int *val2, long info)
918 {
919 struct xadc *xadc = iio_priv(indio_dev);
920 unsigned int bits = chan->scan_type.realbits;
921 uint16_t val16;
922 int ret;
923
924 switch (info) {
925 case IIO_CHAN_INFO_RAW:
926 if (iio_buffer_enabled(indio_dev))
927 return -EBUSY;
928 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
929 if (ret < 0)
930 return ret;
931
932 val16 >>= chan->scan_type.shift;
933 if (chan->scan_type.sign == 'u')
934 *val = val16;
935 else
936 *val = sign_extend32(val16, bits - 1);
937
938 return IIO_VAL_INT;
939 case IIO_CHAN_INFO_SCALE:
940 switch (chan->type) {
941 case IIO_VOLTAGE:
942 /* V = (val * 3.0) / 2**bits */
943 switch (chan->address) {
944 case XADC_REG_VCCINT:
945 case XADC_REG_VCCAUX:
946 case XADC_REG_VREFP:
947 case XADC_REG_VREFN:
948 case XADC_REG_VCCBRAM:
949 case XADC_REG_VCCPINT:
950 case XADC_REG_VCCPAUX:
951 case XADC_REG_VCCO_DDR:
952 *val = 3000;
953 break;
954 default:
955 *val = 1000;
956 break;
957 }
958 *val2 = chan->scan_type.realbits;
959 return IIO_VAL_FRACTIONAL_LOG2;
960 case IIO_TEMP:
961 *val = xadc->ops->temp_scale;
962 *val2 = bits;
963 return IIO_VAL_FRACTIONAL_LOG2;
964 default:
965 return -EINVAL;
966 }
967 case IIO_CHAN_INFO_OFFSET:
968 /* Only the temperature channel has an offset */
969 *val = -((xadc->ops->temp_offset << bits) / xadc->ops->temp_scale);
970 return IIO_VAL_INT;
971 case IIO_CHAN_INFO_SAMP_FREQ:
972 ret = xadc_read_samplerate(xadc);
973 if (ret < 0)
974 return ret;
975
976 *val = ret;
977 return IIO_VAL_INT;
978 default:
979 return -EINVAL;
980 }
981 }
982
xadc_write_samplerate(struct xadc * xadc,int val)983 static int xadc_write_samplerate(struct xadc *xadc, int val)
984 {
985 unsigned long clk_rate = xadc_get_dclk_rate(xadc);
986 unsigned int div;
987
988 if (!clk_rate)
989 return -EINVAL;
990
991 if (val <= 0)
992 return -EINVAL;
993
994 /* Max. 150 kSPS */
995 if (val > XADC_MAX_SAMPLERATE)
996 val = XADC_MAX_SAMPLERATE;
997
998 val *= 26;
999
1000 /* Min 1MHz */
1001 if (val < 1000000)
1002 val = 1000000;
1003
1004 /*
1005 * We want to round down, but only if we do not exceed the 150 kSPS
1006 * limit.
1007 */
1008 div = clk_rate / val;
1009 if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
1010 div++;
1011 if (div < 2)
1012 div = 2;
1013 else if (div > 0xff)
1014 div = 0xff;
1015
1016 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1017 div << XADC_CONF2_DIV_OFFSET);
1018 }
1019
xadc_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)1020 static int xadc_write_raw(struct iio_dev *indio_dev,
1021 struct iio_chan_spec const *chan, int val, int val2, long info)
1022 {
1023 struct xadc *xadc = iio_priv(indio_dev);
1024
1025 if (info != IIO_CHAN_INFO_SAMP_FREQ)
1026 return -EINVAL;
1027
1028 return xadc_write_samplerate(xadc, val);
1029 }
1030
1031 static const struct iio_event_spec xadc_temp_events[] = {
1032 {
1033 .type = IIO_EV_TYPE_THRESH,
1034 .dir = IIO_EV_DIR_RISING,
1035 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1036 BIT(IIO_EV_INFO_VALUE) |
1037 BIT(IIO_EV_INFO_HYSTERESIS),
1038 },
1039 };
1040
1041 /* Separate values for upper and lower thresholds, but only a shared enabled */
1042 static const struct iio_event_spec xadc_voltage_events[] = {
1043 {
1044 .type = IIO_EV_TYPE_THRESH,
1045 .dir = IIO_EV_DIR_RISING,
1046 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1047 }, {
1048 .type = IIO_EV_TYPE_THRESH,
1049 .dir = IIO_EV_DIR_FALLING,
1050 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1051 }, {
1052 .type = IIO_EV_TYPE_THRESH,
1053 .dir = IIO_EV_DIR_EITHER,
1054 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1055 },
1056 };
1057
1058 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1059 .type = IIO_TEMP, \
1060 .indexed = 1, \
1061 .channel = (_chan), \
1062 .address = (_addr), \
1063 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1064 BIT(IIO_CHAN_INFO_SCALE) | \
1065 BIT(IIO_CHAN_INFO_OFFSET), \
1066 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1067 .event_spec = xadc_temp_events, \
1068 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1069 .scan_index = (_scan_index), \
1070 .scan_type = { \
1071 .sign = 'u', \
1072 .realbits = (_bits), \
1073 .storagebits = 16, \
1074 .shift = 16 - (_bits), \
1075 .endianness = IIO_CPU, \
1076 }, \
1077 }
1078
1079 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1080 .type = IIO_VOLTAGE, \
1081 .indexed = 1, \
1082 .channel = (_chan), \
1083 .address = (_addr), \
1084 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1085 BIT(IIO_CHAN_INFO_SCALE), \
1086 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1087 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1088 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1089 .scan_index = (_scan_index), \
1090 .scan_type = { \
1091 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1092 .realbits = (_bits), \
1093 .storagebits = 16, \
1094 .shift = 16 - (_bits), \
1095 .endianness = IIO_CPU, \
1096 }, \
1097 .extend_name = _ext, \
1098 }
1099
1100 /* 7 Series */
1101 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1102 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1103 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1104 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1105
1106 static const struct iio_chan_spec xadc_7s_channels[] = {
1107 XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1108 XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1109 XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1110 XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1111 XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1112 XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1113 XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1114 XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1115 XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1116 XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1117 XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1118 XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1119 XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1120 XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1121 XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1122 XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1123 XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1124 XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1125 XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1126 XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1127 XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1128 XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1129 XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1130 XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1131 XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1132 XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1133 };
1134
1135 /* UltraScale */
1136 #define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1137 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1138 #define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1139 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1140
1141 static const struct iio_chan_spec xadc_us_channels[] = {
1142 XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1143 XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1144 XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1145 XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1146 XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1147 XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1148 XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1149 XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1150 XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1151 XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1152 XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1153 XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1154 XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1155 XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1156 XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1157 XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1158 XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1159 XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1160 XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1161 XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1162 XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1163 XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1164 XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1165 XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1166 XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1167 XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1168 };
1169
1170 static const struct iio_info xadc_info = {
1171 .read_raw = &xadc_read_raw,
1172 .write_raw = &xadc_write_raw,
1173 .read_event_config = &xadc_read_event_config,
1174 .write_event_config = &xadc_write_event_config,
1175 .read_event_value = &xadc_read_event_value,
1176 .write_event_value = &xadc_write_event_value,
1177 .update_scan_mode = &xadc_update_scan_mode,
1178 };
1179
1180 static const struct of_device_id xadc_of_match_table[] = {
1181 {
1182 .compatible = "xlnx,zynq-xadc-1.00.a",
1183 .data = &xadc_zynq_ops
1184 }, {
1185 .compatible = "xlnx,axi-xadc-1.00.a",
1186 .data = &xadc_7s_axi_ops
1187 }, {
1188 .compatible = "xlnx,system-management-wiz-1.3",
1189 .data = &xadc_us_axi_ops
1190 },
1191 { },
1192 };
1193 MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1194
xadc_parse_dt(struct iio_dev * indio_dev,struct device_node * np,unsigned int * conf)1195 static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
1196 unsigned int *conf)
1197 {
1198 struct device *dev = indio_dev->dev.parent;
1199 struct xadc *xadc = iio_priv(indio_dev);
1200 const struct iio_chan_spec *channel_templates;
1201 struct iio_chan_spec *channels, *chan;
1202 struct device_node *chan_node, *child;
1203 unsigned int max_channels;
1204 unsigned int num_channels;
1205 const char *external_mux;
1206 u32 ext_mux_chan;
1207 u32 reg;
1208 int ret;
1209
1210 *conf = 0;
1211
1212 ret = of_property_read_string(np, "xlnx,external-mux", &external_mux);
1213 if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1214 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1215 else if (strcasecmp(external_mux, "single") == 0)
1216 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1217 else if (strcasecmp(external_mux, "dual") == 0)
1218 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1219 else
1220 return -EINVAL;
1221
1222 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1223 ret = of_property_read_u32(np, "xlnx,external-mux-channel",
1224 &ext_mux_chan);
1225 if (ret < 0)
1226 return ret;
1227
1228 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1229 if (ext_mux_chan == 0)
1230 ext_mux_chan = XADC_REG_VPVN;
1231 else if (ext_mux_chan <= 16)
1232 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1233 else
1234 return -EINVAL;
1235 } else {
1236 if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1237 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1238 else
1239 return -EINVAL;
1240 }
1241
1242 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1243 }
1244 if (xadc->ops->type == XADC_TYPE_S7) {
1245 channel_templates = xadc_7s_channels;
1246 max_channels = ARRAY_SIZE(xadc_7s_channels);
1247 } else {
1248 channel_templates = xadc_us_channels;
1249 max_channels = ARRAY_SIZE(xadc_us_channels);
1250 }
1251 channels = devm_kmemdup(dev, channel_templates,
1252 sizeof(channels[0]) * max_channels, GFP_KERNEL);
1253 if (!channels)
1254 return -ENOMEM;
1255
1256 num_channels = 9;
1257 chan = &channels[9];
1258
1259 chan_node = of_get_child_by_name(np, "xlnx,channels");
1260 if (chan_node) {
1261 for_each_child_of_node(chan_node, child) {
1262 if (num_channels >= max_channels) {
1263 of_node_put(child);
1264 break;
1265 }
1266
1267 ret = of_property_read_u32(child, "reg", ®);
1268 if (ret || reg > 16)
1269 continue;
1270
1271 if (of_property_read_bool(child, "xlnx,bipolar"))
1272 chan->scan_type.sign = 's';
1273
1274 if (reg == 0) {
1275 chan->scan_index = 11;
1276 chan->address = XADC_REG_VPVN;
1277 } else {
1278 chan->scan_index = 15 + reg;
1279 chan->address = XADC_REG_VAUX(reg - 1);
1280 }
1281 num_channels++;
1282 chan++;
1283 }
1284 }
1285 of_node_put(chan_node);
1286
1287 indio_dev->num_channels = num_channels;
1288 indio_dev->channels = devm_krealloc(dev, channels,
1289 sizeof(*channels) * num_channels,
1290 GFP_KERNEL);
1291 /* If we can't resize the channels array, just use the original */
1292 if (!indio_dev->channels)
1293 indio_dev->channels = channels;
1294
1295 return 0;
1296 }
1297
1298 static const char * const xadc_type_names[] = {
1299 [XADC_TYPE_S7] = "xadc",
1300 [XADC_TYPE_US] = "xilinx-system-monitor",
1301 };
1302
xadc_clk_disable_unprepare(void * data)1303 static void xadc_clk_disable_unprepare(void *data)
1304 {
1305 struct clk *clk = data;
1306
1307 clk_disable_unprepare(clk);
1308 }
1309
xadc_cancel_delayed_work(void * data)1310 static void xadc_cancel_delayed_work(void *data)
1311 {
1312 struct delayed_work *work = data;
1313
1314 cancel_delayed_work_sync(work);
1315 }
1316
xadc_probe(struct platform_device * pdev)1317 static int xadc_probe(struct platform_device *pdev)
1318 {
1319 struct device *dev = &pdev->dev;
1320 const struct of_device_id *id;
1321 struct iio_dev *indio_dev;
1322 unsigned int bipolar_mask;
1323 unsigned int conf0;
1324 struct xadc *xadc;
1325 int ret;
1326 int irq;
1327 int i;
1328
1329 if (!dev->of_node)
1330 return -ENODEV;
1331
1332 id = of_match_node(xadc_of_match_table, dev->of_node);
1333 if (!id)
1334 return -EINVAL;
1335
1336 irq = platform_get_irq(pdev, 0);
1337 if (irq <= 0)
1338 return -ENXIO;
1339
1340 indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1341 if (!indio_dev)
1342 return -ENOMEM;
1343
1344 xadc = iio_priv(indio_dev);
1345 xadc->ops = id->data;
1346 xadc->irq = irq;
1347 init_completion(&xadc->completion);
1348 mutex_init(&xadc->mutex);
1349 spin_lock_init(&xadc->lock);
1350 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1351
1352 xadc->base = devm_platform_ioremap_resource(pdev, 0);
1353 if (IS_ERR(xadc->base))
1354 return PTR_ERR(xadc->base);
1355
1356 indio_dev->name = xadc_type_names[xadc->ops->type];
1357 indio_dev->modes = INDIO_DIRECT_MODE;
1358 indio_dev->info = &xadc_info;
1359
1360 ret = xadc_parse_dt(indio_dev, dev->of_node, &conf0);
1361 if (ret)
1362 return ret;
1363
1364 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1365 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1366 &iio_pollfunc_store_time,
1367 &xadc_trigger_handler,
1368 &xadc_buffer_ops);
1369 if (ret)
1370 return ret;
1371
1372 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1373 if (IS_ERR(xadc->convst_trigger))
1374 return PTR_ERR(xadc->convst_trigger);
1375
1376 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1377 "samplerate");
1378 if (IS_ERR(xadc->samplerate_trigger))
1379 return PTR_ERR(xadc->samplerate_trigger);
1380 }
1381
1382 xadc->clk = devm_clk_get(dev, NULL);
1383 if (IS_ERR(xadc->clk))
1384 return PTR_ERR(xadc->clk);
1385
1386 ret = clk_prepare_enable(xadc->clk);
1387 if (ret)
1388 return ret;
1389
1390 ret = devm_add_action_or_reset(dev,
1391 xadc_clk_disable_unprepare, xadc->clk);
1392 if (ret)
1393 return ret;
1394
1395 /*
1396 * Make sure not to exceed the maximum samplerate since otherwise the
1397 * resulting interrupt storm will soft-lock the system.
1398 */
1399 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1400 ret = xadc_read_samplerate(xadc);
1401 if (ret < 0)
1402 return ret;
1403
1404 if (ret > XADC_MAX_SAMPLERATE) {
1405 ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1406 if (ret < 0)
1407 return ret;
1408 }
1409 }
1410
1411 ret = devm_request_irq(dev, xadc->irq, xadc->ops->interrupt_handler, 0,
1412 dev_name(dev), indio_dev);
1413 if (ret)
1414 return ret;
1415
1416 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1417 &xadc->zynq_unmask_work);
1418 if (ret)
1419 return ret;
1420
1421 ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);
1422 if (ret)
1423 return ret;
1424
1425 for (i = 0; i < 16; i++)
1426 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1427 &xadc->threshold[i]);
1428
1429 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1430 if (ret)
1431 return ret;
1432
1433 bipolar_mask = 0;
1434 for (i = 0; i < indio_dev->num_channels; i++) {
1435 if (indio_dev->channels[i].scan_type.sign == 's')
1436 bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1437 }
1438
1439 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1440 if (ret)
1441 return ret;
1442
1443 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1444 bipolar_mask >> 16);
1445 if (ret)
1446 return ret;
1447
1448 /* Go to non-buffered mode */
1449 xadc_postdisable(indio_dev);
1450
1451 return devm_iio_device_register(dev, indio_dev);
1452 }
1453
1454 static struct platform_driver xadc_driver = {
1455 .probe = xadc_probe,
1456 .driver = {
1457 .name = "xadc",
1458 .of_match_table = xadc_of_match_table,
1459 },
1460 };
1461 module_platform_driver(xadc_driver);
1462
1463 MODULE_LICENSE("GPL v2");
1464 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1465 MODULE_DESCRIPTION("Xilinx XADC IIO driver");
1466