1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/platform_device.h>
34 #include <linux/acpi.h>
35 #include <linux/etherdevice.h>
36 #include <linux/interrupt.h>
37 #include <linux/of.h>
38 #include <linux/of_platform.h>
39 #include <rdma/ib_umem.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_cmd.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v1.h"
45
46 /**
47 * hns_get_gid_index - Get gid index.
48 * @hr_dev: pointer to structure hns_roce_dev.
49 * @port: port, value range: 0 ~ MAX
50 * @gid_index: gid_index, value range: 0 ~ MAX
51 * Description:
52 * N ports shared gids, allocation method as follow:
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
54 * GID[0][0], GID[1][0],.....GID[N - 1][0],
55 * And so on
56 */
hns_get_gid_index(struct hns_roce_dev * hr_dev,u32 port,int gid_index)57 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index)
58 {
59 return gid_index * hr_dev->caps.num_ports + port;
60 }
61
set_data_seg(struct hns_roce_wqe_data_seg * dseg,struct ib_sge * sg)62 static void set_data_seg(struct hns_roce_wqe_data_seg *dseg, struct ib_sge *sg)
63 {
64 dseg->lkey = cpu_to_le32(sg->lkey);
65 dseg->addr = cpu_to_le64(sg->addr);
66 dseg->len = cpu_to_le32(sg->length);
67 }
68
set_raddr_seg(struct hns_roce_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)69 static void set_raddr_seg(struct hns_roce_wqe_raddr_seg *rseg, u64 remote_addr,
70 u32 rkey)
71 {
72 rseg->raddr = cpu_to_le64(remote_addr);
73 rseg->rkey = cpu_to_le32(rkey);
74 rseg->len = 0;
75 }
76
hns_roce_v1_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)77 static int hns_roce_v1_post_send(struct ib_qp *ibqp,
78 const struct ib_send_wr *wr,
79 const struct ib_send_wr **bad_wr)
80 {
81 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
82 struct hns_roce_ah *ah = to_hr_ah(ud_wr(wr)->ah);
83 struct hns_roce_ud_send_wqe *ud_sq_wqe = NULL;
84 struct hns_roce_wqe_ctrl_seg *ctrl = NULL;
85 struct hns_roce_wqe_data_seg *dseg = NULL;
86 struct hns_roce_qp *qp = to_hr_qp(ibqp);
87 struct device *dev = &hr_dev->pdev->dev;
88 struct hns_roce_sq_db sq_db = {};
89 int ps_opcode, i;
90 unsigned long flags = 0;
91 void *wqe = NULL;
92 __le32 doorbell[2];
93 int ret = 0;
94 int loopback;
95 u32 wqe_idx;
96 int nreq;
97 u8 *smac;
98
99 if (unlikely(ibqp->qp_type != IB_QPT_GSI &&
100 ibqp->qp_type != IB_QPT_RC)) {
101 dev_err(dev, "un-supported QP type\n");
102 *bad_wr = NULL;
103 return -EOPNOTSUPP;
104 }
105
106 spin_lock_irqsave(&qp->sq.lock, flags);
107
108 for (nreq = 0; wr; ++nreq, wr = wr->next) {
109 if (hns_roce_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
110 ret = -ENOMEM;
111 *bad_wr = wr;
112 goto out;
113 }
114
115 wqe_idx = (qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1);
116
117 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
118 dev_err(dev, "num_sge=%d > qp->sq.max_gs=%d\n",
119 wr->num_sge, qp->sq.max_gs);
120 ret = -EINVAL;
121 *bad_wr = wr;
122 goto out;
123 }
124
125 wqe = hns_roce_get_send_wqe(qp, wqe_idx);
126 qp->sq.wrid[wqe_idx] = wr->wr_id;
127
128 /* Corresponding to the RC and RD type wqe process separately */
129 if (ibqp->qp_type == IB_QPT_GSI) {
130 ud_sq_wqe = wqe;
131 roce_set_field(ud_sq_wqe->dmac_h,
132 UD_SEND_WQE_U32_4_DMAC_0_M,
133 UD_SEND_WQE_U32_4_DMAC_0_S,
134 ah->av.mac[0]);
135 roce_set_field(ud_sq_wqe->dmac_h,
136 UD_SEND_WQE_U32_4_DMAC_1_M,
137 UD_SEND_WQE_U32_4_DMAC_1_S,
138 ah->av.mac[1]);
139 roce_set_field(ud_sq_wqe->dmac_h,
140 UD_SEND_WQE_U32_4_DMAC_2_M,
141 UD_SEND_WQE_U32_4_DMAC_2_S,
142 ah->av.mac[2]);
143 roce_set_field(ud_sq_wqe->dmac_h,
144 UD_SEND_WQE_U32_4_DMAC_3_M,
145 UD_SEND_WQE_U32_4_DMAC_3_S,
146 ah->av.mac[3]);
147
148 roce_set_field(ud_sq_wqe->u32_8,
149 UD_SEND_WQE_U32_8_DMAC_4_M,
150 UD_SEND_WQE_U32_8_DMAC_4_S,
151 ah->av.mac[4]);
152 roce_set_field(ud_sq_wqe->u32_8,
153 UD_SEND_WQE_U32_8_DMAC_5_M,
154 UD_SEND_WQE_U32_8_DMAC_5_S,
155 ah->av.mac[5]);
156
157 smac = (u8 *)hr_dev->dev_addr[qp->port];
158 loopback = ether_addr_equal_unaligned(ah->av.mac,
159 smac) ? 1 : 0;
160 roce_set_bit(ud_sq_wqe->u32_8,
161 UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S,
162 loopback);
163
164 roce_set_field(ud_sq_wqe->u32_8,
165 UD_SEND_WQE_U32_8_OPERATION_TYPE_M,
166 UD_SEND_WQE_U32_8_OPERATION_TYPE_S,
167 HNS_ROCE_WQE_OPCODE_SEND);
168 roce_set_field(ud_sq_wqe->u32_8,
169 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M,
170 UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S,
171 2);
172 roce_set_bit(ud_sq_wqe->u32_8,
173 UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S,
174 1);
175
176 ud_sq_wqe->u32_8 |= (wr->send_flags & IB_SEND_SIGNALED ?
177 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
178 (wr->send_flags & IB_SEND_SOLICITED ?
179 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
180 ((wr->opcode == IB_WR_SEND_WITH_IMM) ?
181 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0);
182
183 roce_set_field(ud_sq_wqe->u32_16,
184 UD_SEND_WQE_U32_16_DEST_QP_M,
185 UD_SEND_WQE_U32_16_DEST_QP_S,
186 ud_wr(wr)->remote_qpn);
187 roce_set_field(ud_sq_wqe->u32_16,
188 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M,
189 UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S,
190 ah->av.stat_rate);
191
192 roce_set_field(ud_sq_wqe->u32_36,
193 UD_SEND_WQE_U32_36_FLOW_LABEL_M,
194 UD_SEND_WQE_U32_36_FLOW_LABEL_S,
195 ah->av.flowlabel);
196 roce_set_field(ud_sq_wqe->u32_36,
197 UD_SEND_WQE_U32_36_PRIORITY_M,
198 UD_SEND_WQE_U32_36_PRIORITY_S,
199 ah->av.sl);
200 roce_set_field(ud_sq_wqe->u32_36,
201 UD_SEND_WQE_U32_36_SGID_INDEX_M,
202 UD_SEND_WQE_U32_36_SGID_INDEX_S,
203 hns_get_gid_index(hr_dev, qp->phy_port,
204 ah->av.gid_index));
205
206 roce_set_field(ud_sq_wqe->u32_40,
207 UD_SEND_WQE_U32_40_HOP_LIMIT_M,
208 UD_SEND_WQE_U32_40_HOP_LIMIT_S,
209 ah->av.hop_limit);
210 roce_set_field(ud_sq_wqe->u32_40,
211 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M,
212 UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S,
213 ah->av.tclass);
214
215 memcpy(&ud_sq_wqe->dgid[0], &ah->av.dgid[0], GID_LEN);
216
217 ud_sq_wqe->va0_l =
218 cpu_to_le32((u32)wr->sg_list[0].addr);
219 ud_sq_wqe->va0_h =
220 cpu_to_le32((wr->sg_list[0].addr) >> 32);
221 ud_sq_wqe->l_key0 =
222 cpu_to_le32(wr->sg_list[0].lkey);
223
224 ud_sq_wqe->va1_l =
225 cpu_to_le32((u32)wr->sg_list[1].addr);
226 ud_sq_wqe->va1_h =
227 cpu_to_le32((wr->sg_list[1].addr) >> 32);
228 ud_sq_wqe->l_key1 =
229 cpu_to_le32(wr->sg_list[1].lkey);
230 } else if (ibqp->qp_type == IB_QPT_RC) {
231 u32 tmp_len = 0;
232
233 ctrl = wqe;
234 memset(ctrl, 0, sizeof(struct hns_roce_wqe_ctrl_seg));
235 for (i = 0; i < wr->num_sge; i++)
236 tmp_len += wr->sg_list[i].length;
237
238 ctrl->msg_length =
239 cpu_to_le32(le32_to_cpu(ctrl->msg_length) + tmp_len);
240
241 ctrl->sgl_pa_h = 0;
242 ctrl->flag = 0;
243
244 switch (wr->opcode) {
245 case IB_WR_SEND_WITH_IMM:
246 case IB_WR_RDMA_WRITE_WITH_IMM:
247 ctrl->imm_data = wr->ex.imm_data;
248 break;
249 case IB_WR_SEND_WITH_INV:
250 ctrl->inv_key =
251 cpu_to_le32(wr->ex.invalidate_rkey);
252 break;
253 default:
254 ctrl->imm_data = 0;
255 break;
256 }
257
258 /* Ctrl field, ctrl set type: sig, solic, imm, fence */
259 /* SO wait for conforming application scenarios */
260 ctrl->flag |= (wr->send_flags & IB_SEND_SIGNALED ?
261 cpu_to_le32(HNS_ROCE_WQE_CQ_NOTIFY) : 0) |
262 (wr->send_flags & IB_SEND_SOLICITED ?
263 cpu_to_le32(HNS_ROCE_WQE_SE) : 0) |
264 ((wr->opcode == IB_WR_SEND_WITH_IMM ||
265 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) ?
266 cpu_to_le32(HNS_ROCE_WQE_IMM) : 0) |
267 (wr->send_flags & IB_SEND_FENCE ?
268 (cpu_to_le32(HNS_ROCE_WQE_FENCE)) : 0);
269
270 wqe += sizeof(struct hns_roce_wqe_ctrl_seg);
271
272 switch (wr->opcode) {
273 case IB_WR_RDMA_READ:
274 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_READ;
275 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
276 rdma_wr(wr)->rkey);
277 break;
278 case IB_WR_RDMA_WRITE:
279 case IB_WR_RDMA_WRITE_WITH_IMM:
280 ps_opcode = HNS_ROCE_WQE_OPCODE_RDMA_WRITE;
281 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
282 rdma_wr(wr)->rkey);
283 break;
284 case IB_WR_SEND:
285 case IB_WR_SEND_WITH_INV:
286 case IB_WR_SEND_WITH_IMM:
287 ps_opcode = HNS_ROCE_WQE_OPCODE_SEND;
288 break;
289 case IB_WR_LOCAL_INV:
290 case IB_WR_ATOMIC_CMP_AND_SWP:
291 case IB_WR_ATOMIC_FETCH_AND_ADD:
292 case IB_WR_LSO:
293 default:
294 ps_opcode = HNS_ROCE_WQE_OPCODE_MASK;
295 break;
296 }
297 ctrl->flag |= cpu_to_le32(ps_opcode);
298 wqe += sizeof(struct hns_roce_wqe_raddr_seg);
299
300 dseg = wqe;
301 if (wr->send_flags & IB_SEND_INLINE && wr->num_sge) {
302 if (le32_to_cpu(ctrl->msg_length) >
303 hr_dev->caps.max_sq_inline) {
304 ret = -EINVAL;
305 *bad_wr = wr;
306 dev_err(dev, "inline len(1-%d)=%d, illegal",
307 le32_to_cpu(ctrl->msg_length),
308 hr_dev->caps.max_sq_inline);
309 goto out;
310 }
311 for (i = 0; i < wr->num_sge; i++) {
312 memcpy(wqe, ((void *) (uintptr_t)
313 wr->sg_list[i].addr),
314 wr->sg_list[i].length);
315 wqe += wr->sg_list[i].length;
316 }
317 ctrl->flag |= cpu_to_le32(HNS_ROCE_WQE_INLINE);
318 } else {
319 /* sqe num is two */
320 for (i = 0; i < wr->num_sge; i++)
321 set_data_seg(dseg + i, wr->sg_list + i);
322
323 ctrl->flag |= cpu_to_le32(wr->num_sge <<
324 HNS_ROCE_WQE_SGE_NUM_BIT);
325 }
326 }
327 }
328
329 out:
330 /* Set DB return */
331 if (likely(nreq)) {
332 qp->sq.head += nreq;
333
334 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SQ_HEAD_M,
335 SQ_DOORBELL_U32_4_SQ_HEAD_S,
336 (qp->sq.head & ((qp->sq.wqe_cnt << 1) - 1)));
337 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_SL_M,
338 SQ_DOORBELL_U32_4_SL_S, qp->sl);
339 roce_set_field(sq_db.u32_4, SQ_DOORBELL_U32_4_PORT_M,
340 SQ_DOORBELL_U32_4_PORT_S, qp->phy_port);
341 roce_set_field(sq_db.u32_8, SQ_DOORBELL_U32_8_QPN_M,
342 SQ_DOORBELL_U32_8_QPN_S, qp->doorbell_qpn);
343 roce_set_bit(sq_db.u32_8, SQ_DOORBELL_HW_SYNC_S, 1);
344
345 doorbell[0] = sq_db.u32_4;
346 doorbell[1] = sq_db.u32_8;
347
348 hns_roce_write64_k(doorbell, qp->sq.db_reg);
349 }
350
351 spin_unlock_irqrestore(&qp->sq.lock, flags);
352
353 return ret;
354 }
355
hns_roce_v1_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)356 static int hns_roce_v1_post_recv(struct ib_qp *ibqp,
357 const struct ib_recv_wr *wr,
358 const struct ib_recv_wr **bad_wr)
359 {
360 struct hns_roce_rq_wqe_ctrl *ctrl = NULL;
361 struct hns_roce_wqe_data_seg *scat = NULL;
362 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
363 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
364 struct device *dev = &hr_dev->pdev->dev;
365 struct hns_roce_rq_db rq_db = {};
366 __le32 doorbell[2] = {0};
367 unsigned long flags = 0;
368 unsigned int wqe_idx;
369 int ret = 0;
370 int nreq;
371 int i;
372 u32 reg_val;
373
374 spin_lock_irqsave(&hr_qp->rq.lock, flags);
375
376 for (nreq = 0; wr; ++nreq, wr = wr->next) {
377 if (hns_roce_wq_overflow(&hr_qp->rq, nreq,
378 hr_qp->ibqp.recv_cq)) {
379 ret = -ENOMEM;
380 *bad_wr = wr;
381 goto out;
382 }
383
384 wqe_idx = (hr_qp->rq.head + nreq) & (hr_qp->rq.wqe_cnt - 1);
385
386 if (unlikely(wr->num_sge > hr_qp->rq.max_gs)) {
387 dev_err(dev, "rq:num_sge=%d > qp->sq.max_gs=%d\n",
388 wr->num_sge, hr_qp->rq.max_gs);
389 ret = -EINVAL;
390 *bad_wr = wr;
391 goto out;
392 }
393
394 ctrl = hns_roce_get_recv_wqe(hr_qp, wqe_idx);
395
396 roce_set_field(ctrl->rwqe_byte_12,
397 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M,
398 RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S,
399 wr->num_sge);
400
401 scat = (struct hns_roce_wqe_data_seg *)(ctrl + 1);
402
403 for (i = 0; i < wr->num_sge; i++)
404 set_data_seg(scat + i, wr->sg_list + i);
405
406 hr_qp->rq.wrid[wqe_idx] = wr->wr_id;
407 }
408
409 out:
410 if (likely(nreq)) {
411 hr_qp->rq.head += nreq;
412
413 if (ibqp->qp_type == IB_QPT_GSI) {
414 __le32 tmp;
415
416 /* SW update GSI rq header */
417 reg_val = roce_read(to_hr_dev(ibqp->device),
418 ROCEE_QP1C_CFG3_0_REG +
419 QP1C_CFGN_OFFSET * hr_qp->phy_port);
420 tmp = cpu_to_le32(reg_val);
421 roce_set_field(tmp,
422 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M,
423 ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S,
424 hr_qp->rq.head);
425 reg_val = le32_to_cpu(tmp);
426 roce_write(to_hr_dev(ibqp->device),
427 ROCEE_QP1C_CFG3_0_REG +
428 QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val);
429 } else {
430 roce_set_field(rq_db.u32_4, RQ_DOORBELL_U32_4_RQ_HEAD_M,
431 RQ_DOORBELL_U32_4_RQ_HEAD_S,
432 hr_qp->rq.head);
433 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_QPN_M,
434 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
435 roce_set_field(rq_db.u32_8, RQ_DOORBELL_U32_8_CMD_M,
436 RQ_DOORBELL_U32_8_CMD_S, 1);
437 roce_set_bit(rq_db.u32_8, RQ_DOORBELL_U32_8_HW_SYNC_S,
438 1);
439
440 doorbell[0] = rq_db.u32_4;
441 doorbell[1] = rq_db.u32_8;
442
443 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg);
444 }
445 }
446 spin_unlock_irqrestore(&hr_qp->rq.lock, flags);
447
448 return ret;
449 }
450
hns_roce_set_db_event_mode(struct hns_roce_dev * hr_dev,int sdb_mode,int odb_mode)451 static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev,
452 int sdb_mode, int odb_mode)
453 {
454 __le32 tmp;
455 u32 val;
456
457 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
458 tmp = cpu_to_le32(val);
459 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode);
460 roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode);
461 val = le32_to_cpu(tmp);
462 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
463 }
464
hns_roce_v1_set_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)465 static int hns_roce_v1_set_hem(struct hns_roce_dev *hr_dev,
466 struct hns_roce_hem_table *table, int obj,
467 int step_idx)
468 {
469 spinlock_t *lock = &hr_dev->bt_cmd_lock;
470 struct device *dev = hr_dev->dev;
471 struct hns_roce_hem_iter iter;
472 void __iomem *bt_cmd;
473 __le32 bt_cmd_val[2];
474 __le32 bt_cmd_h = 0;
475 unsigned long flags;
476 __le32 bt_cmd_l;
477 int ret = 0;
478 u64 bt_ba;
479 long end;
480
481 /* Find the HEM(Hardware Entry Memory) entry */
482 unsigned long i = obj / (table->table_chunk_size / table->obj_size);
483
484 switch (table->type) {
485 case HEM_TYPE_QPC:
486 case HEM_TYPE_MTPT:
487 case HEM_TYPE_CQC:
488 case HEM_TYPE_SRQC:
489 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
490 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
491 break;
492 default:
493 return ret;
494 }
495
496 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
497 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
498 roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
499 roce_set_bit(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
500
501 /* Currently iter only a chunk */
502 for (hns_roce_hem_first(table->hem[i], &iter);
503 !hns_roce_hem_last(&iter); hns_roce_hem_next(&iter)) {
504 bt_ba = hns_roce_hem_addr(&iter) >> HNS_HW_PAGE_SHIFT;
505
506 spin_lock_irqsave(lock, flags);
507
508 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
509
510 end = HW_SYNC_TIMEOUT_MSECS;
511 while (end > 0) {
512 if (!(readl(bt_cmd) >> BT_CMD_SYNC_SHIFT))
513 break;
514
515 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
516 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
517 }
518
519 if (end <= 0) {
520 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
521 spin_unlock_irqrestore(lock, flags);
522 return -EBUSY;
523 }
524
525 bt_cmd_l = cpu_to_le32(bt_ba);
526 roce_set_field(bt_cmd_h, ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
527 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S,
528 upper_32_bits(bt_ba));
529
530 bt_cmd_val[0] = bt_cmd_l;
531 bt_cmd_val[1] = bt_cmd_h;
532 hns_roce_write64_k(bt_cmd_val,
533 hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
534 spin_unlock_irqrestore(lock, flags);
535 }
536
537 return ret;
538 }
539
hns_roce_set_db_ext_mode(struct hns_roce_dev * hr_dev,u32 sdb_mode,u32 odb_mode)540 static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode,
541 u32 odb_mode)
542 {
543 __le32 tmp;
544 u32 val;
545
546 /* Configure SDB/ODB extend mode */
547 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
548 tmp = cpu_to_le32(val);
549 roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode);
550 roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode);
551 val = le32_to_cpu(tmp);
552 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
553 }
554
hns_roce_set_sdb(struct hns_roce_dev * hr_dev,u32 sdb_alept,u32 sdb_alful)555 static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept,
556 u32 sdb_alful)
557 {
558 __le32 tmp;
559 u32 val;
560
561 /* Configure SDB */
562 val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG);
563 tmp = cpu_to_le32(val);
564 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M,
565 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful);
566 roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M,
567 ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept);
568 val = le32_to_cpu(tmp);
569 roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val);
570 }
571
hns_roce_set_odb(struct hns_roce_dev * hr_dev,u32 odb_alept,u32 odb_alful)572 static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept,
573 u32 odb_alful)
574 {
575 __le32 tmp;
576 u32 val;
577
578 /* Configure ODB */
579 val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG);
580 tmp = cpu_to_le32(val);
581 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M,
582 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful);
583 roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M,
584 ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept);
585 val = le32_to_cpu(tmp);
586 roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val);
587 }
588
hns_roce_set_sdb_ext(struct hns_roce_dev * hr_dev,u32 ext_sdb_alept,u32 ext_sdb_alful)589 static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept,
590 u32 ext_sdb_alful)
591 {
592 struct hns_roce_v1_priv *priv = hr_dev->priv;
593 struct hns_roce_db_table *db = &priv->db_table;
594 struct device *dev = &hr_dev->pdev->dev;
595 dma_addr_t sdb_dma_addr;
596 __le32 tmp;
597 u32 val;
598
599 /* Configure extend SDB threshold */
600 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_EMPTY_REG, ext_sdb_alept);
601 roce_write(hr_dev, ROCEE_EXT_DB_SQ_WL_REG, ext_sdb_alful);
602
603 /* Configure extend SDB base addr */
604 sdb_dma_addr = db->ext_db->sdb_buf_list->map;
605 roce_write(hr_dev, ROCEE_EXT_DB_SQ_REG, (u32)(sdb_dma_addr >> 12));
606
607 /* Configure extend SDB depth */
608 val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG);
609 tmp = cpu_to_le32(val);
610 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M,
611 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S,
612 db->ext_db->esdb_dep);
613 /*
614 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
615 * using 4K page, and shift more 32 because of
616 * calculating the high 32 bit value evaluated to hardware.
617 */
618 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M,
619 ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44);
620 val = le32_to_cpu(tmp);
621 roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val);
622
623 dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep);
624 dev_dbg(dev, "ext SDB threshold: empty: 0x%x, ful: 0x%x\n",
625 ext_sdb_alept, ext_sdb_alful);
626 }
627
hns_roce_set_odb_ext(struct hns_roce_dev * hr_dev,u32 ext_odb_alept,u32 ext_odb_alful)628 static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept,
629 u32 ext_odb_alful)
630 {
631 struct hns_roce_v1_priv *priv = hr_dev->priv;
632 struct hns_roce_db_table *db = &priv->db_table;
633 struct device *dev = &hr_dev->pdev->dev;
634 dma_addr_t odb_dma_addr;
635 __le32 tmp;
636 u32 val;
637
638 /* Configure extend ODB threshold */
639 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG, ext_odb_alept);
640 roce_write(hr_dev, ROCEE_EXT_DB_OTHERS_WL_REG, ext_odb_alful);
641
642 /* Configure extend ODB base addr */
643 odb_dma_addr = db->ext_db->odb_buf_list->map;
644 roce_write(hr_dev, ROCEE_EXT_DB_OTH_REG, (u32)(odb_dma_addr >> 12));
645
646 /* Configure extend ODB depth */
647 val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG);
648 tmp = cpu_to_le32(val);
649 roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M,
650 ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S,
651 db->ext_db->eodb_dep);
652 roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M,
653 ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S,
654 db->ext_db->eodb_dep);
655 val = le32_to_cpu(tmp);
656 roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val);
657
658 dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep);
659 dev_dbg(dev, "ext ODB threshold: empty: 0x%x, ful: 0x%x\n",
660 ext_odb_alept, ext_odb_alful);
661 }
662
hns_roce_db_ext_init(struct hns_roce_dev * hr_dev,u32 sdb_ext_mod,u32 odb_ext_mod)663 static int hns_roce_db_ext_init(struct hns_roce_dev *hr_dev, u32 sdb_ext_mod,
664 u32 odb_ext_mod)
665 {
666 struct hns_roce_v1_priv *priv = hr_dev->priv;
667 struct hns_roce_db_table *db = &priv->db_table;
668 struct device *dev = &hr_dev->pdev->dev;
669 dma_addr_t sdb_dma_addr;
670 dma_addr_t odb_dma_addr;
671 int ret = 0;
672
673 db->ext_db = kmalloc(sizeof(*db->ext_db), GFP_KERNEL);
674 if (!db->ext_db)
675 return -ENOMEM;
676
677 if (sdb_ext_mod) {
678 db->ext_db->sdb_buf_list = kmalloc(
679 sizeof(*db->ext_db->sdb_buf_list), GFP_KERNEL);
680 if (!db->ext_db->sdb_buf_list) {
681 ret = -ENOMEM;
682 goto ext_sdb_buf_fail_out;
683 }
684
685 db->ext_db->sdb_buf_list->buf = dma_alloc_coherent(dev,
686 HNS_ROCE_V1_EXT_SDB_SIZE,
687 &sdb_dma_addr, GFP_KERNEL);
688 if (!db->ext_db->sdb_buf_list->buf) {
689 ret = -ENOMEM;
690 goto alloc_sq_db_buf_fail;
691 }
692 db->ext_db->sdb_buf_list->map = sdb_dma_addr;
693
694 db->ext_db->esdb_dep = ilog2(HNS_ROCE_V1_EXT_SDB_DEPTH);
695 hns_roce_set_sdb_ext(hr_dev, HNS_ROCE_V1_EXT_SDB_ALEPT,
696 HNS_ROCE_V1_EXT_SDB_ALFUL);
697 } else
698 hns_roce_set_sdb(hr_dev, HNS_ROCE_V1_SDB_ALEPT,
699 HNS_ROCE_V1_SDB_ALFUL);
700
701 if (odb_ext_mod) {
702 db->ext_db->odb_buf_list = kmalloc(
703 sizeof(*db->ext_db->odb_buf_list), GFP_KERNEL);
704 if (!db->ext_db->odb_buf_list) {
705 ret = -ENOMEM;
706 goto ext_odb_buf_fail_out;
707 }
708
709 db->ext_db->odb_buf_list->buf = dma_alloc_coherent(dev,
710 HNS_ROCE_V1_EXT_ODB_SIZE,
711 &odb_dma_addr, GFP_KERNEL);
712 if (!db->ext_db->odb_buf_list->buf) {
713 ret = -ENOMEM;
714 goto alloc_otr_db_buf_fail;
715 }
716 db->ext_db->odb_buf_list->map = odb_dma_addr;
717
718 db->ext_db->eodb_dep = ilog2(HNS_ROCE_V1_EXT_ODB_DEPTH);
719 hns_roce_set_odb_ext(hr_dev, HNS_ROCE_V1_EXT_ODB_ALEPT,
720 HNS_ROCE_V1_EXT_ODB_ALFUL);
721 } else
722 hns_roce_set_odb(hr_dev, HNS_ROCE_V1_ODB_ALEPT,
723 HNS_ROCE_V1_ODB_ALFUL);
724
725 hns_roce_set_db_ext_mode(hr_dev, sdb_ext_mod, odb_ext_mod);
726
727 return 0;
728
729 alloc_otr_db_buf_fail:
730 kfree(db->ext_db->odb_buf_list);
731
732 ext_odb_buf_fail_out:
733 if (sdb_ext_mod) {
734 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
735 db->ext_db->sdb_buf_list->buf,
736 db->ext_db->sdb_buf_list->map);
737 }
738
739 alloc_sq_db_buf_fail:
740 if (sdb_ext_mod)
741 kfree(db->ext_db->sdb_buf_list);
742
743 ext_sdb_buf_fail_out:
744 kfree(db->ext_db);
745 return ret;
746 }
747
hns_roce_v1_create_lp_qp(struct hns_roce_dev * hr_dev,struct ib_pd * pd)748 static struct hns_roce_qp *hns_roce_v1_create_lp_qp(struct hns_roce_dev *hr_dev,
749 struct ib_pd *pd)
750 {
751 struct device *dev = &hr_dev->pdev->dev;
752 struct ib_qp_init_attr init_attr;
753 struct ib_qp *qp;
754
755 memset(&init_attr, 0, sizeof(struct ib_qp_init_attr));
756 init_attr.qp_type = IB_QPT_RC;
757 init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
758 init_attr.cap.max_recv_wr = HNS_ROCE_MIN_WQE_NUM;
759 init_attr.cap.max_send_wr = HNS_ROCE_MIN_WQE_NUM;
760
761 qp = ib_create_qp(pd, &init_attr);
762 if (IS_ERR(qp)) {
763 dev_err(dev, "Create loop qp for mr free failed!");
764 return NULL;
765 }
766
767 return to_hr_qp(qp);
768 }
769
hns_roce_v1_rsv_lp_qp(struct hns_roce_dev * hr_dev)770 static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
771 {
772 struct hns_roce_v1_priv *priv = hr_dev->priv;
773 struct hns_roce_free_mr *free_mr = &priv->free_mr;
774 struct hns_roce_caps *caps = &hr_dev->caps;
775 struct ib_device *ibdev = &hr_dev->ib_dev;
776 struct device *dev = &hr_dev->pdev->dev;
777 struct ib_cq_init_attr cq_init_attr;
778 struct ib_qp_attr attr = { 0 };
779 struct hns_roce_qp *hr_qp;
780 struct ib_cq *cq;
781 struct ib_pd *pd;
782 union ib_gid dgid;
783 __be64 subnet_prefix;
784 int attr_mask = 0;
785 int ret;
786 int i, j;
787 u8 queue_en[HNS_ROCE_V1_RESV_QP] = { 0 };
788 u8 phy_port;
789 u32 port = 0;
790 u8 sl;
791
792 /* Reserved cq for loop qp */
793 cq_init_attr.cqe = HNS_ROCE_MIN_WQE_NUM * 2;
794 cq_init_attr.comp_vector = 0;
795
796 cq = rdma_zalloc_drv_obj(ibdev, ib_cq);
797 if (!cq)
798 return -ENOMEM;
799
800 ret = hns_roce_create_cq(cq, &cq_init_attr, NULL);
801 if (ret) {
802 dev_err(dev, "Create cq for reserved loop qp failed!");
803 goto alloc_cq_failed;
804 }
805 free_mr->mr_free_cq = to_hr_cq(cq);
806 free_mr->mr_free_cq->ib_cq.device = &hr_dev->ib_dev;
807 free_mr->mr_free_cq->ib_cq.uobject = NULL;
808 free_mr->mr_free_cq->ib_cq.comp_handler = NULL;
809 free_mr->mr_free_cq->ib_cq.event_handler = NULL;
810 free_mr->mr_free_cq->ib_cq.cq_context = NULL;
811 atomic_set(&free_mr->mr_free_cq->ib_cq.usecnt, 0);
812
813 pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
814 if (!pd) {
815 ret = -ENOMEM;
816 goto alloc_mem_failed;
817 }
818
819 pd->device = ibdev;
820 ret = hns_roce_alloc_pd(pd, NULL);
821 if (ret)
822 goto alloc_pd_failed;
823
824 free_mr->mr_free_pd = to_hr_pd(pd);
825 free_mr->mr_free_pd->ibpd.device = &hr_dev->ib_dev;
826 free_mr->mr_free_pd->ibpd.uobject = NULL;
827 free_mr->mr_free_pd->ibpd.__internal_mr = NULL;
828 atomic_set(&free_mr->mr_free_pd->ibpd.usecnt, 0);
829
830 attr.qp_access_flags = IB_ACCESS_REMOTE_WRITE;
831 attr.pkey_index = 0;
832 attr.min_rnr_timer = 0;
833 /* Disable read ability */
834 attr.max_dest_rd_atomic = 0;
835 attr.max_rd_atomic = 0;
836 /* Use arbitrary values as rq_psn and sq_psn */
837 attr.rq_psn = 0x0808;
838 attr.sq_psn = 0x0808;
839 attr.retry_cnt = 7;
840 attr.rnr_retry = 7;
841 attr.timeout = 0x12;
842 attr.path_mtu = IB_MTU_256;
843 attr.ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
844 rdma_ah_set_grh(&attr.ah_attr, NULL, 0, 0, 1, 0);
845 rdma_ah_set_static_rate(&attr.ah_attr, 3);
846
847 subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
848 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
849 phy_port = (i >= HNS_ROCE_MAX_PORTS) ? (i - 2) :
850 (i % HNS_ROCE_MAX_PORTS);
851 sl = i / HNS_ROCE_MAX_PORTS;
852
853 for (j = 0; j < caps->num_ports; j++) {
854 if (hr_dev->iboe.phy_port[j] == phy_port) {
855 queue_en[i] = 1;
856 port = j;
857 break;
858 }
859 }
860
861 if (!queue_en[i])
862 continue;
863
864 free_mr->mr_free_qp[i] = hns_roce_v1_create_lp_qp(hr_dev, pd);
865 if (!free_mr->mr_free_qp[i]) {
866 dev_err(dev, "Create loop qp failed!\n");
867 ret = -ENOMEM;
868 goto create_lp_qp_failed;
869 }
870 hr_qp = free_mr->mr_free_qp[i];
871
872 hr_qp->port = port;
873 hr_qp->phy_port = phy_port;
874 hr_qp->ibqp.qp_type = IB_QPT_RC;
875 hr_qp->ibqp.device = &hr_dev->ib_dev;
876 hr_qp->ibqp.uobject = NULL;
877 atomic_set(&hr_qp->ibqp.usecnt, 0);
878 hr_qp->ibqp.pd = pd;
879 hr_qp->ibqp.recv_cq = cq;
880 hr_qp->ibqp.send_cq = cq;
881
882 rdma_ah_set_port_num(&attr.ah_attr, port + 1);
883 rdma_ah_set_sl(&attr.ah_attr, sl);
884 attr.port_num = port + 1;
885
886 attr.dest_qp_num = hr_qp->qpn;
887 memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
888 hr_dev->dev_addr[port],
889 ETH_ALEN);
890
891 memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
892 memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
893 memcpy(&dgid.raw[13], hr_dev->dev_addr[port] + 3, 3);
894 dgid.raw[11] = 0xff;
895 dgid.raw[12] = 0xfe;
896 dgid.raw[8] ^= 2;
897 rdma_ah_set_dgid_raw(&attr.ah_attr, dgid.raw);
898
899 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
900 IB_QPS_RESET, IB_QPS_INIT);
901 if (ret) {
902 dev_err(dev, "modify qp failed(%d)!\n", ret);
903 goto create_lp_qp_failed;
904 }
905
906 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, IB_QP_DEST_QPN,
907 IB_QPS_INIT, IB_QPS_RTR);
908 if (ret) {
909 dev_err(dev, "modify qp failed(%d)!\n", ret);
910 goto create_lp_qp_failed;
911 }
912
913 ret = hr_dev->hw->modify_qp(&hr_qp->ibqp, &attr, attr_mask,
914 IB_QPS_RTR, IB_QPS_RTS);
915 if (ret) {
916 dev_err(dev, "modify qp failed(%d)!\n", ret);
917 goto create_lp_qp_failed;
918 }
919 }
920
921 return 0;
922
923 create_lp_qp_failed:
924 for (i -= 1; i >= 0; i--) {
925 hr_qp = free_mr->mr_free_qp[i];
926 if (ib_destroy_qp(&hr_qp->ibqp))
927 dev_err(dev, "Destroy qp %d for mr free failed!\n", i);
928 }
929
930 hns_roce_dealloc_pd(pd, NULL);
931
932 alloc_pd_failed:
933 kfree(pd);
934
935 alloc_mem_failed:
936 hns_roce_destroy_cq(cq, NULL);
937 alloc_cq_failed:
938 kfree(cq);
939 return ret;
940 }
941
hns_roce_v1_release_lp_qp(struct hns_roce_dev * hr_dev)942 static void hns_roce_v1_release_lp_qp(struct hns_roce_dev *hr_dev)
943 {
944 struct hns_roce_v1_priv *priv = hr_dev->priv;
945 struct hns_roce_free_mr *free_mr = &priv->free_mr;
946 struct device *dev = &hr_dev->pdev->dev;
947 struct hns_roce_qp *hr_qp;
948 int ret;
949 int i;
950
951 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
952 hr_qp = free_mr->mr_free_qp[i];
953 if (!hr_qp)
954 continue;
955
956 ret = ib_destroy_qp(&hr_qp->ibqp);
957 if (ret)
958 dev_err(dev, "Destroy qp %d for mr free failed(%d)!\n",
959 i, ret);
960 }
961
962 hns_roce_destroy_cq(&free_mr->mr_free_cq->ib_cq, NULL);
963 kfree(&free_mr->mr_free_cq->ib_cq);
964 hns_roce_dealloc_pd(&free_mr->mr_free_pd->ibpd, NULL);
965 kfree(&free_mr->mr_free_pd->ibpd);
966 }
967
hns_roce_db_init(struct hns_roce_dev * hr_dev)968 static int hns_roce_db_init(struct hns_roce_dev *hr_dev)
969 {
970 struct hns_roce_v1_priv *priv = hr_dev->priv;
971 struct hns_roce_db_table *db = &priv->db_table;
972 struct device *dev = &hr_dev->pdev->dev;
973 u32 sdb_ext_mod;
974 u32 odb_ext_mod;
975 u32 sdb_evt_mod;
976 u32 odb_evt_mod;
977 int ret;
978
979 memset(db, 0, sizeof(*db));
980
981 /* Default DB mode */
982 sdb_ext_mod = HNS_ROCE_SDB_EXTEND_MODE;
983 odb_ext_mod = HNS_ROCE_ODB_EXTEND_MODE;
984 sdb_evt_mod = HNS_ROCE_SDB_NORMAL_MODE;
985 odb_evt_mod = HNS_ROCE_ODB_POLL_MODE;
986
987 db->sdb_ext_mod = sdb_ext_mod;
988 db->odb_ext_mod = odb_ext_mod;
989
990 /* Init extend DB */
991 ret = hns_roce_db_ext_init(hr_dev, sdb_ext_mod, odb_ext_mod);
992 if (ret) {
993 dev_err(dev, "Failed in extend DB configuration.\n");
994 return ret;
995 }
996
997 hns_roce_set_db_event_mode(hr_dev, sdb_evt_mod, odb_evt_mod);
998
999 return 0;
1000 }
1001
hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct * work)1002 static void hns_roce_v1_recreate_lp_qp_work_fn(struct work_struct *work)
1003 {
1004 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
1005 struct hns_roce_dev *hr_dev;
1006
1007 lp_qp_work = container_of(work, struct hns_roce_recreate_lp_qp_work,
1008 work);
1009 hr_dev = to_hr_dev(lp_qp_work->ib_dev);
1010
1011 hns_roce_v1_release_lp_qp(hr_dev);
1012
1013 if (hns_roce_v1_rsv_lp_qp(hr_dev))
1014 dev_err(&hr_dev->pdev->dev, "create reserver qp failed\n");
1015
1016 if (lp_qp_work->comp_flag)
1017 complete(lp_qp_work->comp);
1018
1019 kfree(lp_qp_work);
1020 }
1021
hns_roce_v1_recreate_lp_qp(struct hns_roce_dev * hr_dev)1022 static int hns_roce_v1_recreate_lp_qp(struct hns_roce_dev *hr_dev)
1023 {
1024 long end = HNS_ROCE_V1_RECREATE_LP_QP_TIMEOUT_MSECS;
1025 struct hns_roce_v1_priv *priv = hr_dev->priv;
1026 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1027 struct hns_roce_recreate_lp_qp_work *lp_qp_work;
1028 struct device *dev = &hr_dev->pdev->dev;
1029 struct completion comp;
1030
1031 lp_qp_work = kzalloc(sizeof(struct hns_roce_recreate_lp_qp_work),
1032 GFP_KERNEL);
1033 if (!lp_qp_work)
1034 return -ENOMEM;
1035
1036 INIT_WORK(&(lp_qp_work->work), hns_roce_v1_recreate_lp_qp_work_fn);
1037
1038 lp_qp_work->ib_dev = &(hr_dev->ib_dev);
1039 lp_qp_work->comp = ∁
1040 lp_qp_work->comp_flag = 1;
1041
1042 init_completion(lp_qp_work->comp);
1043
1044 queue_work(free_mr->free_mr_wq, &(lp_qp_work->work));
1045
1046 while (end > 0) {
1047 if (try_wait_for_completion(&comp))
1048 return 0;
1049 msleep(HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE);
1050 end -= HNS_ROCE_V1_RECREATE_LP_QP_WAIT_VALUE;
1051 }
1052
1053 lp_qp_work->comp_flag = 0;
1054 if (try_wait_for_completion(&comp))
1055 return 0;
1056
1057 dev_warn(dev, "recreate lp qp failed 20s timeout and return failed!\n");
1058 return -ETIMEDOUT;
1059 }
1060
hns_roce_v1_send_lp_wqe(struct hns_roce_qp * hr_qp)1061 static int hns_roce_v1_send_lp_wqe(struct hns_roce_qp *hr_qp)
1062 {
1063 struct hns_roce_dev *hr_dev = to_hr_dev(hr_qp->ibqp.device);
1064 struct device *dev = &hr_dev->pdev->dev;
1065 struct ib_send_wr send_wr;
1066 const struct ib_send_wr *bad_wr;
1067 int ret;
1068
1069 memset(&send_wr, 0, sizeof(send_wr));
1070 send_wr.next = NULL;
1071 send_wr.num_sge = 0;
1072 send_wr.send_flags = 0;
1073 send_wr.sg_list = NULL;
1074 send_wr.wr_id = (unsigned long long)&send_wr;
1075 send_wr.opcode = IB_WR_RDMA_WRITE;
1076
1077 ret = hns_roce_v1_post_send(&hr_qp->ibqp, &send_wr, &bad_wr);
1078 if (ret) {
1079 dev_err(dev, "Post write wqe for mr free failed(%d)!", ret);
1080 return ret;
1081 }
1082
1083 return 0;
1084 }
1085
hns_roce_v1_mr_free_work_fn(struct work_struct * work)1086 static void hns_roce_v1_mr_free_work_fn(struct work_struct *work)
1087 {
1088 unsigned long end =
1089 msecs_to_jiffies(HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS) + jiffies;
1090 struct hns_roce_mr_free_work *mr_work =
1091 container_of(work, struct hns_roce_mr_free_work, work);
1092 struct hns_roce_dev *hr_dev = to_hr_dev(mr_work->ib_dev);
1093 struct hns_roce_v1_priv *priv = hr_dev->priv;
1094 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1095 struct hns_roce_cq *mr_free_cq = free_mr->mr_free_cq;
1096 struct hns_roce_mr *hr_mr = mr_work->mr;
1097 struct device *dev = &hr_dev->pdev->dev;
1098 struct ib_wc wc[HNS_ROCE_V1_RESV_QP];
1099 struct hns_roce_qp *hr_qp;
1100 int ne = 0;
1101 int ret;
1102 int i;
1103
1104 for (i = 0; i < HNS_ROCE_V1_RESV_QP; i++) {
1105 hr_qp = free_mr->mr_free_qp[i];
1106 if (!hr_qp)
1107 continue;
1108 ne++;
1109
1110 ret = hns_roce_v1_send_lp_wqe(hr_qp);
1111 if (ret) {
1112 dev_err(dev,
1113 "Send wqe (qp:0x%lx) for mr free failed(%d)!\n",
1114 hr_qp->qpn, ret);
1115 goto free_work;
1116 }
1117 }
1118
1119 if (!ne) {
1120 dev_err(dev, "Reserved loop qp is absent!\n");
1121 goto free_work;
1122 }
1123
1124 do {
1125 ret = hns_roce_v1_poll_cq(&mr_free_cq->ib_cq, ne, wc);
1126 if (ret < 0 && hr_qp) {
1127 dev_err(dev,
1128 "(qp:0x%lx) starts, Poll cqe failed(%d) for mr 0x%x free! Remain %d cqe\n",
1129 hr_qp->qpn, ret, hr_mr->key, ne);
1130 goto free_work;
1131 }
1132 ne -= ret;
1133 usleep_range(HNS_ROCE_V1_FREE_MR_WAIT_VALUE * 1000,
1134 (1 + HNS_ROCE_V1_FREE_MR_WAIT_VALUE) * 1000);
1135 } while (ne && time_before_eq(jiffies, end));
1136
1137 if (ne != 0)
1138 dev_err(dev,
1139 "Poll cqe for mr 0x%x free timeout! Remain %d cqe\n",
1140 hr_mr->key, ne);
1141
1142 free_work:
1143 if (mr_work->comp_flag)
1144 complete(mr_work->comp);
1145 kfree(mr_work);
1146 }
1147
hns_roce_v1_dereg_mr(struct hns_roce_dev * hr_dev,struct hns_roce_mr * mr,struct ib_udata * udata)1148 static int hns_roce_v1_dereg_mr(struct hns_roce_dev *hr_dev,
1149 struct hns_roce_mr *mr, struct ib_udata *udata)
1150 {
1151 struct hns_roce_v1_priv *priv = hr_dev->priv;
1152 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1153 long end = HNS_ROCE_V1_FREE_MR_TIMEOUT_MSECS;
1154 struct device *dev = &hr_dev->pdev->dev;
1155 struct hns_roce_mr_free_work *mr_work;
1156 unsigned long start = jiffies;
1157 struct completion comp;
1158 int ret = 0;
1159
1160 if (mr->enabled) {
1161 if (hns_roce_hw_destroy_mpt(hr_dev, NULL,
1162 key_to_hw_index(mr->key) &
1163 (hr_dev->caps.num_mtpts - 1)))
1164 dev_warn(dev, "DESTROY_MPT failed!\n");
1165 }
1166
1167 mr_work = kzalloc(sizeof(*mr_work), GFP_KERNEL);
1168 if (!mr_work) {
1169 ret = -ENOMEM;
1170 goto free_mr;
1171 }
1172
1173 INIT_WORK(&(mr_work->work), hns_roce_v1_mr_free_work_fn);
1174
1175 mr_work->ib_dev = &(hr_dev->ib_dev);
1176 mr_work->comp = ∁
1177 mr_work->comp_flag = 1;
1178 mr_work->mr = (void *)mr;
1179 init_completion(mr_work->comp);
1180
1181 queue_work(free_mr->free_mr_wq, &(mr_work->work));
1182
1183 while (end > 0) {
1184 if (try_wait_for_completion(&comp))
1185 goto free_mr;
1186 msleep(HNS_ROCE_V1_FREE_MR_WAIT_VALUE);
1187 end -= HNS_ROCE_V1_FREE_MR_WAIT_VALUE;
1188 }
1189
1190 mr_work->comp_flag = 0;
1191 if (try_wait_for_completion(&comp))
1192 goto free_mr;
1193
1194 dev_warn(dev, "Free mr work 0x%x over 50s and failed!\n", mr->key);
1195 ret = -ETIMEDOUT;
1196
1197 free_mr:
1198 dev_dbg(dev, "Free mr 0x%x use 0x%x us.\n",
1199 mr->key, jiffies_to_usecs(jiffies) - jiffies_to_usecs(start));
1200
1201 ida_free(&hr_dev->mr_table.mtpt_ida.ida, (int)key_to_hw_index(mr->key));
1202 hns_roce_mtr_destroy(hr_dev, &mr->pbl_mtr);
1203 kfree(mr);
1204
1205 return ret;
1206 }
1207
hns_roce_db_free(struct hns_roce_dev * hr_dev)1208 static void hns_roce_db_free(struct hns_roce_dev *hr_dev)
1209 {
1210 struct hns_roce_v1_priv *priv = hr_dev->priv;
1211 struct hns_roce_db_table *db = &priv->db_table;
1212 struct device *dev = &hr_dev->pdev->dev;
1213
1214 if (db->sdb_ext_mod) {
1215 dma_free_coherent(dev, HNS_ROCE_V1_EXT_SDB_SIZE,
1216 db->ext_db->sdb_buf_list->buf,
1217 db->ext_db->sdb_buf_list->map);
1218 kfree(db->ext_db->sdb_buf_list);
1219 }
1220
1221 if (db->odb_ext_mod) {
1222 dma_free_coherent(dev, HNS_ROCE_V1_EXT_ODB_SIZE,
1223 db->ext_db->odb_buf_list->buf,
1224 db->ext_db->odb_buf_list->map);
1225 kfree(db->ext_db->odb_buf_list);
1226 }
1227
1228 kfree(db->ext_db);
1229 }
1230
hns_roce_raq_init(struct hns_roce_dev * hr_dev)1231 static int hns_roce_raq_init(struct hns_roce_dev *hr_dev)
1232 {
1233 struct hns_roce_v1_priv *priv = hr_dev->priv;
1234 struct hns_roce_raq_table *raq = &priv->raq_table;
1235 struct device *dev = &hr_dev->pdev->dev;
1236 dma_addr_t addr;
1237 int raq_shift;
1238 __le32 tmp;
1239 u32 val;
1240 int ret;
1241
1242 raq->e_raq_buf = kzalloc(sizeof(*(raq->e_raq_buf)), GFP_KERNEL);
1243 if (!raq->e_raq_buf)
1244 return -ENOMEM;
1245
1246 raq->e_raq_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_RAQ_SIZE,
1247 &addr, GFP_KERNEL);
1248 if (!raq->e_raq_buf->buf) {
1249 ret = -ENOMEM;
1250 goto err_dma_alloc_raq;
1251 }
1252 raq->e_raq_buf->map = addr;
1253
1254 /* Configure raq extended address. 48bit 4K align */
1255 roce_write(hr_dev, ROCEE_EXT_RAQ_REG, raq->e_raq_buf->map >> 12);
1256
1257 /* Configure raq_shift */
1258 raq_shift = ilog2(HNS_ROCE_V1_RAQ_SIZE / HNS_ROCE_V1_RAQ_ENTRY);
1259 val = roce_read(hr_dev, ROCEE_EXT_RAQ_H_REG);
1260 tmp = cpu_to_le32(val);
1261 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M,
1262 ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S, raq_shift);
1263 /*
1264 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
1265 * using 4K page, and shift more 32 because of
1266 * calculating the high 32 bit value evaluated to hardware.
1267 */
1268 roce_set_field(tmp, ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M,
1269 ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S,
1270 raq->e_raq_buf->map >> 44);
1271 val = le32_to_cpu(tmp);
1272 roce_write(hr_dev, ROCEE_EXT_RAQ_H_REG, val);
1273 dev_dbg(dev, "Configure raq_shift 0x%x.\n", val);
1274
1275 /* Configure raq threshold */
1276 val = roce_read(hr_dev, ROCEE_RAQ_WL_REG);
1277 tmp = cpu_to_le32(val);
1278 roce_set_field(tmp, ROCEE_RAQ_WL_ROCEE_RAQ_WL_M,
1279 ROCEE_RAQ_WL_ROCEE_RAQ_WL_S,
1280 HNS_ROCE_V1_EXT_RAQ_WF);
1281 val = le32_to_cpu(tmp);
1282 roce_write(hr_dev, ROCEE_RAQ_WL_REG, val);
1283 dev_dbg(dev, "Configure raq_wl 0x%x.\n", val);
1284
1285 /* Enable extend raq */
1286 val = roce_read(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG);
1287 tmp = cpu_to_le32(val);
1288 roce_set_field(tmp,
1289 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M,
1290 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S,
1291 POL_TIME_INTERVAL_VAL);
1292 roce_set_bit(tmp, ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE, 1);
1293 roce_set_field(tmp,
1294 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M,
1295 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S,
1296 2);
1297 roce_set_bit(tmp,
1298 ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S, 1);
1299 val = le32_to_cpu(tmp);
1300 roce_write(hr_dev, ROCEE_WRMS_POL_TIME_INTERVAL_REG, val);
1301 dev_dbg(dev, "Configure WrmsPolTimeInterval 0x%x.\n", val);
1302
1303 /* Enable raq drop */
1304 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1305 tmp = cpu_to_le32(val);
1306 roce_set_bit(tmp, ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S, 1);
1307 val = le32_to_cpu(tmp);
1308 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1309 dev_dbg(dev, "Configure GlbCfg = 0x%x.\n", val);
1310
1311 return 0;
1312
1313 err_dma_alloc_raq:
1314 kfree(raq->e_raq_buf);
1315 return ret;
1316 }
1317
hns_roce_raq_free(struct hns_roce_dev * hr_dev)1318 static void hns_roce_raq_free(struct hns_roce_dev *hr_dev)
1319 {
1320 struct hns_roce_v1_priv *priv = hr_dev->priv;
1321 struct hns_roce_raq_table *raq = &priv->raq_table;
1322 struct device *dev = &hr_dev->pdev->dev;
1323
1324 dma_free_coherent(dev, HNS_ROCE_V1_RAQ_SIZE, raq->e_raq_buf->buf,
1325 raq->e_raq_buf->map);
1326 kfree(raq->e_raq_buf);
1327 }
1328
hns_roce_port_enable(struct hns_roce_dev * hr_dev,int enable_flag)1329 static void hns_roce_port_enable(struct hns_roce_dev *hr_dev, int enable_flag)
1330 {
1331 __le32 tmp;
1332 u32 val;
1333
1334 if (enable_flag) {
1335 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1336 /* Open all ports */
1337 tmp = cpu_to_le32(val);
1338 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1339 ROCEE_GLB_CFG_ROCEE_PORT_ST_S,
1340 ALL_PORT_VAL_OPEN);
1341 val = le32_to_cpu(tmp);
1342 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1343 } else {
1344 val = roce_read(hr_dev, ROCEE_GLB_CFG_REG);
1345 /* Close all ports */
1346 tmp = cpu_to_le32(val);
1347 roce_set_field(tmp, ROCEE_GLB_CFG_ROCEE_PORT_ST_M,
1348 ROCEE_GLB_CFG_ROCEE_PORT_ST_S, 0x0);
1349 val = le32_to_cpu(tmp);
1350 roce_write(hr_dev, ROCEE_GLB_CFG_REG, val);
1351 }
1352 }
1353
hns_roce_bt_init(struct hns_roce_dev * hr_dev)1354 static int hns_roce_bt_init(struct hns_roce_dev *hr_dev)
1355 {
1356 struct hns_roce_v1_priv *priv = hr_dev->priv;
1357 struct device *dev = &hr_dev->pdev->dev;
1358 int ret;
1359
1360 priv->bt_table.qpc_buf.buf = dma_alloc_coherent(dev,
1361 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.qpc_buf.map,
1362 GFP_KERNEL);
1363 if (!priv->bt_table.qpc_buf.buf)
1364 return -ENOMEM;
1365
1366 priv->bt_table.mtpt_buf.buf = dma_alloc_coherent(dev,
1367 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.mtpt_buf.map,
1368 GFP_KERNEL);
1369 if (!priv->bt_table.mtpt_buf.buf) {
1370 ret = -ENOMEM;
1371 goto err_failed_alloc_mtpt_buf;
1372 }
1373
1374 priv->bt_table.cqc_buf.buf = dma_alloc_coherent(dev,
1375 HNS_ROCE_BT_RSV_BUF_SIZE, &priv->bt_table.cqc_buf.map,
1376 GFP_KERNEL);
1377 if (!priv->bt_table.cqc_buf.buf) {
1378 ret = -ENOMEM;
1379 goto err_failed_alloc_cqc_buf;
1380 }
1381
1382 return 0;
1383
1384 err_failed_alloc_cqc_buf:
1385 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1386 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1387
1388 err_failed_alloc_mtpt_buf:
1389 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1390 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1391
1392 return ret;
1393 }
1394
hns_roce_bt_free(struct hns_roce_dev * hr_dev)1395 static void hns_roce_bt_free(struct hns_roce_dev *hr_dev)
1396 {
1397 struct hns_roce_v1_priv *priv = hr_dev->priv;
1398 struct device *dev = &hr_dev->pdev->dev;
1399
1400 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1401 priv->bt_table.cqc_buf.buf, priv->bt_table.cqc_buf.map);
1402
1403 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1404 priv->bt_table.mtpt_buf.buf, priv->bt_table.mtpt_buf.map);
1405
1406 dma_free_coherent(dev, HNS_ROCE_BT_RSV_BUF_SIZE,
1407 priv->bt_table.qpc_buf.buf, priv->bt_table.qpc_buf.map);
1408 }
1409
hns_roce_tptr_init(struct hns_roce_dev * hr_dev)1410 static int hns_roce_tptr_init(struct hns_roce_dev *hr_dev)
1411 {
1412 struct hns_roce_v1_priv *priv = hr_dev->priv;
1413 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1414 struct device *dev = &hr_dev->pdev->dev;
1415
1416 /*
1417 * This buffer will be used for CQ's tptr(tail pointer), also
1418 * named ci(customer index). Every CQ will use 2 bytes to save
1419 * cqe ci in hip06. Hardware will read this area to get new ci
1420 * when the queue is almost full.
1421 */
1422 tptr_buf->buf = dma_alloc_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1423 &tptr_buf->map, GFP_KERNEL);
1424 if (!tptr_buf->buf)
1425 return -ENOMEM;
1426
1427 hr_dev->tptr_dma_addr = tptr_buf->map;
1428 hr_dev->tptr_size = HNS_ROCE_V1_TPTR_BUF_SIZE;
1429
1430 return 0;
1431 }
1432
hns_roce_tptr_free(struct hns_roce_dev * hr_dev)1433 static void hns_roce_tptr_free(struct hns_roce_dev *hr_dev)
1434 {
1435 struct hns_roce_v1_priv *priv = hr_dev->priv;
1436 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
1437 struct device *dev = &hr_dev->pdev->dev;
1438
1439 dma_free_coherent(dev, HNS_ROCE_V1_TPTR_BUF_SIZE,
1440 tptr_buf->buf, tptr_buf->map);
1441 }
1442
hns_roce_free_mr_init(struct hns_roce_dev * hr_dev)1443 static int hns_roce_free_mr_init(struct hns_roce_dev *hr_dev)
1444 {
1445 struct hns_roce_v1_priv *priv = hr_dev->priv;
1446 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1447 struct device *dev = &hr_dev->pdev->dev;
1448 int ret;
1449
1450 free_mr->free_mr_wq = create_singlethread_workqueue("hns_roce_free_mr");
1451 if (!free_mr->free_mr_wq) {
1452 dev_err(dev, "Create free mr workqueue failed!\n");
1453 return -ENOMEM;
1454 }
1455
1456 ret = hns_roce_v1_rsv_lp_qp(hr_dev);
1457 if (ret) {
1458 dev_err(dev, "Reserved loop qp failed(%d)!\n", ret);
1459 destroy_workqueue(free_mr->free_mr_wq);
1460 }
1461
1462 return ret;
1463 }
1464
hns_roce_free_mr_free(struct hns_roce_dev * hr_dev)1465 static void hns_roce_free_mr_free(struct hns_roce_dev *hr_dev)
1466 {
1467 struct hns_roce_v1_priv *priv = hr_dev->priv;
1468 struct hns_roce_free_mr *free_mr = &priv->free_mr;
1469
1470 destroy_workqueue(free_mr->free_mr_wq);
1471
1472 hns_roce_v1_release_lp_qp(hr_dev);
1473 }
1474
1475 /**
1476 * hns_roce_v1_reset - reset RoCE
1477 * @hr_dev: RoCE device struct pointer
1478 * @dereset: true -- drop reset, false -- reset
1479 * return 0 - success , negative --fail
1480 */
hns_roce_v1_reset(struct hns_roce_dev * hr_dev,bool dereset)1481 static int hns_roce_v1_reset(struct hns_roce_dev *hr_dev, bool dereset)
1482 {
1483 struct device_node *dsaf_node;
1484 struct device *dev = &hr_dev->pdev->dev;
1485 struct device_node *np = dev->of_node;
1486 struct fwnode_handle *fwnode;
1487 int ret;
1488
1489 /* check if this is DT/ACPI case */
1490 if (dev_of_node(dev)) {
1491 dsaf_node = of_parse_phandle(np, "dsaf-handle", 0);
1492 if (!dsaf_node) {
1493 dev_err(dev, "could not find dsaf-handle\n");
1494 return -EINVAL;
1495 }
1496 fwnode = &dsaf_node->fwnode;
1497 } else if (is_acpi_device_node(dev->fwnode)) {
1498 struct fwnode_reference_args args;
1499
1500 ret = acpi_node_get_property_reference(dev->fwnode,
1501 "dsaf-handle", 0, &args);
1502 if (ret) {
1503 dev_err(dev, "could not find dsaf-handle\n");
1504 return ret;
1505 }
1506 fwnode = args.fwnode;
1507 } else {
1508 dev_err(dev, "cannot read data from DT or ACPI\n");
1509 return -ENXIO;
1510 }
1511
1512 ret = hns_dsaf_roce_reset(fwnode, false);
1513 if (ret)
1514 return ret;
1515
1516 if (dereset) {
1517 msleep(SLEEP_TIME_INTERVAL);
1518 ret = hns_dsaf_roce_reset(fwnode, true);
1519 }
1520
1521 return ret;
1522 }
1523
hns_roce_v1_profile(struct hns_roce_dev * hr_dev)1524 static int hns_roce_v1_profile(struct hns_roce_dev *hr_dev)
1525 {
1526 struct hns_roce_caps *caps = &hr_dev->caps;
1527 int i;
1528
1529 hr_dev->vendor_id = roce_read(hr_dev, ROCEE_VENDOR_ID_REG);
1530 hr_dev->vendor_part_id = roce_read(hr_dev, ROCEE_VENDOR_PART_ID_REG);
1531 hr_dev->sys_image_guid = roce_read(hr_dev, ROCEE_SYS_IMAGE_GUID_L_REG) |
1532 ((u64)roce_read(hr_dev,
1533 ROCEE_SYS_IMAGE_GUID_H_REG) << 32);
1534 hr_dev->hw_rev = HNS_ROCE_HW_VER1;
1535
1536 caps->num_qps = HNS_ROCE_V1_MAX_QP_NUM;
1537 caps->max_wqes = HNS_ROCE_V1_MAX_WQE_NUM;
1538 caps->min_wqes = HNS_ROCE_MIN_WQE_NUM;
1539 caps->num_cqs = HNS_ROCE_V1_MAX_CQ_NUM;
1540 caps->min_cqes = HNS_ROCE_MIN_CQE_NUM;
1541 caps->max_cqes = HNS_ROCE_V1_MAX_CQE_NUM;
1542 caps->max_sq_sg = HNS_ROCE_V1_SG_NUM;
1543 caps->max_rq_sg = HNS_ROCE_V1_SG_NUM;
1544 caps->max_sq_inline = HNS_ROCE_V1_INLINE_SIZE;
1545 caps->num_uars = HNS_ROCE_V1_UAR_NUM;
1546 caps->phy_num_uars = HNS_ROCE_V1_PHY_UAR_NUM;
1547 caps->num_aeq_vectors = HNS_ROCE_V1_AEQE_VEC_NUM;
1548 caps->num_comp_vectors = HNS_ROCE_V1_COMP_VEC_NUM;
1549 caps->num_other_vectors = HNS_ROCE_V1_ABNORMAL_VEC_NUM;
1550 caps->num_mtpts = HNS_ROCE_V1_MAX_MTPT_NUM;
1551 caps->num_mtt_segs = HNS_ROCE_V1_MAX_MTT_SEGS;
1552 caps->num_pds = HNS_ROCE_V1_MAX_PD_NUM;
1553 caps->max_qp_init_rdma = HNS_ROCE_V1_MAX_QP_INIT_RDMA;
1554 caps->max_qp_dest_rdma = HNS_ROCE_V1_MAX_QP_DEST_RDMA;
1555 caps->max_sq_desc_sz = HNS_ROCE_V1_MAX_SQ_DESC_SZ;
1556 caps->max_rq_desc_sz = HNS_ROCE_V1_MAX_RQ_DESC_SZ;
1557 caps->qpc_sz = HNS_ROCE_V1_QPC_SIZE;
1558 caps->irrl_entry_sz = HNS_ROCE_V1_IRRL_ENTRY_SIZE;
1559 caps->cqc_entry_sz = HNS_ROCE_V1_CQC_ENTRY_SIZE;
1560 caps->mtpt_entry_sz = HNS_ROCE_V1_MTPT_ENTRY_SIZE;
1561 caps->mtt_entry_sz = HNS_ROCE_V1_MTT_ENTRY_SIZE;
1562 caps->cqe_sz = HNS_ROCE_V1_CQE_SIZE;
1563 caps->page_size_cap = HNS_ROCE_V1_PAGE_SIZE_SUPPORT;
1564 caps->reserved_lkey = 0;
1565 caps->reserved_pds = 0;
1566 caps->reserved_mrws = 1;
1567 caps->reserved_uars = 0;
1568 caps->reserved_cqs = 0;
1569 caps->reserved_qps = 12; /* 2 SQP per port, six ports total 12 */
1570 caps->chunk_sz = HNS_ROCE_V1_TABLE_CHUNK_SIZE;
1571
1572 for (i = 0; i < caps->num_ports; i++)
1573 caps->pkey_table_len[i] = 1;
1574
1575 for (i = 0; i < caps->num_ports; i++) {
1576 /* Six ports shared 16 GID in v1 engine */
1577 if (i >= (HNS_ROCE_V1_GID_NUM % caps->num_ports))
1578 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1579 caps->num_ports;
1580 else
1581 caps->gid_table_len[i] = HNS_ROCE_V1_GID_NUM /
1582 caps->num_ports + 1;
1583 }
1584
1585 caps->ceqe_depth = HNS_ROCE_V1_COMP_EQE_NUM;
1586 caps->aeqe_depth = HNS_ROCE_V1_ASYNC_EQE_NUM;
1587 caps->local_ca_ack_delay = roce_read(hr_dev, ROCEE_ACK_DELAY_REG);
1588 caps->max_mtu = IB_MTU_2048;
1589
1590 return 0;
1591 }
1592
hns_roce_v1_init(struct hns_roce_dev * hr_dev)1593 static int hns_roce_v1_init(struct hns_roce_dev *hr_dev)
1594 {
1595 int ret;
1596 u32 val;
1597 __le32 tmp;
1598 struct device *dev = &hr_dev->pdev->dev;
1599
1600 /* DMAE user config */
1601 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG);
1602 tmp = cpu_to_le32(val);
1603 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M,
1604 ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf);
1605 roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M,
1606 ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S,
1607 1 << PAGES_SHIFT_16);
1608 val = le32_to_cpu(tmp);
1609 roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val);
1610
1611 val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG);
1612 tmp = cpu_to_le32(val);
1613 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M,
1614 ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf);
1615 roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M,
1616 ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S,
1617 1 << PAGES_SHIFT_16);
1618
1619 ret = hns_roce_db_init(hr_dev);
1620 if (ret) {
1621 dev_err(dev, "doorbell init failed!\n");
1622 return ret;
1623 }
1624
1625 ret = hns_roce_raq_init(hr_dev);
1626 if (ret) {
1627 dev_err(dev, "raq init failed!\n");
1628 goto error_failed_raq_init;
1629 }
1630
1631 ret = hns_roce_bt_init(hr_dev);
1632 if (ret) {
1633 dev_err(dev, "bt init failed!\n");
1634 goto error_failed_bt_init;
1635 }
1636
1637 ret = hns_roce_tptr_init(hr_dev);
1638 if (ret) {
1639 dev_err(dev, "tptr init failed!\n");
1640 goto error_failed_tptr_init;
1641 }
1642
1643 ret = hns_roce_free_mr_init(hr_dev);
1644 if (ret) {
1645 dev_err(dev, "free mr init failed!\n");
1646 goto error_failed_free_mr_init;
1647 }
1648
1649 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_UP);
1650
1651 return 0;
1652
1653 error_failed_free_mr_init:
1654 hns_roce_tptr_free(hr_dev);
1655
1656 error_failed_tptr_init:
1657 hns_roce_bt_free(hr_dev);
1658
1659 error_failed_bt_init:
1660 hns_roce_raq_free(hr_dev);
1661
1662 error_failed_raq_init:
1663 hns_roce_db_free(hr_dev);
1664 return ret;
1665 }
1666
hns_roce_v1_exit(struct hns_roce_dev * hr_dev)1667 static void hns_roce_v1_exit(struct hns_roce_dev *hr_dev)
1668 {
1669 hns_roce_port_enable(hr_dev, HNS_ROCE_PORT_DOWN);
1670 hns_roce_free_mr_free(hr_dev);
1671 hns_roce_tptr_free(hr_dev);
1672 hns_roce_bt_free(hr_dev);
1673 hns_roce_raq_free(hr_dev);
1674 hns_roce_db_free(hr_dev);
1675 }
1676
hns_roce_v1_cmd_pending(struct hns_roce_dev * hr_dev)1677 static int hns_roce_v1_cmd_pending(struct hns_roce_dev *hr_dev)
1678 {
1679 u32 status = readl(hr_dev->reg_base + ROCEE_MB6_REG);
1680
1681 return (!!(status & (1 << HCR_GO_BIT)));
1682 }
1683
hns_roce_v1_post_mbox(struct hns_roce_dev * hr_dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)1684 static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param,
1685 u64 out_param, u32 in_modifier, u8 op_modifier,
1686 u16 op, u16 token, int event)
1687 {
1688 u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG);
1689 unsigned long end;
1690 u32 val = 0;
1691 __le32 tmp;
1692
1693 end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies;
1694 while (hns_roce_v1_cmd_pending(hr_dev)) {
1695 if (time_after(jiffies, end)) {
1696 dev_err(hr_dev->dev, "jiffies=%d end=%d\n",
1697 (int)jiffies, (int)end);
1698 return -EAGAIN;
1699 }
1700 cond_resched();
1701 }
1702
1703 tmp = cpu_to_le32(val);
1704 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S,
1705 op);
1706 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M,
1707 ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier);
1708 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event);
1709 roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1);
1710 roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M,
1711 ROCEE_MB6_ROCEE_MB_TOKEN_S, token);
1712
1713 val = le32_to_cpu(tmp);
1714 writeq(in_param, hcr + 0);
1715 writeq(out_param, hcr + 2);
1716 writel(in_modifier, hcr + 4);
1717 /* Memory barrier */
1718 wmb();
1719
1720 writel(val, hcr + 5);
1721
1722 return 0;
1723 }
1724
hns_roce_v1_chk_mbox(struct hns_roce_dev * hr_dev,unsigned int timeout)1725 static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev,
1726 unsigned int timeout)
1727 {
1728 u8 __iomem *hcr = hr_dev->reg_base + ROCEE_MB1_REG;
1729 unsigned long end;
1730 u32 status = 0;
1731
1732 end = msecs_to_jiffies(timeout) + jiffies;
1733 while (hns_roce_v1_cmd_pending(hr_dev) && time_before(jiffies, end))
1734 cond_resched();
1735
1736 if (hns_roce_v1_cmd_pending(hr_dev)) {
1737 dev_err(hr_dev->dev, "[cmd_poll]hw run cmd TIMEDOUT!\n");
1738 return -ETIMEDOUT;
1739 }
1740
1741 status = le32_to_cpu((__force __le32)
1742 __raw_readl(hcr + HCR_STATUS_OFFSET));
1743 if ((status & STATUS_MASK) != 0x1) {
1744 dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status);
1745 return -EBUSY;
1746 }
1747
1748 return 0;
1749 }
1750
hns_roce_v1_set_gid(struct hns_roce_dev * hr_dev,u32 port,int gid_index,const union ib_gid * gid,const struct ib_gid_attr * attr)1751 static int hns_roce_v1_set_gid(struct hns_roce_dev *hr_dev, u32 port,
1752 int gid_index, const union ib_gid *gid,
1753 const struct ib_gid_attr *attr)
1754 {
1755 unsigned long flags;
1756 u32 *p = NULL;
1757 u8 gid_idx;
1758
1759 gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
1760
1761 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
1762
1763 p = (u32 *)&gid->raw[0];
1764 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_L_0_REG +
1765 (HNS_ROCE_V1_GID_NUM * gid_idx));
1766
1767 p = (u32 *)&gid->raw[4];
1768 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_ML_0_REG +
1769 (HNS_ROCE_V1_GID_NUM * gid_idx));
1770
1771 p = (u32 *)&gid->raw[8];
1772 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_MH_0_REG +
1773 (HNS_ROCE_V1_GID_NUM * gid_idx));
1774
1775 p = (u32 *)&gid->raw[0xc];
1776 roce_raw_write(*p, hr_dev->reg_base + ROCEE_PORT_GID_H_0_REG +
1777 (HNS_ROCE_V1_GID_NUM * gid_idx));
1778
1779 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
1780
1781 return 0;
1782 }
1783
hns_roce_v1_set_mac(struct hns_roce_dev * hr_dev,u8 phy_port,u8 * addr)1784 static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port,
1785 u8 *addr)
1786 {
1787 u32 reg_smac_l;
1788 u16 reg_smac_h;
1789 __le32 tmp;
1790 u16 *p_h;
1791 u32 *p;
1792 u32 val;
1793
1794 /*
1795 * When mac changed, loopback may fail
1796 * because of smac not equal to dmac.
1797 * We Need to release and create reserved qp again.
1798 */
1799 if (hr_dev->hw->dereg_mr) {
1800 int ret;
1801
1802 ret = hns_roce_v1_recreate_lp_qp(hr_dev);
1803 if (ret && ret != -ETIMEDOUT)
1804 return ret;
1805 }
1806
1807 p = (u32 *)(&addr[0]);
1808 reg_smac_l = *p;
1809 roce_raw_write(reg_smac_l, hr_dev->reg_base + ROCEE_SMAC_L_0_REG +
1810 PHY_PORT_OFFSET * phy_port);
1811
1812 val = roce_read(hr_dev,
1813 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1814 tmp = cpu_to_le32(val);
1815 p_h = (u16 *)(&addr[4]);
1816 reg_smac_h = *p_h;
1817 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M,
1818 ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h);
1819 val = le32_to_cpu(tmp);
1820 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1821 val);
1822
1823 return 0;
1824 }
1825
hns_roce_v1_set_mtu(struct hns_roce_dev * hr_dev,u8 phy_port,enum ib_mtu mtu)1826 static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port,
1827 enum ib_mtu mtu)
1828 {
1829 __le32 tmp;
1830 u32 val;
1831
1832 val = roce_read(hr_dev,
1833 ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET);
1834 tmp = cpu_to_le32(val);
1835 roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M,
1836 ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu);
1837 val = le32_to_cpu(tmp);
1838 roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET,
1839 val);
1840 }
1841
hns_roce_v1_write_mtpt(struct hns_roce_dev * hr_dev,void * mb_buf,struct hns_roce_mr * mr,unsigned long mtpt_idx)1842 static int hns_roce_v1_write_mtpt(struct hns_roce_dev *hr_dev, void *mb_buf,
1843 struct hns_roce_mr *mr,
1844 unsigned long mtpt_idx)
1845 {
1846 u64 pages[HNS_ROCE_MAX_INNER_MTPT_NUM] = { 0 };
1847 struct ib_device *ibdev = &hr_dev->ib_dev;
1848 struct hns_roce_v1_mpt_entry *mpt_entry;
1849 dma_addr_t pbl_ba;
1850 int count;
1851 int i;
1852
1853 /* MPT filled into mailbox buf */
1854 mpt_entry = (struct hns_roce_v1_mpt_entry *)mb_buf;
1855 memset(mpt_entry, 0, sizeof(*mpt_entry));
1856
1857 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_STATE_M,
1858 MPT_BYTE_4_KEY_STATE_S, KEY_VALID);
1859 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_KEY_M,
1860 MPT_BYTE_4_KEY_S, mr->key);
1861 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_PAGE_SIZE_M,
1862 MPT_BYTE_4_PAGE_SIZE_S, MR_SIZE_4K);
1863 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_TYPE_S, 0);
1864 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_MW_BIND_ENABLE_S,
1865 (mr->access & IB_ACCESS_MW_BIND ? 1 : 0));
1866 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_OWN_S, 0);
1867 roce_set_field(mpt_entry->mpt_byte_4, MPT_BYTE_4_MEMORY_LOCATION_TYPE_M,
1868 MPT_BYTE_4_MEMORY_LOCATION_TYPE_S, mr->type);
1869 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_ATOMIC_S, 0);
1870 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_LOCAL_WRITE_S,
1871 (mr->access & IB_ACCESS_LOCAL_WRITE ? 1 : 0));
1872 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_WRITE_S,
1873 (mr->access & IB_ACCESS_REMOTE_WRITE ? 1 : 0));
1874 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_READ_S,
1875 (mr->access & IB_ACCESS_REMOTE_READ ? 1 : 0));
1876 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_REMOTE_INVAL_ENABLE_S,
1877 0);
1878 roce_set_bit(mpt_entry->mpt_byte_4, MPT_BYTE_4_ADDRESS_TYPE_S, 0);
1879
1880 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1881 MPT_BYTE_12_PBL_ADDR_H_S, 0);
1882 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M,
1883 MPT_BYTE_12_MW_BIND_COUNTER_S, 0);
1884
1885 mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova);
1886 mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32));
1887 mpt_entry->length = cpu_to_le32((u32)mr->size);
1888
1889 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M,
1890 MPT_BYTE_28_PD_S, mr->pd);
1891 roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_L_KEY_IDX_L_M,
1892 MPT_BYTE_28_L_KEY_IDX_L_S, mtpt_idx);
1893 roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_L_KEY_IDX_H_M,
1894 MPT_BYTE_64_L_KEY_IDX_H_S, mtpt_idx >> MTPT_IDX_SHIFT);
1895
1896 /* DMA memory register */
1897 if (mr->type == MR_TYPE_DMA)
1898 return 0;
1899
1900 count = hns_roce_mtr_find(hr_dev, &mr->pbl_mtr, 0, pages,
1901 ARRAY_SIZE(pages), &pbl_ba);
1902 if (count < 1) {
1903 ibdev_err(ibdev, "failed to find PBL mtr, count = %d.", count);
1904 return -ENOBUFS;
1905 }
1906
1907 /* Register user mr */
1908 for (i = 0; i < count; i++) {
1909 switch (i) {
1910 case 0:
1911 mpt_entry->pa0_l = cpu_to_le32((u32)(pages[i]));
1912 roce_set_field(mpt_entry->mpt_byte_36,
1913 MPT_BYTE_36_PA0_H_M,
1914 MPT_BYTE_36_PA0_H_S,
1915 (u32)(pages[i] >> PAGES_SHIFT_32));
1916 break;
1917 case 1:
1918 roce_set_field(mpt_entry->mpt_byte_36,
1919 MPT_BYTE_36_PA1_L_M,
1920 MPT_BYTE_36_PA1_L_S, (u32)(pages[i]));
1921 roce_set_field(mpt_entry->mpt_byte_40,
1922 MPT_BYTE_40_PA1_H_M,
1923 MPT_BYTE_40_PA1_H_S,
1924 (u32)(pages[i] >> PAGES_SHIFT_24));
1925 break;
1926 case 2:
1927 roce_set_field(mpt_entry->mpt_byte_40,
1928 MPT_BYTE_40_PA2_L_M,
1929 MPT_BYTE_40_PA2_L_S, (u32)(pages[i]));
1930 roce_set_field(mpt_entry->mpt_byte_44,
1931 MPT_BYTE_44_PA2_H_M,
1932 MPT_BYTE_44_PA2_H_S,
1933 (u32)(pages[i] >> PAGES_SHIFT_16));
1934 break;
1935 case 3:
1936 roce_set_field(mpt_entry->mpt_byte_44,
1937 MPT_BYTE_44_PA3_L_M,
1938 MPT_BYTE_44_PA3_L_S, (u32)(pages[i]));
1939 roce_set_field(mpt_entry->mpt_byte_48,
1940 MPT_BYTE_48_PA3_H_M,
1941 MPT_BYTE_48_PA3_H_S,
1942 (u32)(pages[i] >> PAGES_SHIFT_8));
1943 break;
1944 case 4:
1945 mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i]));
1946 roce_set_field(mpt_entry->mpt_byte_56,
1947 MPT_BYTE_56_PA4_H_M,
1948 MPT_BYTE_56_PA4_H_S,
1949 (u32)(pages[i] >> PAGES_SHIFT_32));
1950 break;
1951 case 5:
1952 roce_set_field(mpt_entry->mpt_byte_56,
1953 MPT_BYTE_56_PA5_L_M,
1954 MPT_BYTE_56_PA5_L_S, (u32)(pages[i]));
1955 roce_set_field(mpt_entry->mpt_byte_60,
1956 MPT_BYTE_60_PA5_H_M,
1957 MPT_BYTE_60_PA5_H_S,
1958 (u32)(pages[i] >> PAGES_SHIFT_24));
1959 break;
1960 case 6:
1961 roce_set_field(mpt_entry->mpt_byte_60,
1962 MPT_BYTE_60_PA6_L_M,
1963 MPT_BYTE_60_PA6_L_S, (u32)(pages[i]));
1964 roce_set_field(mpt_entry->mpt_byte_64,
1965 MPT_BYTE_64_PA6_H_M,
1966 MPT_BYTE_64_PA6_H_S,
1967 (u32)(pages[i] >> PAGES_SHIFT_16));
1968 break;
1969 default:
1970 break;
1971 }
1972 }
1973
1974 mpt_entry->pbl_addr_l = cpu_to_le32(pbl_ba);
1975 roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M,
1976 MPT_BYTE_12_PBL_ADDR_H_S, upper_32_bits(pbl_ba));
1977
1978 return 0;
1979 }
1980
get_cqe(struct hns_roce_cq * hr_cq,int n)1981 static void *get_cqe(struct hns_roce_cq *hr_cq, int n)
1982 {
1983 return hns_roce_buf_offset(hr_cq->mtr.kmem, n * HNS_ROCE_V1_CQE_SIZE);
1984 }
1985
get_sw_cqe(struct hns_roce_cq * hr_cq,int n)1986 static void *get_sw_cqe(struct hns_roce_cq *hr_cq, int n)
1987 {
1988 struct hns_roce_cqe *hr_cqe = get_cqe(hr_cq, n & hr_cq->ib_cq.cqe);
1989
1990 /* Get cqe when Owner bit is Conversely with the MSB of cons_idx */
1991 return (roce_get_bit(hr_cqe->cqe_byte_4, CQE_BYTE_4_OWNER_S) ^
1992 !!(n & hr_cq->cq_depth)) ? hr_cqe : NULL;
1993 }
1994
next_cqe_sw(struct hns_roce_cq * hr_cq)1995 static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq)
1996 {
1997 return get_sw_cqe(hr_cq, hr_cq->cons_index);
1998 }
1999
hns_roce_v1_cq_set_ci(struct hns_roce_cq * hr_cq,u32 cons_index)2000 static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index)
2001 {
2002 __le32 doorbell[2];
2003
2004 doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1));
2005 doorbell[1] = 0;
2006 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2007 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2008 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2009 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2010 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 0);
2011 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2012 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S, hr_cq->cqn);
2013
2014 hns_roce_write64_k(doorbell, hr_cq->db_reg);
2015 }
2016
__hns_roce_v1_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2017 static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2018 struct hns_roce_srq *srq)
2019 {
2020 struct hns_roce_cqe *cqe, *dest;
2021 u32 prod_index;
2022 int nfreed = 0;
2023 u8 owner_bit;
2024
2025 for (prod_index = hr_cq->cons_index; get_sw_cqe(hr_cq, prod_index);
2026 ++prod_index) {
2027 if (prod_index == hr_cq->cons_index + hr_cq->ib_cq.cqe)
2028 break;
2029 }
2030
2031 /*
2032 * Now backwards through the CQ, removing CQ entries
2033 * that match our QP by overwriting them with next entries.
2034 */
2035 while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
2036 cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
2037 if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2038 CQE_BYTE_16_LOCAL_QPN_S) &
2039 HNS_ROCE_CQE_QPN_MASK) == qpn) {
2040 /* In v1 engine, not support SRQ */
2041 ++nfreed;
2042 } else if (nfreed) {
2043 dest = get_cqe(hr_cq, (prod_index + nfreed) &
2044 hr_cq->ib_cq.cqe);
2045 owner_bit = roce_get_bit(dest->cqe_byte_4,
2046 CQE_BYTE_4_OWNER_S);
2047 memcpy(dest, cqe, sizeof(*cqe));
2048 roce_set_bit(dest->cqe_byte_4, CQE_BYTE_4_OWNER_S,
2049 owner_bit);
2050 }
2051 }
2052
2053 if (nfreed) {
2054 hr_cq->cons_index += nfreed;
2055 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2056 }
2057 }
2058
hns_roce_v1_cq_clean(struct hns_roce_cq * hr_cq,u32 qpn,struct hns_roce_srq * srq)2059 static void hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
2060 struct hns_roce_srq *srq)
2061 {
2062 spin_lock_irq(&hr_cq->lock);
2063 __hns_roce_v1_cq_clean(hr_cq, qpn, srq);
2064 spin_unlock_irq(&hr_cq->lock);
2065 }
2066
hns_roce_v1_write_cqc(struct hns_roce_dev * hr_dev,struct hns_roce_cq * hr_cq,void * mb_buf,u64 * mtts,dma_addr_t dma_handle)2067 static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
2068 struct hns_roce_cq *hr_cq, void *mb_buf,
2069 u64 *mtts, dma_addr_t dma_handle)
2070 {
2071 struct hns_roce_v1_priv *priv = hr_dev->priv;
2072 struct hns_roce_buf_list *tptr_buf = &priv->tptr_table.tptr_buf;
2073 struct hns_roce_cq_context *cq_context = mb_buf;
2074 dma_addr_t tptr_dma_addr;
2075 int offset;
2076
2077 memset(cq_context, 0, sizeof(*cq_context));
2078
2079 /* Get the tptr for this CQ. */
2080 offset = hr_cq->cqn * HNS_ROCE_V1_TPTR_ENTRY_SIZE;
2081 tptr_dma_addr = tptr_buf->map + offset;
2082 hr_cq->tptr_addr = (u16 *)(tptr_buf->buf + offset);
2083
2084 /* Register cq_context members */
2085 roce_set_field(cq_context->cqc_byte_4,
2086 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_M,
2087 CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID);
2088 roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M,
2089 CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn);
2090
2091 cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle);
2092
2093 roce_set_field(cq_context->cqc_byte_12,
2094 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M,
2095 CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_S,
2096 ((u64)dma_handle >> 32));
2097 roce_set_field(cq_context->cqc_byte_12,
2098 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_M,
2099 CQ_CONTEXT_CQC_BYTE_12_CQ_CQE_SHIFT_S,
2100 ilog2(hr_cq->cq_depth));
2101 roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M,
2102 CQ_CONTEXT_CQC_BYTE_12_CEQN_S, hr_cq->vector);
2103
2104 cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0]));
2105
2106 roce_set_field(cq_context->cqc_byte_20,
2107 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M,
2108 CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32);
2109 /* Dedicated hardware, directly set 0 */
2110 roce_set_field(cq_context->cqc_byte_20,
2111 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M,
2112 CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_S, 0);
2113 /**
2114 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
2115 * using 4K page, and shift more 32 because of
2116 * calculating the high 32 bit value evaluated to hardware.
2117 */
2118 roce_set_field(cq_context->cqc_byte_20,
2119 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M,
2120 CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S,
2121 tptr_dma_addr >> 44);
2122
2123 cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12));
2124
2125 roce_set_field(cq_context->cqc_byte_32,
2126 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M,
2127 CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_S, 0);
2128 roce_set_bit(cq_context->cqc_byte_32,
2129 CQ_CONTEXT_CQC_BYTE_32_SE_FLAG_S, 0);
2130 roce_set_bit(cq_context->cqc_byte_32,
2131 CQ_CONTEXT_CQC_BYTE_32_CE_FLAG_S, 0);
2132 roce_set_bit(cq_context->cqc_byte_32,
2133 CQ_CONTEXT_CQC_BYTE_32_NOTIFICATION_FLAG_S, 0);
2134 roce_set_bit(cq_context->cqc_byte_32,
2135 CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
2136 0);
2137 /* The initial value of cq's ci is 0 */
2138 roce_set_field(cq_context->cqc_byte_32,
2139 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
2140 CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
2141 }
2142
hns_roce_v1_req_notify_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)2143 static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq,
2144 enum ib_cq_notify_flags flags)
2145 {
2146 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2147 u32 notification_flag;
2148 __le32 doorbell[2] = {};
2149
2150 notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
2151 IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
2152 /*
2153 * flags = 0; Notification Flag = 1, next
2154 * flags = 1; Notification Flag = 0, solocited
2155 */
2156 doorbell[0] =
2157 cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1));
2158 roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
2159 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
2160 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3);
2161 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M,
2162 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S, 1);
2163 roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M,
2164 ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S,
2165 hr_cq->cqn | notification_flag);
2166
2167 hns_roce_write64_k(doorbell, hr_cq->db_reg);
2168
2169 return 0;
2170 }
2171
hns_roce_v1_poll_one(struct hns_roce_cq * hr_cq,struct hns_roce_qp ** cur_qp,struct ib_wc * wc)2172 static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
2173 struct hns_roce_qp **cur_qp, struct ib_wc *wc)
2174 {
2175 int qpn;
2176 int is_send;
2177 u16 wqe_ctr;
2178 u32 status;
2179 u32 opcode;
2180 struct hns_roce_cqe *cqe;
2181 struct hns_roce_qp *hr_qp;
2182 struct hns_roce_wq *wq;
2183 struct hns_roce_wqe_ctrl_seg *sq_wqe;
2184 struct hns_roce_dev *hr_dev = to_hr_dev(hr_cq->ib_cq.device);
2185 struct device *dev = &hr_dev->pdev->dev;
2186
2187 /* Find cqe according consumer index */
2188 cqe = next_cqe_sw(hr_cq);
2189 if (!cqe)
2190 return -EAGAIN;
2191
2192 ++hr_cq->cons_index;
2193 /* Memory barrier */
2194 rmb();
2195 /* 0->SQ, 1->RQ */
2196 is_send = !(roce_get_bit(cqe->cqe_byte_4, CQE_BYTE_4_SQ_RQ_FLAG_S));
2197
2198 /* Local_qpn in UD cqe is always 1, so it needs to compute new qpn */
2199 if (roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2200 CQE_BYTE_16_LOCAL_QPN_S) <= 1) {
2201 qpn = roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_PORT_NUM_M,
2202 CQE_BYTE_20_PORT_NUM_S) +
2203 roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2204 CQE_BYTE_16_LOCAL_QPN_S) *
2205 HNS_ROCE_MAX_PORTS;
2206 } else {
2207 qpn = roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
2208 CQE_BYTE_16_LOCAL_QPN_S);
2209 }
2210
2211 if (!*cur_qp || (qpn & HNS_ROCE_CQE_QPN_MASK) != (*cur_qp)->qpn) {
2212 hr_qp = __hns_roce_qp_lookup(hr_dev, qpn);
2213 if (unlikely(!hr_qp)) {
2214 dev_err(dev, "CQ %06lx with entry for unknown QPN %06x\n",
2215 hr_cq->cqn, (qpn & HNS_ROCE_CQE_QPN_MASK));
2216 return -EINVAL;
2217 }
2218
2219 *cur_qp = hr_qp;
2220 }
2221
2222 wc->qp = &(*cur_qp)->ibqp;
2223 wc->vendor_err = 0;
2224
2225 status = roce_get_field(cqe->cqe_byte_4,
2226 CQE_BYTE_4_STATUS_OF_THE_OPERATION_M,
2227 CQE_BYTE_4_STATUS_OF_THE_OPERATION_S) &
2228 HNS_ROCE_CQE_STATUS_MASK;
2229 switch (status) {
2230 case HNS_ROCE_CQE_SUCCESS:
2231 wc->status = IB_WC_SUCCESS;
2232 break;
2233 case HNS_ROCE_CQE_SYNDROME_LOCAL_LENGTH_ERR:
2234 wc->status = IB_WC_LOC_LEN_ERR;
2235 break;
2236 case HNS_ROCE_CQE_SYNDROME_LOCAL_QP_OP_ERR:
2237 wc->status = IB_WC_LOC_QP_OP_ERR;
2238 break;
2239 case HNS_ROCE_CQE_SYNDROME_LOCAL_PROT_ERR:
2240 wc->status = IB_WC_LOC_PROT_ERR;
2241 break;
2242 case HNS_ROCE_CQE_SYNDROME_WR_FLUSH_ERR:
2243 wc->status = IB_WC_WR_FLUSH_ERR;
2244 break;
2245 case HNS_ROCE_CQE_SYNDROME_MEM_MANAGE_OPERATE_ERR:
2246 wc->status = IB_WC_MW_BIND_ERR;
2247 break;
2248 case HNS_ROCE_CQE_SYNDROME_BAD_RESP_ERR:
2249 wc->status = IB_WC_BAD_RESP_ERR;
2250 break;
2251 case HNS_ROCE_CQE_SYNDROME_LOCAL_ACCESS_ERR:
2252 wc->status = IB_WC_LOC_ACCESS_ERR;
2253 break;
2254 case HNS_ROCE_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
2255 wc->status = IB_WC_REM_INV_REQ_ERR;
2256 break;
2257 case HNS_ROCE_CQE_SYNDROME_REMOTE_ACCESS_ERR:
2258 wc->status = IB_WC_REM_ACCESS_ERR;
2259 break;
2260 case HNS_ROCE_CQE_SYNDROME_REMOTE_OP_ERR:
2261 wc->status = IB_WC_REM_OP_ERR;
2262 break;
2263 case HNS_ROCE_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
2264 wc->status = IB_WC_RETRY_EXC_ERR;
2265 break;
2266 case HNS_ROCE_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
2267 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
2268 break;
2269 default:
2270 wc->status = IB_WC_GENERAL_ERR;
2271 break;
2272 }
2273
2274 /* CQE status error, directly return */
2275 if (wc->status != IB_WC_SUCCESS)
2276 return 0;
2277
2278 if (is_send) {
2279 /* SQ conrespond to CQE */
2280 sq_wqe = hns_roce_get_send_wqe(*cur_qp,
2281 roce_get_field(cqe->cqe_byte_4,
2282 CQE_BYTE_4_WQE_INDEX_M,
2283 CQE_BYTE_4_WQE_INDEX_S) &
2284 ((*cur_qp)->sq.wqe_cnt-1));
2285 switch (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_OPCODE_MASK) {
2286 case HNS_ROCE_WQE_OPCODE_SEND:
2287 wc->opcode = IB_WC_SEND;
2288 break;
2289 case HNS_ROCE_WQE_OPCODE_RDMA_READ:
2290 wc->opcode = IB_WC_RDMA_READ;
2291 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2292 break;
2293 case HNS_ROCE_WQE_OPCODE_RDMA_WRITE:
2294 wc->opcode = IB_WC_RDMA_WRITE;
2295 break;
2296 case HNS_ROCE_WQE_OPCODE_LOCAL_INV:
2297 wc->opcode = IB_WC_LOCAL_INV;
2298 break;
2299 case HNS_ROCE_WQE_OPCODE_UD_SEND:
2300 wc->opcode = IB_WC_SEND;
2301 break;
2302 default:
2303 wc->status = IB_WC_GENERAL_ERR;
2304 break;
2305 }
2306 wc->wc_flags = (le32_to_cpu(sq_wqe->flag) & HNS_ROCE_WQE_IMM ?
2307 IB_WC_WITH_IMM : 0);
2308
2309 wq = &(*cur_qp)->sq;
2310 if ((*cur_qp)->sq_signal_bits) {
2311 /*
2312 * If sg_signal_bit is 1,
2313 * firstly tail pointer updated to wqe
2314 * which current cqe correspond to
2315 */
2316 wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
2317 CQE_BYTE_4_WQE_INDEX_M,
2318 CQE_BYTE_4_WQE_INDEX_S);
2319 wq->tail += (wqe_ctr - (u16)wq->tail) &
2320 (wq->wqe_cnt - 1);
2321 }
2322 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2323 ++wq->tail;
2324 } else {
2325 /* RQ conrespond to CQE */
2326 wc->byte_len = le32_to_cpu(cqe->byte_cnt);
2327 opcode = roce_get_field(cqe->cqe_byte_4,
2328 CQE_BYTE_4_OPERATION_TYPE_M,
2329 CQE_BYTE_4_OPERATION_TYPE_S) &
2330 HNS_ROCE_CQE_OPCODE_MASK;
2331 switch (opcode) {
2332 case HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE:
2333 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2334 wc->wc_flags = IB_WC_WITH_IMM;
2335 wc->ex.imm_data =
2336 cpu_to_be32(le32_to_cpu(cqe->immediate_data));
2337 break;
2338 case HNS_ROCE_OPCODE_SEND_DATA_RECEIVE:
2339 if (roce_get_bit(cqe->cqe_byte_4,
2340 CQE_BYTE_4_IMM_INDICATOR_S)) {
2341 wc->opcode = IB_WC_RECV;
2342 wc->wc_flags = IB_WC_WITH_IMM;
2343 wc->ex.imm_data = cpu_to_be32(
2344 le32_to_cpu(cqe->immediate_data));
2345 } else {
2346 wc->opcode = IB_WC_RECV;
2347 wc->wc_flags = 0;
2348 }
2349 break;
2350 default:
2351 wc->status = IB_WC_GENERAL_ERR;
2352 break;
2353 }
2354
2355 /* Update tail pointer, record wr_id */
2356 wq = &(*cur_qp)->rq;
2357 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
2358 ++wq->tail;
2359 wc->sl = (u8)roce_get_field(cqe->cqe_byte_20, CQE_BYTE_20_SL_M,
2360 CQE_BYTE_20_SL_S);
2361 wc->src_qp = (u8)roce_get_field(cqe->cqe_byte_20,
2362 CQE_BYTE_20_REMOTE_QPN_M,
2363 CQE_BYTE_20_REMOTE_QPN_S);
2364 wc->wc_flags |= (roce_get_bit(cqe->cqe_byte_20,
2365 CQE_BYTE_20_GRH_PRESENT_S) ?
2366 IB_WC_GRH : 0);
2367 wc->pkey_index = (u16)roce_get_field(cqe->cqe_byte_28,
2368 CQE_BYTE_28_P_KEY_IDX_M,
2369 CQE_BYTE_28_P_KEY_IDX_S);
2370 }
2371
2372 return 0;
2373 }
2374
hns_roce_v1_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)2375 int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
2376 {
2377 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
2378 struct hns_roce_qp *cur_qp = NULL;
2379 unsigned long flags;
2380 int npolled;
2381 int ret;
2382
2383 spin_lock_irqsave(&hr_cq->lock, flags);
2384
2385 for (npolled = 0; npolled < num_entries; ++npolled) {
2386 ret = hns_roce_v1_poll_one(hr_cq, &cur_qp, wc + npolled);
2387 if (ret)
2388 break;
2389 }
2390
2391 if (npolled) {
2392 *hr_cq->tptr_addr = hr_cq->cons_index &
2393 ((hr_cq->cq_depth << 1) - 1);
2394
2395 hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
2396 }
2397
2398 spin_unlock_irqrestore(&hr_cq->lock, flags);
2399
2400 if (ret == 0 || ret == -EAGAIN)
2401 return npolled;
2402 else
2403 return ret;
2404 }
2405
hns_roce_v1_clear_hem(struct hns_roce_dev * hr_dev,struct hns_roce_hem_table * table,int obj,int step_idx)2406 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
2407 struct hns_roce_hem_table *table, int obj,
2408 int step_idx)
2409 {
2410 struct hns_roce_v1_priv *priv = hr_dev->priv;
2411 struct device *dev = &hr_dev->pdev->dev;
2412 long end = HW_SYNC_TIMEOUT_MSECS;
2413 __le32 bt_cmd_val[2] = {0};
2414 unsigned long flags = 0;
2415 void __iomem *bt_cmd;
2416 u64 bt_ba = 0;
2417
2418 switch (table->type) {
2419 case HEM_TYPE_QPC:
2420 bt_ba = priv->bt_table.qpc_buf.map >> 12;
2421 break;
2422 case HEM_TYPE_MTPT:
2423 bt_ba = priv->bt_table.mtpt_buf.map >> 12;
2424 break;
2425 case HEM_TYPE_CQC:
2426 bt_ba = priv->bt_table.cqc_buf.map >> 12;
2427 break;
2428 case HEM_TYPE_SRQC:
2429 dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
2430 return -EINVAL;
2431 default:
2432 return 0;
2433 }
2434 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M,
2435 ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, table->type);
2436 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
2437 ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
2438 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0);
2439 roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1);
2440
2441 spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags);
2442
2443 bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG;
2444
2445 while (1) {
2446 if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) {
2447 if (!end) {
2448 dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
2449 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
2450 flags);
2451 return -EBUSY;
2452 }
2453 } else {
2454 break;
2455 }
2456 mdelay(HW_SYNC_SLEEP_TIME_INTERVAL);
2457 end -= HW_SYNC_SLEEP_TIME_INTERVAL;
2458 }
2459
2460 bt_cmd_val[0] = cpu_to_le32(bt_ba);
2461 roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M,
2462 ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32);
2463 hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG);
2464
2465 spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
2466
2467 return 0;
2468 }
2469
hns_roce_v1_qp_modify(struct hns_roce_dev * hr_dev,enum hns_roce_qp_state cur_state,enum hns_roce_qp_state new_state,struct hns_roce_qp_context * context,struct hns_roce_qp * hr_qp)2470 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,
2471 enum hns_roce_qp_state cur_state,
2472 enum hns_roce_qp_state new_state,
2473 struct hns_roce_qp_context *context,
2474 struct hns_roce_qp *hr_qp)
2475 {
2476 static const u16
2477 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = {
2478 [HNS_ROCE_QP_STATE_RST] = {
2479 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2480 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2481 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2482 },
2483 [HNS_ROCE_QP_STATE_INIT] = {
2484 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2485 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2486 /* Note: In v1 engine, HW doesn't support RST2INIT.
2487 * We use RST2INIT cmd instead of INIT2INIT.
2488 */
2489 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP,
2490 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP,
2491 },
2492 [HNS_ROCE_QP_STATE_RTR] = {
2493 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2494 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2495 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP,
2496 },
2497 [HNS_ROCE_QP_STATE_RTS] = {
2498 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2499 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2500 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP,
2501 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP,
2502 },
2503 [HNS_ROCE_QP_STATE_SQD] = {
2504 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2505 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2506 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP,
2507 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP,
2508 },
2509 [HNS_ROCE_QP_STATE_ERR] = {
2510 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP,
2511 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP,
2512 }
2513 };
2514
2515 struct hns_roce_cmd_mailbox *mailbox;
2516 struct device *dev = &hr_dev->pdev->dev;
2517 int ret;
2518
2519 if (cur_state >= HNS_ROCE_QP_NUM_STATE ||
2520 new_state >= HNS_ROCE_QP_NUM_STATE ||
2521 !op[cur_state][new_state]) {
2522 dev_err(dev, "[modify_qp]not support state %d to %d\n",
2523 cur_state, new_state);
2524 return -EINVAL;
2525 }
2526
2527 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP)
2528 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2529 HNS_ROCE_CMD_2RST_QP,
2530 HNS_ROCE_CMD_TIMEOUT_MSECS);
2531
2532 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP)
2533 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2,
2534 HNS_ROCE_CMD_2ERR_QP,
2535 HNS_ROCE_CMD_TIMEOUT_MSECS);
2536
2537 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
2538 if (IS_ERR(mailbox))
2539 return PTR_ERR(mailbox);
2540
2541 memcpy(mailbox->buf, context, sizeof(*context));
2542
2543 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0,
2544 op[cur_state][new_state],
2545 HNS_ROCE_CMD_TIMEOUT_MSECS);
2546
2547 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
2548 return ret;
2549 }
2550
find_wqe_mtt(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,u64 * sq_ba,u64 * rq_ba,dma_addr_t * bt_ba)2551 static int find_wqe_mtt(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
2552 u64 *sq_ba, u64 *rq_ba, dma_addr_t *bt_ba)
2553 {
2554 struct ib_device *ibdev = &hr_dev->ib_dev;
2555 int count;
2556
2557 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, 0, sq_ba, 1, bt_ba);
2558 if (count < 1) {
2559 ibdev_err(ibdev, "Failed to find SQ ba\n");
2560 return -ENOBUFS;
2561 }
2562
2563 count = hns_roce_mtr_find(hr_dev, &hr_qp->mtr, hr_qp->rq.offset, rq_ba,
2564 1, NULL);
2565 if (!count) {
2566 ibdev_err(ibdev, "Failed to find RQ ba\n");
2567 return -ENOBUFS;
2568 }
2569
2570 return 0;
2571 }
2572
hns_roce_v1_m_sqp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2573 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2574 int attr_mask, enum ib_qp_state cur_state,
2575 enum ib_qp_state new_state)
2576 {
2577 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2578 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2579 struct hns_roce_sqp_context *context;
2580 dma_addr_t dma_handle = 0;
2581 u32 __iomem *addr;
2582 u64 sq_ba = 0;
2583 u64 rq_ba = 0;
2584 __le32 tmp;
2585 u32 reg_val;
2586
2587 context = kzalloc(sizeof(*context), GFP_KERNEL);
2588 if (!context)
2589 return -ENOMEM;
2590
2591 /* Search QP buf's MTTs */
2592 if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2593 goto out;
2594
2595 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2596 roce_set_field(context->qp1c_bytes_4,
2597 QP1C_BYTES_4_SQ_WQE_SHIFT_M,
2598 QP1C_BYTES_4_SQ_WQE_SHIFT_S,
2599 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2600 roce_set_field(context->qp1c_bytes_4,
2601 QP1C_BYTES_4_RQ_WQE_SHIFT_M,
2602 QP1C_BYTES_4_RQ_WQE_SHIFT_S,
2603 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2604 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M,
2605 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn);
2606
2607 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2608 roce_set_field(context->qp1c_bytes_12,
2609 QP1C_BYTES_12_SQ_RQ_BT_H_M,
2610 QP1C_BYTES_12_SQ_RQ_BT_H_S,
2611 upper_32_bits(dma_handle));
2612
2613 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M,
2614 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head);
2615 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M,
2616 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port);
2617 roce_set_bit(context->qp1c_bytes_16,
2618 QP1C_BYTES_16_SIGNALING_TYPE_S,
2619 hr_qp->sq_signal_bits);
2620 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S,
2621 1);
2622 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S,
2623 1);
2624 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S,
2625 0);
2626
2627 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M,
2628 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head);
2629 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M,
2630 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index);
2631
2632 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
2633
2634 roce_set_field(context->qp1c_bytes_28,
2635 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M,
2636 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S,
2637 upper_32_bits(rq_ba));
2638 roce_set_field(context->qp1c_bytes_28,
2639 QP1C_BYTES_28_RQ_CUR_IDX_M,
2640 QP1C_BYTES_28_RQ_CUR_IDX_S, 0);
2641
2642 roce_set_field(context->qp1c_bytes_32,
2643 QP1C_BYTES_32_RX_CQ_NUM_M,
2644 QP1C_BYTES_32_RX_CQ_NUM_S,
2645 to_hr_cq(ibqp->recv_cq)->cqn);
2646 roce_set_field(context->qp1c_bytes_32,
2647 QP1C_BYTES_32_TX_CQ_NUM_M,
2648 QP1C_BYTES_32_TX_CQ_NUM_S,
2649 to_hr_cq(ibqp->send_cq)->cqn);
2650
2651 context->cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
2652
2653 roce_set_field(context->qp1c_bytes_40,
2654 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M,
2655 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S,
2656 upper_32_bits(sq_ba));
2657 roce_set_field(context->qp1c_bytes_40,
2658 QP1C_BYTES_40_SQ_CUR_IDX_M,
2659 QP1C_BYTES_40_SQ_CUR_IDX_S, 0);
2660
2661 /* Copy context to QP1C register */
2662 addr = (u32 __iomem *)(hr_dev->reg_base +
2663 ROCEE_QP1C_CFG0_0_REG +
2664 hr_qp->phy_port * sizeof(*context));
2665
2666 writel(le32_to_cpu(context->qp1c_bytes_4), addr);
2667 writel(le32_to_cpu(context->sq_rq_bt_l), addr + 1);
2668 writel(le32_to_cpu(context->qp1c_bytes_12), addr + 2);
2669 writel(le32_to_cpu(context->qp1c_bytes_16), addr + 3);
2670 writel(le32_to_cpu(context->qp1c_bytes_20), addr + 4);
2671 writel(le32_to_cpu(context->cur_rq_wqe_ba_l), addr + 5);
2672 writel(le32_to_cpu(context->qp1c_bytes_28), addr + 6);
2673 writel(le32_to_cpu(context->qp1c_bytes_32), addr + 7);
2674 writel(le32_to_cpu(context->cur_sq_wqe_ba_l), addr + 8);
2675 writel(le32_to_cpu(context->qp1c_bytes_40), addr + 9);
2676 }
2677
2678 /* Modify QP1C status */
2679 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2680 hr_qp->phy_port * sizeof(*context));
2681 tmp = cpu_to_le32(reg_val);
2682 roce_set_field(tmp, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M,
2683 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state);
2684 reg_val = le32_to_cpu(tmp);
2685 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG +
2686 hr_qp->phy_port * sizeof(*context), reg_val);
2687
2688 hr_qp->state = new_state;
2689 if (new_state == IB_QPS_RESET) {
2690 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
2691 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
2692 if (ibqp->send_cq != ibqp->recv_cq)
2693 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
2694 hr_qp->qpn, NULL);
2695
2696 hr_qp->rq.head = 0;
2697 hr_qp->rq.tail = 0;
2698 hr_qp->sq.head = 0;
2699 hr_qp->sq.tail = 0;
2700 }
2701
2702 kfree(context);
2703 return 0;
2704
2705 out:
2706 kfree(context);
2707 return -EINVAL;
2708 }
2709
check_qp_state(enum ib_qp_state cur_state,enum ib_qp_state new_state)2710 static bool check_qp_state(enum ib_qp_state cur_state,
2711 enum ib_qp_state new_state)
2712 {
2713 static const bool sm[][IB_QPS_ERR + 1] = {
2714 [IB_QPS_RESET] = { [IB_QPS_RESET] = true,
2715 [IB_QPS_INIT] = true },
2716 [IB_QPS_INIT] = { [IB_QPS_RESET] = true,
2717 [IB_QPS_INIT] = true,
2718 [IB_QPS_RTR] = true,
2719 [IB_QPS_ERR] = true },
2720 [IB_QPS_RTR] = { [IB_QPS_RESET] = true,
2721 [IB_QPS_RTS] = true,
2722 [IB_QPS_ERR] = true },
2723 [IB_QPS_RTS] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true },
2724 [IB_QPS_SQD] = {},
2725 [IB_QPS_SQE] = {},
2726 [IB_QPS_ERR] = { [IB_QPS_RESET] = true, [IB_QPS_ERR] = true }
2727 };
2728
2729 return sm[cur_state][new_state];
2730 }
2731
hns_roce_v1_m_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2732 static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
2733 int attr_mask, enum ib_qp_state cur_state,
2734 enum ib_qp_state new_state)
2735 {
2736 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
2737 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
2738 struct device *dev = &hr_dev->pdev->dev;
2739 struct hns_roce_qp_context *context;
2740 const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
2741 dma_addr_t dma_handle_2 = 0;
2742 dma_addr_t dma_handle = 0;
2743 __le32 doorbell[2] = {0};
2744 u64 *mtts_2 = NULL;
2745 int ret = -EINVAL;
2746 u64 sq_ba = 0;
2747 u64 rq_ba = 0;
2748 u32 port;
2749 u32 port_num;
2750 u8 *dmac;
2751 u8 *smac;
2752
2753 if (!check_qp_state(cur_state, new_state)) {
2754 ibdev_err(ibqp->device,
2755 "not support QP(%u) status from %d to %d\n",
2756 ibqp->qp_num, cur_state, new_state);
2757 return -EINVAL;
2758 }
2759
2760 context = kzalloc(sizeof(*context), GFP_KERNEL);
2761 if (!context)
2762 return -ENOMEM;
2763
2764 /* Search qp buf's mtts */
2765 if (find_wqe_mtt(hr_dev, hr_qp, &sq_ba, &rq_ba, &dma_handle))
2766 goto out;
2767
2768 /* Search IRRL's mtts */
2769 mtts_2 = hns_roce_table_find(hr_dev, &hr_dev->qp_table.irrl_table,
2770 hr_qp->qpn, &dma_handle_2);
2771 if (mtts_2 == NULL) {
2772 dev_err(dev, "qp irrl_table find failed\n");
2773 goto out;
2774 }
2775
2776 /*
2777 * Reset to init
2778 * Mandatory param:
2779 * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
2780 * Optional param: NA
2781 */
2782 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2783 roce_set_field(context->qpc_bytes_4,
2784 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2785 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2786 to_hr_qp_type(hr_qp->ibqp.qp_type));
2787
2788 roce_set_bit(context->qpc_bytes_4,
2789 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2790 roce_set_bit(context->qpc_bytes_4,
2791 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2792 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_READ));
2793 roce_set_bit(context->qpc_bytes_4,
2794 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2795 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
2796 );
2797 roce_set_bit(context->qpc_bytes_4,
2798 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S,
2799 !!(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC)
2800 );
2801 roce_set_bit(context->qpc_bytes_4,
2802 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2803 roce_set_field(context->qpc_bytes_4,
2804 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2805 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2806 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2807 roce_set_field(context->qpc_bytes_4,
2808 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2809 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2810 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2811 roce_set_field(context->qpc_bytes_4,
2812 QP_CONTEXT_QPC_BYTES_4_PD_M,
2813 QP_CONTEXT_QPC_BYTES_4_PD_S,
2814 to_hr_pd(ibqp->pd)->pdn);
2815 hr_qp->access_flags = attr->qp_access_flags;
2816 roce_set_field(context->qpc_bytes_8,
2817 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2818 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2819 to_hr_cq(ibqp->send_cq)->cqn);
2820 roce_set_field(context->qpc_bytes_8,
2821 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2822 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2823 to_hr_cq(ibqp->recv_cq)->cqn);
2824
2825 if (ibqp->srq)
2826 roce_set_field(context->qpc_bytes_12,
2827 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2828 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2829 to_hr_srq(ibqp->srq)->srqn);
2830
2831 roce_set_field(context->qpc_bytes_12,
2832 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2833 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2834 attr->pkey_index);
2835 hr_qp->pkey_index = attr->pkey_index;
2836 roce_set_field(context->qpc_bytes_16,
2837 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2838 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2839 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
2840 roce_set_field(context->qpc_bytes_4,
2841 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
2842 QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_S,
2843 to_hr_qp_type(hr_qp->ibqp.qp_type));
2844 roce_set_bit(context->qpc_bytes_4,
2845 QP_CONTEXT_QPC_BYTE_4_ENABLE_FPMR_S, 0);
2846 if (attr_mask & IB_QP_ACCESS_FLAGS) {
2847 roce_set_bit(context->qpc_bytes_4,
2848 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2849 !!(attr->qp_access_flags &
2850 IB_ACCESS_REMOTE_READ));
2851 roce_set_bit(context->qpc_bytes_4,
2852 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2853 !!(attr->qp_access_flags &
2854 IB_ACCESS_REMOTE_WRITE));
2855 } else {
2856 roce_set_bit(context->qpc_bytes_4,
2857 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S,
2858 !!(hr_qp->access_flags &
2859 IB_ACCESS_REMOTE_READ));
2860 roce_set_bit(context->qpc_bytes_4,
2861 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S,
2862 !!(hr_qp->access_flags &
2863 IB_ACCESS_REMOTE_WRITE));
2864 }
2865
2866 roce_set_bit(context->qpc_bytes_4,
2867 QP_CONTEXT_QPC_BYTE_4_RDMAR_USE_S, 1);
2868 roce_set_field(context->qpc_bytes_4,
2869 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_M,
2870 QP_CONTEXT_QPC_BYTES_4_SQ_WQE_SHIFT_S,
2871 ilog2((unsigned int)hr_qp->sq.wqe_cnt));
2872 roce_set_field(context->qpc_bytes_4,
2873 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_M,
2874 QP_CONTEXT_QPC_BYTES_4_RQ_WQE_SHIFT_S,
2875 ilog2((unsigned int)hr_qp->rq.wqe_cnt));
2876 roce_set_field(context->qpc_bytes_4,
2877 QP_CONTEXT_QPC_BYTES_4_PD_M,
2878 QP_CONTEXT_QPC_BYTES_4_PD_S,
2879 to_hr_pd(ibqp->pd)->pdn);
2880
2881 roce_set_field(context->qpc_bytes_8,
2882 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_M,
2883 QP_CONTEXT_QPC_BYTES_8_TX_COMPLETION_S,
2884 to_hr_cq(ibqp->send_cq)->cqn);
2885 roce_set_field(context->qpc_bytes_8,
2886 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_M,
2887 QP_CONTEXT_QPC_BYTES_8_RX_COMPLETION_S,
2888 to_hr_cq(ibqp->recv_cq)->cqn);
2889
2890 if (ibqp->srq)
2891 roce_set_field(context->qpc_bytes_12,
2892 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_M,
2893 QP_CONTEXT_QPC_BYTES_12_SRQ_NUMBER_S,
2894 to_hr_srq(ibqp->srq)->srqn);
2895 if (attr_mask & IB_QP_PKEY_INDEX)
2896 roce_set_field(context->qpc_bytes_12,
2897 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2898 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2899 attr->pkey_index);
2900 else
2901 roce_set_field(context->qpc_bytes_12,
2902 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
2903 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S,
2904 hr_qp->pkey_index);
2905
2906 roce_set_field(context->qpc_bytes_16,
2907 QP_CONTEXT_QPC_BYTES_16_QP_NUM_M,
2908 QP_CONTEXT_QPC_BYTES_16_QP_NUM_S, hr_qp->qpn);
2909 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2910 if ((attr_mask & IB_QP_ALT_PATH) ||
2911 (attr_mask & IB_QP_ACCESS_FLAGS) ||
2912 (attr_mask & IB_QP_PKEY_INDEX) ||
2913 (attr_mask & IB_QP_QKEY)) {
2914 dev_err(dev, "INIT2RTR attr_mask error\n");
2915 goto out;
2916 }
2917
2918 dmac = (u8 *)attr->ah_attr.roce.dmac;
2919
2920 context->sq_rq_bt_l = cpu_to_le32(dma_handle);
2921 roce_set_field(context->qpc_bytes_24,
2922 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_M,
2923 QP_CONTEXT_QPC_BYTES_24_SQ_RQ_BT_H_S,
2924 upper_32_bits(dma_handle));
2925 roce_set_bit(context->qpc_bytes_24,
2926 QP_CONTEXT_QPC_BYTE_24_REMOTE_ENABLE_E2E_CREDITS_S,
2927 1);
2928 roce_set_field(context->qpc_bytes_24,
2929 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
2930 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S,
2931 attr->min_rnr_timer);
2932 context->irrl_ba_l = cpu_to_le32((u32)(dma_handle_2));
2933 roce_set_field(context->qpc_bytes_32,
2934 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M,
2935 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_S,
2936 ((u32)(dma_handle_2 >> 32)) &
2937 QP_CONTEXT_QPC_BYTES_32_IRRL_BA_H_M);
2938 roce_set_field(context->qpc_bytes_32,
2939 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_M,
2940 QP_CONTEXT_QPC_BYTES_32_MIG_STATE_S, 0);
2941 roce_set_bit(context->qpc_bytes_32,
2942 QP_CONTEXT_QPC_BYTE_32_LOCAL_ENABLE_E2E_CREDITS_S,
2943 1);
2944 roce_set_bit(context->qpc_bytes_32,
2945 QP_CONTEXT_QPC_BYTE_32_SIGNALING_TYPE_S,
2946 hr_qp->sq_signal_bits);
2947
2948 port = (attr_mask & IB_QP_PORT) ? (attr->port_num - 1) :
2949 hr_qp->port;
2950 smac = (u8 *)hr_dev->dev_addr[port];
2951 /* when dmac equals smac or loop_idc is 1, it should loopback */
2952 if (ether_addr_equal_unaligned(dmac, smac) ||
2953 hr_dev->loop_idc == 0x1)
2954 roce_set_bit(context->qpc_bytes_32,
2955 QP_CONTEXT_QPC_BYTE_32_LOOPBACK_INDICATOR_S, 1);
2956
2957 roce_set_bit(context->qpc_bytes_32,
2958 QP_CONTEXT_QPC_BYTE_32_GLOBAL_HEADER_S,
2959 rdma_ah_get_ah_flags(&attr->ah_attr));
2960 roce_set_field(context->qpc_bytes_32,
2961 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
2962 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S,
2963 ilog2((unsigned int)attr->max_dest_rd_atomic));
2964
2965 if (attr_mask & IB_QP_DEST_QPN)
2966 roce_set_field(context->qpc_bytes_36,
2967 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
2968 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S,
2969 attr->dest_qp_num);
2970
2971 /* Configure GID index */
2972 port_num = rdma_ah_get_port_num(&attr->ah_attr);
2973 roce_set_field(context->qpc_bytes_36,
2974 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
2975 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S,
2976 hns_get_gid_index(hr_dev,
2977 port_num - 1,
2978 grh->sgid_index));
2979
2980 memcpy(&(context->dmac_l), dmac, 4);
2981
2982 roce_set_field(context->qpc_bytes_44,
2983 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
2984 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S,
2985 *((u16 *)(&dmac[4])));
2986 roce_set_field(context->qpc_bytes_44,
2987 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_M,
2988 QP_CONTEXT_QPC_BYTES_44_MAXIMUM_STATIC_RATE_S,
2989 rdma_ah_get_static_rate(&attr->ah_attr));
2990 roce_set_field(context->qpc_bytes_44,
2991 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
2992 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S,
2993 grh->hop_limit);
2994
2995 roce_set_field(context->qpc_bytes_48,
2996 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
2997 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S,
2998 grh->flow_label);
2999 roce_set_field(context->qpc_bytes_48,
3000 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3001 QP_CONTEXT_QPC_BYTES_48_TCLASS_S,
3002 grh->traffic_class);
3003 roce_set_field(context->qpc_bytes_48,
3004 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3005 QP_CONTEXT_QPC_BYTES_48_MTU_S, attr->path_mtu);
3006
3007 memcpy(context->dgid, grh->dgid.raw,
3008 sizeof(grh->dgid.raw));
3009
3010 dev_dbg(dev, "dmac:%x :%lx\n", context->dmac_l,
3011 roce_get_field(context->qpc_bytes_44,
3012 QP_CONTEXT_QPC_BYTES_44_DMAC_H_M,
3013 QP_CONTEXT_QPC_BYTES_44_DMAC_H_S));
3014
3015 roce_set_field(context->qpc_bytes_68,
3016 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_M,
3017 QP_CONTEXT_QPC_BYTES_68_RQ_HEAD_S,
3018 hr_qp->rq.head);
3019 roce_set_field(context->qpc_bytes_68,
3020 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_M,
3021 QP_CONTEXT_QPC_BYTES_68_RQ_CUR_INDEX_S, 0);
3022
3023 context->cur_rq_wqe_ba_l = cpu_to_le32(rq_ba);
3024
3025 roce_set_field(context->qpc_bytes_76,
3026 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_M,
3027 QP_CONTEXT_QPC_BYTES_76_CUR_RQ_WQE_BA_H_S,
3028 upper_32_bits(rq_ba));
3029 roce_set_field(context->qpc_bytes_76,
3030 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_M,
3031 QP_CONTEXT_QPC_BYTES_76_RX_REQ_MSN_S, 0);
3032
3033 context->rx_rnr_time = 0;
3034
3035 roce_set_field(context->qpc_bytes_84,
3036 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_M,
3037 QP_CONTEXT_QPC_BYTES_84_LAST_ACK_PSN_S,
3038 attr->rq_psn - 1);
3039 roce_set_field(context->qpc_bytes_84,
3040 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_M,
3041 QP_CONTEXT_QPC_BYTES_84_TRRL_HEAD_S, 0);
3042
3043 roce_set_field(context->qpc_bytes_88,
3044 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3045 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S,
3046 attr->rq_psn);
3047 roce_set_bit(context->qpc_bytes_88,
3048 QP_CONTEXT_QPC_BYTES_88_RX_REQ_PSN_ERR_FLAG_S, 0);
3049 roce_set_bit(context->qpc_bytes_88,
3050 QP_CONTEXT_QPC_BYTES_88_RX_LAST_OPCODE_FLG_S, 0);
3051 roce_set_field(context->qpc_bytes_88,
3052 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_M,
3053 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_LAST_OPERATION_TYPE_S,
3054 0);
3055 roce_set_field(context->qpc_bytes_88,
3056 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_M,
3057 QP_CONTEXT_QPC_BYTES_88_RQ_REQ_RDMA_WR_FLAG_S,
3058 0);
3059
3060 context->dma_length = 0;
3061 context->r_key = 0;
3062 context->va_l = 0;
3063 context->va_h = 0;
3064
3065 roce_set_field(context->qpc_bytes_108,
3066 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_M,
3067 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_S, 0);
3068 roce_set_bit(context->qpc_bytes_108,
3069 QP_CONTEXT_QPC_BYTES_108_TRRL_SDB_PSN_FLG_S, 0);
3070 roce_set_bit(context->qpc_bytes_108,
3071 QP_CONTEXT_QPC_BYTES_108_TRRL_TDB_PSN_FLG_S, 0);
3072
3073 roce_set_field(context->qpc_bytes_112,
3074 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_M,
3075 QP_CONTEXT_QPC_BYTES_112_TRRL_TDB_PSN_S, 0);
3076 roce_set_field(context->qpc_bytes_112,
3077 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_M,
3078 QP_CONTEXT_QPC_BYTES_112_TRRL_TAIL_S, 0);
3079
3080 /* For chip resp ack */
3081 roce_set_field(context->qpc_bytes_156,
3082 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3083 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3084 hr_qp->phy_port);
3085 roce_set_field(context->qpc_bytes_156,
3086 QP_CONTEXT_QPC_BYTES_156_SL_M,
3087 QP_CONTEXT_QPC_BYTES_156_SL_S,
3088 rdma_ah_get_sl(&attr->ah_attr));
3089 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3090 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3091 /* If exist optional param, return error */
3092 if ((attr_mask & IB_QP_ALT_PATH) ||
3093 (attr_mask & IB_QP_ACCESS_FLAGS) ||
3094 (attr_mask & IB_QP_QKEY) ||
3095 (attr_mask & IB_QP_PATH_MIG_STATE) ||
3096 (attr_mask & IB_QP_CUR_STATE) ||
3097 (attr_mask & IB_QP_MIN_RNR_TIMER)) {
3098 dev_err(dev, "RTR2RTS attr_mask error\n");
3099 goto out;
3100 }
3101
3102 context->rx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3103
3104 roce_set_field(context->qpc_bytes_120,
3105 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_M,
3106 QP_CONTEXT_QPC_BYTES_120_RX_CUR_SQ_WQE_BA_H_S,
3107 upper_32_bits(sq_ba));
3108
3109 roce_set_field(context->qpc_bytes_124,
3110 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_M,
3111 QP_CONTEXT_QPC_BYTES_124_RX_ACK_MSN_S, 0);
3112 roce_set_field(context->qpc_bytes_124,
3113 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_M,
3114 QP_CONTEXT_QPC_BYTES_124_IRRL_MSG_IDX_S, 0);
3115
3116 roce_set_field(context->qpc_bytes_128,
3117 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_M,
3118 QP_CONTEXT_QPC_BYTES_128_RX_ACK_EPSN_S,
3119 attr->sq_psn);
3120 roce_set_bit(context->qpc_bytes_128,
3121 QP_CONTEXT_QPC_BYTES_128_RX_ACK_PSN_ERR_FLG_S, 0);
3122 roce_set_field(context->qpc_bytes_128,
3123 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_M,
3124 QP_CONTEXT_QPC_BYTES_128_ACK_LAST_OPERATION_TYPE_S,
3125 0);
3126 roce_set_bit(context->qpc_bytes_128,
3127 QP_CONTEXT_QPC_BYTES_128_IRRL_PSN_VLD_FLG_S, 0);
3128
3129 roce_set_field(context->qpc_bytes_132,
3130 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_M,
3131 QP_CONTEXT_QPC_BYTES_132_IRRL_PSN_S, 0);
3132 roce_set_field(context->qpc_bytes_132,
3133 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_M,
3134 QP_CONTEXT_QPC_BYTES_132_IRRL_TAIL_S, 0);
3135
3136 roce_set_field(context->qpc_bytes_136,
3137 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_M,
3138 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_PSN_S,
3139 attr->sq_psn);
3140 roce_set_field(context->qpc_bytes_136,
3141 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_M,
3142 QP_CONTEXT_QPC_BYTES_136_RETRY_MSG_FPKT_PSN_L_S,
3143 attr->sq_psn);
3144
3145 roce_set_field(context->qpc_bytes_140,
3146 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_M,
3147 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_FPKT_PSN_H_S,
3148 (attr->sq_psn >> SQ_PSN_SHIFT));
3149 roce_set_field(context->qpc_bytes_140,
3150 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_M,
3151 QP_CONTEXT_QPC_BYTES_140_RETRY_MSG_MSN_S, 0);
3152 roce_set_bit(context->qpc_bytes_140,
3153 QP_CONTEXT_QPC_BYTES_140_RNR_RETRY_FLG_S, 0);
3154
3155 roce_set_field(context->qpc_bytes_148,
3156 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_M,
3157 QP_CONTEXT_QPC_BYTES_148_CHECK_FLAG_S, 0);
3158 roce_set_field(context->qpc_bytes_148,
3159 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3160 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S,
3161 attr->retry_cnt);
3162 roce_set_field(context->qpc_bytes_148,
3163 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_M,
3164 QP_CONTEXT_QPC_BYTES_148_RNR_RETRY_COUNT_S,
3165 attr->rnr_retry);
3166 roce_set_field(context->qpc_bytes_148,
3167 QP_CONTEXT_QPC_BYTES_148_LSN_M,
3168 QP_CONTEXT_QPC_BYTES_148_LSN_S, 0x100);
3169
3170 context->rnr_retry = 0;
3171
3172 roce_set_field(context->qpc_bytes_156,
3173 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_M,
3174 QP_CONTEXT_QPC_BYTES_156_RETRY_COUNT_INIT_S,
3175 attr->retry_cnt);
3176 if (attr->timeout < 0x12) {
3177 dev_info(dev, "ack timeout value(0x%x) must bigger than 0x12.\n",
3178 attr->timeout);
3179 roce_set_field(context->qpc_bytes_156,
3180 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3181 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3182 0x12);
3183 } else {
3184 roce_set_field(context->qpc_bytes_156,
3185 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3186 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S,
3187 attr->timeout);
3188 }
3189 roce_set_field(context->qpc_bytes_156,
3190 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_M,
3191 QP_CONTEXT_QPC_BYTES_156_RNR_RETRY_COUNT_INIT_S,
3192 attr->rnr_retry);
3193 roce_set_field(context->qpc_bytes_156,
3194 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_M,
3195 QP_CONTEXT_QPC_BYTES_156_PORT_NUM_S,
3196 hr_qp->phy_port);
3197 roce_set_field(context->qpc_bytes_156,
3198 QP_CONTEXT_QPC_BYTES_156_SL_M,
3199 QP_CONTEXT_QPC_BYTES_156_SL_S,
3200 rdma_ah_get_sl(&attr->ah_attr));
3201 hr_qp->sl = rdma_ah_get_sl(&attr->ah_attr);
3202 roce_set_field(context->qpc_bytes_156,
3203 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3204 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S,
3205 ilog2((unsigned int)attr->max_rd_atomic));
3206 roce_set_field(context->qpc_bytes_156,
3207 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_M,
3208 QP_CONTEXT_QPC_BYTES_156_ACK_REQ_IND_S, 0);
3209 context->pkt_use_len = 0;
3210
3211 roce_set_field(context->qpc_bytes_164,
3212 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3213 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S, attr->sq_psn);
3214 roce_set_field(context->qpc_bytes_164,
3215 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_M,
3216 QP_CONTEXT_QPC_BYTES_164_IRRL_HEAD_S, 0);
3217
3218 roce_set_field(context->qpc_bytes_168,
3219 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_M,
3220 QP_CONTEXT_QPC_BYTES_168_RETRY_SQ_PSN_S,
3221 attr->sq_psn);
3222 roce_set_field(context->qpc_bytes_168,
3223 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_M,
3224 QP_CONTEXT_QPC_BYTES_168_SGE_USE_FLA_S, 0);
3225 roce_set_field(context->qpc_bytes_168,
3226 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_M,
3227 QP_CONTEXT_QPC_BYTES_168_DB_TYPE_S, 0);
3228 roce_set_bit(context->qpc_bytes_168,
3229 QP_CONTEXT_QPC_BYTES_168_MSG_LP_IND_S, 0);
3230 roce_set_bit(context->qpc_bytes_168,
3231 QP_CONTEXT_QPC_BYTES_168_CSDB_LP_IND_S, 0);
3232 roce_set_bit(context->qpc_bytes_168,
3233 QP_CONTEXT_QPC_BYTES_168_QP_ERR_FLG_S, 0);
3234 context->sge_use_len = 0;
3235
3236 roce_set_field(context->qpc_bytes_176,
3237 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_M,
3238 QP_CONTEXT_QPC_BYTES_176_DB_CUR_INDEX_S, 0);
3239 roce_set_field(context->qpc_bytes_176,
3240 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_M,
3241 QP_CONTEXT_QPC_BYTES_176_RETRY_DB_CUR_INDEX_S,
3242 0);
3243 roce_set_field(context->qpc_bytes_180,
3244 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_M,
3245 QP_CONTEXT_QPC_BYTES_180_SQ_CUR_INDEX_S, 0);
3246 roce_set_field(context->qpc_bytes_180,
3247 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_M,
3248 QP_CONTEXT_QPC_BYTES_180_SQ_HEAD_S, 0);
3249
3250 context->tx_cur_sq_wqe_ba_l = cpu_to_le32(sq_ba);
3251
3252 roce_set_field(context->qpc_bytes_188,
3253 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_M,
3254 QP_CONTEXT_QPC_BYTES_188_TX_CUR_SQ_WQE_BA_H_S,
3255 upper_32_bits(sq_ba));
3256 roce_set_bit(context->qpc_bytes_188,
3257 QP_CONTEXT_QPC_BYTES_188_PKT_RETRY_FLG_S, 0);
3258 roce_set_field(context->qpc_bytes_188,
3259 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_M,
3260 QP_CONTEXT_QPC_BYTES_188_TX_RETRY_CUR_INDEX_S,
3261 0);
3262 }
3263
3264 /* Every status migrate must change state */
3265 roce_set_field(context->qpc_bytes_144,
3266 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3267 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S, new_state);
3268
3269 /* SW pass context to HW */
3270 ret = hns_roce_v1_qp_modify(hr_dev, to_hns_roce_state(cur_state),
3271 to_hns_roce_state(new_state), context,
3272 hr_qp);
3273 if (ret) {
3274 dev_err(dev, "hns_roce_qp_modify failed\n");
3275 goto out;
3276 }
3277
3278 /*
3279 * Use rst2init to instead of init2init with drv,
3280 * need to hw to flash RQ HEAD by DB again
3281 */
3282 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3283 roce_set_field(doorbell[0], RQ_DOORBELL_U32_4_RQ_HEAD_M,
3284 RQ_DOORBELL_U32_4_RQ_HEAD_S, hr_qp->rq.head);
3285 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_QPN_M,
3286 RQ_DOORBELL_U32_8_QPN_S, hr_qp->qpn);
3287 roce_set_field(doorbell[1], RQ_DOORBELL_U32_8_CMD_M,
3288 RQ_DOORBELL_U32_8_CMD_S, 1);
3289 roce_set_bit(doorbell[1], RQ_DOORBELL_U32_8_HW_SYNC_S, 1);
3290
3291 if (ibqp->uobject) {
3292 hr_qp->rq.db_reg = hr_dev->reg_base +
3293 hr_dev->odb_offset +
3294 DB_REG_OFFSET * hr_dev->priv_uar.index;
3295 }
3296
3297 hns_roce_write64_k(doorbell, hr_qp->rq.db_reg);
3298 }
3299
3300 hr_qp->state = new_state;
3301
3302 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3303 hr_qp->resp_depth = attr->max_dest_rd_atomic;
3304 if (attr_mask & IB_QP_PORT) {
3305 hr_qp->port = attr->port_num - 1;
3306 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
3307 }
3308
3309 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
3310 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn,
3311 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL);
3312 if (ibqp->send_cq != ibqp->recv_cq)
3313 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq),
3314 hr_qp->qpn, NULL);
3315
3316 hr_qp->rq.head = 0;
3317 hr_qp->rq.tail = 0;
3318 hr_qp->sq.head = 0;
3319 hr_qp->sq.tail = 0;
3320 }
3321 out:
3322 kfree(context);
3323 return ret;
3324 }
3325
hns_roce_v1_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)3326 static int hns_roce_v1_modify_qp(struct ib_qp *ibqp,
3327 const struct ib_qp_attr *attr, int attr_mask,
3328 enum ib_qp_state cur_state,
3329 enum ib_qp_state new_state)
3330 {
3331 if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
3332 return -EOPNOTSUPP;
3333
3334 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
3335 return hns_roce_v1_m_sqp(ibqp, attr, attr_mask, cur_state,
3336 new_state);
3337 else
3338 return hns_roce_v1_m_qp(ibqp, attr, attr_mask, cur_state,
3339 new_state);
3340 }
3341
to_ib_qp_state(enum hns_roce_qp_state state)3342 static enum ib_qp_state to_ib_qp_state(enum hns_roce_qp_state state)
3343 {
3344 switch (state) {
3345 case HNS_ROCE_QP_STATE_RST:
3346 return IB_QPS_RESET;
3347 case HNS_ROCE_QP_STATE_INIT:
3348 return IB_QPS_INIT;
3349 case HNS_ROCE_QP_STATE_RTR:
3350 return IB_QPS_RTR;
3351 case HNS_ROCE_QP_STATE_RTS:
3352 return IB_QPS_RTS;
3353 case HNS_ROCE_QP_STATE_SQD:
3354 return IB_QPS_SQD;
3355 case HNS_ROCE_QP_STATE_ERR:
3356 return IB_QPS_ERR;
3357 default:
3358 return IB_QPS_ERR;
3359 }
3360 }
3361
hns_roce_v1_query_qpc(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp,struct hns_roce_qp_context * hr_context)3362 static int hns_roce_v1_query_qpc(struct hns_roce_dev *hr_dev,
3363 struct hns_roce_qp *hr_qp,
3364 struct hns_roce_qp_context *hr_context)
3365 {
3366 struct hns_roce_cmd_mailbox *mailbox;
3367 int ret;
3368
3369 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
3370 if (IS_ERR(mailbox))
3371 return PTR_ERR(mailbox);
3372
3373 ret = hns_roce_cmd_mbox(hr_dev, 0, mailbox->dma, hr_qp->qpn, 0,
3374 HNS_ROCE_CMD_QUERY_QP,
3375 HNS_ROCE_CMD_TIMEOUT_MSECS);
3376 if (!ret)
3377 memcpy(hr_context, mailbox->buf, sizeof(*hr_context));
3378 else
3379 dev_err(&hr_dev->pdev->dev, "QUERY QP cmd process error\n");
3380
3381 hns_roce_free_cmd_mailbox(hr_dev, mailbox);
3382
3383 return ret;
3384 }
3385
hns_roce_v1_q_sqp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3386 static int hns_roce_v1_q_sqp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3387 int qp_attr_mask,
3388 struct ib_qp_init_attr *qp_init_attr)
3389 {
3390 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3391 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3392 struct hns_roce_sqp_context context;
3393 u32 addr;
3394
3395 mutex_lock(&hr_qp->mutex);
3396
3397 if (hr_qp->state == IB_QPS_RESET) {
3398 qp_attr->qp_state = IB_QPS_RESET;
3399 goto done;
3400 }
3401
3402 addr = ROCEE_QP1C_CFG0_0_REG +
3403 hr_qp->port * sizeof(struct hns_roce_sqp_context);
3404 context.qp1c_bytes_4 = cpu_to_le32(roce_read(hr_dev, addr));
3405 context.sq_rq_bt_l = cpu_to_le32(roce_read(hr_dev, addr + 1));
3406 context.qp1c_bytes_12 = cpu_to_le32(roce_read(hr_dev, addr + 2));
3407 context.qp1c_bytes_16 = cpu_to_le32(roce_read(hr_dev, addr + 3));
3408 context.qp1c_bytes_20 = cpu_to_le32(roce_read(hr_dev, addr + 4));
3409 context.cur_rq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 5));
3410 context.qp1c_bytes_28 = cpu_to_le32(roce_read(hr_dev, addr + 6));
3411 context.qp1c_bytes_32 = cpu_to_le32(roce_read(hr_dev, addr + 7));
3412 context.cur_sq_wqe_ba_l = cpu_to_le32(roce_read(hr_dev, addr + 8));
3413 context.qp1c_bytes_40 = cpu_to_le32(roce_read(hr_dev, addr + 9));
3414
3415 hr_qp->state = roce_get_field(context.qp1c_bytes_4,
3416 QP1C_BYTES_4_QP_STATE_M,
3417 QP1C_BYTES_4_QP_STATE_S);
3418 qp_attr->qp_state = hr_qp->state;
3419 qp_attr->path_mtu = IB_MTU_256;
3420 qp_attr->path_mig_state = IB_MIG_ARMED;
3421 qp_attr->qkey = QKEY_VAL;
3422 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3423 qp_attr->rq_psn = 0;
3424 qp_attr->sq_psn = 0;
3425 qp_attr->dest_qp_num = 1;
3426 qp_attr->qp_access_flags = 6;
3427
3428 qp_attr->pkey_index = roce_get_field(context.qp1c_bytes_20,
3429 QP1C_BYTES_20_PKEY_IDX_M,
3430 QP1C_BYTES_20_PKEY_IDX_S);
3431 qp_attr->port_num = hr_qp->port + 1;
3432 qp_attr->sq_draining = 0;
3433 qp_attr->max_rd_atomic = 0;
3434 qp_attr->max_dest_rd_atomic = 0;
3435 qp_attr->min_rnr_timer = 0;
3436 qp_attr->timeout = 0;
3437 qp_attr->retry_cnt = 0;
3438 qp_attr->rnr_retry = 0;
3439 qp_attr->alt_timeout = 0;
3440
3441 done:
3442 qp_attr->cur_qp_state = qp_attr->qp_state;
3443 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3444 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3445 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3446 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3447 qp_attr->cap.max_inline_data = 0;
3448 qp_init_attr->cap = qp_attr->cap;
3449 qp_init_attr->create_flags = 0;
3450
3451 mutex_unlock(&hr_qp->mutex);
3452
3453 return 0;
3454 }
3455
hns_roce_v1_q_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3456 static int hns_roce_v1_q_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3457 int qp_attr_mask,
3458 struct ib_qp_init_attr *qp_init_attr)
3459 {
3460 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3461 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3462 struct device *dev = &hr_dev->pdev->dev;
3463 struct hns_roce_qp_context *context;
3464 int tmp_qp_state;
3465 int ret = 0;
3466 int state;
3467
3468 context = kzalloc(sizeof(*context), GFP_KERNEL);
3469 if (!context)
3470 return -ENOMEM;
3471
3472 memset(qp_attr, 0, sizeof(*qp_attr));
3473 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
3474
3475 mutex_lock(&hr_qp->mutex);
3476
3477 if (hr_qp->state == IB_QPS_RESET) {
3478 qp_attr->qp_state = IB_QPS_RESET;
3479 goto done;
3480 }
3481
3482 ret = hns_roce_v1_query_qpc(hr_dev, hr_qp, context);
3483 if (ret) {
3484 dev_err(dev, "query qpc error\n");
3485 ret = -EINVAL;
3486 goto out;
3487 }
3488
3489 state = roce_get_field(context->qpc_bytes_144,
3490 QP_CONTEXT_QPC_BYTES_144_QP_STATE_M,
3491 QP_CONTEXT_QPC_BYTES_144_QP_STATE_S);
3492 tmp_qp_state = (int)to_ib_qp_state((enum hns_roce_qp_state)state);
3493 if (tmp_qp_state == -1) {
3494 dev_err(dev, "to_ib_qp_state error\n");
3495 ret = -EINVAL;
3496 goto out;
3497 }
3498 hr_qp->state = (u8)tmp_qp_state;
3499 qp_attr->qp_state = (enum ib_qp_state)hr_qp->state;
3500 qp_attr->path_mtu = (enum ib_mtu)roce_get_field(context->qpc_bytes_48,
3501 QP_CONTEXT_QPC_BYTES_48_MTU_M,
3502 QP_CONTEXT_QPC_BYTES_48_MTU_S);
3503 qp_attr->path_mig_state = IB_MIG_ARMED;
3504 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
3505 if (hr_qp->ibqp.qp_type == IB_QPT_UD)
3506 qp_attr->qkey = QKEY_VAL;
3507
3508 qp_attr->rq_psn = roce_get_field(context->qpc_bytes_88,
3509 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_M,
3510 QP_CONTEXT_QPC_BYTES_88_RX_REQ_EPSN_S);
3511 qp_attr->sq_psn = (u32)roce_get_field(context->qpc_bytes_164,
3512 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_M,
3513 QP_CONTEXT_QPC_BYTES_164_SQ_PSN_S);
3514 qp_attr->dest_qp_num = (u8)roce_get_field(context->qpc_bytes_36,
3515 QP_CONTEXT_QPC_BYTES_36_DEST_QP_M,
3516 QP_CONTEXT_QPC_BYTES_36_DEST_QP_S);
3517 qp_attr->qp_access_flags = ((roce_get_bit(context->qpc_bytes_4,
3518 QP_CONTEXT_QPC_BYTE_4_RDMA_READ_ENABLE_S)) << 2) |
3519 ((roce_get_bit(context->qpc_bytes_4,
3520 QP_CONTEXT_QPC_BYTE_4_RDMA_WRITE_ENABLE_S)) << 1) |
3521 ((roce_get_bit(context->qpc_bytes_4,
3522 QP_CONTEXT_QPC_BYTE_4_ATOMIC_OPERATION_ENABLE_S)) << 3);
3523
3524 if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
3525 struct ib_global_route *grh =
3526 rdma_ah_retrieve_grh(&qp_attr->ah_attr);
3527
3528 rdma_ah_set_sl(&qp_attr->ah_attr,
3529 roce_get_field(context->qpc_bytes_156,
3530 QP_CONTEXT_QPC_BYTES_156_SL_M,
3531 QP_CONTEXT_QPC_BYTES_156_SL_S));
3532 rdma_ah_set_ah_flags(&qp_attr->ah_attr, IB_AH_GRH);
3533 grh->flow_label =
3534 roce_get_field(context->qpc_bytes_48,
3535 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_M,
3536 QP_CONTEXT_QPC_BYTES_48_FLOWLABEL_S);
3537 grh->sgid_index =
3538 roce_get_field(context->qpc_bytes_36,
3539 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_M,
3540 QP_CONTEXT_QPC_BYTES_36_SGID_INDEX_S);
3541 grh->hop_limit =
3542 roce_get_field(context->qpc_bytes_44,
3543 QP_CONTEXT_QPC_BYTES_44_HOPLMT_M,
3544 QP_CONTEXT_QPC_BYTES_44_HOPLMT_S);
3545 grh->traffic_class =
3546 roce_get_field(context->qpc_bytes_48,
3547 QP_CONTEXT_QPC_BYTES_48_TCLASS_M,
3548 QP_CONTEXT_QPC_BYTES_48_TCLASS_S);
3549
3550 memcpy(grh->dgid.raw, context->dgid,
3551 sizeof(grh->dgid.raw));
3552 }
3553
3554 qp_attr->pkey_index = roce_get_field(context->qpc_bytes_12,
3555 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_M,
3556 QP_CONTEXT_QPC_BYTES_12_P_KEY_INDEX_S);
3557 qp_attr->port_num = hr_qp->port + 1;
3558 qp_attr->sq_draining = 0;
3559 qp_attr->max_rd_atomic = 1 << roce_get_field(context->qpc_bytes_156,
3560 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_M,
3561 QP_CONTEXT_QPC_BYTES_156_INITIATOR_DEPTH_S);
3562 qp_attr->max_dest_rd_atomic = 1 << roce_get_field(context->qpc_bytes_32,
3563 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_M,
3564 QP_CONTEXT_QPC_BYTES_32_RESPONDER_RESOURCES_S);
3565 qp_attr->min_rnr_timer = (u8)(roce_get_field(context->qpc_bytes_24,
3566 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_M,
3567 QP_CONTEXT_QPC_BYTES_24_MINIMUM_RNR_NAK_TIMER_S));
3568 qp_attr->timeout = (u8)(roce_get_field(context->qpc_bytes_156,
3569 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_M,
3570 QP_CONTEXT_QPC_BYTES_156_ACK_TIMEOUT_S));
3571 qp_attr->retry_cnt = roce_get_field(context->qpc_bytes_148,
3572 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_M,
3573 QP_CONTEXT_QPC_BYTES_148_RETRY_COUNT_S);
3574 qp_attr->rnr_retry = (u8)le32_to_cpu(context->rnr_retry);
3575
3576 done:
3577 qp_attr->cur_qp_state = qp_attr->qp_state;
3578 qp_attr->cap.max_recv_wr = hr_qp->rq.wqe_cnt;
3579 qp_attr->cap.max_recv_sge = hr_qp->rq.max_gs;
3580
3581 if (!ibqp->uobject) {
3582 qp_attr->cap.max_send_wr = hr_qp->sq.wqe_cnt;
3583 qp_attr->cap.max_send_sge = hr_qp->sq.max_gs;
3584 } else {
3585 qp_attr->cap.max_send_wr = 0;
3586 qp_attr->cap.max_send_sge = 0;
3587 }
3588
3589 qp_init_attr->cap = qp_attr->cap;
3590
3591 out:
3592 mutex_unlock(&hr_qp->mutex);
3593 kfree(context);
3594 return ret;
3595 }
3596
hns_roce_v1_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3597 static int hns_roce_v1_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3598 int qp_attr_mask,
3599 struct ib_qp_init_attr *qp_init_attr)
3600 {
3601 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3602
3603 return hr_qp->doorbell_qpn <= 1 ?
3604 hns_roce_v1_q_sqp(ibqp, qp_attr, qp_attr_mask, qp_init_attr) :
3605 hns_roce_v1_q_qp(ibqp, qp_attr, qp_attr_mask, qp_init_attr);
3606 }
3607
hns_roce_v1_destroy_qp(struct ib_qp * ibqp,struct ib_udata * udata)3608 int hns_roce_v1_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
3609 {
3610 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
3611 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
3612 struct hns_roce_cq *send_cq, *recv_cq;
3613 int ret;
3614
3615 ret = hns_roce_v1_modify_qp(ibqp, NULL, 0, hr_qp->state, IB_QPS_RESET);
3616 if (ret)
3617 return ret;
3618
3619 send_cq = hr_qp->ibqp.send_cq ? to_hr_cq(hr_qp->ibqp.send_cq) : NULL;
3620 recv_cq = hr_qp->ibqp.recv_cq ? to_hr_cq(hr_qp->ibqp.recv_cq) : NULL;
3621
3622 hns_roce_lock_cqs(send_cq, recv_cq);
3623 if (!udata) {
3624 if (recv_cq)
3625 __hns_roce_v1_cq_clean(recv_cq, hr_qp->qpn,
3626 (hr_qp->ibqp.srq ?
3627 to_hr_srq(hr_qp->ibqp.srq) :
3628 NULL));
3629
3630 if (send_cq && send_cq != recv_cq)
3631 __hns_roce_v1_cq_clean(send_cq, hr_qp->qpn, NULL);
3632 }
3633 hns_roce_qp_remove(hr_dev, hr_qp);
3634 hns_roce_unlock_cqs(send_cq, recv_cq);
3635
3636 hns_roce_qp_destroy(hr_dev, hr_qp, udata);
3637
3638 return 0;
3639 }
3640
hns_roce_v1_destroy_cq(struct ib_cq * ibcq,struct ib_udata * udata)3641 static int hns_roce_v1_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
3642 {
3643 struct hns_roce_dev *hr_dev = to_hr_dev(ibcq->device);
3644 struct hns_roce_cq *hr_cq = to_hr_cq(ibcq);
3645 struct device *dev = &hr_dev->pdev->dev;
3646 u32 cqe_cnt_ori;
3647 u32 cqe_cnt_cur;
3648 int wait_time = 0;
3649
3650 /*
3651 * Before freeing cq buffer, we need to ensure that the outstanding CQE
3652 * have been written by checking the CQE counter.
3653 */
3654 cqe_cnt_ori = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3655 while (1) {
3656 if (roce_read(hr_dev, ROCEE_CAEP_CQE_WCMD_EMPTY) &
3657 HNS_ROCE_CQE_WCMD_EMPTY_BIT)
3658 break;
3659
3660 cqe_cnt_cur = roce_read(hr_dev, ROCEE_SCAEP_WR_CQE_CNT);
3661 if ((cqe_cnt_cur - cqe_cnt_ori) >= HNS_ROCE_MIN_CQE_CNT)
3662 break;
3663
3664 msleep(HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS);
3665 if (wait_time > HNS_ROCE_MAX_FREE_CQ_WAIT_CNT) {
3666 dev_warn(dev, "Destroy cq 0x%lx timeout!\n",
3667 hr_cq->cqn);
3668 break;
3669 }
3670 wait_time++;
3671 }
3672 return 0;
3673 }
3674
set_eq_cons_index_v1(struct hns_roce_eq * eq,u32 req_not)3675 static void set_eq_cons_index_v1(struct hns_roce_eq *eq, u32 req_not)
3676 {
3677 roce_raw_write((eq->cons_index & HNS_ROCE_V1_CONS_IDX_M) |
3678 (req_not << eq->log_entries), eq->db_reg);
3679 }
3680
hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int qpn)3681 static void hns_roce_v1_wq_catas_err_handle(struct hns_roce_dev *hr_dev,
3682 struct hns_roce_aeqe *aeqe, int qpn)
3683 {
3684 struct device *dev = &hr_dev->pdev->dev;
3685
3686 dev_warn(dev, "Local Work Queue Catastrophic Error.\n");
3687 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3688 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3689 case HNS_ROCE_LWQCE_QPC_ERROR:
3690 dev_warn(dev, "QP %d, QPC error.\n", qpn);
3691 break;
3692 case HNS_ROCE_LWQCE_MTU_ERROR:
3693 dev_warn(dev, "QP %d, MTU error.\n", qpn);
3694 break;
3695 case HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR:
3696 dev_warn(dev, "QP %d, WQE BA addr error.\n", qpn);
3697 break;
3698 case HNS_ROCE_LWQCE_WQE_ADDR_ERROR:
3699 dev_warn(dev, "QP %d, WQE addr error.\n", qpn);
3700 break;
3701 case HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR:
3702 dev_warn(dev, "QP %d, WQE shift error\n", qpn);
3703 break;
3704 case HNS_ROCE_LWQCE_SL_ERROR:
3705 dev_warn(dev, "QP %d, SL error.\n", qpn);
3706 break;
3707 case HNS_ROCE_LWQCE_PORT_ERROR:
3708 dev_warn(dev, "QP %d, port error.\n", qpn);
3709 break;
3710 default:
3711 break;
3712 }
3713 }
3714
hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int qpn)3715 static void hns_roce_v1_local_wq_access_err_handle(struct hns_roce_dev *hr_dev,
3716 struct hns_roce_aeqe *aeqe,
3717 int qpn)
3718 {
3719 struct device *dev = &hr_dev->pdev->dev;
3720
3721 dev_warn(dev, "Local Access Violation Work Queue Error.\n");
3722 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3723 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3724 case HNS_ROCE_LAVWQE_R_KEY_VIOLATION:
3725 dev_warn(dev, "QP %d, R_key violation.\n", qpn);
3726 break;
3727 case HNS_ROCE_LAVWQE_LENGTH_ERROR:
3728 dev_warn(dev, "QP %d, length error.\n", qpn);
3729 break;
3730 case HNS_ROCE_LAVWQE_VA_ERROR:
3731 dev_warn(dev, "QP %d, VA error.\n", qpn);
3732 break;
3733 case HNS_ROCE_LAVWQE_PD_ERROR:
3734 dev_err(dev, "QP %d, PD error.\n", qpn);
3735 break;
3736 case HNS_ROCE_LAVWQE_RW_ACC_ERROR:
3737 dev_warn(dev, "QP %d, rw acc error.\n", qpn);
3738 break;
3739 case HNS_ROCE_LAVWQE_KEY_STATE_ERROR:
3740 dev_warn(dev, "QP %d, key state error.\n", qpn);
3741 break;
3742 case HNS_ROCE_LAVWQE_MR_OPERATION_ERROR:
3743 dev_warn(dev, "QP %d, MR operation error.\n", qpn);
3744 break;
3745 default:
3746 break;
3747 }
3748 }
3749
hns_roce_v1_qp_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int event_type)3750 static void hns_roce_v1_qp_err_handle(struct hns_roce_dev *hr_dev,
3751 struct hns_roce_aeqe *aeqe,
3752 int event_type)
3753 {
3754 struct device *dev = &hr_dev->pdev->dev;
3755 int phy_port;
3756 int qpn;
3757
3758 qpn = roce_get_field(aeqe->event.queue_event.num,
3759 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M,
3760 HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S);
3761 phy_port = roce_get_field(aeqe->event.queue_event.num,
3762 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M,
3763 HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S);
3764 if (qpn <= 1)
3765 qpn = HNS_ROCE_MAX_PORTS * qpn + phy_port;
3766
3767 switch (event_type) {
3768 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3769 dev_warn(dev, "Invalid Req Local Work Queue Error.\n"
3770 "QP %d, phy_port %d.\n", qpn, phy_port);
3771 break;
3772 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3773 hns_roce_v1_wq_catas_err_handle(hr_dev, aeqe, qpn);
3774 break;
3775 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3776 hns_roce_v1_local_wq_access_err_handle(hr_dev, aeqe, qpn);
3777 break;
3778 default:
3779 break;
3780 }
3781
3782 hns_roce_qp_event(hr_dev, qpn, event_type);
3783 }
3784
hns_roce_v1_cq_err_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe,int event_type)3785 static void hns_roce_v1_cq_err_handle(struct hns_roce_dev *hr_dev,
3786 struct hns_roce_aeqe *aeqe,
3787 int event_type)
3788 {
3789 struct device *dev = &hr_dev->pdev->dev;
3790 u32 cqn;
3791
3792 cqn = roce_get_field(aeqe->event.queue_event.num,
3793 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M,
3794 HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S);
3795
3796 switch (event_type) {
3797 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3798 dev_warn(dev, "CQ 0x%x access err.\n", cqn);
3799 break;
3800 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3801 dev_warn(dev, "CQ 0x%x overflow\n", cqn);
3802 break;
3803 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3804 dev_warn(dev, "CQ 0x%x ID invalid.\n", cqn);
3805 break;
3806 default:
3807 break;
3808 }
3809
3810 hns_roce_cq_event(hr_dev, cqn, event_type);
3811 }
3812
hns_roce_v1_db_overflow_handle(struct hns_roce_dev * hr_dev,struct hns_roce_aeqe * aeqe)3813 static void hns_roce_v1_db_overflow_handle(struct hns_roce_dev *hr_dev,
3814 struct hns_roce_aeqe *aeqe)
3815 {
3816 struct device *dev = &hr_dev->pdev->dev;
3817
3818 switch (roce_get_field(aeqe->asyn, HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M,
3819 HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)) {
3820 case HNS_ROCE_DB_SUBTYPE_SDB_OVF:
3821 dev_warn(dev, "SDB overflow.\n");
3822 break;
3823 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF:
3824 dev_warn(dev, "SDB almost overflow.\n");
3825 break;
3826 case HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP:
3827 dev_warn(dev, "SDB almost empty.\n");
3828 break;
3829 case HNS_ROCE_DB_SUBTYPE_ODB_OVF:
3830 dev_warn(dev, "ODB overflow.\n");
3831 break;
3832 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF:
3833 dev_warn(dev, "ODB almost overflow.\n");
3834 break;
3835 case HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP:
3836 dev_warn(dev, "SDB almost empty.\n");
3837 break;
3838 default:
3839 break;
3840 }
3841 }
3842
get_aeqe_v1(struct hns_roce_eq * eq,u32 entry)3843 static struct hns_roce_aeqe *get_aeqe_v1(struct hns_roce_eq *eq, u32 entry)
3844 {
3845 unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_AEQE_SIZE;
3846
3847 return (struct hns_roce_aeqe *)((u8 *)
3848 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3849 off % HNS_ROCE_BA_SIZE);
3850 }
3851
next_aeqe_sw_v1(struct hns_roce_eq * eq)3852 static struct hns_roce_aeqe *next_aeqe_sw_v1(struct hns_roce_eq *eq)
3853 {
3854 struct hns_roce_aeqe *aeqe = get_aeqe_v1(eq, eq->cons_index);
3855
3856 return (roce_get_bit(aeqe->asyn, HNS_ROCE_AEQE_U32_4_OWNER_S) ^
3857 !!(eq->cons_index & eq->entries)) ? aeqe : NULL;
3858 }
3859
hns_roce_v1_aeq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)3860 static int hns_roce_v1_aeq_int(struct hns_roce_dev *hr_dev,
3861 struct hns_roce_eq *eq)
3862 {
3863 struct device *dev = &hr_dev->pdev->dev;
3864 struct hns_roce_aeqe *aeqe;
3865 int aeqes_found = 0;
3866 int event_type;
3867
3868 while ((aeqe = next_aeqe_sw_v1(eq))) {
3869 /* Make sure we read the AEQ entry after we have checked the
3870 * ownership bit
3871 */
3872 dma_rmb();
3873
3874 dev_dbg(dev, "aeqe = %pK, aeqe->asyn.event_type = 0x%lx\n",
3875 aeqe,
3876 roce_get_field(aeqe->asyn,
3877 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3878 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S));
3879 event_type = roce_get_field(aeqe->asyn,
3880 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M,
3881 HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S);
3882 switch (event_type) {
3883 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
3884 dev_warn(dev, "PATH MIG not supported\n");
3885 break;
3886 case HNS_ROCE_EVENT_TYPE_COMM_EST:
3887 dev_warn(dev, "COMMUNICATION established\n");
3888 break;
3889 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
3890 dev_warn(dev, "SQ DRAINED not supported\n");
3891 break;
3892 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
3893 dev_warn(dev, "PATH MIG failed\n");
3894 break;
3895 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
3896 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
3897 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
3898 hns_roce_v1_qp_err_handle(hr_dev, aeqe, event_type);
3899 break;
3900 case HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH:
3901 case HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR:
3902 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
3903 dev_warn(dev, "SRQ not support!\n");
3904 break;
3905 case HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR:
3906 case HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW:
3907 case HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID:
3908 hns_roce_v1_cq_err_handle(hr_dev, aeqe, event_type);
3909 break;
3910 case HNS_ROCE_EVENT_TYPE_PORT_CHANGE:
3911 dev_warn(dev, "port change.\n");
3912 break;
3913 case HNS_ROCE_EVENT_TYPE_MB:
3914 hns_roce_cmd_event(hr_dev,
3915 le16_to_cpu(aeqe->event.cmd.token),
3916 aeqe->event.cmd.status,
3917 le64_to_cpu(aeqe->event.cmd.out_param
3918 ));
3919 break;
3920 case HNS_ROCE_EVENT_TYPE_DB_OVERFLOW:
3921 hns_roce_v1_db_overflow_handle(hr_dev, aeqe);
3922 break;
3923 default:
3924 dev_warn(dev, "Unhandled event %d on EQ %d at idx %u.\n",
3925 event_type, eq->eqn, eq->cons_index);
3926 break;
3927 }
3928
3929 eq->cons_index++;
3930 aeqes_found = 1;
3931
3932 if (eq->cons_index > 2 * hr_dev->caps.aeqe_depth - 1)
3933 eq->cons_index = 0;
3934 }
3935
3936 set_eq_cons_index_v1(eq, 0);
3937
3938 return aeqes_found;
3939 }
3940
get_ceqe_v1(struct hns_roce_eq * eq,u32 entry)3941 static struct hns_roce_ceqe *get_ceqe_v1(struct hns_roce_eq *eq, u32 entry)
3942 {
3943 unsigned long off = (entry & (eq->entries - 1)) * HNS_ROCE_CEQE_SIZE;
3944
3945 return (struct hns_roce_ceqe *)((u8 *)
3946 (eq->buf_list[off / HNS_ROCE_BA_SIZE].buf) +
3947 off % HNS_ROCE_BA_SIZE);
3948 }
3949
next_ceqe_sw_v1(struct hns_roce_eq * eq)3950 static struct hns_roce_ceqe *next_ceqe_sw_v1(struct hns_roce_eq *eq)
3951 {
3952 struct hns_roce_ceqe *ceqe = get_ceqe_v1(eq, eq->cons_index);
3953
3954 return (!!(roce_get_bit(ceqe->comp,
3955 HNS_ROCE_CEQE_CEQE_COMP_OWNER_S))) ^
3956 (!!(eq->cons_index & eq->entries)) ? ceqe : NULL;
3957 }
3958
hns_roce_v1_ceq_int(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)3959 static int hns_roce_v1_ceq_int(struct hns_roce_dev *hr_dev,
3960 struct hns_roce_eq *eq)
3961 {
3962 struct hns_roce_ceqe *ceqe;
3963 int ceqes_found = 0;
3964 u32 cqn;
3965
3966 while ((ceqe = next_ceqe_sw_v1(eq))) {
3967 /* Make sure we read CEQ entry after we have checked the
3968 * ownership bit
3969 */
3970 dma_rmb();
3971
3972 cqn = roce_get_field(ceqe->comp,
3973 HNS_ROCE_CEQE_CEQE_COMP_CQN_M,
3974 HNS_ROCE_CEQE_CEQE_COMP_CQN_S);
3975 hns_roce_cq_completion(hr_dev, cqn);
3976
3977 ++eq->cons_index;
3978 ceqes_found = 1;
3979
3980 if (eq->cons_index >
3981 EQ_DEPTH_COEFF * hr_dev->caps.ceqe_depth - 1)
3982 eq->cons_index = 0;
3983 }
3984
3985 set_eq_cons_index_v1(eq, 0);
3986
3987 return ceqes_found;
3988 }
3989
hns_roce_v1_msix_interrupt_eq(int irq,void * eq_ptr)3990 static irqreturn_t hns_roce_v1_msix_interrupt_eq(int irq, void *eq_ptr)
3991 {
3992 struct hns_roce_eq *eq = eq_ptr;
3993 struct hns_roce_dev *hr_dev = eq->hr_dev;
3994 int int_work;
3995
3996 if (eq->type_flag == HNS_ROCE_CEQ)
3997 /* CEQ irq routine, CEQ is pulse irq, not clear */
3998 int_work = hns_roce_v1_ceq_int(hr_dev, eq);
3999 else
4000 /* AEQ irq routine, AEQ is pulse irq, not clear */
4001 int_work = hns_roce_v1_aeq_int(hr_dev, eq);
4002
4003 return IRQ_RETVAL(int_work);
4004 }
4005
hns_roce_v1_msix_interrupt_abn(int irq,void * dev_id)4006 static irqreturn_t hns_roce_v1_msix_interrupt_abn(int irq, void *dev_id)
4007 {
4008 struct hns_roce_dev *hr_dev = dev_id;
4009 struct device *dev = &hr_dev->pdev->dev;
4010 int int_work = 0;
4011 u32 caepaemask_val;
4012 u32 cealmovf_val;
4013 u32 caepaest_val;
4014 u32 aeshift_val;
4015 u32 ceshift_val;
4016 u32 cemask_val;
4017 __le32 tmp;
4018 int i;
4019
4020 /*
4021 * Abnormal interrupt:
4022 * AEQ overflow, ECC multi-bit err, CEQ overflow must clear
4023 * interrupt, mask irq, clear irq, cancel mask operation
4024 */
4025 aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
4026 tmp = cpu_to_le32(aeshift_val);
4027
4028 /* AEQE overflow */
4029 if (roce_get_bit(tmp,
4030 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S) == 1) {
4031 dev_warn(dev, "AEQ overflow!\n");
4032
4033 /* Set mask */
4034 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4035 tmp = cpu_to_le32(caepaemask_val);
4036 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4037 HNS_ROCE_INT_MASK_ENABLE);
4038 caepaemask_val = le32_to_cpu(tmp);
4039 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4040
4041 /* Clear int state(INT_WC : write 1 clear) */
4042 caepaest_val = roce_read(hr_dev, ROCEE_CAEP_AE_ST_REG);
4043 tmp = cpu_to_le32(caepaest_val);
4044 roce_set_bit(tmp, ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S, 1);
4045 caepaest_val = le32_to_cpu(tmp);
4046 roce_write(hr_dev, ROCEE_CAEP_AE_ST_REG, caepaest_val);
4047
4048 /* Clear mask */
4049 caepaemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4050 tmp = cpu_to_le32(caepaemask_val);
4051 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4052 HNS_ROCE_INT_MASK_DISABLE);
4053 caepaemask_val = le32_to_cpu(tmp);
4054 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, caepaemask_val);
4055 }
4056
4057 /* CEQ almost overflow */
4058 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4059 ceshift_val = roce_read(hr_dev, ROCEE_CAEP_CEQC_SHIFT_0_REG +
4060 i * CEQ_REG_OFFSET);
4061 tmp = cpu_to_le32(ceshift_val);
4062
4063 if (roce_get_bit(tmp,
4064 ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S) == 1) {
4065 dev_warn(dev, "CEQ[%d] almost overflow!\n", i);
4066 int_work++;
4067
4068 /* Set mask */
4069 cemask_val = roce_read(hr_dev,
4070 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4071 i * CEQ_REG_OFFSET);
4072 tmp = cpu_to_le32(cemask_val);
4073 roce_set_bit(tmp,
4074 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4075 HNS_ROCE_INT_MASK_ENABLE);
4076 cemask_val = le32_to_cpu(tmp);
4077 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4078 i * CEQ_REG_OFFSET, cemask_val);
4079
4080 /* Clear int state(INT_WC : write 1 clear) */
4081 cealmovf_val = roce_read(hr_dev,
4082 ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4083 i * CEQ_REG_OFFSET);
4084 tmp = cpu_to_le32(cealmovf_val);
4085 roce_set_bit(tmp,
4086 ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S,
4087 1);
4088 cealmovf_val = le32_to_cpu(tmp);
4089 roce_write(hr_dev, ROCEE_CAEP_CEQ_ALM_OVF_0_REG +
4090 i * CEQ_REG_OFFSET, cealmovf_val);
4091
4092 /* Clear mask */
4093 cemask_val = roce_read(hr_dev,
4094 ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4095 i * CEQ_REG_OFFSET);
4096 tmp = cpu_to_le32(cemask_val);
4097 roce_set_bit(tmp,
4098 ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S,
4099 HNS_ROCE_INT_MASK_DISABLE);
4100 cemask_val = le32_to_cpu(tmp);
4101 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4102 i * CEQ_REG_OFFSET, cemask_val);
4103 }
4104 }
4105
4106 /* ECC multi-bit error alarm */
4107 dev_warn(dev, "ECC UCERR ALARM: 0x%x, 0x%x, 0x%x\n",
4108 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM0_REG),
4109 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM1_REG),
4110 roce_read(hr_dev, ROCEE_ECC_UCERR_ALM2_REG));
4111
4112 dev_warn(dev, "ECC CERR ALARM: 0x%x, 0x%x, 0x%x\n",
4113 roce_read(hr_dev, ROCEE_ECC_CERR_ALM0_REG),
4114 roce_read(hr_dev, ROCEE_ECC_CERR_ALM1_REG),
4115 roce_read(hr_dev, ROCEE_ECC_CERR_ALM2_REG));
4116
4117 return IRQ_RETVAL(int_work);
4118 }
4119
hns_roce_v1_int_mask_enable(struct hns_roce_dev * hr_dev)4120 static void hns_roce_v1_int_mask_enable(struct hns_roce_dev *hr_dev)
4121 {
4122 u32 aemask_val;
4123 int masken = 0;
4124 __le32 tmp;
4125 int i;
4126
4127 /* AEQ INT */
4128 aemask_val = roce_read(hr_dev, ROCEE_CAEP_AE_MASK_REG);
4129 tmp = cpu_to_le32(aemask_val);
4130 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S,
4131 masken);
4132 roce_set_bit(tmp, ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S, masken);
4133 aemask_val = le32_to_cpu(tmp);
4134 roce_write(hr_dev, ROCEE_CAEP_AE_MASK_REG, aemask_val);
4135
4136 /* CEQ INT */
4137 for (i = 0; i < hr_dev->caps.num_comp_vectors; i++) {
4138 /* IRQ mask */
4139 roce_write(hr_dev, ROCEE_CAEP_CE_IRQ_MASK_0_REG +
4140 i * CEQ_REG_OFFSET, masken);
4141 }
4142 }
4143
hns_roce_v1_free_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4144 static void hns_roce_v1_free_eq(struct hns_roce_dev *hr_dev,
4145 struct hns_roce_eq *eq)
4146 {
4147 int npages = (PAGE_ALIGN(eq->eqe_size * eq->entries) +
4148 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4149 int i;
4150
4151 if (!eq->buf_list)
4152 return;
4153
4154 for (i = 0; i < npages; ++i)
4155 dma_free_coherent(&hr_dev->pdev->dev, HNS_ROCE_BA_SIZE,
4156 eq->buf_list[i].buf, eq->buf_list[i].map);
4157
4158 kfree(eq->buf_list);
4159 }
4160
hns_roce_v1_enable_eq(struct hns_roce_dev * hr_dev,int eq_num,int enable_flag)4161 static void hns_roce_v1_enable_eq(struct hns_roce_dev *hr_dev, int eq_num,
4162 int enable_flag)
4163 {
4164 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq_num];
4165 __le32 tmp;
4166 u32 val;
4167
4168 val = readl(eqc);
4169 tmp = cpu_to_le32(val);
4170
4171 if (enable_flag)
4172 roce_set_field(tmp,
4173 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4174 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4175 HNS_ROCE_EQ_STAT_VALID);
4176 else
4177 roce_set_field(tmp,
4178 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4179 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4180 HNS_ROCE_EQ_STAT_INVALID);
4181
4182 val = le32_to_cpu(tmp);
4183 writel(val, eqc);
4184 }
4185
hns_roce_v1_create_eq(struct hns_roce_dev * hr_dev,struct hns_roce_eq * eq)4186 static int hns_roce_v1_create_eq(struct hns_roce_dev *hr_dev,
4187 struct hns_roce_eq *eq)
4188 {
4189 void __iomem *eqc = hr_dev->eq_table.eqc_base[eq->eqn];
4190 struct device *dev = &hr_dev->pdev->dev;
4191 dma_addr_t tmp_dma_addr;
4192 u32 eqcuridx_val;
4193 u32 eqconsindx_val;
4194 u32 eqshift_val;
4195 __le32 tmp2 = 0;
4196 __le32 tmp1 = 0;
4197 __le32 tmp = 0;
4198 int num_bas;
4199 int ret;
4200 int i;
4201
4202 num_bas = (PAGE_ALIGN(eq->entries * eq->eqe_size) +
4203 HNS_ROCE_BA_SIZE - 1) / HNS_ROCE_BA_SIZE;
4204
4205 if ((eq->entries * eq->eqe_size) > HNS_ROCE_BA_SIZE) {
4206 dev_err(dev, "[error]eq buf %d gt ba size(%d) need bas=%d\n",
4207 (eq->entries * eq->eqe_size), HNS_ROCE_BA_SIZE,
4208 num_bas);
4209 return -EINVAL;
4210 }
4211
4212 eq->buf_list = kcalloc(num_bas, sizeof(*eq->buf_list), GFP_KERNEL);
4213 if (!eq->buf_list)
4214 return -ENOMEM;
4215
4216 for (i = 0; i < num_bas; ++i) {
4217 eq->buf_list[i].buf = dma_alloc_coherent(dev, HNS_ROCE_BA_SIZE,
4218 &tmp_dma_addr,
4219 GFP_KERNEL);
4220 if (!eq->buf_list[i].buf) {
4221 ret = -ENOMEM;
4222 goto err_out_free_pages;
4223 }
4224
4225 eq->buf_list[i].map = tmp_dma_addr;
4226 }
4227 eq->cons_index = 0;
4228 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M,
4229 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S,
4230 HNS_ROCE_EQ_STAT_INVALID);
4231 roce_set_field(tmp, ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M,
4232 ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S,
4233 eq->log_entries);
4234 eqshift_val = le32_to_cpu(tmp);
4235 writel(eqshift_val, eqc);
4236
4237 /* Configure eq extended address 12~44bit */
4238 writel((u32)(eq->buf_list[0].map >> 12), eqc + 4);
4239
4240 /*
4241 * Configure eq extended address 45~49 bit.
4242 * 44 = 32 + 12, When evaluating addr to hardware, shift 12 because of
4243 * using 4K page, and shift more 32 because of
4244 * calculating the high 32 bit value evaluated to hardware.
4245 */
4246 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M,
4247 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S,
4248 eq->buf_list[0].map >> 44);
4249 roce_set_field(tmp1, ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M,
4250 ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S, 0);
4251 eqcuridx_val = le32_to_cpu(tmp1);
4252 writel(eqcuridx_val, eqc + 8);
4253
4254 /* Configure eq consumer index */
4255 roce_set_field(tmp2, ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M,
4256 ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S, 0);
4257 eqconsindx_val = le32_to_cpu(tmp2);
4258 writel(eqconsindx_val, eqc + 0xc);
4259
4260 return 0;
4261
4262 err_out_free_pages:
4263 for (i -= 1; i >= 0; i--)
4264 dma_free_coherent(dev, HNS_ROCE_BA_SIZE, eq->buf_list[i].buf,
4265 eq->buf_list[i].map);
4266
4267 kfree(eq->buf_list);
4268 return ret;
4269 }
4270
hns_roce_v1_init_eq_table(struct hns_roce_dev * hr_dev)4271 static int hns_roce_v1_init_eq_table(struct hns_roce_dev *hr_dev)
4272 {
4273 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4274 struct device *dev = &hr_dev->pdev->dev;
4275 struct hns_roce_eq *eq;
4276 int irq_num;
4277 int eq_num;
4278 int ret;
4279 int i, j;
4280
4281 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4282 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4283
4284 eq_table->eq = kcalloc(eq_num, sizeof(*eq_table->eq), GFP_KERNEL);
4285 if (!eq_table->eq)
4286 return -ENOMEM;
4287
4288 eq_table->eqc_base = kcalloc(eq_num, sizeof(*eq_table->eqc_base),
4289 GFP_KERNEL);
4290 if (!eq_table->eqc_base) {
4291 ret = -ENOMEM;
4292 goto err_eqc_base_alloc_fail;
4293 }
4294
4295 for (i = 0; i < eq_num; i++) {
4296 eq = &eq_table->eq[i];
4297 eq->hr_dev = hr_dev;
4298 eq->eqn = i;
4299 eq->irq = hr_dev->irq[i];
4300 eq->log_page_size = PAGE_SHIFT;
4301
4302 if (i < hr_dev->caps.num_comp_vectors) {
4303 /* CEQ */
4304 eq_table->eqc_base[i] = hr_dev->reg_base +
4305 ROCEE_CAEP_CEQC_SHIFT_0_REG +
4306 CEQ_REG_OFFSET * i;
4307 eq->type_flag = HNS_ROCE_CEQ;
4308 eq->db_reg = hr_dev->reg_base +
4309 ROCEE_CAEP_CEQC_CONS_IDX_0_REG +
4310 CEQ_REG_OFFSET * i;
4311 eq->entries = hr_dev->caps.ceqe_depth;
4312 eq->log_entries = ilog2(eq->entries);
4313 eq->eqe_size = HNS_ROCE_CEQE_SIZE;
4314 } else {
4315 /* AEQ */
4316 eq_table->eqc_base[i] = hr_dev->reg_base +
4317 ROCEE_CAEP_AEQC_AEQE_SHIFT_REG;
4318 eq->type_flag = HNS_ROCE_AEQ;
4319 eq->db_reg = hr_dev->reg_base +
4320 ROCEE_CAEP_AEQE_CONS_IDX_REG;
4321 eq->entries = hr_dev->caps.aeqe_depth;
4322 eq->log_entries = ilog2(eq->entries);
4323 eq->eqe_size = HNS_ROCE_AEQE_SIZE;
4324 }
4325 }
4326
4327 /* Disable irq */
4328 hns_roce_v1_int_mask_enable(hr_dev);
4329
4330 /* Configure ce int interval */
4331 roce_write(hr_dev, ROCEE_CAEP_CE_INTERVAL_CFG_REG,
4332 HNS_ROCE_CEQ_DEFAULT_INTERVAL);
4333
4334 /* Configure ce int burst num */
4335 roce_write(hr_dev, ROCEE_CAEP_CE_BURST_NUM_CFG_REG,
4336 HNS_ROCE_CEQ_DEFAULT_BURST_NUM);
4337
4338 for (i = 0; i < eq_num; i++) {
4339 ret = hns_roce_v1_create_eq(hr_dev, &eq_table->eq[i]);
4340 if (ret) {
4341 dev_err(dev, "eq create failed\n");
4342 goto err_create_eq_fail;
4343 }
4344 }
4345
4346 for (j = 0; j < irq_num; j++) {
4347 if (j < eq_num)
4348 ret = request_irq(hr_dev->irq[j],
4349 hns_roce_v1_msix_interrupt_eq, 0,
4350 hr_dev->irq_names[j],
4351 &eq_table->eq[j]);
4352 else
4353 ret = request_irq(hr_dev->irq[j],
4354 hns_roce_v1_msix_interrupt_abn, 0,
4355 hr_dev->irq_names[j], hr_dev);
4356
4357 if (ret) {
4358 dev_err(dev, "request irq error!\n");
4359 goto err_request_irq_fail;
4360 }
4361 }
4362
4363 for (i = 0; i < eq_num; i++)
4364 hns_roce_v1_enable_eq(hr_dev, i, EQ_ENABLE);
4365
4366 return 0;
4367
4368 err_request_irq_fail:
4369 for (j -= 1; j >= 0; j--)
4370 free_irq(hr_dev->irq[j], &eq_table->eq[j]);
4371
4372 err_create_eq_fail:
4373 for (i -= 1; i >= 0; i--)
4374 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4375
4376 kfree(eq_table->eqc_base);
4377
4378 err_eqc_base_alloc_fail:
4379 kfree(eq_table->eq);
4380
4381 return ret;
4382 }
4383
hns_roce_v1_cleanup_eq_table(struct hns_roce_dev * hr_dev)4384 static void hns_roce_v1_cleanup_eq_table(struct hns_roce_dev *hr_dev)
4385 {
4386 struct hns_roce_eq_table *eq_table = &hr_dev->eq_table;
4387 int irq_num;
4388 int eq_num;
4389 int i;
4390
4391 eq_num = hr_dev->caps.num_comp_vectors + hr_dev->caps.num_aeq_vectors;
4392 irq_num = eq_num + hr_dev->caps.num_other_vectors;
4393 for (i = 0; i < eq_num; i++) {
4394 /* Disable EQ */
4395 hns_roce_v1_enable_eq(hr_dev, i, EQ_DISABLE);
4396
4397 free_irq(hr_dev->irq[i], &eq_table->eq[i]);
4398
4399 hns_roce_v1_free_eq(hr_dev, &eq_table->eq[i]);
4400 }
4401 for (i = eq_num; i < irq_num; i++)
4402 free_irq(hr_dev->irq[i], hr_dev);
4403
4404 kfree(eq_table->eqc_base);
4405 kfree(eq_table->eq);
4406 }
4407
4408 static const struct ib_device_ops hns_roce_v1_dev_ops = {
4409 .destroy_qp = hns_roce_v1_destroy_qp,
4410 .poll_cq = hns_roce_v1_poll_cq,
4411 .post_recv = hns_roce_v1_post_recv,
4412 .post_send = hns_roce_v1_post_send,
4413 .query_qp = hns_roce_v1_query_qp,
4414 .req_notify_cq = hns_roce_v1_req_notify_cq,
4415 };
4416
4417 static const struct hns_roce_hw hns_roce_hw_v1 = {
4418 .reset = hns_roce_v1_reset,
4419 .hw_profile = hns_roce_v1_profile,
4420 .hw_init = hns_roce_v1_init,
4421 .hw_exit = hns_roce_v1_exit,
4422 .post_mbox = hns_roce_v1_post_mbox,
4423 .poll_mbox_done = hns_roce_v1_chk_mbox,
4424 .set_gid = hns_roce_v1_set_gid,
4425 .set_mac = hns_roce_v1_set_mac,
4426 .set_mtu = hns_roce_v1_set_mtu,
4427 .write_mtpt = hns_roce_v1_write_mtpt,
4428 .write_cqc = hns_roce_v1_write_cqc,
4429 .set_hem = hns_roce_v1_set_hem,
4430 .clear_hem = hns_roce_v1_clear_hem,
4431 .modify_qp = hns_roce_v1_modify_qp,
4432 .dereg_mr = hns_roce_v1_dereg_mr,
4433 .destroy_cq = hns_roce_v1_destroy_cq,
4434 .init_eq = hns_roce_v1_init_eq_table,
4435 .cleanup_eq = hns_roce_v1_cleanup_eq_table,
4436 .hns_roce_dev_ops = &hns_roce_v1_dev_ops,
4437 };
4438
4439 static const struct of_device_id hns_roce_of_match[] = {
4440 { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
4441 {},
4442 };
4443 MODULE_DEVICE_TABLE(of, hns_roce_of_match);
4444
4445 static const struct acpi_device_id hns_roce_acpi_match[] = {
4446 { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
4447 {},
4448 };
4449 MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
4450
4451 static struct
hns_roce_find_pdev(struct fwnode_handle * fwnode)4452 platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
4453 {
4454 struct device *dev;
4455
4456 /* get the 'device' corresponding to the matching 'fwnode' */
4457 dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode);
4458 /* get the platform device */
4459 return dev ? to_platform_device(dev) : NULL;
4460 }
4461
hns_roce_get_cfg(struct hns_roce_dev * hr_dev)4462 static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
4463 {
4464 struct device *dev = &hr_dev->pdev->dev;
4465 struct platform_device *pdev = NULL;
4466 struct net_device *netdev = NULL;
4467 struct device_node *net_node;
4468 int port_cnt = 0;
4469 u8 phy_port;
4470 int ret;
4471 int i;
4472
4473 /* check if we are compatible with the underlying SoC */
4474 if (dev_of_node(dev)) {
4475 const struct of_device_id *of_id;
4476
4477 of_id = of_match_node(hns_roce_of_match, dev->of_node);
4478 if (!of_id) {
4479 dev_err(dev, "device is not compatible!\n");
4480 return -ENXIO;
4481 }
4482 hr_dev->hw = (const struct hns_roce_hw *)of_id->data;
4483 if (!hr_dev->hw) {
4484 dev_err(dev, "couldn't get H/W specific DT data!\n");
4485 return -ENXIO;
4486 }
4487 } else if (is_acpi_device_node(dev->fwnode)) {
4488 const struct acpi_device_id *acpi_id;
4489
4490 acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
4491 if (!acpi_id) {
4492 dev_err(dev, "device is not compatible!\n");
4493 return -ENXIO;
4494 }
4495 hr_dev->hw = (const struct hns_roce_hw *) acpi_id->driver_data;
4496 if (!hr_dev->hw) {
4497 dev_err(dev, "couldn't get H/W specific ACPI data!\n");
4498 return -ENXIO;
4499 }
4500 } else {
4501 dev_err(dev, "can't read compatibility data from DT or ACPI\n");
4502 return -ENXIO;
4503 }
4504
4505 /* get the mapped register base address */
4506 hr_dev->reg_base = devm_platform_ioremap_resource(hr_dev->pdev, 0);
4507 if (IS_ERR(hr_dev->reg_base))
4508 return PTR_ERR(hr_dev->reg_base);
4509
4510 /* read the node_guid of IB device from the DT or ACPI */
4511 ret = device_property_read_u8_array(dev, "node-guid",
4512 (u8 *)&hr_dev->ib_dev.node_guid,
4513 GUID_LEN);
4514 if (ret) {
4515 dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
4516 return ret;
4517 }
4518
4519 /* get the RoCE associated ethernet ports or netdevices */
4520 for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
4521 if (dev_of_node(dev)) {
4522 net_node = of_parse_phandle(dev->of_node, "eth-handle",
4523 i);
4524 if (!net_node)
4525 continue;
4526 pdev = of_find_device_by_node(net_node);
4527 } else if (is_acpi_device_node(dev->fwnode)) {
4528 struct fwnode_reference_args args;
4529
4530 ret = acpi_node_get_property_reference(dev->fwnode,
4531 "eth-handle",
4532 i, &args);
4533 if (ret)
4534 continue;
4535 pdev = hns_roce_find_pdev(args.fwnode);
4536 } else {
4537 dev_err(dev, "cannot read data from DT or ACPI\n");
4538 return -ENXIO;
4539 }
4540
4541 if (pdev) {
4542 netdev = platform_get_drvdata(pdev);
4543 phy_port = (u8)i;
4544 if (netdev) {
4545 hr_dev->iboe.netdevs[port_cnt] = netdev;
4546 hr_dev->iboe.phy_port[port_cnt] = phy_port;
4547 } else {
4548 dev_err(dev, "no netdev found with pdev %s\n",
4549 pdev->name);
4550 return -ENODEV;
4551 }
4552 port_cnt++;
4553 }
4554 }
4555
4556 if (port_cnt == 0) {
4557 dev_err(dev, "unable to get eth-handle for available ports!\n");
4558 return -EINVAL;
4559 }
4560
4561 hr_dev->caps.num_ports = port_cnt;
4562
4563 /* cmd issue mode: 0 is poll, 1 is event */
4564 hr_dev->cmd_mod = 1;
4565 hr_dev->loop_idc = 0;
4566 hr_dev->sdb_offset = ROCEE_DB_SQ_L_0_REG;
4567 hr_dev->odb_offset = ROCEE_DB_OTHERS_L_0_REG;
4568
4569 /* read the interrupt names from the DT or ACPI */
4570 ret = device_property_read_string_array(dev, "interrupt-names",
4571 hr_dev->irq_names,
4572 HNS_ROCE_V1_MAX_IRQ_NUM);
4573 if (ret < 0) {
4574 dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
4575 return ret;
4576 }
4577
4578 /* fetch the interrupt numbers */
4579 for (i = 0; i < HNS_ROCE_V1_MAX_IRQ_NUM; i++) {
4580 hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
4581 if (hr_dev->irq[i] <= 0)
4582 return -EINVAL;
4583 }
4584
4585 return 0;
4586 }
4587
4588 /**
4589 * hns_roce_probe - RoCE driver entrance
4590 * @pdev: pointer to platform device
4591 * Return : int
4592 *
4593 */
hns_roce_probe(struct platform_device * pdev)4594 static int hns_roce_probe(struct platform_device *pdev)
4595 {
4596 int ret;
4597 struct hns_roce_dev *hr_dev;
4598 struct device *dev = &pdev->dev;
4599
4600 hr_dev = ib_alloc_device(hns_roce_dev, ib_dev);
4601 if (!hr_dev)
4602 return -ENOMEM;
4603
4604 hr_dev->priv = kzalloc(sizeof(struct hns_roce_v1_priv), GFP_KERNEL);
4605 if (!hr_dev->priv) {
4606 ret = -ENOMEM;
4607 goto error_failed_kzalloc;
4608 }
4609
4610 hr_dev->pdev = pdev;
4611 hr_dev->dev = dev;
4612 platform_set_drvdata(pdev, hr_dev);
4613
4614 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
4615 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
4616 dev_err(dev, "Not usable DMA addressing mode\n");
4617 ret = -EIO;
4618 goto error_failed_get_cfg;
4619 }
4620
4621 ret = hns_roce_get_cfg(hr_dev);
4622 if (ret) {
4623 dev_err(dev, "Get Configuration failed!\n");
4624 goto error_failed_get_cfg;
4625 }
4626
4627 ret = hns_roce_init(hr_dev);
4628 if (ret) {
4629 dev_err(dev, "RoCE engine init failed!\n");
4630 goto error_failed_get_cfg;
4631 }
4632
4633 return 0;
4634
4635 error_failed_get_cfg:
4636 kfree(hr_dev->priv);
4637
4638 error_failed_kzalloc:
4639 ib_dealloc_device(&hr_dev->ib_dev);
4640
4641 return ret;
4642 }
4643
4644 /**
4645 * hns_roce_remove - remove RoCE device
4646 * @pdev: pointer to platform device
4647 */
hns_roce_remove(struct platform_device * pdev)4648 static int hns_roce_remove(struct platform_device *pdev)
4649 {
4650 struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
4651
4652 hns_roce_exit(hr_dev);
4653 kfree(hr_dev->priv);
4654 ib_dealloc_device(&hr_dev->ib_dev);
4655
4656 return 0;
4657 }
4658
4659 static struct platform_driver hns_roce_driver = {
4660 .probe = hns_roce_probe,
4661 .remove = hns_roce_remove,
4662 .driver = {
4663 .name = DRV_NAME,
4664 .of_match_table = hns_roce_of_match,
4665 .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
4666 },
4667 };
4668
4669 module_platform_driver(hns_roce_driver);
4670
4671 MODULE_LICENSE("Dual BSD/GPL");
4672 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
4673 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
4674 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
4675 MODULE_DESCRIPTION("Hisilicon Hip06 Family RoCE Driver");
4676