1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/of_platform.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <rdma/ib_addr.h>
38 #include <rdma/ib_smi.h>
39 #include <rdma/ib_user_verbs.h>
40 #include <rdma/ib_cache.h>
41 #include "hns_roce_common.h"
42 #include "hns_roce_device.h"
43 #include "hns_roce_hem.h"
44
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u32 port,u8 * addr)45 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port, u8 *addr)
46 {
47 u8 phy_port;
48 u32 i;
49
50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
51 return 0;
52
53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
54 return 0;
55
56 for (i = 0; i < ETH_ALEN; i++)
57 hr_dev->dev_addr[port][i] = addr[i];
58
59 phy_port = hr_dev->iboe.phy_port[port];
60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
61 }
62
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
64 {
65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
66 u32 port = attr->port_num - 1;
67 int ret;
68
69 if (port >= hr_dev->caps.num_ports)
70 return -EINVAL;
71
72 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
73
74 return ret;
75 }
76
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
78 {
79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
80 u32 port = attr->port_num - 1;
81 int ret;
82
83 if (port >= hr_dev->caps.num_ports)
84 return -EINVAL;
85
86 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, NULL, NULL);
87
88 return ret;
89 }
90
handle_en_event(struct hns_roce_dev * hr_dev,u32 port,unsigned long event)91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
92 unsigned long event)
93 {
94 struct device *dev = hr_dev->dev;
95 struct net_device *netdev;
96 int ret = 0;
97
98 netdev = hr_dev->iboe.netdevs[port];
99 if (!netdev) {
100 dev_err(dev, "Can't find netdev on port(%u)!\n", port);
101 return -ENODEV;
102 }
103
104 switch (event) {
105 case NETDEV_UP:
106 case NETDEV_CHANGE:
107 case NETDEV_REGISTER:
108 case NETDEV_CHANGEADDR:
109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
110 break;
111 case NETDEV_DOWN:
112 /*
113 * In v1 engine, only support all ports closed together.
114 */
115 break;
116 default:
117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
118 break;
119 }
120
121 return ret;
122 }
123
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)124 static int hns_roce_netdev_event(struct notifier_block *self,
125 unsigned long event, void *ptr)
126 {
127 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
128 struct hns_roce_ib_iboe *iboe = NULL;
129 struct hns_roce_dev *hr_dev = NULL;
130 int ret;
131 u32 port;
132
133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
134 iboe = &hr_dev->iboe;
135
136 for (port = 0; port < hr_dev->caps.num_ports; port++) {
137 if (dev == iboe->netdevs[port]) {
138 ret = handle_en_event(hr_dev, port, event);
139 if (ret)
140 return NOTIFY_DONE;
141 break;
142 }
143 }
144
145 return NOTIFY_DONE;
146 }
147
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
149 {
150 int ret;
151 u8 i;
152
153 for (i = 0; i < hr_dev->caps.num_ports; i++) {
154 if (hr_dev->hw->set_mtu)
155 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
156 hr_dev->caps.max_mtu);
157 ret = hns_roce_set_mac(hr_dev, i,
158 hr_dev->iboe.netdevs[i]->dev_addr);
159 if (ret)
160 return ret;
161 }
162
163 return 0;
164 }
165
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)166 static int hns_roce_query_device(struct ib_device *ib_dev,
167 struct ib_device_attr *props,
168 struct ib_udata *uhw)
169 {
170 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
171
172 memset(props, 0, sizeof(*props));
173
174 props->fw_ver = hr_dev->caps.fw_ver;
175 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
176 props->max_mr_size = (u64)(~(0ULL));
177 props->page_size_cap = hr_dev->caps.page_size_cap;
178 props->vendor_id = hr_dev->vendor_id;
179 props->vendor_part_id = hr_dev->vendor_part_id;
180 props->hw_ver = hr_dev->hw_rev;
181 props->max_qp = hr_dev->caps.num_qps;
182 props->max_qp_wr = hr_dev->caps.max_wqes;
183 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
184 IB_DEVICE_RC_RNR_NAK_GEN;
185 props->max_send_sge = hr_dev->caps.max_sq_sg;
186 props->max_recv_sge = hr_dev->caps.max_rq_sg;
187 props->max_sge_rd = 1;
188 props->max_cq = hr_dev->caps.num_cqs;
189 props->max_cqe = hr_dev->caps.max_cqes;
190 props->max_mr = hr_dev->caps.num_mtpts;
191 props->max_pd = hr_dev->caps.num_pds;
192 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
193 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
194 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
195 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
196 props->max_pkeys = 1;
197 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
198 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
199 props->max_srq = hr_dev->caps.num_srqs;
200 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
201 props->max_srq_sge = hr_dev->caps.max_srq_sges;
202 }
203
204 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
205 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
206 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
207 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
208 }
209
210 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
211 props->device_cap_flags |= IB_DEVICE_XRC;
212
213 return 0;
214 }
215
hns_roce_query_port(struct ib_device * ib_dev,u32 port_num,struct ib_port_attr * props)216 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
217 struct ib_port_attr *props)
218 {
219 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
220 struct device *dev = hr_dev->dev;
221 struct net_device *net_dev;
222 unsigned long flags;
223 enum ib_mtu mtu;
224 u32 port;
225 int ret;
226
227 port = port_num - 1;
228
229 /* props being zeroed by the caller, avoid zeroing it here */
230
231 props->max_mtu = hr_dev->caps.max_mtu;
232 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
233 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
234 IB_PORT_VENDOR_CLASS_SUP |
235 IB_PORT_BOOT_MGMT_SUP;
236 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
237 props->pkey_tbl_len = 1;
238 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
239 &props->active_width);
240 if (ret)
241 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
242
243 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
244
245 net_dev = hr_dev->iboe.netdevs[port];
246 if (!net_dev) {
247 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
248 dev_err(dev, "Find netdev %u failed!\n", port);
249 return -EINVAL;
250 }
251
252 mtu = iboe_get_mtu(net_dev->mtu);
253 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
254 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
255 IB_PORT_ACTIVE :
256 IB_PORT_DOWN;
257 props->phys_state = props->state == IB_PORT_ACTIVE ?
258 IB_PORT_PHYS_STATE_LINK_UP :
259 IB_PORT_PHYS_STATE_DISABLED;
260
261 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
262
263 return 0;
264 }
265
hns_roce_get_link_layer(struct ib_device * device,u32 port_num)266 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
267 u32 port_num)
268 {
269 return IB_LINK_LAYER_ETHERNET;
270 }
271
hns_roce_query_pkey(struct ib_device * ib_dev,u32 port,u16 index,u16 * pkey)272 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
273 u16 *pkey)
274 {
275 if (index > 0)
276 return -EINVAL;
277
278 *pkey = PKEY_ID;
279
280 return 0;
281 }
282
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)283 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
284 struct ib_device_modify *props)
285 {
286 unsigned long flags;
287
288 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
289 return -EOPNOTSUPP;
290
291 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
292 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
293 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
294 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
295 }
296
297 return 0;
298 }
299
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)300 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
301 struct ib_udata *udata)
302 {
303 int ret;
304 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
305 struct hns_roce_ib_alloc_ucontext_resp resp = {};
306 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
307
308 if (!hr_dev->active)
309 return -EAGAIN;
310
311 resp.qp_tab_size = hr_dev->caps.num_qps;
312 resp.srq_tab_size = hr_dev->caps.num_srqs;
313
314 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
315 if (ret)
316 goto error_fail_uar_alloc;
317
318 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
319 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
320 INIT_LIST_HEAD(&context->page_list);
321 mutex_init(&context->page_mutex);
322 }
323
324 resp.cqe_size = hr_dev->caps.cqe_sz;
325
326 ret = ib_copy_to_udata(udata, &resp,
327 min(udata->outlen, sizeof(resp)));
328 if (ret)
329 goto error_fail_copy_to_udata;
330
331 return 0;
332
333 error_fail_copy_to_udata:
334 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
335
336 error_fail_uar_alloc:
337 return ret;
338 }
339
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)340 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
341 {
342 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
343 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
344
345 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
346 }
347
hns_roce_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)348 static int hns_roce_mmap(struct ib_ucontext *context,
349 struct vm_area_struct *vma)
350 {
351 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
352
353 switch (vma->vm_pgoff) {
354 case 0:
355 return rdma_user_mmap_io(context, vma,
356 to_hr_ucontext(context)->uar.pfn,
357 PAGE_SIZE,
358 pgprot_device(vma->vm_page_prot),
359 NULL);
360
361 /* vm_pgoff: 1 -- TPTR */
362 case 1:
363 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
364 return -EINVAL;
365 /*
366 * FIXME: using io_remap_pfn_range on the dma address returned
367 * by dma_alloc_coherent is totally wrong.
368 */
369 return rdma_user_mmap_io(context, vma,
370 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
371 hr_dev->tptr_size,
372 vma->vm_page_prot,
373 NULL);
374
375 default:
376 return -EINVAL;
377 }
378 }
379
hns_roce_port_immutable(struct ib_device * ib_dev,u32 port_num,struct ib_port_immutable * immutable)380 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
381 struct ib_port_immutable *immutable)
382 {
383 struct ib_port_attr attr;
384 int ret;
385
386 ret = ib_query_port(ib_dev, port_num, &attr);
387 if (ret)
388 return ret;
389
390 immutable->pkey_tbl_len = attr.pkey_tbl_len;
391 immutable->gid_tbl_len = attr.gid_tbl_len;
392
393 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
394 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
395 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
396 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
397
398 return 0;
399 }
400
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)401 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
402 {
403 }
404
hns_roce_get_fw_ver(struct ib_device * device,char * str)405 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
406 {
407 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
408 unsigned int major, minor, sub_minor;
409
410 major = upper_32_bits(fw_ver);
411 minor = high_16_bits(lower_32_bits(fw_ver));
412 sub_minor = low_16_bits(fw_ver);
413
414 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
415 sub_minor);
416 }
417
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)418 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
419 {
420 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
421
422 hr_dev->active = false;
423 unregister_netdevice_notifier(&iboe->nb);
424 ib_unregister_device(&hr_dev->ib_dev);
425 }
426
427 static const struct ib_device_ops hns_roce_dev_ops = {
428 .owner = THIS_MODULE,
429 .driver_id = RDMA_DRIVER_HNS,
430 .uverbs_abi_ver = 1,
431 .uverbs_no_driver_id_binding = 1,
432
433 .get_dev_fw_str = hns_roce_get_fw_ver,
434 .add_gid = hns_roce_add_gid,
435 .alloc_pd = hns_roce_alloc_pd,
436 .alloc_ucontext = hns_roce_alloc_ucontext,
437 .create_ah = hns_roce_create_ah,
438 .create_user_ah = hns_roce_create_ah,
439 .create_cq = hns_roce_create_cq,
440 .create_qp = hns_roce_create_qp,
441 .dealloc_pd = hns_roce_dealloc_pd,
442 .dealloc_ucontext = hns_roce_dealloc_ucontext,
443 .del_gid = hns_roce_del_gid,
444 .dereg_mr = hns_roce_dereg_mr,
445 .destroy_ah = hns_roce_destroy_ah,
446 .destroy_cq = hns_roce_destroy_cq,
447 .disassociate_ucontext = hns_roce_disassociate_ucontext,
448 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
449 .get_dma_mr = hns_roce_get_dma_mr,
450 .get_link_layer = hns_roce_get_link_layer,
451 .get_port_immutable = hns_roce_port_immutable,
452 .mmap = hns_roce_mmap,
453 .modify_device = hns_roce_modify_device,
454 .modify_qp = hns_roce_modify_qp,
455 .query_ah = hns_roce_query_ah,
456 .query_device = hns_roce_query_device,
457 .query_pkey = hns_roce_query_pkey,
458 .query_port = hns_roce_query_port,
459 .reg_user_mr = hns_roce_reg_user_mr,
460
461 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
462 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
463 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
464 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
465 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
466 };
467
468 static const struct ib_device_ops hns_roce_dev_mr_ops = {
469 .rereg_user_mr = hns_roce_rereg_user_mr,
470 };
471
472 static const struct ib_device_ops hns_roce_dev_mw_ops = {
473 .alloc_mw = hns_roce_alloc_mw,
474 .dealloc_mw = hns_roce_dealloc_mw,
475
476 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
477 };
478
479 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
480 .alloc_mr = hns_roce_alloc_mr,
481 .map_mr_sg = hns_roce_map_mr_sg,
482 };
483
484 static const struct ib_device_ops hns_roce_dev_srq_ops = {
485 .create_srq = hns_roce_create_srq,
486 .destroy_srq = hns_roce_destroy_srq,
487
488 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
489 };
490
491 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
492 .alloc_xrcd = hns_roce_alloc_xrcd,
493 .dealloc_xrcd = hns_roce_dealloc_xrcd,
494
495 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
496 };
497
hns_roce_register_device(struct hns_roce_dev * hr_dev)498 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
499 {
500 int ret;
501 struct hns_roce_ib_iboe *iboe = NULL;
502 struct ib_device *ib_dev = NULL;
503 struct device *dev = hr_dev->dev;
504 unsigned int i;
505
506 iboe = &hr_dev->iboe;
507 spin_lock_init(&iboe->lock);
508
509 ib_dev = &hr_dev->ib_dev;
510
511 ib_dev->node_type = RDMA_NODE_IB_CA;
512 ib_dev->dev.parent = dev;
513
514 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
515 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
516 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
517
518 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
519 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
520
521 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
522 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
523
524 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
525 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
526
527 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
528 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
529 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
530 }
531
532 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
533 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
534
535 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
536 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
537 for (i = 0; i < hr_dev->caps.num_ports; i++) {
538 if (!hr_dev->iboe.netdevs[i])
539 continue;
540
541 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
542 i + 1);
543 if (ret)
544 return ret;
545 }
546 dma_set_max_seg_size(dev, UINT_MAX);
547 ret = ib_register_device(ib_dev, "hns_%d", dev);
548 if (ret) {
549 dev_err(dev, "ib_register_device failed!\n");
550 return ret;
551 }
552
553 ret = hns_roce_setup_mtu_mac(hr_dev);
554 if (ret) {
555 dev_err(dev, "setup_mtu_mac failed!\n");
556 goto error_failed_setup_mtu_mac;
557 }
558
559 iboe->nb.notifier_call = hns_roce_netdev_event;
560 ret = register_netdevice_notifier(&iboe->nb);
561 if (ret) {
562 dev_err(dev, "register_netdevice_notifier failed!\n");
563 goto error_failed_setup_mtu_mac;
564 }
565
566 hr_dev->active = true;
567 return 0;
568
569 error_failed_setup_mtu_mac:
570 ib_unregister_device(ib_dev);
571
572 return ret;
573 }
574
hns_roce_init_hem(struct hns_roce_dev * hr_dev)575 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
576 {
577 struct device *dev = hr_dev->dev;
578 int ret;
579
580 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
581 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
582 hr_dev->caps.num_mtpts, 1);
583 if (ret) {
584 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
585 return ret;
586 }
587
588 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
589 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
590 hr_dev->caps.num_qps, 1);
591 if (ret) {
592 dev_err(dev, "Failed to init QP context memory, aborting.\n");
593 goto err_unmap_dmpt;
594 }
595
596 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
597 HEM_TYPE_IRRL,
598 hr_dev->caps.irrl_entry_sz *
599 hr_dev->caps.max_qp_init_rdma,
600 hr_dev->caps.num_qps, 1);
601 if (ret) {
602 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
603 goto err_unmap_qp;
604 }
605
606 if (hr_dev->caps.trrl_entry_sz) {
607 ret = hns_roce_init_hem_table(hr_dev,
608 &hr_dev->qp_table.trrl_table,
609 HEM_TYPE_TRRL,
610 hr_dev->caps.trrl_entry_sz *
611 hr_dev->caps.max_qp_dest_rdma,
612 hr_dev->caps.num_qps, 1);
613 if (ret) {
614 dev_err(dev,
615 "Failed to init trrl_table memory, aborting.\n");
616 goto err_unmap_irrl;
617 }
618 }
619
620 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
621 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
622 hr_dev->caps.num_cqs, 1);
623 if (ret) {
624 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
625 goto err_unmap_trrl;
626 }
627
628 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
629 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
630 HEM_TYPE_SRQC,
631 hr_dev->caps.srqc_entry_sz,
632 hr_dev->caps.num_srqs, 1);
633 if (ret) {
634 dev_err(dev,
635 "Failed to init SRQ context memory, aborting.\n");
636 goto err_unmap_cq;
637 }
638 }
639
640 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
641 ret = hns_roce_init_hem_table(hr_dev,
642 &hr_dev->qp_table.sccc_table,
643 HEM_TYPE_SCCC,
644 hr_dev->caps.sccc_sz,
645 hr_dev->caps.num_qps, 1);
646 if (ret) {
647 dev_err(dev,
648 "Failed to init SCC context memory, aborting.\n");
649 goto err_unmap_srq;
650 }
651 }
652
653 if (hr_dev->caps.qpc_timer_entry_sz) {
654 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
655 HEM_TYPE_QPC_TIMER,
656 hr_dev->caps.qpc_timer_entry_sz,
657 hr_dev->caps.num_qpc_timer, 1);
658 if (ret) {
659 dev_err(dev,
660 "Failed to init QPC timer memory, aborting.\n");
661 goto err_unmap_ctx;
662 }
663 }
664
665 if (hr_dev->caps.cqc_timer_entry_sz) {
666 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
667 HEM_TYPE_CQC_TIMER,
668 hr_dev->caps.cqc_timer_entry_sz,
669 hr_dev->caps.cqc_timer_bt_num, 1);
670 if (ret) {
671 dev_err(dev,
672 "Failed to init CQC timer memory, aborting.\n");
673 goto err_unmap_qpc_timer;
674 }
675 }
676
677 if (hr_dev->caps.gmv_entry_sz) {
678 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
679 HEM_TYPE_GMV,
680 hr_dev->caps.gmv_entry_sz,
681 hr_dev->caps.gmv_entry_num, 1);
682 if (ret) {
683 dev_err(dev,
684 "failed to init gmv table memory, ret = %d\n",
685 ret);
686 goto err_unmap_cqc_timer;
687 }
688 }
689
690 return 0;
691
692 err_unmap_cqc_timer:
693 if (hr_dev->caps.cqc_timer_entry_sz)
694 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
695
696 err_unmap_qpc_timer:
697 if (hr_dev->caps.qpc_timer_entry_sz)
698 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
699
700 err_unmap_ctx:
701 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
702 hns_roce_cleanup_hem_table(hr_dev,
703 &hr_dev->qp_table.sccc_table);
704 err_unmap_srq:
705 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
706 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
707
708 err_unmap_cq:
709 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
710
711 err_unmap_trrl:
712 if (hr_dev->caps.trrl_entry_sz)
713 hns_roce_cleanup_hem_table(hr_dev,
714 &hr_dev->qp_table.trrl_table);
715
716 err_unmap_irrl:
717 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
718
719 err_unmap_qp:
720 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
721
722 err_unmap_dmpt:
723 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
724
725 return ret;
726 }
727
728 /**
729 * hns_roce_setup_hca - setup host channel adapter
730 * @hr_dev: pointer to hns roce device
731 * Return : int
732 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)733 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
734 {
735 struct device *dev = hr_dev->dev;
736 int ret;
737
738 spin_lock_init(&hr_dev->sm_lock);
739 spin_lock_init(&hr_dev->bt_cmd_lock);
740
741 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
742 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
743 INIT_LIST_HEAD(&hr_dev->pgdir_list);
744 mutex_init(&hr_dev->pgdir_mutex);
745 }
746
747 hns_roce_init_uar_table(hr_dev);
748
749 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
750 if (ret) {
751 dev_err(dev, "Failed to allocate priv_uar.\n");
752 goto err_uar_table_free;
753 }
754
755 ret = hns_roce_init_qp_table(hr_dev);
756 if (ret) {
757 dev_err(dev, "Failed to init qp_table.\n");
758 goto err_uar_table_free;
759 }
760
761 hns_roce_init_pd_table(hr_dev);
762
763 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
764 hns_roce_init_xrcd_table(hr_dev);
765
766 hns_roce_init_mr_table(hr_dev);
767
768 hns_roce_init_cq_table(hr_dev);
769
770 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
771 hns_roce_init_srq_table(hr_dev);
772 }
773
774 return 0;
775
776 err_uar_table_free:
777 ida_destroy(&hr_dev->uar_ida.ida);
778 return ret;
779 }
780
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)781 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
782 {
783 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
784 unsigned long flags;
785
786 spin_lock_irqsave(&hr_cq->lock, flags);
787 if (cq->comp_handler) {
788 if (!hr_cq->is_armed) {
789 hr_cq->is_armed = 1;
790 list_add_tail(&hr_cq->node, cq_list);
791 }
792 }
793 spin_unlock_irqrestore(&hr_cq->lock, flags);
794 }
795
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)796 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
797 {
798 struct hns_roce_qp *hr_qp;
799 struct hns_roce_cq *hr_cq;
800 struct list_head cq_list;
801 unsigned long flags_qp;
802 unsigned long flags;
803
804 INIT_LIST_HEAD(&cq_list);
805
806 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
807 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
808 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
809 if (hr_qp->sq.tail != hr_qp->sq.head)
810 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
811 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
812
813 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
814 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
815 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
816 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
817 }
818
819 list_for_each_entry(hr_cq, &cq_list, node)
820 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
821
822 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
823 }
824
hns_roce_init(struct hns_roce_dev * hr_dev)825 int hns_roce_init(struct hns_roce_dev *hr_dev)
826 {
827 struct device *dev = hr_dev->dev;
828 int ret;
829
830 if (hr_dev->hw->reset) {
831 ret = hr_dev->hw->reset(hr_dev, true);
832 if (ret) {
833 dev_err(dev, "Reset RoCE engine failed!\n");
834 return ret;
835 }
836 }
837 hr_dev->is_reset = false;
838
839 if (hr_dev->hw->cmq_init) {
840 ret = hr_dev->hw->cmq_init(hr_dev);
841 if (ret) {
842 dev_err(dev, "Init RoCE Command Queue failed!\n");
843 goto error_failed_cmq_init;
844 }
845 }
846
847 ret = hr_dev->hw->hw_profile(hr_dev);
848 if (ret) {
849 dev_err(dev, "Get RoCE engine profile failed!\n");
850 goto error_failed_cmd_init;
851 }
852
853 ret = hns_roce_cmd_init(hr_dev);
854 if (ret) {
855 dev_err(dev, "cmd init failed!\n");
856 goto error_failed_cmd_init;
857 }
858
859 /* EQ depends on poll mode, event mode depends on EQ */
860 ret = hr_dev->hw->init_eq(hr_dev);
861 if (ret) {
862 dev_err(dev, "eq init failed!\n");
863 goto error_failed_eq_table;
864 }
865
866 if (hr_dev->cmd_mod) {
867 ret = hns_roce_cmd_use_events(hr_dev);
868 if (ret)
869 dev_warn(dev,
870 "Cmd event mode failed, set back to poll!\n");
871 }
872
873 ret = hns_roce_init_hem(hr_dev);
874 if (ret) {
875 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
876 goto error_failed_init_hem;
877 }
878
879 ret = hns_roce_setup_hca(hr_dev);
880 if (ret) {
881 dev_err(dev, "setup hca failed!\n");
882 goto error_failed_setup_hca;
883 }
884
885 if (hr_dev->hw->hw_init) {
886 ret = hr_dev->hw->hw_init(hr_dev);
887 if (ret) {
888 dev_err(dev, "hw_init failed!\n");
889 goto error_failed_engine_init;
890 }
891 }
892
893 INIT_LIST_HEAD(&hr_dev->qp_list);
894 spin_lock_init(&hr_dev->qp_list_lock);
895 INIT_LIST_HEAD(&hr_dev->dip_list);
896 spin_lock_init(&hr_dev->dip_list_lock);
897
898 ret = hns_roce_register_device(hr_dev);
899 if (ret)
900 goto error_failed_register_device;
901
902 return 0;
903
904 error_failed_register_device:
905 if (hr_dev->hw->hw_exit)
906 hr_dev->hw->hw_exit(hr_dev);
907
908 error_failed_engine_init:
909 hns_roce_cleanup_bitmap(hr_dev);
910
911 error_failed_setup_hca:
912 hns_roce_cleanup_hem(hr_dev);
913
914 error_failed_init_hem:
915 if (hr_dev->cmd_mod)
916 hns_roce_cmd_use_polling(hr_dev);
917 hr_dev->hw->cleanup_eq(hr_dev);
918
919 error_failed_eq_table:
920 hns_roce_cmd_cleanup(hr_dev);
921
922 error_failed_cmd_init:
923 if (hr_dev->hw->cmq_exit)
924 hr_dev->hw->cmq_exit(hr_dev);
925
926 error_failed_cmq_init:
927 if (hr_dev->hw->reset) {
928 if (hr_dev->hw->reset(hr_dev, false))
929 dev_err(dev, "Dereset RoCE engine failed!\n");
930 }
931
932 return ret;
933 }
934
hns_roce_exit(struct hns_roce_dev * hr_dev)935 void hns_roce_exit(struct hns_roce_dev *hr_dev)
936 {
937 hns_roce_unregister_device(hr_dev);
938
939 if (hr_dev->hw->hw_exit)
940 hr_dev->hw->hw_exit(hr_dev);
941 hns_roce_cleanup_bitmap(hr_dev);
942 hns_roce_cleanup_hem(hr_dev);
943
944 if (hr_dev->cmd_mod)
945 hns_roce_cmd_use_polling(hr_dev);
946
947 hr_dev->hw->cleanup_eq(hr_dev);
948 hns_roce_cmd_cleanup(hr_dev);
949 if (hr_dev->hw->cmq_exit)
950 hr_dev->hw->cmq_exit(hr_dev);
951 if (hr_dev->hw->reset)
952 hr_dev->hw->reset(hr_dev, false);
953 }
954
955 MODULE_LICENSE("Dual BSD/GPL");
956 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
957 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
958 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
959 MODULE_DESCRIPTION("HNS RoCE Driver");
960