1 /* QLogic qedr NIC Driver
2 * Copyright (c) 2015-2016 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <linux/module.h>
33 #include <rdma/ib_verbs.h>
34 #include <rdma/ib_addr.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/iw_cm.h>
37 #include <rdma/ib_mad.h>
38 #include <linux/netdevice.h>
39 #include <linux/iommu.h>
40 #include <linux/pci.h>
41 #include <net/addrconf.h>
42
43 #include <linux/qed/qed_chain.h>
44 #include <linux/qed/qed_if.h>
45 #include "qedr.h"
46 #include "verbs.h"
47 #include <rdma/qedr-abi.h>
48 #include "qedr_iw_cm.h"
49
50 MODULE_DESCRIPTION("QLogic 40G/100G ROCE Driver");
51 MODULE_AUTHOR("QLogic Corporation");
52 MODULE_LICENSE("Dual BSD/GPL");
53
54 #define QEDR_WQ_MULTIPLIER_DFT (3)
55
qedr_ib_dispatch_event(struct qedr_dev * dev,u32 port_num,enum ib_event_type type)56 static void qedr_ib_dispatch_event(struct qedr_dev *dev, u32 port_num,
57 enum ib_event_type type)
58 {
59 struct ib_event ibev;
60
61 ibev.device = &dev->ibdev;
62 ibev.element.port_num = port_num;
63 ibev.event = type;
64
65 ib_dispatch_event(&ibev);
66 }
67
qedr_link_layer(struct ib_device * device,u32 port_num)68 static enum rdma_link_layer qedr_link_layer(struct ib_device *device,
69 u32 port_num)
70 {
71 return IB_LINK_LAYER_ETHERNET;
72 }
73
qedr_get_dev_fw_str(struct ib_device * ibdev,char * str)74 static void qedr_get_dev_fw_str(struct ib_device *ibdev, char *str)
75 {
76 struct qedr_dev *qedr = get_qedr_dev(ibdev);
77 u32 fw_ver = (u32)qedr->attr.fw_ver;
78
79 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
80 (fw_ver >> 24) & 0xFF, (fw_ver >> 16) & 0xFF,
81 (fw_ver >> 8) & 0xFF, fw_ver & 0xFF);
82 }
83
qedr_roce_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)84 static int qedr_roce_port_immutable(struct ib_device *ibdev, u32 port_num,
85 struct ib_port_immutable *immutable)
86 {
87 struct ib_port_attr attr;
88 int err;
89
90 err = qedr_query_port(ibdev, port_num, &attr);
91 if (err)
92 return err;
93
94 immutable->pkey_tbl_len = attr.pkey_tbl_len;
95 immutable->gid_tbl_len = attr.gid_tbl_len;
96 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
97 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
98 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
99
100 return 0;
101 }
102
qedr_iw_port_immutable(struct ib_device * ibdev,u32 port_num,struct ib_port_immutable * immutable)103 static int qedr_iw_port_immutable(struct ib_device *ibdev, u32 port_num,
104 struct ib_port_immutable *immutable)
105 {
106 struct ib_port_attr attr;
107 int err;
108
109 err = qedr_query_port(ibdev, port_num, &attr);
110 if (err)
111 return err;
112
113 immutable->gid_tbl_len = 1;
114 immutable->core_cap_flags = RDMA_CORE_PORT_IWARP;
115 immutable->max_mad_size = 0;
116
117 return 0;
118 }
119
120 /* QEDR sysfs interface */
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)121 static ssize_t hw_rev_show(struct device *device, struct device_attribute *attr,
122 char *buf)
123 {
124 struct qedr_dev *dev =
125 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
126
127 return sysfs_emit(buf, "0x%x\n", dev->attr.hw_ver);
128 }
129 static DEVICE_ATTR_RO(hw_rev);
130
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)131 static ssize_t hca_type_show(struct device *device,
132 struct device_attribute *attr, char *buf)
133 {
134 struct qedr_dev *dev =
135 rdma_device_to_drv_device(device, struct qedr_dev, ibdev);
136
137 return sysfs_emit(buf, "FastLinQ QL%x %s\n", dev->pdev->device,
138 rdma_protocol_iwarp(&dev->ibdev, 1) ? "iWARP" :
139 "RoCE");
140 }
141 static DEVICE_ATTR_RO(hca_type);
142
143 static struct attribute *qedr_attributes[] = {
144 &dev_attr_hw_rev.attr,
145 &dev_attr_hca_type.attr,
146 NULL
147 };
148
149 static const struct attribute_group qedr_attr_group = {
150 .attrs = qedr_attributes,
151 };
152
153 static const struct ib_device_ops qedr_iw_dev_ops = {
154 .get_port_immutable = qedr_iw_port_immutable,
155 .iw_accept = qedr_iw_accept,
156 .iw_add_ref = qedr_iw_qp_add_ref,
157 .iw_connect = qedr_iw_connect,
158 .iw_create_listen = qedr_iw_create_listen,
159 .iw_destroy_listen = qedr_iw_destroy_listen,
160 .iw_get_qp = qedr_iw_get_qp,
161 .iw_reject = qedr_iw_reject,
162 .iw_rem_ref = qedr_iw_qp_rem_ref,
163 .query_gid = qedr_iw_query_gid,
164 };
165
qedr_iw_register_device(struct qedr_dev * dev)166 static int qedr_iw_register_device(struct qedr_dev *dev)
167 {
168 dev->ibdev.node_type = RDMA_NODE_RNIC;
169
170 ib_set_device_ops(&dev->ibdev, &qedr_iw_dev_ops);
171
172 memcpy(dev->ibdev.iw_ifname,
173 dev->ndev->name, sizeof(dev->ibdev.iw_ifname));
174
175 return 0;
176 }
177
178 static const struct ib_device_ops qedr_roce_dev_ops = {
179 .alloc_xrcd = qedr_alloc_xrcd,
180 .dealloc_xrcd = qedr_dealloc_xrcd,
181 .get_port_immutable = qedr_roce_port_immutable,
182 .query_pkey = qedr_query_pkey,
183 };
184
qedr_roce_register_device(struct qedr_dev * dev)185 static void qedr_roce_register_device(struct qedr_dev *dev)
186 {
187 dev->ibdev.node_type = RDMA_NODE_IB_CA;
188
189 ib_set_device_ops(&dev->ibdev, &qedr_roce_dev_ops);
190 }
191
192 static const struct ib_device_ops qedr_dev_ops = {
193 .owner = THIS_MODULE,
194 .driver_id = RDMA_DRIVER_QEDR,
195 .uverbs_abi_ver = QEDR_ABI_VERSION,
196
197 .alloc_mr = qedr_alloc_mr,
198 .alloc_pd = qedr_alloc_pd,
199 .alloc_ucontext = qedr_alloc_ucontext,
200 .create_ah = qedr_create_ah,
201 .create_cq = qedr_create_cq,
202 .create_qp = qedr_create_qp,
203 .create_srq = qedr_create_srq,
204 .dealloc_pd = qedr_dealloc_pd,
205 .dealloc_ucontext = qedr_dealloc_ucontext,
206 .dereg_mr = qedr_dereg_mr,
207 .destroy_ah = qedr_destroy_ah,
208 .destroy_cq = qedr_destroy_cq,
209 .destroy_qp = qedr_destroy_qp,
210 .destroy_srq = qedr_destroy_srq,
211 .device_group = &qedr_attr_group,
212 .get_dev_fw_str = qedr_get_dev_fw_str,
213 .get_dma_mr = qedr_get_dma_mr,
214 .get_link_layer = qedr_link_layer,
215 .map_mr_sg = qedr_map_mr_sg,
216 .mmap = qedr_mmap,
217 .mmap_free = qedr_mmap_free,
218 .modify_qp = qedr_modify_qp,
219 .modify_srq = qedr_modify_srq,
220 .poll_cq = qedr_poll_cq,
221 .post_recv = qedr_post_recv,
222 .post_send = qedr_post_send,
223 .post_srq_recv = qedr_post_srq_recv,
224 .process_mad = qedr_process_mad,
225 .query_device = qedr_query_device,
226 .query_port = qedr_query_port,
227 .query_qp = qedr_query_qp,
228 .query_srq = qedr_query_srq,
229 .reg_user_mr = qedr_reg_user_mr,
230 .req_notify_cq = qedr_arm_cq,
231 .resize_cq = qedr_resize_cq,
232
233 INIT_RDMA_OBJ_SIZE(ib_ah, qedr_ah, ibah),
234 INIT_RDMA_OBJ_SIZE(ib_cq, qedr_cq, ibcq),
235 INIT_RDMA_OBJ_SIZE(ib_pd, qedr_pd, ibpd),
236 INIT_RDMA_OBJ_SIZE(ib_qp, qedr_qp, ibqp),
237 INIT_RDMA_OBJ_SIZE(ib_srq, qedr_srq, ibsrq),
238 INIT_RDMA_OBJ_SIZE(ib_xrcd, qedr_xrcd, ibxrcd),
239 INIT_RDMA_OBJ_SIZE(ib_ucontext, qedr_ucontext, ibucontext),
240 };
241
qedr_register_device(struct qedr_dev * dev)242 static int qedr_register_device(struct qedr_dev *dev)
243 {
244 int rc;
245
246 dev->ibdev.node_guid = dev->attr.node_guid;
247 memcpy(dev->ibdev.node_desc, QEDR_NODE_DESC, sizeof(QEDR_NODE_DESC));
248
249 if (IS_IWARP(dev)) {
250 rc = qedr_iw_register_device(dev);
251 if (rc)
252 return rc;
253 } else {
254 qedr_roce_register_device(dev);
255 }
256
257 dev->ibdev.phys_port_cnt = 1;
258 dev->ibdev.num_comp_vectors = dev->num_cnq;
259 dev->ibdev.dev.parent = &dev->pdev->dev;
260
261 ib_set_device_ops(&dev->ibdev, &qedr_dev_ops);
262
263 rc = ib_device_set_netdev(&dev->ibdev, dev->ndev, 1);
264 if (rc)
265 return rc;
266
267 dma_set_max_seg_size(&dev->pdev->dev, UINT_MAX);
268 return ib_register_device(&dev->ibdev, "qedr%d", &dev->pdev->dev);
269 }
270
271 /* This function allocates fast-path status block memory */
qedr_alloc_mem_sb(struct qedr_dev * dev,struct qed_sb_info * sb_info,u16 sb_id)272 static int qedr_alloc_mem_sb(struct qedr_dev *dev,
273 struct qed_sb_info *sb_info, u16 sb_id)
274 {
275 struct status_block_e4 *sb_virt;
276 dma_addr_t sb_phys;
277 int rc;
278
279 sb_virt = dma_alloc_coherent(&dev->pdev->dev,
280 sizeof(*sb_virt), &sb_phys, GFP_KERNEL);
281 if (!sb_virt)
282 return -ENOMEM;
283
284 rc = dev->ops->common->sb_init(dev->cdev, sb_info,
285 sb_virt, sb_phys, sb_id,
286 QED_SB_TYPE_CNQ);
287 if (rc) {
288 pr_err("Status block initialization failed\n");
289 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_virt),
290 sb_virt, sb_phys);
291 return rc;
292 }
293
294 return 0;
295 }
296
qedr_free_mem_sb(struct qedr_dev * dev,struct qed_sb_info * sb_info,int sb_id)297 static void qedr_free_mem_sb(struct qedr_dev *dev,
298 struct qed_sb_info *sb_info, int sb_id)
299 {
300 if (sb_info->sb_virt) {
301 dev->ops->common->sb_release(dev->cdev, sb_info, sb_id,
302 QED_SB_TYPE_CNQ);
303 dma_free_coherent(&dev->pdev->dev, sizeof(*sb_info->sb_virt),
304 (void *)sb_info->sb_virt, sb_info->sb_phys);
305 }
306 }
307
qedr_free_resources(struct qedr_dev * dev)308 static void qedr_free_resources(struct qedr_dev *dev)
309 {
310 int i;
311
312 if (IS_IWARP(dev))
313 destroy_workqueue(dev->iwarp_wq);
314
315 for (i = 0; i < dev->num_cnq; i++) {
316 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
317 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
318 }
319
320 kfree(dev->cnq_array);
321 kfree(dev->sb_array);
322 kfree(dev->sgid_tbl);
323 }
324
qedr_alloc_resources(struct qedr_dev * dev)325 static int qedr_alloc_resources(struct qedr_dev *dev)
326 {
327 struct qed_chain_init_params params = {
328 .mode = QED_CHAIN_MODE_PBL,
329 .intended_use = QED_CHAIN_USE_TO_CONSUME,
330 .cnt_type = QED_CHAIN_CNT_TYPE_U16,
331 .elem_size = sizeof(struct regpair *),
332 };
333 struct qedr_cnq *cnq;
334 __le16 *cons_pi;
335 int i, rc;
336
337 dev->sgid_tbl = kcalloc(QEDR_MAX_SGID, sizeof(union ib_gid),
338 GFP_KERNEL);
339 if (!dev->sgid_tbl)
340 return -ENOMEM;
341
342 spin_lock_init(&dev->sgid_lock);
343 xa_init_flags(&dev->srqs, XA_FLAGS_LOCK_IRQ);
344
345 if (IS_IWARP(dev)) {
346 xa_init(&dev->qps);
347 dev->iwarp_wq = create_singlethread_workqueue("qedr_iwarpq");
348 if (!dev->iwarp_wq) {
349 rc = -ENOMEM;
350 goto err1;
351 }
352 }
353
354 /* Allocate Status blocks for CNQ */
355 dev->sb_array = kcalloc(dev->num_cnq, sizeof(*dev->sb_array),
356 GFP_KERNEL);
357 if (!dev->sb_array) {
358 rc = -ENOMEM;
359 goto err_destroy_wq;
360 }
361
362 dev->cnq_array = kcalloc(dev->num_cnq,
363 sizeof(*dev->cnq_array), GFP_KERNEL);
364 if (!dev->cnq_array) {
365 rc = -ENOMEM;
366 goto err2;
367 }
368
369 dev->sb_start = dev->ops->rdma_get_start_sb(dev->cdev);
370
371 /* Allocate CNQ PBLs */
372 params.num_elems = min_t(u32, QED_RDMA_MAX_CNQ_SIZE,
373 QEDR_ROCE_MAX_CNQ_SIZE);
374
375 for (i = 0; i < dev->num_cnq; i++) {
376 cnq = &dev->cnq_array[i];
377
378 rc = qedr_alloc_mem_sb(dev, &dev->sb_array[i],
379 dev->sb_start + i);
380 if (rc)
381 goto err3;
382
383 rc = dev->ops->common->chain_alloc(dev->cdev, &cnq->pbl,
384 ¶ms);
385 if (rc)
386 goto err4;
387
388 cnq->dev = dev;
389 cnq->sb = &dev->sb_array[i];
390 cons_pi = dev->sb_array[i].sb_virt->pi_array;
391 cnq->hw_cons_ptr = &cons_pi[QED_ROCE_PROTOCOL_INDEX];
392 cnq->index = i;
393 sprintf(cnq->name, "qedr%d@pci:%s", i, pci_name(dev->pdev));
394
395 DP_DEBUG(dev, QEDR_MSG_INIT, "cnq[%d].cons=%d\n",
396 i, qed_chain_get_cons_idx(&cnq->pbl));
397 }
398
399 return 0;
400 err4:
401 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
402 err3:
403 for (--i; i >= 0; i--) {
404 dev->ops->common->chain_free(dev->cdev, &dev->cnq_array[i].pbl);
405 qedr_free_mem_sb(dev, &dev->sb_array[i], dev->sb_start + i);
406 }
407 kfree(dev->cnq_array);
408 err2:
409 kfree(dev->sb_array);
410 err_destroy_wq:
411 if (IS_IWARP(dev))
412 destroy_workqueue(dev->iwarp_wq);
413 err1:
414 kfree(dev->sgid_tbl);
415 return rc;
416 }
417
qedr_pci_set_atomic(struct qedr_dev * dev,struct pci_dev * pdev)418 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
419 {
420 int rc = pci_enable_atomic_ops_to_root(pdev,
421 PCI_EXP_DEVCAP2_ATOMIC_COMP64);
422
423 if (rc) {
424 dev->atomic_cap = IB_ATOMIC_NONE;
425 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
426 } else {
427 dev->atomic_cap = IB_ATOMIC_GLOB;
428 DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
429 }
430 }
431
432 static const struct qed_rdma_ops *qed_ops;
433
434 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
435
qedr_irq_handler(int irq,void * handle)436 static irqreturn_t qedr_irq_handler(int irq, void *handle)
437 {
438 u16 hw_comp_cons, sw_comp_cons;
439 struct qedr_cnq *cnq = handle;
440 struct regpair *cq_handle;
441 struct qedr_cq *cq;
442
443 qed_sb_ack(cnq->sb, IGU_INT_DISABLE, 0);
444
445 qed_sb_update_sb_idx(cnq->sb);
446
447 hw_comp_cons = le16_to_cpu(*cnq->hw_cons_ptr);
448 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
449
450 /* Align protocol-index and chain reads */
451 rmb();
452
453 while (sw_comp_cons != hw_comp_cons) {
454 cq_handle = (struct regpair *)qed_chain_consume(&cnq->pbl);
455 cq = (struct qedr_cq *)(uintptr_t)HILO_U64(cq_handle->hi,
456 cq_handle->lo);
457
458 if (cq == NULL) {
459 DP_ERR(cnq->dev,
460 "Received NULL CQ cq_handle->hi=%d cq_handle->lo=%d sw_comp_cons=%d hw_comp_cons=%d\n",
461 cq_handle->hi, cq_handle->lo, sw_comp_cons,
462 hw_comp_cons);
463
464 break;
465 }
466
467 if (cq->sig != QEDR_CQ_MAGIC_NUMBER) {
468 DP_ERR(cnq->dev,
469 "Problem with cq signature, cq_handle->hi=%d ch_handle->lo=%d cq=%p\n",
470 cq_handle->hi, cq_handle->lo, cq);
471 break;
472 }
473
474 cq->arm_flags = 0;
475
476 if (!cq->destroyed && cq->ibcq.comp_handler)
477 (*cq->ibcq.comp_handler)
478 (&cq->ibcq, cq->ibcq.cq_context);
479
480 /* The CQ's CNQ notification counter is checked before
481 * destroying the CQ in a busy-wait loop that waits for all of
482 * the CQ's CNQ interrupts to be processed. It is increased
483 * here, only after the completion handler, to ensure that the
484 * the handler is not running when the CQ is destroyed.
485 */
486 cq->cnq_notif++;
487
488 sw_comp_cons = qed_chain_get_cons_idx(&cnq->pbl);
489
490 cnq->n_comp++;
491 }
492
493 qed_ops->rdma_cnq_prod_update(cnq->dev->rdma_ctx, cnq->index,
494 sw_comp_cons);
495
496 qed_sb_ack(cnq->sb, IGU_INT_ENABLE, 1);
497
498 return IRQ_HANDLED;
499 }
500
qedr_sync_free_irqs(struct qedr_dev * dev)501 static void qedr_sync_free_irqs(struct qedr_dev *dev)
502 {
503 u32 vector;
504 u16 idx;
505 int i;
506
507 for (i = 0; i < dev->int_info.used_cnt; i++) {
508 if (dev->int_info.msix_cnt) {
509 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
510 vector = dev->int_info.msix[idx].vector;
511 synchronize_irq(vector);
512 free_irq(vector, &dev->cnq_array[i]);
513 }
514 }
515
516 dev->int_info.used_cnt = 0;
517 }
518
qedr_req_msix_irqs(struct qedr_dev * dev)519 static int qedr_req_msix_irqs(struct qedr_dev *dev)
520 {
521 int i, rc = 0;
522 u16 idx;
523
524 if (dev->num_cnq > dev->int_info.msix_cnt) {
525 DP_ERR(dev,
526 "Interrupt mismatch: %d CNQ queues > %d MSI-x vectors\n",
527 dev->num_cnq, dev->int_info.msix_cnt);
528 return -EINVAL;
529 }
530
531 for (i = 0; i < dev->num_cnq; i++) {
532 idx = i * dev->num_hwfns + dev->affin_hwfn_idx;
533 rc = request_irq(dev->int_info.msix[idx].vector,
534 qedr_irq_handler, 0, dev->cnq_array[i].name,
535 &dev->cnq_array[i]);
536 if (rc) {
537 DP_ERR(dev, "Request cnq %d irq failed\n", i);
538 qedr_sync_free_irqs(dev);
539 } else {
540 DP_DEBUG(dev, QEDR_MSG_INIT,
541 "Requested cnq irq for %s [entry %d]. Cookie is at %p\n",
542 dev->cnq_array[i].name, i,
543 &dev->cnq_array[i]);
544 dev->int_info.used_cnt++;
545 }
546 }
547
548 return rc;
549 }
550
qedr_setup_irqs(struct qedr_dev * dev)551 static int qedr_setup_irqs(struct qedr_dev *dev)
552 {
553 int rc;
554
555 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs\n");
556
557 /* Learn Interrupt configuration */
558 rc = dev->ops->rdma_set_rdma_int(dev->cdev, dev->num_cnq);
559 if (rc < 0)
560 return rc;
561
562 rc = dev->ops->rdma_get_rdma_int(dev->cdev, &dev->int_info);
563 if (rc) {
564 DP_DEBUG(dev, QEDR_MSG_INIT, "get_rdma_int failed\n");
565 return rc;
566 }
567
568 if (dev->int_info.msix_cnt) {
569 DP_DEBUG(dev, QEDR_MSG_INIT, "rdma msix_cnt = %d\n",
570 dev->int_info.msix_cnt);
571 rc = qedr_req_msix_irqs(dev);
572 if (rc)
573 return rc;
574 }
575
576 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr_setup_irqs succeeded\n");
577
578 return 0;
579 }
580
qedr_set_device_attr(struct qedr_dev * dev)581 static int qedr_set_device_attr(struct qedr_dev *dev)
582 {
583 struct qed_rdma_device *qed_attr;
584 struct qedr_device_attr *attr;
585 u32 page_size;
586
587 /* Part 1 - query core capabilities */
588 qed_attr = dev->ops->rdma_query_device(dev->rdma_ctx);
589
590 /* Part 2 - check capabilities */
591 page_size = ~qed_attr->page_size_caps + 1;
592 if (page_size > PAGE_SIZE) {
593 DP_ERR(dev,
594 "Kernel PAGE_SIZE is %ld which is smaller than minimum page size (%d) required by qedr\n",
595 PAGE_SIZE, page_size);
596 return -ENODEV;
597 }
598
599 /* Part 3 - copy and update capabilities */
600 attr = &dev->attr;
601 attr->vendor_id = qed_attr->vendor_id;
602 attr->vendor_part_id = qed_attr->vendor_part_id;
603 attr->hw_ver = qed_attr->hw_ver;
604 attr->fw_ver = qed_attr->fw_ver;
605 attr->node_guid = qed_attr->node_guid;
606 attr->sys_image_guid = qed_attr->sys_image_guid;
607 attr->max_cnq = qed_attr->max_cnq;
608 attr->max_sge = qed_attr->max_sge;
609 attr->max_inline = qed_attr->max_inline;
610 attr->max_sqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_SQE);
611 attr->max_rqe = min_t(u32, qed_attr->max_wqe, QEDR_MAX_RQE);
612 attr->max_qp_resp_rd_atomic_resc = qed_attr->max_qp_resp_rd_atomic_resc;
613 attr->max_qp_req_rd_atomic_resc = qed_attr->max_qp_req_rd_atomic_resc;
614 attr->max_dev_resp_rd_atomic_resc =
615 qed_attr->max_dev_resp_rd_atomic_resc;
616 attr->max_cq = qed_attr->max_cq;
617 attr->max_qp = qed_attr->max_qp;
618 attr->max_mr = qed_attr->max_mr;
619 attr->max_mr_size = qed_attr->max_mr_size;
620 attr->max_cqe = min_t(u64, qed_attr->max_cqe, QEDR_MAX_CQES);
621 attr->max_mw = qed_attr->max_mw;
622 attr->max_mr_mw_fmr_pbl = qed_attr->max_mr_mw_fmr_pbl;
623 attr->max_mr_mw_fmr_size = qed_attr->max_mr_mw_fmr_size;
624 attr->max_pd = qed_attr->max_pd;
625 attr->max_ah = qed_attr->max_ah;
626 attr->max_pkey = qed_attr->max_pkey;
627 attr->max_srq = qed_attr->max_srq;
628 attr->max_srq_wr = qed_attr->max_srq_wr;
629 attr->dev_caps = qed_attr->dev_caps;
630 attr->page_size_caps = qed_attr->page_size_caps;
631 attr->dev_ack_delay = qed_attr->dev_ack_delay;
632 attr->reserved_lkey = qed_attr->reserved_lkey;
633 attr->bad_pkey_counter = qed_attr->bad_pkey_counter;
634 attr->max_stats_queues = qed_attr->max_stats_queues;
635
636 return 0;
637 }
638
qedr_unaffiliated_event(void * context,u8 event_code)639 static void qedr_unaffiliated_event(void *context, u8 event_code)
640 {
641 pr_err("unaffiliated event not implemented yet\n");
642 }
643
qedr_affiliated_event(void * context,u8 e_code,void * fw_handle)644 static void qedr_affiliated_event(void *context, u8 e_code, void *fw_handle)
645 {
646 #define EVENT_TYPE_NOT_DEFINED 0
647 #define EVENT_TYPE_CQ 1
648 #define EVENT_TYPE_QP 2
649 #define EVENT_TYPE_SRQ 3
650 struct qedr_dev *dev = (struct qedr_dev *)context;
651 struct regpair *async_handle = (struct regpair *)fw_handle;
652 u64 roce_handle64 = ((u64) async_handle->hi << 32) + async_handle->lo;
653 u8 event_type = EVENT_TYPE_NOT_DEFINED;
654 struct ib_event event;
655 struct ib_srq *ibsrq;
656 struct qedr_srq *srq;
657 unsigned long flags;
658 struct ib_cq *ibcq;
659 struct ib_qp *ibqp;
660 struct qedr_cq *cq;
661 struct qedr_qp *qp;
662 u16 srq_id;
663
664 if (IS_ROCE(dev)) {
665 switch (e_code) {
666 case ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR:
667 event.event = IB_EVENT_CQ_ERR;
668 event_type = EVENT_TYPE_CQ;
669 break;
670 case ROCE_ASYNC_EVENT_SQ_DRAINED:
671 event.event = IB_EVENT_SQ_DRAINED;
672 event_type = EVENT_TYPE_QP;
673 break;
674 case ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR:
675 event.event = IB_EVENT_QP_FATAL;
676 event_type = EVENT_TYPE_QP;
677 break;
678 case ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR:
679 event.event = IB_EVENT_QP_REQ_ERR;
680 event_type = EVENT_TYPE_QP;
681 break;
682 case ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR:
683 event.event = IB_EVENT_QP_ACCESS_ERR;
684 event_type = EVENT_TYPE_QP;
685 break;
686 case ROCE_ASYNC_EVENT_SRQ_LIMIT:
687 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
688 event_type = EVENT_TYPE_SRQ;
689 break;
690 case ROCE_ASYNC_EVENT_SRQ_EMPTY:
691 event.event = IB_EVENT_SRQ_ERR;
692 event_type = EVENT_TYPE_SRQ;
693 break;
694 case ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR:
695 event.event = IB_EVENT_QP_ACCESS_ERR;
696 event_type = EVENT_TYPE_QP;
697 break;
698 case ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR:
699 event.event = IB_EVENT_QP_ACCESS_ERR;
700 event_type = EVENT_TYPE_QP;
701 break;
702 case ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR:
703 event.event = IB_EVENT_CQ_ERR;
704 event_type = EVENT_TYPE_CQ;
705 break;
706 default:
707 DP_ERR(dev, "unsupported event %d on handle=%llx\n",
708 e_code, roce_handle64);
709 }
710 } else {
711 switch (e_code) {
712 case QED_IWARP_EVENT_SRQ_LIMIT:
713 event.event = IB_EVENT_SRQ_LIMIT_REACHED;
714 event_type = EVENT_TYPE_SRQ;
715 break;
716 case QED_IWARP_EVENT_SRQ_EMPTY:
717 event.event = IB_EVENT_SRQ_ERR;
718 event_type = EVENT_TYPE_SRQ;
719 break;
720 default:
721 DP_ERR(dev, "unsupported event %d on handle=%llx\n", e_code,
722 roce_handle64);
723 }
724 }
725 switch (event_type) {
726 case EVENT_TYPE_CQ:
727 cq = (struct qedr_cq *)(uintptr_t)roce_handle64;
728 if (cq) {
729 ibcq = &cq->ibcq;
730 if (ibcq->event_handler) {
731 event.device = ibcq->device;
732 event.element.cq = ibcq;
733 ibcq->event_handler(&event, ibcq->cq_context);
734 }
735 } else {
736 WARN(1,
737 "Error: CQ event with NULL pointer ibcq. Handle=%llx\n",
738 roce_handle64);
739 }
740 DP_ERR(dev, "CQ event %d on handle %p\n", e_code, cq);
741 break;
742 case EVENT_TYPE_QP:
743 qp = (struct qedr_qp *)(uintptr_t)roce_handle64;
744 if (qp) {
745 ibqp = &qp->ibqp;
746 if (ibqp->event_handler) {
747 event.device = ibqp->device;
748 event.element.qp = ibqp;
749 ibqp->event_handler(&event, ibqp->qp_context);
750 }
751 } else {
752 WARN(1,
753 "Error: QP event with NULL pointer ibqp. Handle=%llx\n",
754 roce_handle64);
755 }
756 DP_ERR(dev, "QP event %d on handle %p\n", e_code, qp);
757 break;
758 case EVENT_TYPE_SRQ:
759 srq_id = (u16)roce_handle64;
760 xa_lock_irqsave(&dev->srqs, flags);
761 srq = xa_load(&dev->srqs, srq_id);
762 if (srq) {
763 ibsrq = &srq->ibsrq;
764 if (ibsrq->event_handler) {
765 event.device = ibsrq->device;
766 event.element.srq = ibsrq;
767 ibsrq->event_handler(&event,
768 ibsrq->srq_context);
769 }
770 } else {
771 DP_NOTICE(dev,
772 "SRQ event with NULL pointer ibsrq. Handle=%llx\n",
773 roce_handle64);
774 }
775 xa_unlock_irqrestore(&dev->srqs, flags);
776 DP_NOTICE(dev, "SRQ event %d on handle %p\n", e_code, srq);
777 break;
778 default:
779 break;
780 }
781 }
782
qedr_init_hw(struct qedr_dev * dev)783 static int qedr_init_hw(struct qedr_dev *dev)
784 {
785 struct qed_rdma_add_user_out_params out_params;
786 struct qed_rdma_start_in_params *in_params;
787 struct qed_rdma_cnq_params *cur_pbl;
788 struct qed_rdma_events events;
789 dma_addr_t p_phys_table;
790 u32 page_cnt;
791 int rc = 0;
792 int i;
793
794 in_params = kzalloc(sizeof(*in_params), GFP_KERNEL);
795 if (!in_params) {
796 rc = -ENOMEM;
797 goto out;
798 }
799
800 in_params->desired_cnq = dev->num_cnq;
801 for (i = 0; i < dev->num_cnq; i++) {
802 cur_pbl = &in_params->cnq_pbl_list[i];
803
804 page_cnt = qed_chain_get_page_cnt(&dev->cnq_array[i].pbl);
805 cur_pbl->num_pbl_pages = page_cnt;
806
807 p_phys_table = qed_chain_get_pbl_phys(&dev->cnq_array[i].pbl);
808 cur_pbl->pbl_ptr = (u64)p_phys_table;
809 }
810
811 events.affiliated_event = qedr_affiliated_event;
812 events.unaffiliated_event = qedr_unaffiliated_event;
813 events.context = dev;
814
815 in_params->events = &events;
816 in_params->cq_mode = QED_RDMA_CQ_MODE_32_BITS;
817 in_params->max_mtu = dev->ndev->mtu;
818 dev->iwarp_max_mtu = dev->ndev->mtu;
819 ether_addr_copy(&in_params->mac_addr[0], dev->ndev->dev_addr);
820
821 rc = dev->ops->rdma_init(dev->cdev, in_params);
822 if (rc)
823 goto out;
824
825 rc = dev->ops->rdma_add_user(dev->rdma_ctx, &out_params);
826 if (rc)
827 goto out;
828
829 dev->db_addr = out_params.dpi_addr;
830 dev->db_phys_addr = out_params.dpi_phys_addr;
831 dev->db_size = out_params.dpi_size;
832 dev->dpi = out_params.dpi;
833
834 rc = qedr_set_device_attr(dev);
835 out:
836 kfree(in_params);
837 if (rc)
838 DP_ERR(dev, "Init HW Failed rc = %d\n", rc);
839
840 return rc;
841 }
842
qedr_stop_hw(struct qedr_dev * dev)843 static void qedr_stop_hw(struct qedr_dev *dev)
844 {
845 dev->ops->rdma_remove_user(dev->rdma_ctx, dev->dpi);
846 dev->ops->rdma_stop(dev->rdma_ctx);
847 }
848
qedr_add(struct qed_dev * cdev,struct pci_dev * pdev,struct net_device * ndev)849 static struct qedr_dev *qedr_add(struct qed_dev *cdev, struct pci_dev *pdev,
850 struct net_device *ndev)
851 {
852 struct qed_dev_rdma_info dev_info;
853 struct qedr_dev *dev;
854 int rc = 0;
855
856 dev = ib_alloc_device(qedr_dev, ibdev);
857 if (!dev) {
858 pr_err("Unable to allocate ib device\n");
859 return NULL;
860 }
861
862 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr add device called\n");
863
864 dev->pdev = pdev;
865 dev->ndev = ndev;
866 dev->cdev = cdev;
867
868 qed_ops = qed_get_rdma_ops();
869 if (!qed_ops) {
870 DP_ERR(dev, "Failed to get qed roce operations\n");
871 goto init_err;
872 }
873
874 dev->ops = qed_ops;
875 rc = qed_ops->fill_dev_info(cdev, &dev_info);
876 if (rc)
877 goto init_err;
878
879 dev->user_dpm_enabled = dev_info.user_dpm_enabled;
880 dev->rdma_type = dev_info.rdma_type;
881 dev->num_hwfns = dev_info.common.num_hwfns;
882
883 if (IS_IWARP(dev) && QEDR_IS_CMT(dev)) {
884 rc = dev->ops->iwarp_set_engine_affin(cdev, false);
885 if (rc) {
886 DP_ERR(dev, "iWARP is disabled over a 100g device Enabling it may impact L2 performance. To enable it run devlink dev param set <dev> name iwarp_cmt value true cmode runtime\n");
887 goto init_err;
888 }
889 }
890 dev->affin_hwfn_idx = dev->ops->common->get_affin_hwfn_idx(cdev);
891
892 dev->rdma_ctx = dev->ops->rdma_get_rdma_ctx(cdev);
893
894 dev->num_cnq = dev->ops->rdma_get_min_cnq_msix(cdev);
895 if (!dev->num_cnq) {
896 DP_ERR(dev, "Failed. At least one CNQ is required.\n");
897 rc = -ENOMEM;
898 goto init_err;
899 }
900
901 dev->wq_multiplier = QEDR_WQ_MULTIPLIER_DFT;
902
903 qedr_pci_set_atomic(dev, pdev);
904
905 rc = qedr_alloc_resources(dev);
906 if (rc)
907 goto init_err;
908
909 rc = qedr_init_hw(dev);
910 if (rc)
911 goto alloc_err;
912
913 rc = qedr_setup_irqs(dev);
914 if (rc)
915 goto irq_err;
916
917 rc = qedr_register_device(dev);
918 if (rc) {
919 DP_ERR(dev, "Unable to allocate register device\n");
920 goto reg_err;
921 }
922
923 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
924 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
925
926 DP_DEBUG(dev, QEDR_MSG_INIT, "qedr driver loaded successfully\n");
927 return dev;
928
929 reg_err:
930 qedr_sync_free_irqs(dev);
931 irq_err:
932 qedr_stop_hw(dev);
933 alloc_err:
934 qedr_free_resources(dev);
935 init_err:
936 ib_dealloc_device(&dev->ibdev);
937 DP_ERR(dev, "qedr driver load failed rc=%d\n", rc);
938
939 return NULL;
940 }
941
qedr_remove(struct qedr_dev * dev)942 static void qedr_remove(struct qedr_dev *dev)
943 {
944 /* First unregister with stack to stop all the active traffic
945 * of the registered clients.
946 */
947 ib_unregister_device(&dev->ibdev);
948
949 qedr_stop_hw(dev);
950 qedr_sync_free_irqs(dev);
951 qedr_free_resources(dev);
952
953 if (IS_IWARP(dev) && QEDR_IS_CMT(dev))
954 dev->ops->iwarp_set_engine_affin(dev->cdev, true);
955
956 ib_dealloc_device(&dev->ibdev);
957 }
958
qedr_close(struct qedr_dev * dev)959 static void qedr_close(struct qedr_dev *dev)
960 {
961 if (test_and_clear_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
962 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ERR);
963 }
964
qedr_shutdown(struct qedr_dev * dev)965 static void qedr_shutdown(struct qedr_dev *dev)
966 {
967 qedr_close(dev);
968 qedr_remove(dev);
969 }
970
qedr_open(struct qedr_dev * dev)971 static void qedr_open(struct qedr_dev *dev)
972 {
973 if (!test_and_set_bit(QEDR_ENET_STATE_BIT, &dev->enet_state))
974 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_PORT_ACTIVE);
975 }
976
qedr_mac_address_change(struct qedr_dev * dev)977 static void qedr_mac_address_change(struct qedr_dev *dev)
978 {
979 union ib_gid *sgid = &dev->sgid_tbl[0];
980 u8 guid[8], mac_addr[6];
981 int rc;
982
983 /* Update SGID */
984 ether_addr_copy(&mac_addr[0], dev->ndev->dev_addr);
985 guid[0] = mac_addr[0] ^ 2;
986 guid[1] = mac_addr[1];
987 guid[2] = mac_addr[2];
988 guid[3] = 0xff;
989 guid[4] = 0xfe;
990 guid[5] = mac_addr[3];
991 guid[6] = mac_addr[4];
992 guid[7] = mac_addr[5];
993 sgid->global.subnet_prefix = cpu_to_be64(0xfe80000000000000LL);
994 memcpy(&sgid->raw[8], guid, sizeof(guid));
995
996 /* Update LL2 */
997 rc = dev->ops->ll2_set_mac_filter(dev->cdev,
998 dev->gsi_ll2_mac_address,
999 dev->ndev->dev_addr);
1000
1001 ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
1002
1003 qedr_ib_dispatch_event(dev, QEDR_PORT, IB_EVENT_GID_CHANGE);
1004
1005 if (rc)
1006 DP_ERR(dev, "Error updating mac filter\n");
1007 }
1008
1009 /* event handling via NIC driver ensures that all the NIC specific
1010 * initialization done before RoCE driver notifies
1011 * event to stack.
1012 */
qedr_notify(struct qedr_dev * dev,enum qede_rdma_event event)1013 static void qedr_notify(struct qedr_dev *dev, enum qede_rdma_event event)
1014 {
1015 switch (event) {
1016 case QEDE_UP:
1017 qedr_open(dev);
1018 break;
1019 case QEDE_DOWN:
1020 qedr_close(dev);
1021 break;
1022 case QEDE_CLOSE:
1023 qedr_shutdown(dev);
1024 break;
1025 case QEDE_CHANGE_ADDR:
1026 qedr_mac_address_change(dev);
1027 break;
1028 case QEDE_CHANGE_MTU:
1029 if (rdma_protocol_iwarp(&dev->ibdev, 1))
1030 if (dev->ndev->mtu != dev->iwarp_max_mtu)
1031 DP_NOTICE(dev,
1032 "Mtu was changed from %d to %d. This will not take affect for iWARP until qedr is reloaded\n",
1033 dev->iwarp_max_mtu, dev->ndev->mtu);
1034 break;
1035 default:
1036 pr_err("Event not supported\n");
1037 }
1038 }
1039
1040 static struct qedr_driver qedr_drv = {
1041 .name = "qedr_driver",
1042 .add = qedr_add,
1043 .remove = qedr_remove,
1044 .notify = qedr_notify,
1045 };
1046
qedr_init_module(void)1047 static int __init qedr_init_module(void)
1048 {
1049 return qede_rdma_register_driver(&qedr_drv);
1050 }
1051
qedr_exit_module(void)1052 static void __exit qedr_exit_module(void)
1053 {
1054 qede_rdma_unregister_driver(&qedr_drv);
1055 }
1056
1057 module_init(qedr_init_module);
1058 module_exit(qedr_exit_module);
1059