1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Intel Corporation.
3
4 #include <asm/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/delay.h>
7 #include <linux/i2c.h>
8 #include <linux/module.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/nvmem-provider.h>
11 #include <linux/regmap.h>
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-fwnode.h>
15
16 #define OV2740_LINK_FREQ_360MHZ 360000000ULL
17 #define OV2740_SCLK 72000000LL
18 #define OV2740_MCLK 19200000
19 #define OV2740_DATA_LANES 2
20 #define OV2740_RGB_DEPTH 10
21
22 #define OV2740_REG_CHIP_ID 0x300a
23 #define OV2740_CHIP_ID 0x2740
24
25 #define OV2740_REG_MODE_SELECT 0x0100
26 #define OV2740_MODE_STANDBY 0x00
27 #define OV2740_MODE_STREAMING 0x01
28
29 /* vertical-timings from sensor */
30 #define OV2740_REG_VTS 0x380e
31 #define OV2740_VTS_DEF 0x088a
32 #define OV2740_VTS_MIN 0x0460
33 #define OV2740_VTS_MAX 0x7fff
34
35 /* horizontal-timings from sensor */
36 #define OV2740_REG_HTS 0x380c
37
38 /* Exposure controls from sensor */
39 #define OV2740_REG_EXPOSURE 0x3500
40 #define OV2740_EXPOSURE_MIN 4
41 #define OV2740_EXPOSURE_MAX_MARGIN 8
42 #define OV2740_EXPOSURE_STEP 1
43
44 /* Analog gain controls from sensor */
45 #define OV2740_REG_ANALOG_GAIN 0x3508
46 #define OV2740_ANAL_GAIN_MIN 128
47 #define OV2740_ANAL_GAIN_MAX 1983
48 #define OV2740_ANAL_GAIN_STEP 1
49
50 /* Digital gain controls from sensor */
51 #define OV2740_REG_MWB_R_GAIN 0x500a
52 #define OV2740_REG_MWB_G_GAIN 0x500c
53 #define OV2740_REG_MWB_B_GAIN 0x500e
54 #define OV2740_DGTL_GAIN_MIN 1024
55 #define OV2740_DGTL_GAIN_MAX 4095
56 #define OV2740_DGTL_GAIN_STEP 1
57 #define OV2740_DGTL_GAIN_DEFAULT 1024
58
59 /* Test Pattern Control */
60 #define OV2740_REG_TEST_PATTERN 0x5040
61 #define OV2740_TEST_PATTERN_ENABLE BIT(7)
62 #define OV2740_TEST_PATTERN_BAR_SHIFT 2
63
64 /* Group Access */
65 #define OV2740_REG_GROUP_ACCESS 0x3208
66 #define OV2740_GROUP_HOLD_START 0x0
67 #define OV2740_GROUP_HOLD_END 0x10
68 #define OV2740_GROUP_HOLD_LAUNCH 0xa0
69
70 /* ISP CTRL00 */
71 #define OV2740_REG_ISP_CTRL00 0x5000
72 /* ISP CTRL01 */
73 #define OV2740_REG_ISP_CTRL01 0x5001
74 /* Customer Addresses: 0x7010 - 0x710F */
75 #define CUSTOMER_USE_OTP_SIZE 0x100
76 /* OTP registers from sensor */
77 #define OV2740_REG_OTP_CUSTOMER 0x7010
78
79 struct nvm_data {
80 struct i2c_client *client;
81 struct nvmem_device *nvmem;
82 struct regmap *regmap;
83 char *nvm_buffer;
84 };
85
86 enum {
87 OV2740_LINK_FREQ_360MHZ_INDEX,
88 };
89
90 struct ov2740_reg {
91 u16 address;
92 u8 val;
93 };
94
95 struct ov2740_reg_list {
96 u32 num_of_regs;
97 const struct ov2740_reg *regs;
98 };
99
100 struct ov2740_link_freq_config {
101 const struct ov2740_reg_list reg_list;
102 };
103
104 struct ov2740_mode {
105 /* Frame width in pixels */
106 u32 width;
107
108 /* Frame height in pixels */
109 u32 height;
110
111 /* Horizontal timining size */
112 u32 hts;
113
114 /* Default vertical timining size */
115 u32 vts_def;
116
117 /* Min vertical timining size */
118 u32 vts_min;
119
120 /* Link frequency needed for this resolution */
121 u32 link_freq_index;
122
123 /* Sensor register settings for this resolution */
124 const struct ov2740_reg_list reg_list;
125 };
126
127 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
128 {0x0103, 0x01},
129 {0x0302, 0x4b},
130 {0x030d, 0x4b},
131 {0x030e, 0x02},
132 {0x030a, 0x01},
133 {0x0312, 0x11},
134 };
135
136 static const struct ov2740_reg mode_1932x1092_regs[] = {
137 {0x3000, 0x00},
138 {0x3018, 0x32},
139 {0x3031, 0x0a},
140 {0x3080, 0x08},
141 {0x3083, 0xB4},
142 {0x3103, 0x00},
143 {0x3104, 0x01},
144 {0x3106, 0x01},
145 {0x3500, 0x00},
146 {0x3501, 0x44},
147 {0x3502, 0x40},
148 {0x3503, 0x88},
149 {0x3507, 0x00},
150 {0x3508, 0x00},
151 {0x3509, 0x80},
152 {0x350c, 0x00},
153 {0x350d, 0x80},
154 {0x3510, 0x00},
155 {0x3511, 0x00},
156 {0x3512, 0x20},
157 {0x3632, 0x00},
158 {0x3633, 0x10},
159 {0x3634, 0x10},
160 {0x3635, 0x10},
161 {0x3645, 0x13},
162 {0x3646, 0x81},
163 {0x3636, 0x10},
164 {0x3651, 0x0a},
165 {0x3656, 0x02},
166 {0x3659, 0x04},
167 {0x365a, 0xda},
168 {0x365b, 0xa2},
169 {0x365c, 0x04},
170 {0x365d, 0x1d},
171 {0x365e, 0x1a},
172 {0x3662, 0xd7},
173 {0x3667, 0x78},
174 {0x3669, 0x0a},
175 {0x366a, 0x92},
176 {0x3700, 0x54},
177 {0x3702, 0x10},
178 {0x3706, 0x42},
179 {0x3709, 0x30},
180 {0x370b, 0xc2},
181 {0x3714, 0x63},
182 {0x3715, 0x01},
183 {0x3716, 0x00},
184 {0x371a, 0x3e},
185 {0x3732, 0x0e},
186 {0x3733, 0x10},
187 {0x375f, 0x0e},
188 {0x3768, 0x30},
189 {0x3769, 0x44},
190 {0x376a, 0x22},
191 {0x377b, 0x20},
192 {0x377c, 0x00},
193 {0x377d, 0x0c},
194 {0x3798, 0x00},
195 {0x37a1, 0x55},
196 {0x37a8, 0x6d},
197 {0x37c2, 0x04},
198 {0x37c5, 0x00},
199 {0x37c8, 0x00},
200 {0x3800, 0x00},
201 {0x3801, 0x00},
202 {0x3802, 0x00},
203 {0x3803, 0x00},
204 {0x3804, 0x07},
205 {0x3805, 0x8f},
206 {0x3806, 0x04},
207 {0x3807, 0x47},
208 {0x3808, 0x07},
209 {0x3809, 0x88},
210 {0x380a, 0x04},
211 {0x380b, 0x40},
212 {0x380c, 0x04},
213 {0x380d, 0x38},
214 {0x380e, 0x04},
215 {0x380f, 0x60},
216 {0x3810, 0x00},
217 {0x3811, 0x04},
218 {0x3812, 0x00},
219 {0x3813, 0x04},
220 {0x3814, 0x01},
221 {0x3815, 0x01},
222 {0x3820, 0x80},
223 {0x3821, 0x46},
224 {0x3822, 0x84},
225 {0x3829, 0x00},
226 {0x382a, 0x01},
227 {0x382b, 0x01},
228 {0x3830, 0x04},
229 {0x3836, 0x01},
230 {0x3837, 0x08},
231 {0x3839, 0x01},
232 {0x383a, 0x00},
233 {0x383b, 0x08},
234 {0x383c, 0x00},
235 {0x3f0b, 0x00},
236 {0x4001, 0x20},
237 {0x4009, 0x07},
238 {0x4003, 0x10},
239 {0x4010, 0xe0},
240 {0x4016, 0x00},
241 {0x4017, 0x10},
242 {0x4044, 0x02},
243 {0x4304, 0x08},
244 {0x4307, 0x30},
245 {0x4320, 0x80},
246 {0x4322, 0x00},
247 {0x4323, 0x00},
248 {0x4324, 0x00},
249 {0x4325, 0x00},
250 {0x4326, 0x00},
251 {0x4327, 0x00},
252 {0x4328, 0x00},
253 {0x4329, 0x00},
254 {0x432c, 0x03},
255 {0x432d, 0x81},
256 {0x4501, 0x84},
257 {0x4502, 0x40},
258 {0x4503, 0x18},
259 {0x4504, 0x04},
260 {0x4508, 0x02},
261 {0x4601, 0x10},
262 {0x4800, 0x00},
263 {0x4816, 0x52},
264 {0x4837, 0x16},
265 {0x5000, 0x7f},
266 {0x5001, 0x00},
267 {0x5005, 0x38},
268 {0x501e, 0x0d},
269 {0x5040, 0x00},
270 {0x5901, 0x00},
271 {0x3800, 0x00},
272 {0x3801, 0x00},
273 {0x3802, 0x00},
274 {0x3803, 0x00},
275 {0x3804, 0x07},
276 {0x3805, 0x8f},
277 {0x3806, 0x04},
278 {0x3807, 0x47},
279 {0x3808, 0x07},
280 {0x3809, 0x8c},
281 {0x380a, 0x04},
282 {0x380b, 0x44},
283 {0x3810, 0x00},
284 {0x3811, 0x00},
285 {0x3812, 0x00},
286 {0x3813, 0x01},
287 };
288
289 static const char * const ov2740_test_pattern_menu[] = {
290 "Disabled",
291 "Color Bar",
292 "Top-Bottom Darker Color Bar",
293 "Right-Left Darker Color Bar",
294 "Bottom-Top Darker Color Bar",
295 };
296
297 static const s64 link_freq_menu_items[] = {
298 OV2740_LINK_FREQ_360MHZ,
299 };
300
301 static const struct ov2740_link_freq_config link_freq_configs[] = {
302 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
303 .reg_list = {
304 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
305 .regs = mipi_data_rate_720mbps,
306 }
307 },
308 };
309
310 static const struct ov2740_mode supported_modes[] = {
311 {
312 .width = 1932,
313 .height = 1092,
314 .hts = 1080,
315 .vts_def = OV2740_VTS_DEF,
316 .vts_min = OV2740_VTS_MIN,
317 .reg_list = {
318 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
319 .regs = mode_1932x1092_regs,
320 },
321 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
322 },
323 };
324
325 struct ov2740 {
326 struct v4l2_subdev sd;
327 struct media_pad pad;
328 struct v4l2_ctrl_handler ctrl_handler;
329
330 /* V4L2 Controls */
331 struct v4l2_ctrl *link_freq;
332 struct v4l2_ctrl *pixel_rate;
333 struct v4l2_ctrl *vblank;
334 struct v4l2_ctrl *hblank;
335 struct v4l2_ctrl *exposure;
336
337 /* Current mode */
338 const struct ov2740_mode *cur_mode;
339
340 /* To serialize asynchronus callbacks */
341 struct mutex mutex;
342
343 /* Streaming on/off */
344 bool streaming;
345
346 /* NVM data inforamtion */
347 struct nvm_data *nvm;
348 };
349
to_ov2740(struct v4l2_subdev * subdev)350 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
351 {
352 return container_of(subdev, struct ov2740, sd);
353 }
354
to_pixel_rate(u32 f_index)355 static u64 to_pixel_rate(u32 f_index)
356 {
357 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
358
359 do_div(pixel_rate, OV2740_RGB_DEPTH);
360
361 return pixel_rate;
362 }
363
to_pixels_per_line(u32 hts,u32 f_index)364 static u64 to_pixels_per_line(u32 hts, u32 f_index)
365 {
366 u64 ppl = hts * to_pixel_rate(f_index);
367
368 do_div(ppl, OV2740_SCLK);
369
370 return ppl;
371 }
372
ov2740_read_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 * val)373 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
374 {
375 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
376 struct i2c_msg msgs[2];
377 u8 addr_buf[2];
378 u8 data_buf[4] = {0};
379 int ret = 0;
380
381 if (len > sizeof(data_buf))
382 return -EINVAL;
383
384 put_unaligned_be16(reg, addr_buf);
385 msgs[0].addr = client->addr;
386 msgs[0].flags = 0;
387 msgs[0].len = sizeof(addr_buf);
388 msgs[0].buf = addr_buf;
389 msgs[1].addr = client->addr;
390 msgs[1].flags = I2C_M_RD;
391 msgs[1].len = len;
392 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
393
394 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
395 if (ret != ARRAY_SIZE(msgs))
396 return ret < 0 ? ret : -EIO;
397
398 *val = get_unaligned_be32(data_buf);
399
400 return 0;
401 }
402
ov2740_write_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 val)403 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
404 {
405 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
406 u8 buf[6];
407 int ret = 0;
408
409 if (len > 4)
410 return -EINVAL;
411
412 put_unaligned_be16(reg, buf);
413 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
414
415 ret = i2c_master_send(client, buf, len + 2);
416 if (ret != len + 2)
417 return ret < 0 ? ret : -EIO;
418
419 return 0;
420 }
421
ov2740_write_reg_list(struct ov2740 * ov2740,const struct ov2740_reg_list * r_list)422 static int ov2740_write_reg_list(struct ov2740 *ov2740,
423 const struct ov2740_reg_list *r_list)
424 {
425 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
426 unsigned int i;
427 int ret = 0;
428
429 for (i = 0; i < r_list->num_of_regs; i++) {
430 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
431 r_list->regs[i].val);
432 if (ret) {
433 dev_err_ratelimited(&client->dev,
434 "write reg 0x%4.4x return err = %d",
435 r_list->regs[i].address, ret);
436 return ret;
437 }
438 }
439
440 return 0;
441 }
442
ov2740_update_digital_gain(struct ov2740 * ov2740,u32 d_gain)443 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
444 {
445 int ret = 0;
446
447 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
448 OV2740_GROUP_HOLD_START);
449 if (ret)
450 return ret;
451
452 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
453 if (ret)
454 return ret;
455
456 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
457 if (ret)
458 return ret;
459
460 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
461 if (ret)
462 return ret;
463
464 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
465 OV2740_GROUP_HOLD_END);
466 if (ret)
467 return ret;
468
469 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
470 OV2740_GROUP_HOLD_LAUNCH);
471 return ret;
472 }
473
ov2740_test_pattern(struct ov2740 * ov2740,u32 pattern)474 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
475 {
476 if (pattern)
477 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
478 OV2740_TEST_PATTERN_ENABLE;
479
480 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
481 }
482
ov2740_set_ctrl(struct v4l2_ctrl * ctrl)483 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
484 {
485 struct ov2740 *ov2740 = container_of(ctrl->handler,
486 struct ov2740, ctrl_handler);
487 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
488 s64 exposure_max;
489 int ret = 0;
490
491 /* Propagate change of current control to all related controls */
492 if (ctrl->id == V4L2_CID_VBLANK) {
493 /* Update max exposure while meeting expected vblanking */
494 exposure_max = ov2740->cur_mode->height + ctrl->val -
495 OV2740_EXPOSURE_MAX_MARGIN;
496 __v4l2_ctrl_modify_range(ov2740->exposure,
497 ov2740->exposure->minimum,
498 exposure_max, ov2740->exposure->step,
499 exposure_max);
500 }
501
502 /* V4L2 controls values will be applied only when power is already up */
503 if (!pm_runtime_get_if_in_use(&client->dev))
504 return 0;
505
506 switch (ctrl->id) {
507 case V4L2_CID_ANALOGUE_GAIN:
508 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
509 ctrl->val);
510 break;
511
512 case V4L2_CID_DIGITAL_GAIN:
513 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
514 break;
515
516 case V4L2_CID_EXPOSURE:
517 /* 4 least significant bits of expsoure are fractional part */
518 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
519 ctrl->val << 4);
520 break;
521
522 case V4L2_CID_VBLANK:
523 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
524 ov2740->cur_mode->height + ctrl->val);
525 break;
526
527 case V4L2_CID_TEST_PATTERN:
528 ret = ov2740_test_pattern(ov2740, ctrl->val);
529 break;
530
531 default:
532 ret = -EINVAL;
533 break;
534 }
535
536 pm_runtime_put(&client->dev);
537
538 return ret;
539 }
540
541 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
542 .s_ctrl = ov2740_set_ctrl,
543 };
544
ov2740_init_controls(struct ov2740 * ov2740)545 static int ov2740_init_controls(struct ov2740 *ov2740)
546 {
547 struct v4l2_ctrl_handler *ctrl_hdlr;
548 const struct ov2740_mode *cur_mode;
549 s64 exposure_max, h_blank, pixel_rate;
550 u32 vblank_min, vblank_max, vblank_default;
551 int size;
552 int ret = 0;
553
554 ctrl_hdlr = &ov2740->ctrl_handler;
555 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
556 if (ret)
557 return ret;
558
559 ctrl_hdlr->lock = &ov2740->mutex;
560 cur_mode = ov2740->cur_mode;
561 size = ARRAY_SIZE(link_freq_menu_items);
562
563 ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
564 V4L2_CID_LINK_FREQ,
565 size - 1, 0,
566 link_freq_menu_items);
567 if (ov2740->link_freq)
568 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
569
570 pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
571 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
572 V4L2_CID_PIXEL_RATE, 0,
573 pixel_rate, 1, pixel_rate);
574
575 vblank_min = cur_mode->vts_min - cur_mode->height;
576 vblank_max = OV2740_VTS_MAX - cur_mode->height;
577 vblank_default = cur_mode->vts_def - cur_mode->height;
578 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
579 V4L2_CID_VBLANK, vblank_min,
580 vblank_max, 1, vblank_default);
581
582 h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
583 h_blank -= cur_mode->width;
584 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
585 V4L2_CID_HBLANK, h_blank, h_blank, 1,
586 h_blank);
587 if (ov2740->hblank)
588 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
589
590 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
591 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
592 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
593 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
594 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
595 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
596 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
597 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
598 V4L2_CID_EXPOSURE,
599 OV2740_EXPOSURE_MIN, exposure_max,
600 OV2740_EXPOSURE_STEP,
601 exposure_max);
602 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
603 V4L2_CID_TEST_PATTERN,
604 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
605 0, 0, ov2740_test_pattern_menu);
606 if (ctrl_hdlr->error) {
607 v4l2_ctrl_handler_free(ctrl_hdlr);
608 return ctrl_hdlr->error;
609 }
610
611 ov2740->sd.ctrl_handler = ctrl_hdlr;
612
613 return 0;
614 }
615
ov2740_update_pad_format(const struct ov2740_mode * mode,struct v4l2_mbus_framefmt * fmt)616 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
617 struct v4l2_mbus_framefmt *fmt)
618 {
619 fmt->width = mode->width;
620 fmt->height = mode->height;
621 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
622 fmt->field = V4L2_FIELD_NONE;
623 }
624
ov2740_load_otp_data(struct nvm_data * nvm)625 static int ov2740_load_otp_data(struct nvm_data *nvm)
626 {
627 struct i2c_client *client;
628 struct ov2740 *ov2740;
629 u32 isp_ctrl00 = 0;
630 u32 isp_ctrl01 = 0;
631 int ret;
632
633 if (!nvm)
634 return -EINVAL;
635
636 if (nvm->nvm_buffer)
637 return 0;
638
639 client = nvm->client;
640 ov2740 = to_ov2740(i2c_get_clientdata(client));
641
642 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
643 if (!nvm->nvm_buffer)
644 return -ENOMEM;
645
646 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
647 if (ret) {
648 dev_err(&client->dev, "failed to read ISP CTRL00\n");
649 goto err;
650 }
651
652 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
653 if (ret) {
654 dev_err(&client->dev, "failed to read ISP CTRL01\n");
655 goto err;
656 }
657
658 /* Clear bit 5 of ISP CTRL00 */
659 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
660 isp_ctrl00 & ~BIT(5));
661 if (ret) {
662 dev_err(&client->dev, "failed to set ISP CTRL00\n");
663 goto err;
664 }
665
666 /* Clear bit 7 of ISP CTRL01 */
667 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
668 isp_ctrl01 & ~BIT(7));
669 if (ret) {
670 dev_err(&client->dev, "failed to set ISP CTRL01\n");
671 goto err;
672 }
673
674 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
675 OV2740_MODE_STREAMING);
676 if (ret) {
677 dev_err(&client->dev, "failed to set streaming mode\n");
678 goto err;
679 }
680
681 /*
682 * Users are not allowed to access OTP-related registers and memory
683 * during the 20 ms period after streaming starts (0x100 = 0x01).
684 */
685 msleep(20);
686
687 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
688 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
689 if (ret) {
690 dev_err(&client->dev, "failed to read OTP data, ret %d\n", ret);
691 goto err;
692 }
693
694 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
695 OV2740_MODE_STANDBY);
696 if (ret) {
697 dev_err(&client->dev, "failed to set streaming mode\n");
698 goto err;
699 }
700
701 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
702 if (ret) {
703 dev_err(&client->dev, "failed to set ISP CTRL01\n");
704 goto err;
705 }
706
707 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
708 if (ret) {
709 dev_err(&client->dev, "failed to set ISP CTRL00\n");
710 goto err;
711 }
712
713 return 0;
714 err:
715 kfree(nvm->nvm_buffer);
716 nvm->nvm_buffer = NULL;
717
718 return ret;
719 }
720
ov2740_start_streaming(struct ov2740 * ov2740)721 static int ov2740_start_streaming(struct ov2740 *ov2740)
722 {
723 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
724 struct nvm_data *nvm = ov2740->nvm;
725 const struct ov2740_reg_list *reg_list;
726 int link_freq_index;
727 int ret = 0;
728
729 ov2740_load_otp_data(nvm);
730
731 link_freq_index = ov2740->cur_mode->link_freq_index;
732 reg_list = &link_freq_configs[link_freq_index].reg_list;
733 ret = ov2740_write_reg_list(ov2740, reg_list);
734 if (ret) {
735 dev_err(&client->dev, "failed to set plls");
736 return ret;
737 }
738
739 reg_list = &ov2740->cur_mode->reg_list;
740 ret = ov2740_write_reg_list(ov2740, reg_list);
741 if (ret) {
742 dev_err(&client->dev, "failed to set mode");
743 return ret;
744 }
745
746 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
747 if (ret)
748 return ret;
749
750 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
751 OV2740_MODE_STREAMING);
752 if (ret)
753 dev_err(&client->dev, "failed to start streaming");
754
755 return ret;
756 }
757
ov2740_stop_streaming(struct ov2740 * ov2740)758 static void ov2740_stop_streaming(struct ov2740 *ov2740)
759 {
760 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
761
762 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
763 OV2740_MODE_STANDBY))
764 dev_err(&client->dev, "failed to stop streaming");
765 }
766
ov2740_set_stream(struct v4l2_subdev * sd,int enable)767 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
768 {
769 struct ov2740 *ov2740 = to_ov2740(sd);
770 struct i2c_client *client = v4l2_get_subdevdata(sd);
771 int ret = 0;
772
773 if (ov2740->streaming == enable)
774 return 0;
775
776 mutex_lock(&ov2740->mutex);
777 if (enable) {
778 ret = pm_runtime_resume_and_get(&client->dev);
779 if (ret < 0) {
780 mutex_unlock(&ov2740->mutex);
781 return ret;
782 }
783
784 ret = ov2740_start_streaming(ov2740);
785 if (ret) {
786 enable = 0;
787 ov2740_stop_streaming(ov2740);
788 pm_runtime_put(&client->dev);
789 }
790 } else {
791 ov2740_stop_streaming(ov2740);
792 pm_runtime_put(&client->dev);
793 }
794
795 ov2740->streaming = enable;
796 mutex_unlock(&ov2740->mutex);
797
798 return ret;
799 }
800
ov2740_suspend(struct device * dev)801 static int __maybe_unused ov2740_suspend(struct device *dev)
802 {
803 struct v4l2_subdev *sd = dev_get_drvdata(dev);
804 struct ov2740 *ov2740 = to_ov2740(sd);
805
806 mutex_lock(&ov2740->mutex);
807 if (ov2740->streaming)
808 ov2740_stop_streaming(ov2740);
809
810 mutex_unlock(&ov2740->mutex);
811
812 return 0;
813 }
814
ov2740_resume(struct device * dev)815 static int __maybe_unused ov2740_resume(struct device *dev)
816 {
817 struct v4l2_subdev *sd = dev_get_drvdata(dev);
818 struct ov2740 *ov2740 = to_ov2740(sd);
819 int ret = 0;
820
821 mutex_lock(&ov2740->mutex);
822 if (!ov2740->streaming)
823 goto exit;
824
825 ret = ov2740_start_streaming(ov2740);
826 if (ret) {
827 ov2740->streaming = false;
828 ov2740_stop_streaming(ov2740);
829 }
830
831 exit:
832 mutex_unlock(&ov2740->mutex);
833 return ret;
834 }
835
ov2740_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)836 static int ov2740_set_format(struct v4l2_subdev *sd,
837 struct v4l2_subdev_state *sd_state,
838 struct v4l2_subdev_format *fmt)
839 {
840 struct ov2740 *ov2740 = to_ov2740(sd);
841 const struct ov2740_mode *mode;
842 s32 vblank_def, h_blank;
843
844 mode = v4l2_find_nearest_size(supported_modes,
845 ARRAY_SIZE(supported_modes), width,
846 height, fmt->format.width,
847 fmt->format.height);
848
849 mutex_lock(&ov2740->mutex);
850 ov2740_update_pad_format(mode, &fmt->format);
851 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
852 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
853 } else {
854 ov2740->cur_mode = mode;
855 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
856 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
857 to_pixel_rate(mode->link_freq_index));
858
859 /* Update limits and set FPS to default */
860 vblank_def = mode->vts_def - mode->height;
861 __v4l2_ctrl_modify_range(ov2740->vblank,
862 mode->vts_min - mode->height,
863 OV2740_VTS_MAX - mode->height, 1,
864 vblank_def);
865 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
866 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
867 mode->width;
868 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
869 h_blank);
870 }
871 mutex_unlock(&ov2740->mutex);
872
873 return 0;
874 }
875
ov2740_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)876 static int ov2740_get_format(struct v4l2_subdev *sd,
877 struct v4l2_subdev_state *sd_state,
878 struct v4l2_subdev_format *fmt)
879 {
880 struct ov2740 *ov2740 = to_ov2740(sd);
881
882 mutex_lock(&ov2740->mutex);
883 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
884 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd,
885 sd_state,
886 fmt->pad);
887 else
888 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
889
890 mutex_unlock(&ov2740->mutex);
891
892 return 0;
893 }
894
ov2740_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)895 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
896 struct v4l2_subdev_state *sd_state,
897 struct v4l2_subdev_mbus_code_enum *code)
898 {
899 if (code->index > 0)
900 return -EINVAL;
901
902 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
903
904 return 0;
905 }
906
ov2740_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)907 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
908 struct v4l2_subdev_state *sd_state,
909 struct v4l2_subdev_frame_size_enum *fse)
910 {
911 if (fse->index >= ARRAY_SIZE(supported_modes))
912 return -EINVAL;
913
914 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
915 return -EINVAL;
916
917 fse->min_width = supported_modes[fse->index].width;
918 fse->max_width = fse->min_width;
919 fse->min_height = supported_modes[fse->index].height;
920 fse->max_height = fse->min_height;
921
922 return 0;
923 }
924
ov2740_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)925 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
926 {
927 struct ov2740 *ov2740 = to_ov2740(sd);
928
929 mutex_lock(&ov2740->mutex);
930 ov2740_update_pad_format(&supported_modes[0],
931 v4l2_subdev_get_try_format(sd, fh->state, 0));
932 mutex_unlock(&ov2740->mutex);
933
934 return 0;
935 }
936
937 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
938 .s_stream = ov2740_set_stream,
939 };
940
941 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
942 .set_fmt = ov2740_set_format,
943 .get_fmt = ov2740_get_format,
944 .enum_mbus_code = ov2740_enum_mbus_code,
945 .enum_frame_size = ov2740_enum_frame_size,
946 };
947
948 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
949 .video = &ov2740_video_ops,
950 .pad = &ov2740_pad_ops,
951 };
952
953 static const struct media_entity_operations ov2740_subdev_entity_ops = {
954 .link_validate = v4l2_subdev_link_validate,
955 };
956
957 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
958 .open = ov2740_open,
959 };
960
ov2740_identify_module(struct ov2740 * ov2740)961 static int ov2740_identify_module(struct ov2740 *ov2740)
962 {
963 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
964 int ret;
965 u32 val;
966
967 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
968 if (ret)
969 return ret;
970
971 if (val != OV2740_CHIP_ID) {
972 dev_err(&client->dev, "chip id mismatch: %x!=%x",
973 OV2740_CHIP_ID, val);
974 return -ENXIO;
975 }
976
977 return 0;
978 }
979
ov2740_check_hwcfg(struct device * dev)980 static int ov2740_check_hwcfg(struct device *dev)
981 {
982 struct fwnode_handle *ep;
983 struct fwnode_handle *fwnode = dev_fwnode(dev);
984 struct v4l2_fwnode_endpoint bus_cfg = {
985 .bus_type = V4L2_MBUS_CSI2_DPHY
986 };
987 u32 mclk;
988 int ret;
989 unsigned int i, j;
990
991 if (!fwnode)
992 return -ENXIO;
993
994 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
995 if (ret)
996 return ret;
997
998 if (mclk != OV2740_MCLK) {
999 dev_err(dev, "external clock %d is not supported", mclk);
1000 return -EINVAL;
1001 }
1002
1003 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1004 if (!ep)
1005 return -ENXIO;
1006
1007 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1008 fwnode_handle_put(ep);
1009 if (ret)
1010 return ret;
1011
1012 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1013 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1014 bus_cfg.bus.mipi_csi2.num_data_lanes);
1015 ret = -EINVAL;
1016 goto check_hwcfg_error;
1017 }
1018
1019 if (!bus_cfg.nr_of_link_frequencies) {
1020 dev_err(dev, "no link frequencies defined");
1021 ret = -EINVAL;
1022 goto check_hwcfg_error;
1023 }
1024
1025 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1026 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1027 if (link_freq_menu_items[i] ==
1028 bus_cfg.link_frequencies[j])
1029 break;
1030 }
1031
1032 if (j == bus_cfg.nr_of_link_frequencies) {
1033 dev_err(dev, "no link frequency %lld supported",
1034 link_freq_menu_items[i]);
1035 ret = -EINVAL;
1036 goto check_hwcfg_error;
1037 }
1038 }
1039
1040 check_hwcfg_error:
1041 v4l2_fwnode_endpoint_free(&bus_cfg);
1042
1043 return ret;
1044 }
1045
ov2740_remove(struct i2c_client * client)1046 static int ov2740_remove(struct i2c_client *client)
1047 {
1048 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1049 struct ov2740 *ov2740 = to_ov2740(sd);
1050
1051 v4l2_async_unregister_subdev(sd);
1052 media_entity_cleanup(&sd->entity);
1053 v4l2_ctrl_handler_free(sd->ctrl_handler);
1054 pm_runtime_disable(&client->dev);
1055 mutex_destroy(&ov2740->mutex);
1056
1057 return 0;
1058 }
1059
ov2740_nvmem_read(void * priv,unsigned int off,void * val,size_t count)1060 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1061 size_t count)
1062 {
1063 struct nvm_data *nvm = priv;
1064 struct v4l2_subdev *sd = i2c_get_clientdata(nvm->client);
1065 struct device *dev = &nvm->client->dev;
1066 struct ov2740 *ov2740 = to_ov2740(sd);
1067 int ret = 0;
1068
1069 mutex_lock(&ov2740->mutex);
1070
1071 if (nvm->nvm_buffer) {
1072 memcpy(val, nvm->nvm_buffer + off, count);
1073 goto exit;
1074 }
1075
1076 ret = pm_runtime_resume_and_get(dev);
1077 if (ret < 0) {
1078 goto exit;
1079 }
1080
1081 ret = ov2740_load_otp_data(nvm);
1082 if (!ret)
1083 memcpy(val, nvm->nvm_buffer + off, count);
1084
1085 pm_runtime_put(dev);
1086 exit:
1087 mutex_unlock(&ov2740->mutex);
1088 return ret;
1089 }
1090
ov2740_register_nvmem(struct i2c_client * client,struct ov2740 * ov2740)1091 static int ov2740_register_nvmem(struct i2c_client *client,
1092 struct ov2740 *ov2740)
1093 {
1094 struct nvm_data *nvm;
1095 struct regmap_config regmap_config = { };
1096 struct nvmem_config nvmem_config = { };
1097 struct regmap *regmap;
1098 struct device *dev = &client->dev;
1099 int ret;
1100
1101 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1102 if (!nvm)
1103 return -ENOMEM;
1104
1105 regmap_config.val_bits = 8;
1106 regmap_config.reg_bits = 16;
1107 regmap_config.disable_locking = true;
1108 regmap = devm_regmap_init_i2c(client, ®map_config);
1109 if (IS_ERR(regmap))
1110 return PTR_ERR(regmap);
1111
1112 nvm->regmap = regmap;
1113 nvm->client = client;
1114
1115 nvmem_config.name = dev_name(dev);
1116 nvmem_config.dev = dev;
1117 nvmem_config.read_only = true;
1118 nvmem_config.root_only = true;
1119 nvmem_config.owner = THIS_MODULE;
1120 nvmem_config.compat = true;
1121 nvmem_config.base_dev = dev;
1122 nvmem_config.reg_read = ov2740_nvmem_read;
1123 nvmem_config.reg_write = NULL;
1124 nvmem_config.priv = nvm;
1125 nvmem_config.stride = 1;
1126 nvmem_config.word_size = 1;
1127 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1128
1129 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1130
1131 ret = PTR_ERR_OR_ZERO(nvm->nvmem);
1132 if (!ret)
1133 ov2740->nvm = nvm;
1134
1135 return ret;
1136 }
1137
ov2740_probe(struct i2c_client * client)1138 static int ov2740_probe(struct i2c_client *client)
1139 {
1140 struct ov2740 *ov2740;
1141 int ret = 0;
1142
1143 ret = ov2740_check_hwcfg(&client->dev);
1144 if (ret) {
1145 dev_err(&client->dev, "failed to check HW configuration: %d",
1146 ret);
1147 return ret;
1148 }
1149
1150 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1151 if (!ov2740)
1152 return -ENOMEM;
1153
1154 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1155 ret = ov2740_identify_module(ov2740);
1156 if (ret) {
1157 dev_err(&client->dev, "failed to find sensor: %d", ret);
1158 return ret;
1159 }
1160
1161 mutex_init(&ov2740->mutex);
1162 ov2740->cur_mode = &supported_modes[0];
1163 ret = ov2740_init_controls(ov2740);
1164 if (ret) {
1165 dev_err(&client->dev, "failed to init controls: %d", ret);
1166 goto probe_error_v4l2_ctrl_handler_free;
1167 }
1168
1169 ov2740->sd.internal_ops = &ov2740_internal_ops;
1170 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1171 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1172 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1173 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1174 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1175 if (ret) {
1176 dev_err(&client->dev, "failed to init entity pads: %d", ret);
1177 goto probe_error_v4l2_ctrl_handler_free;
1178 }
1179
1180 ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1181 if (ret < 0) {
1182 dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1183 ret);
1184 goto probe_error_media_entity_cleanup;
1185 }
1186
1187 ret = ov2740_register_nvmem(client, ov2740);
1188 if (ret)
1189 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1190
1191 /*
1192 * Device is already turned on by i2c-core with ACPI domain PM.
1193 * Enable runtime PM and turn off the device.
1194 */
1195 pm_runtime_set_active(&client->dev);
1196 pm_runtime_enable(&client->dev);
1197 pm_runtime_idle(&client->dev);
1198
1199 return 0;
1200
1201 probe_error_media_entity_cleanup:
1202 media_entity_cleanup(&ov2740->sd.entity);
1203
1204 probe_error_v4l2_ctrl_handler_free:
1205 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1206 mutex_destroy(&ov2740->mutex);
1207
1208 return ret;
1209 }
1210
1211 static const struct dev_pm_ops ov2740_pm_ops = {
1212 SET_SYSTEM_SLEEP_PM_OPS(ov2740_suspend, ov2740_resume)
1213 };
1214
1215 static const struct acpi_device_id ov2740_acpi_ids[] = {
1216 {"INT3474"},
1217 {}
1218 };
1219
1220 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1221
1222 static struct i2c_driver ov2740_i2c_driver = {
1223 .driver = {
1224 .name = "ov2740",
1225 .pm = &ov2740_pm_ops,
1226 .acpi_match_table = ov2740_acpi_ids,
1227 },
1228 .probe_new = ov2740_probe,
1229 .remove = ov2740_remove,
1230 };
1231
1232 module_i2c_driver(ov2740_i2c_driver);
1233
1234 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1235 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1236 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1237 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1238 MODULE_LICENSE("GPL v2");
1239