1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 MediaTek Inc.
4 * Author: PC Chen <pc.chen@mediatek.com>
5 * Tiffany Lin <tiffany.lin@mediatek.com>
6 */
7
8 #include <linux/slab.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/of.h>
14 #include <media/v4l2-event.h>
15 #include <media/v4l2-mem2mem.h>
16 #include <media/videobuf2-dma-contig.h>
17 #include <linux/pm_runtime.h>
18
19 #include "mtk_vcodec_drv.h"
20 #include "mtk_vcodec_enc.h"
21 #include "mtk_vcodec_enc_pm.h"
22 #include "mtk_vcodec_intr.h"
23 #include "mtk_vcodec_util.h"
24 #include "mtk_vcodec_fw.h"
25
26 module_param(mtk_v4l2_dbg_level, int, S_IRUGO | S_IWUSR);
27 module_param(mtk_vcodec_dbg, bool, S_IRUGO | S_IWUSR);
28
29 static const struct mtk_video_fmt mtk_video_formats_output_mt8173[] = {
30 {
31 .fourcc = V4L2_PIX_FMT_NV12M,
32 .type = MTK_FMT_FRAME,
33 .num_planes = 2,
34 },
35 {
36 .fourcc = V4L2_PIX_FMT_NV21M,
37 .type = MTK_FMT_FRAME,
38 .num_planes = 2,
39 },
40 {
41 .fourcc = V4L2_PIX_FMT_YUV420M,
42 .type = MTK_FMT_FRAME,
43 .num_planes = 3,
44 },
45 {
46 .fourcc = V4L2_PIX_FMT_YVU420M,
47 .type = MTK_FMT_FRAME,
48 .num_planes = 3,
49 },
50 };
51
52 static const struct mtk_video_fmt mtk_video_formats_capture_mt8173_avc[] = {
53 {
54 .fourcc = V4L2_PIX_FMT_H264,
55 .type = MTK_FMT_ENC,
56 .num_planes = 1,
57 },
58 };
59
60 static const struct mtk_video_fmt mtk_video_formats_capture_mt8173_vp8[] = {
61 {
62 .fourcc = V4L2_PIX_FMT_VP8,
63 .type = MTK_FMT_ENC,
64 .num_planes = 1,
65 },
66 };
67
68 static const struct mtk_video_fmt mtk_video_formats_capture_mt8183[] = {
69 {
70 .fourcc = V4L2_PIX_FMT_H264,
71 .type = MTK_FMT_ENC,
72 .num_planes = 1,
73 },
74 };
75
76 /* Wake up context wait_queue */
wake_up_ctx(struct mtk_vcodec_ctx * ctx,unsigned int reason)77 static void wake_up_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason)
78 {
79 ctx->int_cond = 1;
80 ctx->int_type = reason;
81 wake_up_interruptible(&ctx->queue);
82 }
83
clean_irq_status(unsigned int irq_status,void __iomem * addr)84 static void clean_irq_status(unsigned int irq_status, void __iomem *addr)
85 {
86 if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE)
87 writel(MTK_VENC_IRQ_STATUS_PAUSE, addr);
88
89 if (irq_status & MTK_VENC_IRQ_STATUS_SWITCH)
90 writel(MTK_VENC_IRQ_STATUS_SWITCH, addr);
91
92 if (irq_status & MTK_VENC_IRQ_STATUS_DRAM)
93 writel(MTK_VENC_IRQ_STATUS_DRAM, addr);
94
95 if (irq_status & MTK_VENC_IRQ_STATUS_SPS)
96 writel(MTK_VENC_IRQ_STATUS_SPS, addr);
97
98 if (irq_status & MTK_VENC_IRQ_STATUS_PPS)
99 writel(MTK_VENC_IRQ_STATUS_PPS, addr);
100
101 if (irq_status & MTK_VENC_IRQ_STATUS_FRM)
102 writel(MTK_VENC_IRQ_STATUS_FRM, addr);
103
104 }
mtk_vcodec_enc_irq_handler(int irq,void * priv)105 static irqreturn_t mtk_vcodec_enc_irq_handler(int irq, void *priv)
106 {
107 struct mtk_vcodec_dev *dev = priv;
108 struct mtk_vcodec_ctx *ctx;
109 unsigned long flags;
110 void __iomem *addr;
111
112 spin_lock_irqsave(&dev->irqlock, flags);
113 ctx = dev->curr_ctx;
114 spin_unlock_irqrestore(&dev->irqlock, flags);
115
116 mtk_v4l2_debug(1, "id=%d coreid:%d", ctx->id, dev->venc_pdata->core_id);
117 addr = dev->reg_base[dev->venc_pdata->core_id] +
118 MTK_VENC_IRQ_ACK_OFFSET;
119
120 ctx->irq_status = readl(dev->reg_base[dev->venc_pdata->core_id] +
121 (MTK_VENC_IRQ_STATUS_OFFSET));
122
123 clean_irq_status(ctx->irq_status, addr);
124
125 wake_up_ctx(ctx, MTK_INST_IRQ_RECEIVED);
126 return IRQ_HANDLED;
127 }
128
fops_vcodec_open(struct file * file)129 static int fops_vcodec_open(struct file *file)
130 {
131 struct mtk_vcodec_dev *dev = video_drvdata(file);
132 struct mtk_vcodec_ctx *ctx = NULL;
133 int ret = 0;
134
135 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
136 if (!ctx)
137 return -ENOMEM;
138
139 mutex_lock(&dev->dev_mutex);
140 /*
141 * Use simple counter to uniquely identify this context. Only
142 * used for logging.
143 */
144 ctx->id = dev->id_counter++;
145 v4l2_fh_init(&ctx->fh, video_devdata(file));
146 file->private_data = &ctx->fh;
147 v4l2_fh_add(&ctx->fh);
148 INIT_LIST_HEAD(&ctx->list);
149 ctx->dev = dev;
150 init_waitqueue_head(&ctx->queue);
151
152 ctx->type = MTK_INST_ENCODER;
153 ret = mtk_vcodec_enc_ctrls_setup(ctx);
154 if (ret) {
155 mtk_v4l2_err("Failed to setup controls() (%d)",
156 ret);
157 goto err_ctrls_setup;
158 }
159 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev_enc, ctx,
160 &mtk_vcodec_enc_queue_init);
161 if (IS_ERR((__force void *)ctx->m2m_ctx)) {
162 ret = PTR_ERR((__force void *)ctx->m2m_ctx);
163 mtk_v4l2_err("Failed to v4l2_m2m_ctx_init() (%d)",
164 ret);
165 goto err_m2m_ctx_init;
166 }
167 mtk_vcodec_enc_set_default_params(ctx);
168
169 if (v4l2_fh_is_singular(&ctx->fh)) {
170 /*
171 * load fireware to checks if it was loaded already and
172 * does nothing in that case
173 */
174 ret = mtk_vcodec_fw_load_firmware(dev->fw_handler);
175 if (ret < 0) {
176 /*
177 * Return 0 if downloading firmware successfully,
178 * otherwise it is failed
179 */
180 mtk_v4l2_err("vpu_load_firmware failed!");
181 goto err_load_fw;
182 }
183
184 dev->enc_capability =
185 mtk_vcodec_fw_get_venc_capa(dev->fw_handler);
186 mtk_v4l2_debug(0, "encoder capability %x", dev->enc_capability);
187 }
188
189 mtk_v4l2_debug(2, "Create instance [%d]@%p m2m_ctx=%p ",
190 ctx->id, ctx, ctx->m2m_ctx);
191
192 list_add(&ctx->list, &dev->ctx_list);
193
194 mutex_unlock(&dev->dev_mutex);
195 mtk_v4l2_debug(0, "%s encoder [%d]", dev_name(&dev->plat_dev->dev),
196 ctx->id);
197 return ret;
198
199 /* Deinit when failure occurred */
200 err_load_fw:
201 v4l2_m2m_ctx_release(ctx->m2m_ctx);
202 err_m2m_ctx_init:
203 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
204 err_ctrls_setup:
205 v4l2_fh_del(&ctx->fh);
206 v4l2_fh_exit(&ctx->fh);
207 kfree(ctx);
208 mutex_unlock(&dev->dev_mutex);
209
210 return ret;
211 }
212
fops_vcodec_release(struct file * file)213 static int fops_vcodec_release(struct file *file)
214 {
215 struct mtk_vcodec_dev *dev = video_drvdata(file);
216 struct mtk_vcodec_ctx *ctx = fh_to_ctx(file->private_data);
217
218 mtk_v4l2_debug(1, "[%d] encoder", ctx->id);
219 mutex_lock(&dev->dev_mutex);
220
221 v4l2_m2m_ctx_release(ctx->m2m_ctx);
222 mtk_vcodec_enc_release(ctx);
223 v4l2_fh_del(&ctx->fh);
224 v4l2_fh_exit(&ctx->fh);
225 v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
226
227 list_del_init(&ctx->list);
228 kfree(ctx);
229 mutex_unlock(&dev->dev_mutex);
230 return 0;
231 }
232
233 static const struct v4l2_file_operations mtk_vcodec_fops = {
234 .owner = THIS_MODULE,
235 .open = fops_vcodec_open,
236 .release = fops_vcodec_release,
237 .poll = v4l2_m2m_fop_poll,
238 .unlocked_ioctl = video_ioctl2,
239 .mmap = v4l2_m2m_fop_mmap,
240 };
241
mtk_vcodec_probe(struct platform_device * pdev)242 static int mtk_vcodec_probe(struct platform_device *pdev)
243 {
244 struct mtk_vcodec_dev *dev;
245 struct video_device *vfd_enc;
246 struct resource *res;
247 phandle rproc_phandle;
248 enum mtk_vcodec_fw_type fw_type;
249 int ret;
250
251 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
252 if (!dev)
253 return -ENOMEM;
254
255 INIT_LIST_HEAD(&dev->ctx_list);
256 dev->plat_dev = pdev;
257
258 if (!of_property_read_u32(pdev->dev.of_node, "mediatek,vpu",
259 &rproc_phandle)) {
260 fw_type = VPU;
261 } else if (!of_property_read_u32(pdev->dev.of_node, "mediatek,scp",
262 &rproc_phandle)) {
263 fw_type = SCP;
264 } else {
265 mtk_v4l2_err("Could not get venc IPI device");
266 return -ENODEV;
267 }
268 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
269
270 dev->fw_handler = mtk_vcodec_fw_select(dev, fw_type, ENCODER);
271 if (IS_ERR(dev->fw_handler))
272 return PTR_ERR(dev->fw_handler);
273
274 dev->venc_pdata = of_device_get_match_data(&pdev->dev);
275 ret = mtk_vcodec_init_enc_pm(dev);
276 if (ret < 0) {
277 dev_err(&pdev->dev, "Failed to get mtk vcodec clock source!");
278 goto err_enc_pm;
279 }
280
281 pm_runtime_enable(&pdev->dev);
282
283 dev->reg_base[dev->venc_pdata->core_id] =
284 devm_platform_ioremap_resource(pdev, 0);
285 if (IS_ERR(dev->reg_base[dev->venc_pdata->core_id])) {
286 ret = PTR_ERR(dev->reg_base[dev->venc_pdata->core_id]);
287 goto err_res;
288 }
289
290 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
291 if (res == NULL) {
292 dev_err(&pdev->dev, "failed to get irq resource");
293 ret = -ENOENT;
294 goto err_res;
295 }
296
297 dev->enc_irq = platform_get_irq(pdev, 0);
298 irq_set_status_flags(dev->enc_irq, IRQ_NOAUTOEN);
299 ret = devm_request_irq(&pdev->dev, dev->enc_irq,
300 mtk_vcodec_enc_irq_handler,
301 0, pdev->name, dev);
302 if (ret) {
303 dev_err(&pdev->dev,
304 "Failed to install dev->enc_irq %d (%d) core_id (%d)",
305 dev->enc_irq, ret, dev->venc_pdata->core_id);
306 ret = -EINVAL;
307 goto err_res;
308 }
309
310 mutex_init(&dev->enc_mutex);
311 mutex_init(&dev->dev_mutex);
312 spin_lock_init(&dev->irqlock);
313
314 snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), "%s",
315 "[MTK_V4L2_VENC]");
316
317 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
318 if (ret) {
319 mtk_v4l2_err("v4l2_device_register err=%d", ret);
320 goto err_res;
321 }
322
323 init_waitqueue_head(&dev->queue);
324
325 /* allocate video device for encoder and register it */
326 vfd_enc = video_device_alloc();
327 if (!vfd_enc) {
328 mtk_v4l2_err("Failed to allocate video device");
329 ret = -ENOMEM;
330 goto err_enc_alloc;
331 }
332 vfd_enc->fops = &mtk_vcodec_fops;
333 vfd_enc->ioctl_ops = &mtk_venc_ioctl_ops;
334 vfd_enc->release = video_device_release;
335 vfd_enc->lock = &dev->dev_mutex;
336 vfd_enc->v4l2_dev = &dev->v4l2_dev;
337 vfd_enc->vfl_dir = VFL_DIR_M2M;
338 vfd_enc->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE |
339 V4L2_CAP_STREAMING;
340
341 snprintf(vfd_enc->name, sizeof(vfd_enc->name), "%s",
342 MTK_VCODEC_ENC_NAME);
343 video_set_drvdata(vfd_enc, dev);
344 dev->vfd_enc = vfd_enc;
345 platform_set_drvdata(pdev, dev);
346
347 dev->m2m_dev_enc = v4l2_m2m_init(&mtk_venc_m2m_ops);
348 if (IS_ERR((__force void *)dev->m2m_dev_enc)) {
349 mtk_v4l2_err("Failed to init mem2mem enc device");
350 ret = PTR_ERR((__force void *)dev->m2m_dev_enc);
351 goto err_enc_mem_init;
352 }
353
354 dev->encode_workqueue =
355 alloc_ordered_workqueue(MTK_VCODEC_ENC_NAME,
356 WQ_MEM_RECLAIM |
357 WQ_FREEZABLE);
358 if (!dev->encode_workqueue) {
359 mtk_v4l2_err("Failed to create encode workqueue");
360 ret = -EINVAL;
361 goto err_event_workq;
362 }
363
364 if (of_get_property(pdev->dev.of_node, "dma-ranges", NULL))
365 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34));
366
367 ret = video_register_device(vfd_enc, VFL_TYPE_VIDEO, 1);
368 if (ret) {
369 mtk_v4l2_err("Failed to register video device");
370 goto err_enc_reg;
371 }
372
373 mtk_v4l2_debug(0, "encoder %d registered as /dev/video%d",
374 dev->venc_pdata->core_id, vfd_enc->num);
375
376 return 0;
377
378 err_enc_reg:
379 destroy_workqueue(dev->encode_workqueue);
380 err_event_workq:
381 v4l2_m2m_release(dev->m2m_dev_enc);
382 err_enc_mem_init:
383 video_unregister_device(vfd_enc);
384 err_enc_alloc:
385 v4l2_device_unregister(&dev->v4l2_dev);
386 err_res:
387 mtk_vcodec_release_enc_pm(dev);
388 err_enc_pm:
389 mtk_vcodec_fw_release(dev->fw_handler);
390 return ret;
391 }
392
393 static const struct mtk_vcodec_enc_pdata mt8173_avc_pdata = {
394 .chip = MTK_MT8173,
395 .capture_formats = mtk_video_formats_capture_mt8173_avc,
396 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_mt8173_avc),
397 .output_formats = mtk_video_formats_output_mt8173,
398 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
399 .min_bitrate = 1,
400 .max_bitrate = 4000000,
401 .core_id = VENC_SYS,
402 };
403
404 static const struct mtk_vcodec_enc_pdata mt8173_vp8_pdata = {
405 .chip = MTK_MT8173,
406 .capture_formats = mtk_video_formats_capture_mt8173_vp8,
407 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_mt8173_vp8),
408 .output_formats = mtk_video_formats_output_mt8173,
409 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
410 .min_bitrate = 64,
411 .max_bitrate = 4000000,
412 .core_id = VENC_LT_SYS,
413 };
414
415 static const struct mtk_vcodec_enc_pdata mt8183_pdata = {
416 .chip = MTK_MT8183,
417 .uses_ext = true,
418 .capture_formats = mtk_video_formats_capture_mt8183,
419 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_mt8183),
420 /* MT8183 supports the same output formats as MT8173 */
421 .output_formats = mtk_video_formats_output_mt8173,
422 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
423 .min_bitrate = 64,
424 .max_bitrate = 40000000,
425 .core_id = VENC_SYS,
426 };
427
428 static const struct mtk_vcodec_enc_pdata mt8192_pdata = {
429 .chip = MTK_MT8192,
430 .uses_ext = true,
431 /* MT8192 supports the same capture formats as MT8183 */
432 .capture_formats = mtk_video_formats_capture_mt8183,
433 .num_capture_formats = ARRAY_SIZE(mtk_video_formats_capture_mt8183),
434 /* MT8192 supports the same output formats as MT8173 */
435 .output_formats = mtk_video_formats_output_mt8173,
436 .num_output_formats = ARRAY_SIZE(mtk_video_formats_output_mt8173),
437 .min_bitrate = 64,
438 .max_bitrate = 100000000,
439 .core_id = VENC_SYS,
440 };
441 static const struct of_device_id mtk_vcodec_enc_match[] = {
442 {.compatible = "mediatek,mt8173-vcodec-enc",
443 .data = &mt8173_avc_pdata},
444 {.compatible = "mediatek,mt8173-vcodec-enc-vp8",
445 .data = &mt8173_vp8_pdata},
446 {.compatible = "mediatek,mt8183-vcodec-enc", .data = &mt8183_pdata},
447 {.compatible = "mediatek,mt8192-vcodec-enc", .data = &mt8192_pdata},
448 {},
449 };
450 MODULE_DEVICE_TABLE(of, mtk_vcodec_enc_match);
451
mtk_vcodec_enc_remove(struct platform_device * pdev)452 static int mtk_vcodec_enc_remove(struct platform_device *pdev)
453 {
454 struct mtk_vcodec_dev *dev = platform_get_drvdata(pdev);
455
456 mtk_v4l2_debug_enter();
457 flush_workqueue(dev->encode_workqueue);
458 destroy_workqueue(dev->encode_workqueue);
459 if (dev->m2m_dev_enc)
460 v4l2_m2m_release(dev->m2m_dev_enc);
461
462 if (dev->vfd_enc)
463 video_unregister_device(dev->vfd_enc);
464
465 v4l2_device_unregister(&dev->v4l2_dev);
466 mtk_vcodec_release_enc_pm(dev);
467 mtk_vcodec_fw_release(dev->fw_handler);
468 return 0;
469 }
470
471 static struct platform_driver mtk_vcodec_enc_driver = {
472 .probe = mtk_vcodec_probe,
473 .remove = mtk_vcodec_enc_remove,
474 .driver = {
475 .name = MTK_VCODEC_ENC_NAME,
476 .of_match_table = mtk_vcodec_enc_match,
477 },
478 };
479
480 module_platform_driver(mtk_vcodec_enc_driver);
481
482
483 MODULE_LICENSE("GPL v2");
484 MODULE_DESCRIPTION("Mediatek video codec V4L2 encoder driver");
485