1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/reset.h>
18 #include <linux/sys_soc.h>
19
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mc.h>
24 #include <media/v4l2-subdev.h>
25
26 struct rcar_csi2;
27
28 /* Register offsets and bits */
29
30 /* Control Timing Select */
31 #define TREF_REG 0x00
32 #define TREF_TREF BIT(0)
33
34 /* Software Reset */
35 #define SRST_REG 0x04
36 #define SRST_SRST BIT(0)
37
38 /* PHY Operation Control */
39 #define PHYCNT_REG 0x08
40 #define PHYCNT_SHUTDOWNZ BIT(17)
41 #define PHYCNT_RSTZ BIT(16)
42 #define PHYCNT_ENABLECLK BIT(4)
43 #define PHYCNT_ENABLE_3 BIT(3)
44 #define PHYCNT_ENABLE_2 BIT(2)
45 #define PHYCNT_ENABLE_1 BIT(1)
46 #define PHYCNT_ENABLE_0 BIT(0)
47
48 /* Checksum Control */
49 #define CHKSUM_REG 0x0c
50 #define CHKSUM_ECC_EN BIT(1)
51 #define CHKSUM_CRC_EN BIT(0)
52
53 /*
54 * Channel Data Type Select
55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
57 */
58 #define VCDT_REG 0x10
59 #define VCDT2_REG 0x14
60 #define VCDT_VCDTN_EN BIT(15)
61 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
62 #define VCDT_SEL_DTN_ON BIT(6)
63 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
64
65 /* Frame Data Type Select */
66 #define FRDT_REG 0x18
67
68 /* Field Detection Control */
69 #define FLD_REG 0x1c
70 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
71 #define FLD_DET_SEL(n) (((n) & 0x3) << 4)
72 #define FLD_FLD_EN4 BIT(3)
73 #define FLD_FLD_EN3 BIT(2)
74 #define FLD_FLD_EN2 BIT(1)
75 #define FLD_FLD_EN BIT(0)
76
77 /* Automatic Standby Control */
78 #define ASTBY_REG 0x20
79
80 /* Long Data Type Setting 0 */
81 #define LNGDT0_REG 0x28
82
83 /* Long Data Type Setting 1 */
84 #define LNGDT1_REG 0x2c
85
86 /* Interrupt Enable */
87 #define INTEN_REG 0x30
88 #define INTEN_INT_AFIFO_OF BIT(27)
89 #define INTEN_INT_ERRSOTHS BIT(4)
90 #define INTEN_INT_ERRSOTSYNCHS BIT(3)
91
92 /* Interrupt Source Mask */
93 #define INTCLOSE_REG 0x34
94
95 /* Interrupt Status Monitor */
96 #define INTSTATE_REG 0x38
97 #define INTSTATE_INT_ULPS_START BIT(7)
98 #define INTSTATE_INT_ULPS_END BIT(6)
99
100 /* Interrupt Error Status Monitor */
101 #define INTERRSTATE_REG 0x3c
102
103 /* Short Packet Data */
104 #define SHPDAT_REG 0x40
105
106 /* Short Packet Count */
107 #define SHPCNT_REG 0x44
108
109 /* LINK Operation Control */
110 #define LINKCNT_REG 0x48
111 #define LINKCNT_MONITOR_EN BIT(31)
112 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
113 #define LINKCNT_ICLK_NONSTOP BIT(24)
114
115 /* Lane Swap */
116 #define LSWAP_REG 0x4c
117 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
118 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
119 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
120 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
121
122 /* PHY Test Interface Write Register */
123 #define PHTW_REG 0x50
124 #define PHTW_DWEN BIT(24)
125 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
126 #define PHTW_CWEN BIT(8)
127 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
128
129 struct phtw_value {
130 u16 data;
131 u16 code;
132 };
133
134 struct rcsi2_mbps_reg {
135 u16 mbps;
136 u16 reg;
137 };
138
139 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = {
140 { .mbps = 80, .reg = 0x86 },
141 { .mbps = 90, .reg = 0x86 },
142 { .mbps = 100, .reg = 0x87 },
143 { .mbps = 110, .reg = 0x87 },
144 { .mbps = 120, .reg = 0x88 },
145 { .mbps = 130, .reg = 0x88 },
146 { .mbps = 140, .reg = 0x89 },
147 { .mbps = 150, .reg = 0x89 },
148 { .mbps = 160, .reg = 0x8a },
149 { .mbps = 170, .reg = 0x8a },
150 { .mbps = 180, .reg = 0x8b },
151 { .mbps = 190, .reg = 0x8b },
152 { .mbps = 205, .reg = 0x8c },
153 { .mbps = 220, .reg = 0x8d },
154 { .mbps = 235, .reg = 0x8e },
155 { .mbps = 250, .reg = 0x8e },
156 { /* sentinel */ },
157 };
158
159 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = {
160 { .mbps = 80, .reg = 0x00 },
161 { .mbps = 90, .reg = 0x20 },
162 { .mbps = 100, .reg = 0x40 },
163 { .mbps = 110, .reg = 0x02 },
164 { .mbps = 130, .reg = 0x22 },
165 { .mbps = 140, .reg = 0x42 },
166 { .mbps = 150, .reg = 0x04 },
167 { .mbps = 170, .reg = 0x24 },
168 { .mbps = 180, .reg = 0x44 },
169 { .mbps = 200, .reg = 0x06 },
170 { .mbps = 220, .reg = 0x26 },
171 { .mbps = 240, .reg = 0x46 },
172 { .mbps = 250, .reg = 0x08 },
173 { .mbps = 270, .reg = 0x28 },
174 { .mbps = 300, .reg = 0x0a },
175 { .mbps = 330, .reg = 0x2a },
176 { .mbps = 360, .reg = 0x4a },
177 { .mbps = 400, .reg = 0x0c },
178 { .mbps = 450, .reg = 0x2c },
179 { .mbps = 500, .reg = 0x0e },
180 { .mbps = 550, .reg = 0x2e },
181 { .mbps = 600, .reg = 0x10 },
182 { .mbps = 650, .reg = 0x30 },
183 { .mbps = 700, .reg = 0x12 },
184 { .mbps = 750, .reg = 0x32 },
185 { .mbps = 800, .reg = 0x52 },
186 { .mbps = 850, .reg = 0x72 },
187 { .mbps = 900, .reg = 0x14 },
188 { .mbps = 950, .reg = 0x34 },
189 { .mbps = 1000, .reg = 0x54 },
190 { .mbps = 1050, .reg = 0x74 },
191 { .mbps = 1125, .reg = 0x16 },
192 { /* sentinel */ },
193 };
194
195 /* PHY Test Interface Clear */
196 #define PHTC_REG 0x58
197 #define PHTC_TESTCLR BIT(0)
198
199 /* PHY Frequency Control */
200 #define PHYPLL_REG 0x68
201 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
202
203 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = {
204 { .mbps = 80, .reg = 0x00 },
205 { .mbps = 90, .reg = 0x10 },
206 { .mbps = 100, .reg = 0x20 },
207 { .mbps = 110, .reg = 0x30 },
208 { .mbps = 120, .reg = 0x01 },
209 { .mbps = 130, .reg = 0x11 },
210 { .mbps = 140, .reg = 0x21 },
211 { .mbps = 150, .reg = 0x31 },
212 { .mbps = 160, .reg = 0x02 },
213 { .mbps = 170, .reg = 0x12 },
214 { .mbps = 180, .reg = 0x22 },
215 { .mbps = 190, .reg = 0x32 },
216 { .mbps = 205, .reg = 0x03 },
217 { .mbps = 220, .reg = 0x13 },
218 { .mbps = 235, .reg = 0x23 },
219 { .mbps = 250, .reg = 0x33 },
220 { .mbps = 275, .reg = 0x04 },
221 { .mbps = 300, .reg = 0x14 },
222 { .mbps = 325, .reg = 0x25 },
223 { .mbps = 350, .reg = 0x35 },
224 { .mbps = 400, .reg = 0x05 },
225 { .mbps = 450, .reg = 0x16 },
226 { .mbps = 500, .reg = 0x26 },
227 { .mbps = 550, .reg = 0x37 },
228 { .mbps = 600, .reg = 0x07 },
229 { .mbps = 650, .reg = 0x18 },
230 { .mbps = 700, .reg = 0x28 },
231 { .mbps = 750, .reg = 0x39 },
232 { .mbps = 800, .reg = 0x09 },
233 { .mbps = 850, .reg = 0x19 },
234 { .mbps = 900, .reg = 0x29 },
235 { .mbps = 950, .reg = 0x3a },
236 { .mbps = 1000, .reg = 0x0a },
237 { .mbps = 1050, .reg = 0x1a },
238 { .mbps = 1100, .reg = 0x2a },
239 { .mbps = 1150, .reg = 0x3b },
240 { .mbps = 1200, .reg = 0x0b },
241 { .mbps = 1250, .reg = 0x1b },
242 { .mbps = 1300, .reg = 0x2b },
243 { .mbps = 1350, .reg = 0x3c },
244 { .mbps = 1400, .reg = 0x0c },
245 { .mbps = 1450, .reg = 0x1c },
246 { .mbps = 1500, .reg = 0x2c },
247 { /* sentinel */ },
248 };
249
250 static const struct rcsi2_mbps_reg hsfreqrange_m3w_h3es1[] = {
251 { .mbps = 80, .reg = 0x00 },
252 { .mbps = 90, .reg = 0x10 },
253 { .mbps = 100, .reg = 0x20 },
254 { .mbps = 110, .reg = 0x30 },
255 { .mbps = 120, .reg = 0x01 },
256 { .mbps = 130, .reg = 0x11 },
257 { .mbps = 140, .reg = 0x21 },
258 { .mbps = 150, .reg = 0x31 },
259 { .mbps = 160, .reg = 0x02 },
260 { .mbps = 170, .reg = 0x12 },
261 { .mbps = 180, .reg = 0x22 },
262 { .mbps = 190, .reg = 0x32 },
263 { .mbps = 205, .reg = 0x03 },
264 { .mbps = 220, .reg = 0x13 },
265 { .mbps = 235, .reg = 0x23 },
266 { .mbps = 250, .reg = 0x33 },
267 { .mbps = 275, .reg = 0x04 },
268 { .mbps = 300, .reg = 0x14 },
269 { .mbps = 325, .reg = 0x05 },
270 { .mbps = 350, .reg = 0x15 },
271 { .mbps = 400, .reg = 0x25 },
272 { .mbps = 450, .reg = 0x06 },
273 { .mbps = 500, .reg = 0x16 },
274 { .mbps = 550, .reg = 0x07 },
275 { .mbps = 600, .reg = 0x17 },
276 { .mbps = 650, .reg = 0x08 },
277 { .mbps = 700, .reg = 0x18 },
278 { .mbps = 750, .reg = 0x09 },
279 { .mbps = 800, .reg = 0x19 },
280 { .mbps = 850, .reg = 0x29 },
281 { .mbps = 900, .reg = 0x39 },
282 { .mbps = 950, .reg = 0x0a },
283 { .mbps = 1000, .reg = 0x1a },
284 { .mbps = 1050, .reg = 0x2a },
285 { .mbps = 1100, .reg = 0x3a },
286 { .mbps = 1150, .reg = 0x0b },
287 { .mbps = 1200, .reg = 0x1b },
288 { .mbps = 1250, .reg = 0x2b },
289 { .mbps = 1300, .reg = 0x3b },
290 { .mbps = 1350, .reg = 0x0c },
291 { .mbps = 1400, .reg = 0x1c },
292 { .mbps = 1450, .reg = 0x2c },
293 { .mbps = 1500, .reg = 0x3c },
294 { /* sentinel */ },
295 };
296
297 /* PHY ESC Error Monitor */
298 #define PHEERM_REG 0x74
299
300 /* PHY Clock Lane Monitor */
301 #define PHCLM_REG 0x78
302 #define PHCLM_STOPSTATECKL BIT(0)
303
304 /* PHY Data Lane Monitor */
305 #define PHDLM_REG 0x7c
306
307 /* CSI0CLK Frequency Configuration Preset Register */
308 #define CSI0CLKFCPR_REG 0x260
309 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
310
311 struct rcar_csi2_format {
312 u32 code;
313 unsigned int datatype;
314 unsigned int bpp;
315 };
316
317 static const struct rcar_csi2_format rcar_csi2_formats[] = {
318 { .code = MEDIA_BUS_FMT_RGB888_1X24, .datatype = 0x24, .bpp = 24 },
319 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .datatype = 0x1e, .bpp = 16 },
320 { .code = MEDIA_BUS_FMT_YUYV8_1X16, .datatype = 0x1e, .bpp = 16 },
321 { .code = MEDIA_BUS_FMT_UYVY8_2X8, .datatype = 0x1e, .bpp = 16 },
322 { .code = MEDIA_BUS_FMT_YUYV10_2X10, .datatype = 0x1e, .bpp = 20 },
323 { .code = MEDIA_BUS_FMT_Y10_1X10, .datatype = 0x2b, .bpp = 10 },
324 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .datatype = 0x2a, .bpp = 8 },
325 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .datatype = 0x2a, .bpp = 8 },
326 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .datatype = 0x2a, .bpp = 8 },
327 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .datatype = 0x2a, .bpp = 8 },
328 { .code = MEDIA_BUS_FMT_Y8_1X8, .datatype = 0x2a, .bpp = 8 },
329 };
330
rcsi2_code_to_fmt(unsigned int code)331 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
332 {
333 unsigned int i;
334
335 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
336 if (rcar_csi2_formats[i].code == code)
337 return &rcar_csi2_formats[i];
338
339 return NULL;
340 }
341
342 enum rcar_csi2_pads {
343 RCAR_CSI2_SINK,
344 RCAR_CSI2_SOURCE_VC0,
345 RCAR_CSI2_SOURCE_VC1,
346 RCAR_CSI2_SOURCE_VC2,
347 RCAR_CSI2_SOURCE_VC3,
348 NR_OF_RCAR_CSI2_PAD,
349 };
350
351 struct rcar_csi2_info {
352 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
353 int (*phy_post_init)(struct rcar_csi2 *priv);
354 const struct rcsi2_mbps_reg *hsfreqrange;
355 unsigned int csi0clkfreqrange;
356 unsigned int num_channels;
357 bool clear_ulps;
358 };
359
360 struct rcar_csi2 {
361 struct device *dev;
362 void __iomem *base;
363 const struct rcar_csi2_info *info;
364 struct reset_control *rstc;
365
366 struct v4l2_subdev subdev;
367 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
368
369 struct v4l2_async_notifier notifier;
370 struct v4l2_subdev *remote;
371 unsigned int remote_pad;
372
373 struct v4l2_mbus_framefmt mf;
374
375 struct mutex lock;
376 int stream_count;
377
378 unsigned short lanes;
379 unsigned char lane_swap[4];
380 };
381
sd_to_csi2(struct v4l2_subdev * sd)382 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
383 {
384 return container_of(sd, struct rcar_csi2, subdev);
385 }
386
notifier_to_csi2(struct v4l2_async_notifier * n)387 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
388 {
389 return container_of(n, struct rcar_csi2, notifier);
390 }
391
rcsi2_read(struct rcar_csi2 * priv,unsigned int reg)392 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
393 {
394 return ioread32(priv->base + reg);
395 }
396
rcsi2_write(struct rcar_csi2 * priv,unsigned int reg,u32 data)397 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
398 {
399 iowrite32(data, priv->base + reg);
400 }
401
rcsi2_enter_standby(struct rcar_csi2 * priv)402 static void rcsi2_enter_standby(struct rcar_csi2 *priv)
403 {
404 rcsi2_write(priv, PHYCNT_REG, 0);
405 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
406 reset_control_assert(priv->rstc);
407 usleep_range(100, 150);
408 pm_runtime_put(priv->dev);
409 }
410
rcsi2_exit_standby(struct rcar_csi2 * priv)411 static int rcsi2_exit_standby(struct rcar_csi2 *priv)
412 {
413 int ret;
414
415 ret = pm_runtime_resume_and_get(priv->dev);
416 if (ret < 0)
417 return ret;
418
419 reset_control_deassert(priv->rstc);
420
421 return 0;
422 }
423
rcsi2_wait_phy_start(struct rcar_csi2 * priv,unsigned int lanes)424 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
425 unsigned int lanes)
426 {
427 unsigned int timeout;
428
429 /* Wait for the clock and data lanes to enter LP-11 state. */
430 for (timeout = 0; timeout <= 20; timeout++) {
431 const u32 lane_mask = (1 << lanes) - 1;
432
433 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
434 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
435 return 0;
436
437 usleep_range(1000, 2000);
438 }
439
440 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
441
442 return -ETIMEDOUT;
443 }
444
rcsi2_set_phypll(struct rcar_csi2 * priv,unsigned int mbps)445 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
446 {
447 const struct rcsi2_mbps_reg *hsfreq;
448 const struct rcsi2_mbps_reg *hsfreq_prev = NULL;
449
450 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) {
451 if (hsfreq->mbps >= mbps)
452 break;
453 hsfreq_prev = hsfreq;
454 }
455
456 if (!hsfreq->mbps) {
457 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
458 return -ERANGE;
459 }
460
461 if (hsfreq_prev &&
462 ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps)))
463 hsfreq = hsfreq_prev;
464
465 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg));
466
467 return 0;
468 }
469
rcsi2_calc_mbps(struct rcar_csi2 * priv,unsigned int bpp,unsigned int lanes)470 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
471 unsigned int lanes)
472 {
473 struct v4l2_subdev *source;
474 struct v4l2_ctrl *ctrl;
475 u64 mbps;
476
477 if (!priv->remote)
478 return -ENODEV;
479
480 source = priv->remote;
481
482 /* Read the pixel rate control from remote. */
483 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
484 if (!ctrl) {
485 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
486 source->name);
487 return -EINVAL;
488 }
489
490 /*
491 * Calculate the phypll in mbps.
492 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
493 * bps = link_freq * 2
494 */
495 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
496 do_div(mbps, lanes * 1000000);
497
498 return mbps;
499 }
500
rcsi2_get_active_lanes(struct rcar_csi2 * priv,unsigned int * lanes)501 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
502 unsigned int *lanes)
503 {
504 struct v4l2_mbus_config mbus_config = { 0 };
505 unsigned int num_lanes = UINT_MAX;
506 int ret;
507
508 *lanes = priv->lanes;
509
510 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
511 priv->remote_pad, &mbus_config);
512 if (ret == -ENOIOCTLCMD) {
513 dev_dbg(priv->dev, "No remote mbus configuration available\n");
514 return 0;
515 }
516
517 if (ret) {
518 dev_err(priv->dev, "Failed to get remote mbus configuration\n");
519 return ret;
520 }
521
522 if (mbus_config.type != V4L2_MBUS_CSI2_DPHY) {
523 dev_err(priv->dev, "Unsupported media bus type %u\n",
524 mbus_config.type);
525 return -EINVAL;
526 }
527
528 if (mbus_config.flags & V4L2_MBUS_CSI2_1_LANE)
529 num_lanes = 1;
530 else if (mbus_config.flags & V4L2_MBUS_CSI2_2_LANE)
531 num_lanes = 2;
532 else if (mbus_config.flags & V4L2_MBUS_CSI2_3_LANE)
533 num_lanes = 3;
534 else if (mbus_config.flags & V4L2_MBUS_CSI2_4_LANE)
535 num_lanes = 4;
536
537 if (num_lanes > priv->lanes) {
538 dev_err(priv->dev,
539 "Unsupported mbus config: too many data lanes %u\n",
540 num_lanes);
541 return -EINVAL;
542 }
543
544 *lanes = num_lanes;
545
546 return 0;
547 }
548
rcsi2_start_receiver(struct rcar_csi2 * priv)549 static int rcsi2_start_receiver(struct rcar_csi2 *priv)
550 {
551 const struct rcar_csi2_format *format;
552 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
553 unsigned int lanes;
554 unsigned int i;
555 int mbps, ret;
556
557 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
558 priv->mf.width, priv->mf.height,
559 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i');
560
561 /* Code is validated in set_fmt. */
562 format = rcsi2_code_to_fmt(priv->mf.code);
563 if (!format)
564 return -EINVAL;
565
566 /*
567 * Enable all supported CSI-2 channels with virtual channel and
568 * data type matching.
569 *
570 * NOTE: It's not possible to get individual datatype for each
571 * source virtual channel. Once this is possible in V4L2
572 * it should be used here.
573 */
574 for (i = 0; i < priv->info->num_channels; i++) {
575 u32 vcdt_part;
576
577 vcdt_part = VCDT_SEL_VC(i) | VCDT_VCDTN_EN | VCDT_SEL_DTN_ON |
578 VCDT_SEL_DT(format->datatype);
579
580 /* Store in correct reg and offset. */
581 if (i < 2)
582 vcdt |= vcdt_part << ((i % 2) * 16);
583 else
584 vcdt2 |= vcdt_part << ((i % 2) * 16);
585 }
586
587 if (priv->mf.field == V4L2_FIELD_ALTERNATE) {
588 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
589 | FLD_FLD_EN;
590
591 if (priv->mf.height == 240)
592 fld |= FLD_FLD_NUM(0);
593 else
594 fld |= FLD_FLD_NUM(1);
595 }
596
597 /*
598 * Get the number of active data lanes inspecting the remote mbus
599 * configuration.
600 */
601 ret = rcsi2_get_active_lanes(priv, &lanes);
602 if (ret)
603 return ret;
604
605 phycnt = PHYCNT_ENABLECLK;
606 phycnt |= (1 << lanes) - 1;
607
608 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
609 if (mbps < 0)
610 return mbps;
611
612 /* Enable interrupts. */
613 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
614 | INTEN_INT_ERRSOTSYNCHS);
615
616 /* Init */
617 rcsi2_write(priv, TREF_REG, TREF_TREF);
618 rcsi2_write(priv, PHTC_REG, 0);
619
620 /* Configure */
621 rcsi2_write(priv, VCDT_REG, vcdt);
622 if (vcdt2)
623 rcsi2_write(priv, VCDT2_REG, vcdt2);
624 /* Lanes are zero indexed. */
625 rcsi2_write(priv, LSWAP_REG,
626 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
627 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
628 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
629 LSWAP_L3SEL(priv->lane_swap[3] - 1));
630
631 /* Start */
632 if (priv->info->init_phtw) {
633 ret = priv->info->init_phtw(priv, mbps);
634 if (ret)
635 return ret;
636 }
637
638 if (priv->info->hsfreqrange) {
639 ret = rcsi2_set_phypll(priv, mbps);
640 if (ret)
641 return ret;
642 }
643
644 if (priv->info->csi0clkfreqrange)
645 rcsi2_write(priv, CSI0CLKFCPR_REG,
646 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
647
648 rcsi2_write(priv, PHYCNT_REG, phycnt);
649 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
650 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
651 rcsi2_write(priv, FLD_REG, fld);
652 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
653 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
654
655 ret = rcsi2_wait_phy_start(priv, lanes);
656 if (ret)
657 return ret;
658
659 /* Run post PHY start initialization, if needed. */
660 if (priv->info->phy_post_init) {
661 ret = priv->info->phy_post_init(priv);
662 if (ret)
663 return ret;
664 }
665
666 /* Clear Ultra Low Power interrupt. */
667 if (priv->info->clear_ulps)
668 rcsi2_write(priv, INTSTATE_REG,
669 INTSTATE_INT_ULPS_START |
670 INTSTATE_INT_ULPS_END);
671 return 0;
672 }
673
rcsi2_start(struct rcar_csi2 * priv)674 static int rcsi2_start(struct rcar_csi2 *priv)
675 {
676 int ret;
677
678 ret = rcsi2_exit_standby(priv);
679 if (ret < 0)
680 return ret;
681
682 ret = rcsi2_start_receiver(priv);
683 if (ret) {
684 rcsi2_enter_standby(priv);
685 return ret;
686 }
687
688 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
689 if (ret) {
690 rcsi2_enter_standby(priv);
691 return ret;
692 }
693
694 return 0;
695 }
696
rcsi2_stop(struct rcar_csi2 * priv)697 static void rcsi2_stop(struct rcar_csi2 *priv)
698 {
699 rcsi2_enter_standby(priv);
700 v4l2_subdev_call(priv->remote, video, s_stream, 0);
701 }
702
rcsi2_s_stream(struct v4l2_subdev * sd,int enable)703 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
704 {
705 struct rcar_csi2 *priv = sd_to_csi2(sd);
706 int ret = 0;
707
708 mutex_lock(&priv->lock);
709
710 if (!priv->remote) {
711 ret = -ENODEV;
712 goto out;
713 }
714
715 if (enable && priv->stream_count == 0) {
716 ret = rcsi2_start(priv);
717 if (ret)
718 goto out;
719 } else if (!enable && priv->stream_count == 1) {
720 rcsi2_stop(priv);
721 }
722
723 priv->stream_count += enable ? 1 : -1;
724 out:
725 mutex_unlock(&priv->lock);
726
727 return ret;
728 }
729
rcsi2_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)730 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
731 struct v4l2_subdev_state *sd_state,
732 struct v4l2_subdev_format *format)
733 {
734 struct rcar_csi2 *priv = sd_to_csi2(sd);
735 struct v4l2_mbus_framefmt *framefmt;
736
737 if (!rcsi2_code_to_fmt(format->format.code))
738 format->format.code = rcar_csi2_formats[0].code;
739
740 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
741 priv->mf = format->format;
742 } else {
743 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
744 *framefmt = format->format;
745 }
746
747 return 0;
748 }
749
rcsi2_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)750 static int rcsi2_get_pad_format(struct v4l2_subdev *sd,
751 struct v4l2_subdev_state *sd_state,
752 struct v4l2_subdev_format *format)
753 {
754 struct rcar_csi2 *priv = sd_to_csi2(sd);
755
756 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
757 format->format = priv->mf;
758 else
759 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
760
761 return 0;
762 }
763
764 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
765 .s_stream = rcsi2_s_stream,
766 };
767
768 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
769 .set_fmt = rcsi2_set_pad_format,
770 .get_fmt = rcsi2_get_pad_format,
771 };
772
773 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
774 .video = &rcar_csi2_video_ops,
775 .pad = &rcar_csi2_pad_ops,
776 };
777
rcsi2_irq(int irq,void * data)778 static irqreturn_t rcsi2_irq(int irq, void *data)
779 {
780 struct rcar_csi2 *priv = data;
781 u32 status, err_status;
782
783 status = rcsi2_read(priv, INTSTATE_REG);
784 err_status = rcsi2_read(priv, INTERRSTATE_REG);
785
786 if (!status)
787 return IRQ_HANDLED;
788
789 rcsi2_write(priv, INTSTATE_REG, status);
790
791 if (!err_status)
792 return IRQ_HANDLED;
793
794 rcsi2_write(priv, INTERRSTATE_REG, err_status);
795
796 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
797
798 return IRQ_WAKE_THREAD;
799 }
800
rcsi2_irq_thread(int irq,void * data)801 static irqreturn_t rcsi2_irq_thread(int irq, void *data)
802 {
803 struct rcar_csi2 *priv = data;
804
805 mutex_lock(&priv->lock);
806 rcsi2_stop(priv);
807 usleep_range(1000, 2000);
808 if (rcsi2_start(priv))
809 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
810 mutex_unlock(&priv->lock);
811
812 return IRQ_HANDLED;
813 }
814
815 /* -----------------------------------------------------------------------------
816 * Async handling and registration of subdevices and links.
817 */
818
rcsi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)819 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
820 struct v4l2_subdev *subdev,
821 struct v4l2_async_subdev *asd)
822 {
823 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
824 int pad;
825
826 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
827 MEDIA_PAD_FL_SOURCE);
828 if (pad < 0) {
829 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
830 return pad;
831 }
832
833 priv->remote = subdev;
834 priv->remote_pad = pad;
835
836 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
837
838 return media_create_pad_link(&subdev->entity, pad,
839 &priv->subdev.entity, 0,
840 MEDIA_LNK_FL_ENABLED |
841 MEDIA_LNK_FL_IMMUTABLE);
842 }
843
rcsi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)844 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
845 struct v4l2_subdev *subdev,
846 struct v4l2_async_subdev *asd)
847 {
848 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
849
850 priv->remote = NULL;
851
852 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
853 }
854
855 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
856 .bound = rcsi2_notify_bound,
857 .unbind = rcsi2_notify_unbind,
858 };
859
rcsi2_parse_v4l2(struct rcar_csi2 * priv,struct v4l2_fwnode_endpoint * vep)860 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
861 struct v4l2_fwnode_endpoint *vep)
862 {
863 unsigned int i;
864
865 /* Only port 0 endpoint 0 is valid. */
866 if (vep->base.port || vep->base.id)
867 return -ENOTCONN;
868
869 if (vep->bus_type != V4L2_MBUS_CSI2_DPHY) {
870 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
871 return -EINVAL;
872 }
873
874 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
875 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
876 dev_err(priv->dev, "Unsupported number of data-lanes: %u\n",
877 priv->lanes);
878 return -EINVAL;
879 }
880
881 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
882 priv->lane_swap[i] = i < priv->lanes ?
883 vep->bus.mipi_csi2.data_lanes[i] : i;
884
885 /* Check for valid lane number. */
886 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
887 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
888 return -EINVAL;
889 }
890 }
891
892 return 0;
893 }
894
rcsi2_parse_dt(struct rcar_csi2 * priv)895 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
896 {
897 struct v4l2_async_subdev *asd;
898 struct fwnode_handle *fwnode;
899 struct fwnode_handle *ep;
900 struct v4l2_fwnode_endpoint v4l2_ep = {
901 .bus_type = V4L2_MBUS_CSI2_DPHY
902 };
903 int ret;
904
905 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
906 if (!ep) {
907 dev_err(priv->dev, "Not connected to subdevice\n");
908 return -EINVAL;
909 }
910
911 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
912 if (ret) {
913 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
914 fwnode_handle_put(ep);
915 return -EINVAL;
916 }
917
918 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
919 if (ret) {
920 fwnode_handle_put(ep);
921 return ret;
922 }
923
924 fwnode = fwnode_graph_get_remote_endpoint(ep);
925 fwnode_handle_put(ep);
926
927 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
928
929 v4l2_async_notifier_init(&priv->notifier);
930 priv->notifier.ops = &rcar_csi2_notify_ops;
931
932 asd = v4l2_async_notifier_add_fwnode_subdev(&priv->notifier, fwnode,
933 struct v4l2_async_subdev);
934 fwnode_handle_put(fwnode);
935 if (IS_ERR(asd))
936 return PTR_ERR(asd);
937
938 ret = v4l2_async_subdev_notifier_register(&priv->subdev,
939 &priv->notifier);
940 if (ret)
941 v4l2_async_notifier_cleanup(&priv->notifier);
942
943 return ret;
944 }
945
946 /* -----------------------------------------------------------------------------
947 * PHTW initialization sequences.
948 *
949 * NOTE: Magic values are from the datasheet and lack documentation.
950 */
951
rcsi2_phtw_write(struct rcar_csi2 * priv,u16 data,u16 code)952 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code)
953 {
954 unsigned int timeout;
955
956 rcsi2_write(priv, PHTW_REG,
957 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
958 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
959
960 /* Wait for DWEN and CWEN to be cleared by hardware. */
961 for (timeout = 0; timeout <= 20; timeout++) {
962 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN)))
963 return 0;
964
965 usleep_range(1000, 2000);
966 }
967
968 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
969
970 return -ETIMEDOUT;
971 }
972
rcsi2_phtw_write_array(struct rcar_csi2 * priv,const struct phtw_value * values)973 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
974 const struct phtw_value *values)
975 {
976 const struct phtw_value *value;
977 int ret;
978
979 for (value = values; value->data || value->code; value++) {
980 ret = rcsi2_phtw_write(priv, value->data, value->code);
981 if (ret)
982 return ret;
983 }
984
985 return 0;
986 }
987
rcsi2_phtw_write_mbps(struct rcar_csi2 * priv,unsigned int mbps,const struct rcsi2_mbps_reg * values,u16 code)988 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
989 const struct rcsi2_mbps_reg *values, u16 code)
990 {
991 const struct rcsi2_mbps_reg *value;
992 const struct rcsi2_mbps_reg *prev_value = NULL;
993
994 for (value = values; value->mbps; value++) {
995 if (value->mbps >= mbps)
996 break;
997 prev_value = value;
998 }
999
1000 if (prev_value &&
1001 ((mbps - prev_value->mbps) <= (value->mbps - mbps)))
1002 value = prev_value;
1003
1004 if (!value->mbps) {
1005 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
1006 return -ERANGE;
1007 }
1008
1009 return rcsi2_phtw_write(priv, value->reg, code);
1010 }
1011
__rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1012 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
1013 unsigned int mbps)
1014 {
1015 static const struct phtw_value step1[] = {
1016 { .data = 0xcc, .code = 0xe2 },
1017 { .data = 0x01, .code = 0xe3 },
1018 { .data = 0x11, .code = 0xe4 },
1019 { .data = 0x01, .code = 0xe5 },
1020 { .data = 0x10, .code = 0x04 },
1021 { /* sentinel */ },
1022 };
1023
1024 static const struct phtw_value step2[] = {
1025 { .data = 0x38, .code = 0x08 },
1026 { .data = 0x01, .code = 0x00 },
1027 { .data = 0x4b, .code = 0xac },
1028 { .data = 0x03, .code = 0x00 },
1029 { .data = 0x80, .code = 0x07 },
1030 { /* sentinel */ },
1031 };
1032
1033 int ret;
1034
1035 ret = rcsi2_phtw_write_array(priv, step1);
1036 if (ret)
1037 return ret;
1038
1039 if (mbps != 0 && mbps <= 250) {
1040 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
1041 if (ret)
1042 return ret;
1043
1044 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
1045 0xf1);
1046 if (ret)
1047 return ret;
1048 }
1049
1050 return rcsi2_phtw_write_array(priv, step2);
1051 }
1052
rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1053 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
1054 {
1055 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
1056 }
1057
rcsi2_init_phtw_h3es2(struct rcar_csi2 * priv,unsigned int mbps)1058 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
1059 {
1060 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
1061 }
1062
rcsi2_init_phtw_v3m_e3(struct rcar_csi2 * priv,unsigned int mbps)1063 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
1064 {
1065 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
1066 }
1067
rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 * priv)1068 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
1069 {
1070 static const struct phtw_value step1[] = {
1071 { .data = 0xee, .code = 0x34 },
1072 { .data = 0xee, .code = 0x44 },
1073 { .data = 0xee, .code = 0x54 },
1074 { .data = 0xee, .code = 0x84 },
1075 { .data = 0xee, .code = 0x94 },
1076 { /* sentinel */ },
1077 };
1078
1079 return rcsi2_phtw_write_array(priv, step1);
1080 }
1081
1082 /* -----------------------------------------------------------------------------
1083 * Platform Device Driver.
1084 */
1085
1086 static const struct media_entity_operations rcar_csi2_entity_ops = {
1087 .link_validate = v4l2_subdev_link_validate,
1088 };
1089
rcsi2_probe_resources(struct rcar_csi2 * priv,struct platform_device * pdev)1090 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
1091 struct platform_device *pdev)
1092 {
1093 struct resource *res;
1094 int irq, ret;
1095
1096 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1097 priv->base = devm_ioremap_resource(&pdev->dev, res);
1098 if (IS_ERR(priv->base))
1099 return PTR_ERR(priv->base);
1100
1101 irq = platform_get_irq(pdev, 0);
1102 if (irq < 0)
1103 return irq;
1104
1105 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
1106 rcsi2_irq_thread, IRQF_SHARED,
1107 KBUILD_MODNAME, priv);
1108 if (ret)
1109 return ret;
1110
1111 priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
1112
1113 return PTR_ERR_OR_ZERO(priv->rstc);
1114 }
1115
1116 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
1117 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1118 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1119 .csi0clkfreqrange = 0x20,
1120 .num_channels = 4,
1121 .clear_ulps = true,
1122 };
1123
1124 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es1 = {
1125 .hsfreqrange = hsfreqrange_m3w_h3es1,
1126 .num_channels = 4,
1127 };
1128
1129 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
1130 .init_phtw = rcsi2_init_phtw_h3es2,
1131 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1132 .csi0clkfreqrange = 0x20,
1133 .num_channels = 4,
1134 .clear_ulps = true,
1135 };
1136
1137 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
1138 .hsfreqrange = hsfreqrange_m3w_h3es1,
1139 .num_channels = 4,
1140 };
1141
1142 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {
1143 .hsfreqrange = hsfreqrange_m3w_h3es1,
1144 .num_channels = 4,
1145 };
1146
1147 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
1148 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1149 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1150 .csi0clkfreqrange = 0x20,
1151 .num_channels = 4,
1152 .clear_ulps = true,
1153 };
1154
1155 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
1156 .init_phtw = rcsi2_init_phtw_v3m_e3,
1157 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1158 .num_channels = 4,
1159 };
1160
1161 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
1162 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
1163 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
1164 .csi0clkfreqrange = 0x20,
1165 .clear_ulps = true,
1166 };
1167
1168 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
1169 .init_phtw = rcsi2_init_phtw_v3m_e3,
1170 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
1171 .num_channels = 2,
1172 };
1173
1174 static const struct of_device_id rcar_csi2_of_table[] = {
1175 {
1176 .compatible = "renesas,r8a774a1-csi2",
1177 .data = &rcar_csi2_info_r8a7796,
1178 },
1179 {
1180 .compatible = "renesas,r8a774b1-csi2",
1181 .data = &rcar_csi2_info_r8a77965,
1182 },
1183 {
1184 .compatible = "renesas,r8a774c0-csi2",
1185 .data = &rcar_csi2_info_r8a77990,
1186 },
1187 {
1188 .compatible = "renesas,r8a774e1-csi2",
1189 .data = &rcar_csi2_info_r8a7795,
1190 },
1191 {
1192 .compatible = "renesas,r8a7795-csi2",
1193 .data = &rcar_csi2_info_r8a7795,
1194 },
1195 {
1196 .compatible = "renesas,r8a7796-csi2",
1197 .data = &rcar_csi2_info_r8a7796,
1198 },
1199 {
1200 .compatible = "renesas,r8a77961-csi2",
1201 .data = &rcar_csi2_info_r8a77961,
1202 },
1203 {
1204 .compatible = "renesas,r8a77965-csi2",
1205 .data = &rcar_csi2_info_r8a77965,
1206 },
1207 {
1208 .compatible = "renesas,r8a77970-csi2",
1209 .data = &rcar_csi2_info_r8a77970,
1210 },
1211 {
1212 .compatible = "renesas,r8a77980-csi2",
1213 .data = &rcar_csi2_info_r8a77980,
1214 },
1215 {
1216 .compatible = "renesas,r8a77990-csi2",
1217 .data = &rcar_csi2_info_r8a77990,
1218 },
1219 { /* sentinel */ },
1220 };
1221 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
1222
1223 static const struct soc_device_attribute r8a7795[] = {
1224 {
1225 .soc_id = "r8a7795", .revision = "ES1.*",
1226 .data = &rcar_csi2_info_r8a7795es1,
1227 },
1228 {
1229 .soc_id = "r8a7795", .revision = "ES2.*",
1230 .data = &rcar_csi2_info_r8a7795es2,
1231 },
1232 { /* sentinel */ },
1233 };
1234
rcsi2_probe(struct platform_device * pdev)1235 static int rcsi2_probe(struct platform_device *pdev)
1236 {
1237 const struct soc_device_attribute *attr;
1238 struct rcar_csi2 *priv;
1239 unsigned int i;
1240 int ret;
1241
1242 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1243 if (!priv)
1244 return -ENOMEM;
1245
1246 priv->info = of_device_get_match_data(&pdev->dev);
1247
1248 /*
1249 * The different ES versions of r8a7795 (H3) behave differently but
1250 * share the same compatible string.
1251 */
1252 attr = soc_device_match(r8a7795);
1253 if (attr)
1254 priv->info = attr->data;
1255
1256 priv->dev = &pdev->dev;
1257
1258 mutex_init(&priv->lock);
1259 priv->stream_count = 0;
1260
1261 ret = rcsi2_probe_resources(priv, pdev);
1262 if (ret) {
1263 dev_err(priv->dev, "Failed to get resources\n");
1264 return ret;
1265 }
1266
1267 platform_set_drvdata(pdev, priv);
1268
1269 ret = rcsi2_parse_dt(priv);
1270 if (ret)
1271 return ret;
1272
1273 priv->subdev.owner = THIS_MODULE;
1274 priv->subdev.dev = &pdev->dev;
1275 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
1276 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
1277 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s",
1278 KBUILD_MODNAME, dev_name(&pdev->dev));
1279 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
1280
1281 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1282 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
1283
1284 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
1285 for (i = RCAR_CSI2_SOURCE_VC0; i < NR_OF_RCAR_CSI2_PAD; i++)
1286 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
1287
1288 ret = media_entity_pads_init(&priv->subdev.entity, NR_OF_RCAR_CSI2_PAD,
1289 priv->pads);
1290 if (ret)
1291 goto error;
1292
1293 pm_runtime_enable(&pdev->dev);
1294
1295 ret = v4l2_async_register_subdev(&priv->subdev);
1296 if (ret < 0)
1297 goto error;
1298
1299 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
1300
1301 return 0;
1302
1303 error:
1304 v4l2_async_notifier_unregister(&priv->notifier);
1305 v4l2_async_notifier_cleanup(&priv->notifier);
1306
1307 return ret;
1308 }
1309
rcsi2_remove(struct platform_device * pdev)1310 static int rcsi2_remove(struct platform_device *pdev)
1311 {
1312 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
1313
1314 v4l2_async_notifier_unregister(&priv->notifier);
1315 v4l2_async_notifier_cleanup(&priv->notifier);
1316 v4l2_async_unregister_subdev(&priv->subdev);
1317
1318 pm_runtime_disable(&pdev->dev);
1319
1320 return 0;
1321 }
1322
1323 static struct platform_driver rcar_csi2_pdrv = {
1324 .remove = rcsi2_remove,
1325 .probe = rcsi2_probe,
1326 .driver = {
1327 .name = "rcar-csi2",
1328 .of_match_table = rcar_csi2_of_table,
1329 },
1330 };
1331
1332 module_platform_driver(rcar_csi2_pdrv);
1333
1334 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>");
1335 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
1336 MODULE_LICENSE("GPL");
1337