1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Rockchip ISP1 Driver - V4l resizer device
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 *
7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
9 */
10
11 #include "rkisp1-common.h"
12
13 #define RKISP1_RSZ_SP_DEV_NAME RKISP1_DRIVER_NAME "_resizer_selfpath"
14 #define RKISP1_RSZ_MP_DEV_NAME RKISP1_DRIVER_NAME "_resizer_mainpath"
15
16 #define RKISP1_DEF_FMT MEDIA_BUS_FMT_YUYV8_2X8
17 #define RKISP1_DEF_PIXEL_ENC V4L2_PIXEL_ENC_YUV
18
19 struct rkisp1_rsz_yuv_mbus_info {
20 u32 mbus_code;
21 u32 hdiv;
22 u32 vdiv;
23 };
24
25 static const struct rkisp1_rsz_yuv_mbus_info rkisp1_rsz_yuv_src_formats[] = {
26 {
27 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, /* YUV422 */
28 .hdiv = 2,
29 .vdiv = 1,
30 },
31 {
32 .mbus_code = MEDIA_BUS_FMT_YUYV8_1_5X8, /* YUV420 */
33 .hdiv = 2,
34 .vdiv = 2,
35 },
36 };
37
rkisp1_rsz_get_yuv_mbus_info(u32 mbus_code)38 static const struct rkisp1_rsz_yuv_mbus_info *rkisp1_rsz_get_yuv_mbus_info(u32 mbus_code)
39 {
40 unsigned int i;
41
42 for (i = 0; i < ARRAY_SIZE(rkisp1_rsz_yuv_src_formats); i++) {
43 if (rkisp1_rsz_yuv_src_formats[i].mbus_code == mbus_code)
44 return &rkisp1_rsz_yuv_src_formats[i];
45 }
46
47 return NULL;
48 }
49
50 enum rkisp1_shadow_regs_when {
51 RKISP1_SHADOW_REGS_SYNC,
52 RKISP1_SHADOW_REGS_ASYNC,
53 };
54
55 struct rkisp1_rsz_config {
56 /* constrains */
57 const int max_rsz_width;
58 const int max_rsz_height;
59 const int min_rsz_width;
60 const int min_rsz_height;
61 /* registers */
62 struct {
63 u32 ctrl;
64 u32 ctrl_shd;
65 u32 scale_hy;
66 u32 scale_hcr;
67 u32 scale_hcb;
68 u32 scale_vy;
69 u32 scale_vc;
70 u32 scale_lut;
71 u32 scale_lut_addr;
72 u32 scale_hy_shd;
73 u32 scale_hcr_shd;
74 u32 scale_hcb_shd;
75 u32 scale_vy_shd;
76 u32 scale_vc_shd;
77 u32 phase_hy;
78 u32 phase_hc;
79 u32 phase_vy;
80 u32 phase_vc;
81 u32 phase_hy_shd;
82 u32 phase_hc_shd;
83 u32 phase_vy_shd;
84 u32 phase_vc_shd;
85 } rsz;
86 struct {
87 u32 ctrl;
88 u32 yuvmode_mask;
89 u32 rawmode_mask;
90 u32 h_offset;
91 u32 v_offset;
92 u32 h_size;
93 u32 v_size;
94 } dual_crop;
95 };
96
97 static const struct rkisp1_rsz_config rkisp1_rsz_config_mp = {
98 /* constraints */
99 .max_rsz_width = RKISP1_RSZ_MP_SRC_MAX_WIDTH,
100 .max_rsz_height = RKISP1_RSZ_MP_SRC_MAX_HEIGHT,
101 .min_rsz_width = RKISP1_RSZ_SRC_MIN_WIDTH,
102 .min_rsz_height = RKISP1_RSZ_SRC_MIN_HEIGHT,
103 /* registers */
104 .rsz = {
105 .ctrl = RKISP1_CIF_MRSZ_CTRL,
106 .scale_hy = RKISP1_CIF_MRSZ_SCALE_HY,
107 .scale_hcr = RKISP1_CIF_MRSZ_SCALE_HCR,
108 .scale_hcb = RKISP1_CIF_MRSZ_SCALE_HCB,
109 .scale_vy = RKISP1_CIF_MRSZ_SCALE_VY,
110 .scale_vc = RKISP1_CIF_MRSZ_SCALE_VC,
111 .scale_lut = RKISP1_CIF_MRSZ_SCALE_LUT,
112 .scale_lut_addr = RKISP1_CIF_MRSZ_SCALE_LUT_ADDR,
113 .scale_hy_shd = RKISP1_CIF_MRSZ_SCALE_HY_SHD,
114 .scale_hcr_shd = RKISP1_CIF_MRSZ_SCALE_HCR_SHD,
115 .scale_hcb_shd = RKISP1_CIF_MRSZ_SCALE_HCB_SHD,
116 .scale_vy_shd = RKISP1_CIF_MRSZ_SCALE_VY_SHD,
117 .scale_vc_shd = RKISP1_CIF_MRSZ_SCALE_VC_SHD,
118 .phase_hy = RKISP1_CIF_MRSZ_PHASE_HY,
119 .phase_hc = RKISP1_CIF_MRSZ_PHASE_HC,
120 .phase_vy = RKISP1_CIF_MRSZ_PHASE_VY,
121 .phase_vc = RKISP1_CIF_MRSZ_PHASE_VC,
122 .ctrl_shd = RKISP1_CIF_MRSZ_CTRL_SHD,
123 .phase_hy_shd = RKISP1_CIF_MRSZ_PHASE_HY_SHD,
124 .phase_hc_shd = RKISP1_CIF_MRSZ_PHASE_HC_SHD,
125 .phase_vy_shd = RKISP1_CIF_MRSZ_PHASE_VY_SHD,
126 .phase_vc_shd = RKISP1_CIF_MRSZ_PHASE_VC_SHD,
127 },
128 .dual_crop = {
129 .ctrl = RKISP1_CIF_DUAL_CROP_CTRL,
130 .yuvmode_mask = RKISP1_CIF_DUAL_CROP_MP_MODE_YUV,
131 .rawmode_mask = RKISP1_CIF_DUAL_CROP_MP_MODE_RAW,
132 .h_offset = RKISP1_CIF_DUAL_CROP_M_H_OFFS,
133 .v_offset = RKISP1_CIF_DUAL_CROP_M_V_OFFS,
134 .h_size = RKISP1_CIF_DUAL_CROP_M_H_SIZE,
135 .v_size = RKISP1_CIF_DUAL_CROP_M_V_SIZE,
136 },
137 };
138
139 static const struct rkisp1_rsz_config rkisp1_rsz_config_sp = {
140 /* constraints */
141 .max_rsz_width = RKISP1_RSZ_SP_SRC_MAX_WIDTH,
142 .max_rsz_height = RKISP1_RSZ_SP_SRC_MAX_HEIGHT,
143 .min_rsz_width = RKISP1_RSZ_SRC_MIN_WIDTH,
144 .min_rsz_height = RKISP1_RSZ_SRC_MIN_HEIGHT,
145 /* registers */
146 .rsz = {
147 .ctrl = RKISP1_CIF_SRSZ_CTRL,
148 .scale_hy = RKISP1_CIF_SRSZ_SCALE_HY,
149 .scale_hcr = RKISP1_CIF_SRSZ_SCALE_HCR,
150 .scale_hcb = RKISP1_CIF_SRSZ_SCALE_HCB,
151 .scale_vy = RKISP1_CIF_SRSZ_SCALE_VY,
152 .scale_vc = RKISP1_CIF_SRSZ_SCALE_VC,
153 .scale_lut = RKISP1_CIF_SRSZ_SCALE_LUT,
154 .scale_lut_addr = RKISP1_CIF_SRSZ_SCALE_LUT_ADDR,
155 .scale_hy_shd = RKISP1_CIF_SRSZ_SCALE_HY_SHD,
156 .scale_hcr_shd = RKISP1_CIF_SRSZ_SCALE_HCR_SHD,
157 .scale_hcb_shd = RKISP1_CIF_SRSZ_SCALE_HCB_SHD,
158 .scale_vy_shd = RKISP1_CIF_SRSZ_SCALE_VY_SHD,
159 .scale_vc_shd = RKISP1_CIF_SRSZ_SCALE_VC_SHD,
160 .phase_hy = RKISP1_CIF_SRSZ_PHASE_HY,
161 .phase_hc = RKISP1_CIF_SRSZ_PHASE_HC,
162 .phase_vy = RKISP1_CIF_SRSZ_PHASE_VY,
163 .phase_vc = RKISP1_CIF_SRSZ_PHASE_VC,
164 .ctrl_shd = RKISP1_CIF_SRSZ_CTRL_SHD,
165 .phase_hy_shd = RKISP1_CIF_SRSZ_PHASE_HY_SHD,
166 .phase_hc_shd = RKISP1_CIF_SRSZ_PHASE_HC_SHD,
167 .phase_vy_shd = RKISP1_CIF_SRSZ_PHASE_VY_SHD,
168 .phase_vc_shd = RKISP1_CIF_SRSZ_PHASE_VC_SHD,
169 },
170 .dual_crop = {
171 .ctrl = RKISP1_CIF_DUAL_CROP_CTRL,
172 .yuvmode_mask = RKISP1_CIF_DUAL_CROP_SP_MODE_YUV,
173 .rawmode_mask = RKISP1_CIF_DUAL_CROP_SP_MODE_RAW,
174 .h_offset = RKISP1_CIF_DUAL_CROP_S_H_OFFS,
175 .v_offset = RKISP1_CIF_DUAL_CROP_S_V_OFFS,
176 .h_size = RKISP1_CIF_DUAL_CROP_S_H_SIZE,
177 .v_size = RKISP1_CIF_DUAL_CROP_S_V_SIZE,
178 },
179 };
180
181 static struct v4l2_mbus_framefmt *
rkisp1_rsz_get_pad_fmt(struct rkisp1_resizer * rsz,struct v4l2_subdev_state * sd_state,unsigned int pad,u32 which)182 rkisp1_rsz_get_pad_fmt(struct rkisp1_resizer *rsz,
183 struct v4l2_subdev_state *sd_state,
184 unsigned int pad, u32 which)
185 {
186 struct v4l2_subdev_state state = {
187 .pads = rsz->pad_cfg
188 };
189 if (which == V4L2_SUBDEV_FORMAT_TRY)
190 return v4l2_subdev_get_try_format(&rsz->sd, sd_state, pad);
191 else
192 return v4l2_subdev_get_try_format(&rsz->sd, &state, pad);
193 }
194
195 static struct v4l2_rect *
rkisp1_rsz_get_pad_crop(struct rkisp1_resizer * rsz,struct v4l2_subdev_state * sd_state,unsigned int pad,u32 which)196 rkisp1_rsz_get_pad_crop(struct rkisp1_resizer *rsz,
197 struct v4l2_subdev_state *sd_state,
198 unsigned int pad, u32 which)
199 {
200 struct v4l2_subdev_state state = {
201 .pads = rsz->pad_cfg
202 };
203 if (which == V4L2_SUBDEV_FORMAT_TRY)
204 return v4l2_subdev_get_try_crop(&rsz->sd, sd_state, pad);
205 else
206 return v4l2_subdev_get_try_crop(&rsz->sd, &state, pad);
207 }
208
209 /* ----------------------------------------------------------------------------
210 * Dual crop hw configs
211 */
212
rkisp1_dcrop_disable(struct rkisp1_resizer * rsz,enum rkisp1_shadow_regs_when when)213 static void rkisp1_dcrop_disable(struct rkisp1_resizer *rsz,
214 enum rkisp1_shadow_regs_when when)
215 {
216 u32 dc_ctrl = rkisp1_read(rsz->rkisp1, rsz->config->dual_crop.ctrl);
217 u32 mask = ~(rsz->config->dual_crop.yuvmode_mask |
218 rsz->config->dual_crop.rawmode_mask);
219
220 dc_ctrl &= mask;
221 if (when == RKISP1_SHADOW_REGS_ASYNC)
222 dc_ctrl |= RKISP1_CIF_DUAL_CROP_GEN_CFG_UPD;
223 else
224 dc_ctrl |= RKISP1_CIF_DUAL_CROP_CFG_UPD;
225 rkisp1_write(rsz->rkisp1, dc_ctrl, rsz->config->dual_crop.ctrl);
226 }
227
228 /* configure dual-crop unit */
rkisp1_dcrop_config(struct rkisp1_resizer * rsz)229 static void rkisp1_dcrop_config(struct rkisp1_resizer *rsz)
230 {
231 struct rkisp1_device *rkisp1 = rsz->rkisp1;
232 struct v4l2_mbus_framefmt *sink_fmt;
233 struct v4l2_rect *sink_crop;
234 u32 dc_ctrl;
235
236 sink_crop = rkisp1_rsz_get_pad_crop(rsz, NULL, RKISP1_RSZ_PAD_SINK,
237 V4L2_SUBDEV_FORMAT_ACTIVE);
238 sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, NULL, RKISP1_RSZ_PAD_SINK,
239 V4L2_SUBDEV_FORMAT_ACTIVE);
240
241 if (sink_crop->width == sink_fmt->width &&
242 sink_crop->height == sink_fmt->height &&
243 sink_crop->left == 0 && sink_crop->top == 0) {
244 rkisp1_dcrop_disable(rsz, RKISP1_SHADOW_REGS_SYNC);
245 dev_dbg(rkisp1->dev, "capture %d crop disabled\n", rsz->id);
246 return;
247 }
248
249 dc_ctrl = rkisp1_read(rkisp1, rsz->config->dual_crop.ctrl);
250 rkisp1_write(rkisp1, sink_crop->left, rsz->config->dual_crop.h_offset);
251 rkisp1_write(rkisp1, sink_crop->top, rsz->config->dual_crop.v_offset);
252 rkisp1_write(rkisp1, sink_crop->width, rsz->config->dual_crop.h_size);
253 rkisp1_write(rkisp1, sink_crop->height, rsz->config->dual_crop.v_size);
254 dc_ctrl |= rsz->config->dual_crop.yuvmode_mask;
255 dc_ctrl |= RKISP1_CIF_DUAL_CROP_CFG_UPD;
256 rkisp1_write(rkisp1, dc_ctrl, rsz->config->dual_crop.ctrl);
257
258 dev_dbg(rkisp1->dev, "stream %d crop: %dx%d -> %dx%d\n", rsz->id,
259 sink_fmt->width, sink_fmt->height,
260 sink_crop->width, sink_crop->height);
261 }
262
263 /* ----------------------------------------------------------------------------
264 * Resizer hw configs
265 */
266
rkisp1_rsz_dump_regs(struct rkisp1_resizer * rsz)267 static void rkisp1_rsz_dump_regs(struct rkisp1_resizer *rsz)
268 {
269 dev_dbg(rsz->rkisp1->dev,
270 "RSZ_CTRL 0x%08x/0x%08x\n"
271 "RSZ_SCALE_HY %d/%d\n"
272 "RSZ_SCALE_HCB %d/%d\n"
273 "RSZ_SCALE_HCR %d/%d\n"
274 "RSZ_SCALE_VY %d/%d\n"
275 "RSZ_SCALE_VC %d/%d\n"
276 "RSZ_PHASE_HY %d/%d\n"
277 "RSZ_PHASE_HC %d/%d\n"
278 "RSZ_PHASE_VY %d/%d\n"
279 "RSZ_PHASE_VC %d/%d\n",
280 rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl),
281 rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl_shd),
282 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hy),
283 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hy_shd),
284 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcb),
285 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcb_shd),
286 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcr),
287 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_hcr_shd),
288 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vy),
289 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vy_shd),
290 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vc),
291 rkisp1_read(rsz->rkisp1, rsz->config->rsz.scale_vc_shd),
292 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hy),
293 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hy_shd),
294 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hc),
295 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_hc_shd),
296 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vy),
297 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vy_shd),
298 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vc),
299 rkisp1_read(rsz->rkisp1, rsz->config->rsz.phase_vc_shd));
300 }
301
rkisp1_rsz_update_shadow(struct rkisp1_resizer * rsz,enum rkisp1_shadow_regs_when when)302 static void rkisp1_rsz_update_shadow(struct rkisp1_resizer *rsz,
303 enum rkisp1_shadow_regs_when when)
304 {
305 u32 ctrl_cfg = rkisp1_read(rsz->rkisp1, rsz->config->rsz.ctrl);
306
307 if (when == RKISP1_SHADOW_REGS_ASYNC)
308 ctrl_cfg |= RKISP1_CIF_RSZ_CTRL_CFG_UPD_AUTO;
309 else
310 ctrl_cfg |= RKISP1_CIF_RSZ_CTRL_CFG_UPD;
311
312 rkisp1_write(rsz->rkisp1, ctrl_cfg, rsz->config->rsz.ctrl);
313 }
314
rkisp1_rsz_calc_ratio(u32 len_sink,u32 len_src)315 static u32 rkisp1_rsz_calc_ratio(u32 len_sink, u32 len_src)
316 {
317 if (len_sink < len_src)
318 return ((len_sink - 1) * RKISP1_CIF_RSZ_SCALER_FACTOR) /
319 (len_src - 1);
320
321 return ((len_src - 1) * RKISP1_CIF_RSZ_SCALER_FACTOR) /
322 (len_sink - 1) + 1;
323 }
324
rkisp1_rsz_disable(struct rkisp1_resizer * rsz,enum rkisp1_shadow_regs_when when)325 static void rkisp1_rsz_disable(struct rkisp1_resizer *rsz,
326 enum rkisp1_shadow_regs_when when)
327 {
328 rkisp1_write(rsz->rkisp1, 0, rsz->config->rsz.ctrl);
329
330 if (when == RKISP1_SHADOW_REGS_SYNC)
331 rkisp1_rsz_update_shadow(rsz, when);
332 }
333
rkisp1_rsz_config_regs(struct rkisp1_resizer * rsz,struct v4l2_rect * sink_y,struct v4l2_rect * sink_c,struct v4l2_rect * src_y,struct v4l2_rect * src_c,enum rkisp1_shadow_regs_when when)334 static void rkisp1_rsz_config_regs(struct rkisp1_resizer *rsz,
335 struct v4l2_rect *sink_y,
336 struct v4l2_rect *sink_c,
337 struct v4l2_rect *src_y,
338 struct v4l2_rect *src_c,
339 enum rkisp1_shadow_regs_when when)
340 {
341 struct rkisp1_device *rkisp1 = rsz->rkisp1;
342 u32 ratio, rsz_ctrl = 0;
343 unsigned int i;
344
345 /* No phase offset */
346 rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_hy);
347 rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_hc);
348 rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_vy);
349 rkisp1_write(rkisp1, 0, rsz->config->rsz.phase_vc);
350
351 /* Linear interpolation */
352 for (i = 0; i < 64; i++) {
353 rkisp1_write(rkisp1, i, rsz->config->rsz.scale_lut_addr);
354 rkisp1_write(rkisp1, i, rsz->config->rsz.scale_lut);
355 }
356
357 if (sink_y->width != src_y->width) {
358 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HY_ENABLE;
359 if (sink_y->width < src_y->width)
360 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HY_UP;
361 ratio = rkisp1_rsz_calc_ratio(sink_y->width, src_y->width);
362 rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_hy);
363 }
364
365 if (sink_c->width != src_c->width) {
366 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HC_ENABLE;
367 if (sink_c->width < src_c->width)
368 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_HC_UP;
369 ratio = rkisp1_rsz_calc_ratio(sink_c->width, src_c->width);
370 rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_hcb);
371 rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_hcr);
372 }
373
374 if (sink_y->height != src_y->height) {
375 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VY_ENABLE;
376 if (sink_y->height < src_y->height)
377 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VY_UP;
378 ratio = rkisp1_rsz_calc_ratio(sink_y->height, src_y->height);
379 rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_vy);
380 }
381
382 if (sink_c->height != src_c->height) {
383 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VC_ENABLE;
384 if (sink_c->height < src_c->height)
385 rsz_ctrl |= RKISP1_CIF_RSZ_CTRL_SCALE_VC_UP;
386 ratio = rkisp1_rsz_calc_ratio(sink_c->height, src_c->height);
387 rkisp1_write(rkisp1, ratio, rsz->config->rsz.scale_vc);
388 }
389
390 rkisp1_write(rkisp1, rsz_ctrl, rsz->config->rsz.ctrl);
391
392 rkisp1_rsz_update_shadow(rsz, when);
393 }
394
rkisp1_rsz_config(struct rkisp1_resizer * rsz,enum rkisp1_shadow_regs_when when)395 static void rkisp1_rsz_config(struct rkisp1_resizer *rsz,
396 enum rkisp1_shadow_regs_when when)
397 {
398 const struct rkisp1_rsz_yuv_mbus_info *sink_yuv_info, *src_yuv_info;
399 struct v4l2_rect sink_y, sink_c, src_y, src_c;
400 struct v4l2_mbus_framefmt *src_fmt, *sink_fmt;
401 struct v4l2_rect *sink_crop;
402
403 sink_crop = rkisp1_rsz_get_pad_crop(rsz, NULL, RKISP1_RSZ_PAD_SINK,
404 V4L2_SUBDEV_FORMAT_ACTIVE);
405 src_fmt = rkisp1_rsz_get_pad_fmt(rsz, NULL, RKISP1_RSZ_PAD_SRC,
406 V4L2_SUBDEV_FORMAT_ACTIVE);
407 src_yuv_info = rkisp1_rsz_get_yuv_mbus_info(src_fmt->code);
408 sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, NULL, RKISP1_RSZ_PAD_SINK,
409 V4L2_SUBDEV_FORMAT_ACTIVE);
410 sink_yuv_info = rkisp1_rsz_get_yuv_mbus_info(sink_fmt->code);
411
412 /*
413 * The resizer only works on yuv formats,
414 * so return if it is bayer format.
415 */
416 if (rsz->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
417 rkisp1_rsz_disable(rsz, when);
418 return;
419 }
420
421 sink_y.width = sink_crop->width;
422 sink_y.height = sink_crop->height;
423 src_y.width = src_fmt->width;
424 src_y.height = src_fmt->height;
425
426 sink_c.width = sink_y.width / sink_yuv_info->hdiv;
427 sink_c.height = sink_y.height / sink_yuv_info->vdiv;
428
429 /*
430 * The resizer is used not only to change the dimensions of the frame
431 * but also to change the scale for YUV formats,
432 * (4:2:2 -> 4:2:0 for example). So the width/height of the CbCr
433 * streams should be set according to the media bus format in the src pad.
434 */
435 src_c.width = src_y.width / src_yuv_info->hdiv;
436 src_c.height = src_y.height / src_yuv_info->vdiv;
437
438 if (sink_c.width == src_c.width && sink_c.height == src_c.height) {
439 rkisp1_rsz_disable(rsz, when);
440 return;
441 }
442
443 dev_dbg(rsz->rkisp1->dev, "stream %d rsz/scale: %dx%d -> %dx%d\n",
444 rsz->id, sink_crop->width, sink_crop->height,
445 src_fmt->width, src_fmt->height);
446 dev_dbg(rsz->rkisp1->dev, "chroma scaling %dx%d -> %dx%d\n",
447 sink_c.width, sink_c.height, src_c.width, src_c.height);
448
449 /* set values in the hw */
450 rkisp1_rsz_config_regs(rsz, &sink_y, &sink_c, &src_y, &src_c, when);
451
452 rkisp1_rsz_dump_regs(rsz);
453 }
454
455 /* ----------------------------------------------------------------------------
456 * Subdev pad operations
457 */
458
rkisp1_rsz_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)459 static int rkisp1_rsz_enum_mbus_code(struct v4l2_subdev *sd,
460 struct v4l2_subdev_state *sd_state,
461 struct v4l2_subdev_mbus_code_enum *code)
462 {
463 struct rkisp1_resizer *rsz =
464 container_of(sd, struct rkisp1_resizer, sd);
465 struct v4l2_subdev_pad_config dummy_cfg;
466 struct v4l2_subdev_state pad_state = {
467 .pads = &dummy_cfg
468 };
469 u32 pad = code->pad;
470 int ret;
471
472 if (code->pad == RKISP1_RSZ_PAD_SRC) {
473 /* supported mbus codes on the src are the same as in the capture */
474 struct rkisp1_capture *cap = &rsz->rkisp1->capture_devs[rsz->id];
475
476 return rkisp1_cap_enum_mbus_codes(cap, code);
477 }
478
479 /*
480 * The selfpath capture doesn't support bayer formats. Therefore the selfpath resizer
481 * should support only YUV422 on the sink pad
482 */
483 if (rsz->id == RKISP1_SELFPATH) {
484 if (code->index > 0)
485 return -EINVAL;
486 code->code = MEDIA_BUS_FMT_YUYV8_2X8;
487 return 0;
488 }
489
490 /* supported mbus codes on the sink pad are the same as isp src pad */
491 code->pad = RKISP1_ISP_PAD_SOURCE_VIDEO;
492 ret = v4l2_subdev_call(&rsz->rkisp1->isp.sd, pad, enum_mbus_code,
493 &pad_state, code);
494
495 /* restore pad */
496 code->pad = pad;
497 code->flags = 0;
498 return ret;
499 }
500
rkisp1_rsz_init_config(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)501 static int rkisp1_rsz_init_config(struct v4l2_subdev *sd,
502 struct v4l2_subdev_state *sd_state)
503 {
504 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
505 struct v4l2_rect *sink_crop;
506
507 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state,
508 RKISP1_RSZ_PAD_SRC);
509 sink_fmt->width = RKISP1_DEFAULT_WIDTH;
510 sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
511 sink_fmt->field = V4L2_FIELD_NONE;
512 sink_fmt->code = RKISP1_DEF_FMT;
513 sink_fmt->colorspace = V4L2_COLORSPACE_SRGB;
514 sink_fmt->xfer_func = V4L2_XFER_FUNC_SRGB;
515 sink_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
516 sink_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE;
517
518 sink_crop = v4l2_subdev_get_try_crop(sd, sd_state,
519 RKISP1_RSZ_PAD_SINK);
520 sink_crop->width = RKISP1_DEFAULT_WIDTH;
521 sink_crop->height = RKISP1_DEFAULT_HEIGHT;
522 sink_crop->left = 0;
523 sink_crop->top = 0;
524
525 src_fmt = v4l2_subdev_get_try_format(sd, sd_state,
526 RKISP1_RSZ_PAD_SINK);
527 *src_fmt = *sink_fmt;
528
529 /* NOTE: there is no crop in the source pad, only in the sink */
530
531 return 0;
532 }
533
rkisp1_rsz_set_src_fmt(struct rkisp1_resizer * rsz,struct v4l2_subdev_state * sd_state,struct v4l2_mbus_framefmt * format,unsigned int which)534 static void rkisp1_rsz_set_src_fmt(struct rkisp1_resizer *rsz,
535 struct v4l2_subdev_state *sd_state,
536 struct v4l2_mbus_framefmt *format,
537 unsigned int which)
538 {
539 const struct rkisp1_isp_mbus_info *sink_mbus_info;
540 struct v4l2_mbus_framefmt *src_fmt, *sink_fmt;
541
542 sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, sd_state, RKISP1_RSZ_PAD_SINK,
543 which);
544 src_fmt = rkisp1_rsz_get_pad_fmt(rsz, sd_state, RKISP1_RSZ_PAD_SRC,
545 which);
546 sink_mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
547
548 /* for YUV formats, userspace can change the mbus code on the src pad if it is supported */
549 if (sink_mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV &&
550 rkisp1_rsz_get_yuv_mbus_info(format->code))
551 src_fmt->code = format->code;
552
553 src_fmt->width = clamp_t(u32, format->width,
554 rsz->config->min_rsz_width,
555 rsz->config->max_rsz_width);
556 src_fmt->height = clamp_t(u32, format->height,
557 rsz->config->min_rsz_height,
558 rsz->config->max_rsz_height);
559
560 *format = *src_fmt;
561 }
562
rkisp1_rsz_set_sink_crop(struct rkisp1_resizer * rsz,struct v4l2_subdev_state * sd_state,struct v4l2_rect * r,unsigned int which)563 static void rkisp1_rsz_set_sink_crop(struct rkisp1_resizer *rsz,
564 struct v4l2_subdev_state *sd_state,
565 struct v4l2_rect *r,
566 unsigned int which)
567 {
568 const struct rkisp1_isp_mbus_info *mbus_info;
569 struct v4l2_mbus_framefmt *sink_fmt;
570 struct v4l2_rect *sink_crop;
571
572 sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, sd_state, RKISP1_RSZ_PAD_SINK,
573 which);
574 sink_crop = rkisp1_rsz_get_pad_crop(rsz, sd_state,
575 RKISP1_RSZ_PAD_SINK,
576 which);
577
578 /* Not crop for MP bayer raw data */
579 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
580
581 if (rsz->id == RKISP1_MAINPATH &&
582 mbus_info->pixel_enc == V4L2_PIXEL_ENC_BAYER) {
583 sink_crop->left = 0;
584 sink_crop->top = 0;
585 sink_crop->width = sink_fmt->width;
586 sink_crop->height = sink_fmt->height;
587
588 *r = *sink_crop;
589 return;
590 }
591
592 sink_crop->left = ALIGN(r->left, 2);
593 sink_crop->width = ALIGN(r->width, 2);
594 sink_crop->top = r->top;
595 sink_crop->height = r->height;
596 rkisp1_sd_adjust_crop(sink_crop, sink_fmt);
597
598 *r = *sink_crop;
599 }
600
rkisp1_rsz_set_sink_fmt(struct rkisp1_resizer * rsz,struct v4l2_subdev_state * sd_state,struct v4l2_mbus_framefmt * format,unsigned int which)601 static void rkisp1_rsz_set_sink_fmt(struct rkisp1_resizer *rsz,
602 struct v4l2_subdev_state *sd_state,
603 struct v4l2_mbus_framefmt *format,
604 unsigned int which)
605 {
606 const struct rkisp1_isp_mbus_info *mbus_info;
607 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
608 struct v4l2_rect *sink_crop;
609
610 sink_fmt = rkisp1_rsz_get_pad_fmt(rsz, sd_state, RKISP1_RSZ_PAD_SINK,
611 which);
612 src_fmt = rkisp1_rsz_get_pad_fmt(rsz, sd_state, RKISP1_RSZ_PAD_SRC,
613 which);
614 sink_crop = rkisp1_rsz_get_pad_crop(rsz, sd_state,
615 RKISP1_RSZ_PAD_SINK,
616 which);
617 if (rsz->id == RKISP1_SELFPATH)
618 sink_fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
619 else
620 sink_fmt->code = format->code;
621
622 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
623 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) {
624 sink_fmt->code = RKISP1_DEF_FMT;
625 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code);
626 }
627 if (which == V4L2_SUBDEV_FORMAT_ACTIVE)
628 rsz->pixel_enc = mbus_info->pixel_enc;
629
630 /* Propagete to source pad */
631 src_fmt->code = sink_fmt->code;
632
633 sink_fmt->width = clamp_t(u32, format->width,
634 RKISP1_ISP_MIN_WIDTH,
635 RKISP1_ISP_MAX_WIDTH);
636 sink_fmt->height = clamp_t(u32, format->height,
637 RKISP1_ISP_MIN_HEIGHT,
638 RKISP1_ISP_MAX_HEIGHT);
639
640 *format = *sink_fmt;
641
642 /* Update sink crop */
643 rkisp1_rsz_set_sink_crop(rsz, sd_state, sink_crop, which);
644 }
645
rkisp1_rsz_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)646 static int rkisp1_rsz_get_fmt(struct v4l2_subdev *sd,
647 struct v4l2_subdev_state *sd_state,
648 struct v4l2_subdev_format *fmt)
649 {
650 struct rkisp1_resizer *rsz =
651 container_of(sd, struct rkisp1_resizer, sd);
652
653 mutex_lock(&rsz->ops_lock);
654 fmt->format = *rkisp1_rsz_get_pad_fmt(rsz, sd_state, fmt->pad,
655 fmt->which);
656 mutex_unlock(&rsz->ops_lock);
657 return 0;
658 }
659
rkisp1_rsz_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)660 static int rkisp1_rsz_set_fmt(struct v4l2_subdev *sd,
661 struct v4l2_subdev_state *sd_state,
662 struct v4l2_subdev_format *fmt)
663 {
664 struct rkisp1_resizer *rsz =
665 container_of(sd, struct rkisp1_resizer, sd);
666
667 mutex_lock(&rsz->ops_lock);
668 if (fmt->pad == RKISP1_RSZ_PAD_SINK)
669 rkisp1_rsz_set_sink_fmt(rsz, sd_state, &fmt->format,
670 fmt->which);
671 else
672 rkisp1_rsz_set_src_fmt(rsz, sd_state, &fmt->format,
673 fmt->which);
674
675 mutex_unlock(&rsz->ops_lock);
676 return 0;
677 }
678
rkisp1_rsz_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)679 static int rkisp1_rsz_get_selection(struct v4l2_subdev *sd,
680 struct v4l2_subdev_state *sd_state,
681 struct v4l2_subdev_selection *sel)
682 {
683 struct rkisp1_resizer *rsz =
684 container_of(sd, struct rkisp1_resizer, sd);
685 struct v4l2_mbus_framefmt *mf_sink;
686 int ret = 0;
687
688 if (sel->pad == RKISP1_RSZ_PAD_SRC)
689 return -EINVAL;
690
691 mutex_lock(&rsz->ops_lock);
692 switch (sel->target) {
693 case V4L2_SEL_TGT_CROP_BOUNDS:
694 mf_sink = rkisp1_rsz_get_pad_fmt(rsz, sd_state,
695 RKISP1_RSZ_PAD_SINK,
696 sel->which);
697 sel->r.height = mf_sink->height;
698 sel->r.width = mf_sink->width;
699 sel->r.left = 0;
700 sel->r.top = 0;
701 break;
702 case V4L2_SEL_TGT_CROP:
703 sel->r = *rkisp1_rsz_get_pad_crop(rsz, sd_state,
704 RKISP1_RSZ_PAD_SINK,
705 sel->which);
706 break;
707 default:
708 ret = -EINVAL;
709 }
710
711 mutex_unlock(&rsz->ops_lock);
712 return ret;
713 }
714
rkisp1_rsz_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_selection * sel)715 static int rkisp1_rsz_set_selection(struct v4l2_subdev *sd,
716 struct v4l2_subdev_state *sd_state,
717 struct v4l2_subdev_selection *sel)
718 {
719 struct rkisp1_resizer *rsz =
720 container_of(sd, struct rkisp1_resizer, sd);
721
722 if (sel->target != V4L2_SEL_TGT_CROP || sel->pad == RKISP1_RSZ_PAD_SRC)
723 return -EINVAL;
724
725 dev_dbg(rsz->rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__,
726 sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height);
727
728 mutex_lock(&rsz->ops_lock);
729 rkisp1_rsz_set_sink_crop(rsz, sd_state, &sel->r, sel->which);
730 mutex_unlock(&rsz->ops_lock);
731
732 return 0;
733 }
734
735 static const struct media_entity_operations rkisp1_rsz_media_ops = {
736 .link_validate = v4l2_subdev_link_validate,
737 };
738
739 static const struct v4l2_subdev_pad_ops rkisp1_rsz_pad_ops = {
740 .enum_mbus_code = rkisp1_rsz_enum_mbus_code,
741 .get_selection = rkisp1_rsz_get_selection,
742 .set_selection = rkisp1_rsz_set_selection,
743 .init_cfg = rkisp1_rsz_init_config,
744 .get_fmt = rkisp1_rsz_get_fmt,
745 .set_fmt = rkisp1_rsz_set_fmt,
746 .link_validate = v4l2_subdev_link_validate_default,
747 };
748
749 /* ----------------------------------------------------------------------------
750 * Stream operations
751 */
752
rkisp1_rsz_s_stream(struct v4l2_subdev * sd,int enable)753 static int rkisp1_rsz_s_stream(struct v4l2_subdev *sd, int enable)
754 {
755 struct rkisp1_resizer *rsz =
756 container_of(sd, struct rkisp1_resizer, sd);
757 struct rkisp1_device *rkisp1 = rsz->rkisp1;
758 struct rkisp1_capture *other = &rkisp1->capture_devs[rsz->id ^ 1];
759 enum rkisp1_shadow_regs_when when = RKISP1_SHADOW_REGS_SYNC;
760
761 if (!enable) {
762 rkisp1_dcrop_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
763 rkisp1_rsz_disable(rsz, RKISP1_SHADOW_REGS_ASYNC);
764 return 0;
765 }
766
767 if (other->is_streaming)
768 when = RKISP1_SHADOW_REGS_ASYNC;
769
770 mutex_lock(&rsz->ops_lock);
771 rkisp1_rsz_config(rsz, when);
772 rkisp1_dcrop_config(rsz);
773
774 mutex_unlock(&rsz->ops_lock);
775 return 0;
776 }
777
778 static const struct v4l2_subdev_video_ops rkisp1_rsz_video_ops = {
779 .s_stream = rkisp1_rsz_s_stream,
780 };
781
782 static const struct v4l2_subdev_ops rkisp1_rsz_ops = {
783 .video = &rkisp1_rsz_video_ops,
784 .pad = &rkisp1_rsz_pad_ops,
785 };
786
rkisp1_rsz_unregister(struct rkisp1_resizer * rsz)787 static void rkisp1_rsz_unregister(struct rkisp1_resizer *rsz)
788 {
789 v4l2_device_unregister_subdev(&rsz->sd);
790 media_entity_cleanup(&rsz->sd.entity);
791 }
792
rkisp1_rsz_register(struct rkisp1_resizer * rsz)793 static int rkisp1_rsz_register(struct rkisp1_resizer *rsz)
794 {
795 struct v4l2_subdev_state state = {
796 .pads = rsz->pad_cfg
797 };
798 static const char * const dev_names[] = {
799 RKISP1_RSZ_MP_DEV_NAME,
800 RKISP1_RSZ_SP_DEV_NAME
801 };
802 struct media_pad *pads = rsz->pads;
803 struct v4l2_subdev *sd = &rsz->sd;
804 int ret;
805
806 if (rsz->id == RKISP1_SELFPATH)
807 rsz->config = &rkisp1_rsz_config_sp;
808 else
809 rsz->config = &rkisp1_rsz_config_mp;
810
811 v4l2_subdev_init(sd, &rkisp1_rsz_ops);
812 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
813 sd->entity.ops = &rkisp1_rsz_media_ops;
814 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_SCALER;
815 sd->owner = THIS_MODULE;
816 strscpy(sd->name, dev_names[rsz->id], sizeof(sd->name));
817
818 pads[RKISP1_RSZ_PAD_SINK].flags = MEDIA_PAD_FL_SINK |
819 MEDIA_PAD_FL_MUST_CONNECT;
820 pads[RKISP1_RSZ_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE |
821 MEDIA_PAD_FL_MUST_CONNECT;
822
823 rsz->pixel_enc = RKISP1_DEF_PIXEL_ENC;
824
825 mutex_init(&rsz->ops_lock);
826 ret = media_entity_pads_init(&sd->entity, RKISP1_RSZ_PAD_MAX, pads);
827 if (ret)
828 return ret;
829
830 ret = v4l2_device_register_subdev(&rsz->rkisp1->v4l2_dev, sd);
831 if (ret) {
832 dev_err(sd->dev, "Failed to register resizer subdev\n");
833 goto err_cleanup_media_entity;
834 }
835
836 rkisp1_rsz_init_config(sd, &state);
837 return 0;
838
839 err_cleanup_media_entity:
840 media_entity_cleanup(&sd->entity);
841
842 return ret;
843 }
844
rkisp1_resizer_devs_register(struct rkisp1_device * rkisp1)845 int rkisp1_resizer_devs_register(struct rkisp1_device *rkisp1)
846 {
847 struct rkisp1_resizer *rsz;
848 unsigned int i, j;
849 int ret;
850
851 for (i = 0; i < ARRAY_SIZE(rkisp1->resizer_devs); i++) {
852 rsz = &rkisp1->resizer_devs[i];
853 rsz->rkisp1 = rkisp1;
854 rsz->id = i;
855 ret = rkisp1_rsz_register(rsz);
856 if (ret)
857 goto err_unreg_resizer_devs;
858 }
859
860 return 0;
861
862 err_unreg_resizer_devs:
863 for (j = 0; j < i; j++) {
864 rsz = &rkisp1->resizer_devs[j];
865 rkisp1_rsz_unregister(rsz);
866 }
867
868 return ret;
869 }
870
rkisp1_resizer_devs_unregister(struct rkisp1_device * rkisp1)871 void rkisp1_resizer_devs_unregister(struct rkisp1_device *rkisp1)
872 {
873 struct rkisp1_resizer *mp = &rkisp1->resizer_devs[RKISP1_MAINPATH];
874 struct rkisp1_resizer *sp = &rkisp1->resizer_devs[RKISP1_SELFPATH];
875
876 rkisp1_rsz_unregister(mp);
877 rkisp1_rsz_unregister(sp);
878 }
879