1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/io.h>
7 #include <linux/iommu.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12
13 #include <soc/tegra/mc.h>
14
15 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
16 #include <dt-bindings/memory/tegra186-mc.h>
17 #endif
18
19 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
20 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
21 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
22
tegra186_mc_probe(struct tegra_mc * mc)23 static int tegra186_mc_probe(struct tegra_mc *mc)
24 {
25 int err;
26
27 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
28 if (err < 0)
29 return err;
30
31 return 0;
32 }
33
tegra186_mc_remove(struct tegra_mc * mc)34 static void tegra186_mc_remove(struct tegra_mc *mc)
35 {
36 of_platform_depopulate(mc->dev);
37 }
38
39 #if IS_ENABLED(CONFIG_IOMMU_API)
tegra186_mc_client_sid_override(struct tegra_mc * mc,const struct tegra_mc_client * client,unsigned int sid)40 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
41 const struct tegra_mc_client *client,
42 unsigned int sid)
43 {
44 u32 value, old;
45
46 value = readl(mc->regs + client->regs.sid.security);
47 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
48 /*
49 * If the secure firmware has locked this down the override
50 * for this memory client, there's nothing we can do here.
51 */
52 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
53 return;
54
55 /*
56 * Otherwise, try to set the override itself. Typically the
57 * secure firmware will never have set this configuration.
58 * Instead, it will either have disabled write access to
59 * this field, or it will already have set an explicit
60 * override itself.
61 */
62 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
63
64 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
65 writel(value, mc->regs + client->regs.sid.security);
66 }
67
68 value = readl(mc->regs + client->regs.sid.override);
69 old = value & MC_SID_STREAMID_OVERRIDE_MASK;
70
71 if (old != sid) {
72 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
73 client->name, sid);
74 writel(sid, mc->regs + client->regs.sid.override);
75 }
76 }
77 #endif
78
tegra186_mc_probe_device(struct tegra_mc * mc,struct device * dev)79 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
80 {
81 #if IS_ENABLED(CONFIG_IOMMU_API)
82 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
83 struct of_phandle_args args;
84 unsigned int i, index = 0;
85
86 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
87 index, &args)) {
88 if (args.np == mc->dev->of_node && args.args_count != 0) {
89 for (i = 0; i < mc->soc->num_clients; i++) {
90 const struct tegra_mc_client *client = &mc->soc->clients[i];
91
92 if (client->id == args.args[0]) {
93 u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
94
95 tegra186_mc_client_sid_override(mc, client, sid);
96 }
97 }
98 }
99
100 index++;
101 }
102 #endif
103
104 return 0;
105 }
106
107 const struct tegra_mc_ops tegra186_mc_ops = {
108 .probe = tegra186_mc_probe,
109 .remove = tegra186_mc_remove,
110 .probe_device = tegra186_mc_probe_device,
111 };
112
113 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
114 static const struct tegra_mc_client tegra186_mc_clients[] = {
115 {
116 .id = TEGRA186_MEMORY_CLIENT_PTCR,
117 .name = "ptcr",
118 .sid = TEGRA186_SID_PASSTHROUGH,
119 .regs = {
120 .sid = {
121 .override = 0x000,
122 .security = 0x004,
123 },
124 },
125 }, {
126 .id = TEGRA186_MEMORY_CLIENT_AFIR,
127 .name = "afir",
128 .sid = TEGRA186_SID_AFI,
129 .regs = {
130 .sid = {
131 .override = 0x070,
132 .security = 0x074,
133 },
134 },
135 }, {
136 .id = TEGRA186_MEMORY_CLIENT_HDAR,
137 .name = "hdar",
138 .sid = TEGRA186_SID_HDA,
139 .regs = {
140 .sid = {
141 .override = 0x0a8,
142 .security = 0x0ac,
143 },
144 },
145 }, {
146 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
147 .name = "host1xdmar",
148 .sid = TEGRA186_SID_HOST1X,
149 .regs = {
150 .sid = {
151 .override = 0x0b0,
152 .security = 0x0b4,
153 },
154 },
155 }, {
156 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
157 .name = "nvencsrd",
158 .sid = TEGRA186_SID_NVENC,
159 .regs = {
160 .sid = {
161 .override = 0x0e0,
162 .security = 0x0e4,
163 },
164 },
165 }, {
166 .id = TEGRA186_MEMORY_CLIENT_SATAR,
167 .name = "satar",
168 .sid = TEGRA186_SID_SATA,
169 .regs = {
170 .sid = {
171 .override = 0x0f8,
172 .security = 0x0fc,
173 },
174 },
175 }, {
176 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
177 .name = "mpcorer",
178 .sid = TEGRA186_SID_PASSTHROUGH,
179 .regs = {
180 .sid = {
181 .override = 0x138,
182 .security = 0x13c,
183 },
184 },
185 }, {
186 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
187 .name = "nvencswr",
188 .sid = TEGRA186_SID_NVENC,
189 .regs = {
190 .sid = {
191 .override = 0x158,
192 .security = 0x15c,
193 },
194 },
195 }, {
196 .id = TEGRA186_MEMORY_CLIENT_AFIW,
197 .name = "afiw",
198 .sid = TEGRA186_SID_AFI,
199 .regs = {
200 .sid = {
201 .override = 0x188,
202 .security = 0x18c,
203 },
204 },
205 }, {
206 .id = TEGRA186_MEMORY_CLIENT_HDAW,
207 .name = "hdaw",
208 .sid = TEGRA186_SID_HDA,
209 .regs = {
210 .sid = {
211 .override = 0x1a8,
212 .security = 0x1ac,
213 },
214 },
215 }, {
216 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
217 .name = "mpcorew",
218 .sid = TEGRA186_SID_PASSTHROUGH,
219 .regs = {
220 .sid = {
221 .override = 0x1c8,
222 .security = 0x1cc,
223 },
224 },
225 }, {
226 .id = TEGRA186_MEMORY_CLIENT_SATAW,
227 .name = "sataw",
228 .sid = TEGRA186_SID_SATA,
229 .regs = {
230 .sid = {
231 .override = 0x1e8,
232 .security = 0x1ec,
233 },
234 },
235 }, {
236 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
237 .name = "ispra",
238 .sid = TEGRA186_SID_ISP,
239 .regs = {
240 .sid = {
241 .override = 0x220,
242 .security = 0x224,
243 },
244 },
245 }, {
246 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
247 .name = "ispwa",
248 .sid = TEGRA186_SID_ISP,
249 .regs = {
250 .sid = {
251 .override = 0x230,
252 .security = 0x234,
253 },
254 },
255 }, {
256 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
257 .name = "ispwb",
258 .sid = TEGRA186_SID_ISP,
259 .regs = {
260 .sid = {
261 .override = 0x238,
262 .security = 0x23c,
263 },
264 },
265 }, {
266 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
267 .name = "xusb_hostr",
268 .sid = TEGRA186_SID_XUSB_HOST,
269 .regs = {
270 .sid = {
271 .override = 0x250,
272 .security = 0x254,
273 },
274 },
275 }, {
276 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
277 .name = "xusb_hostw",
278 .sid = TEGRA186_SID_XUSB_HOST,
279 .regs = {
280 .sid = {
281 .override = 0x258,
282 .security = 0x25c,
283 },
284 },
285 }, {
286 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
287 .name = "xusb_devr",
288 .sid = TEGRA186_SID_XUSB_DEV,
289 .regs = {
290 .sid = {
291 .override = 0x260,
292 .security = 0x264,
293 },
294 },
295 }, {
296 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
297 .name = "xusb_devw",
298 .sid = TEGRA186_SID_XUSB_DEV,
299 .regs = {
300 .sid = {
301 .override = 0x268,
302 .security = 0x26c,
303 },
304 },
305 }, {
306 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
307 .name = "tsecsrd",
308 .sid = TEGRA186_SID_TSEC,
309 .regs = {
310 .sid = {
311 .override = 0x2a0,
312 .security = 0x2a4,
313 },
314 },
315 }, {
316 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
317 .name = "tsecswr",
318 .sid = TEGRA186_SID_TSEC,
319 .regs = {
320 .sid = {
321 .override = 0x2a8,
322 .security = 0x2ac,
323 },
324 },
325 }, {
326 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
327 .name = "gpusrd",
328 .sid = TEGRA186_SID_GPU,
329 .regs = {
330 .sid = {
331 .override = 0x2c0,
332 .security = 0x2c4,
333 },
334 },
335 }, {
336 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
337 .name = "gpuswr",
338 .sid = TEGRA186_SID_GPU,
339 .regs = {
340 .sid = {
341 .override = 0x2c8,
342 .security = 0x2cc,
343 },
344 },
345 }, {
346 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
347 .name = "sdmmcra",
348 .sid = TEGRA186_SID_SDMMC1,
349 .regs = {
350 .sid = {
351 .override = 0x300,
352 .security = 0x304,
353 },
354 },
355 }, {
356 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
357 .name = "sdmmcraa",
358 .sid = TEGRA186_SID_SDMMC2,
359 .regs = {
360 .sid = {
361 .override = 0x308,
362 .security = 0x30c,
363 },
364 },
365 }, {
366 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
367 .name = "sdmmcr",
368 .sid = TEGRA186_SID_SDMMC3,
369 .regs = {
370 .sid = {
371 .override = 0x310,
372 .security = 0x314,
373 },
374 },
375 }, {
376 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
377 .name = "sdmmcrab",
378 .sid = TEGRA186_SID_SDMMC4,
379 .regs = {
380 .sid = {
381 .override = 0x318,
382 .security = 0x31c,
383 },
384 },
385 }, {
386 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
387 .name = "sdmmcwa",
388 .sid = TEGRA186_SID_SDMMC1,
389 .regs = {
390 .sid = {
391 .override = 0x320,
392 .security = 0x324,
393 },
394 },
395 }, {
396 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
397 .name = "sdmmcwaa",
398 .sid = TEGRA186_SID_SDMMC2,
399 .regs = {
400 .sid = {
401 .override = 0x328,
402 .security = 0x32c,
403 },
404 },
405 }, {
406 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
407 .name = "sdmmcw",
408 .sid = TEGRA186_SID_SDMMC3,
409 .regs = {
410 .sid = {
411 .override = 0x330,
412 .security = 0x334,
413 },
414 },
415 }, {
416 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
417 .name = "sdmmcwab",
418 .sid = TEGRA186_SID_SDMMC4,
419 .regs = {
420 .sid = {
421 .override = 0x338,
422 .security = 0x33c,
423 },
424 },
425 }, {
426 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
427 .name = "vicsrd",
428 .sid = TEGRA186_SID_VIC,
429 .regs = {
430 .sid = {
431 .override = 0x360,
432 .security = 0x364,
433 },
434 },
435 }, {
436 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
437 .name = "vicswr",
438 .sid = TEGRA186_SID_VIC,
439 .regs = {
440 .sid = {
441 .override = 0x368,
442 .security = 0x36c,
443 },
444 },
445 }, {
446 .id = TEGRA186_MEMORY_CLIENT_VIW,
447 .name = "viw",
448 .sid = TEGRA186_SID_VI,
449 .regs = {
450 .sid = {
451 .override = 0x390,
452 .security = 0x394,
453 },
454 },
455 }, {
456 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
457 .name = "nvdecsrd",
458 .sid = TEGRA186_SID_NVDEC,
459 .regs = {
460 .sid = {
461 .override = 0x3c0,
462 .security = 0x3c4,
463 },
464 },
465 }, {
466 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
467 .name = "nvdecswr",
468 .sid = TEGRA186_SID_NVDEC,
469 .regs = {
470 .sid = {
471 .override = 0x3c8,
472 .security = 0x3cc,
473 },
474 },
475 }, {
476 .id = TEGRA186_MEMORY_CLIENT_APER,
477 .name = "aper",
478 .sid = TEGRA186_SID_APE,
479 .regs = {
480 .sid = {
481 .override = 0x3d0,
482 .security = 0x3d4,
483 },
484 },
485 }, {
486 .id = TEGRA186_MEMORY_CLIENT_APEW,
487 .name = "apew",
488 .sid = TEGRA186_SID_APE,
489 .regs = {
490 .sid = {
491 .override = 0x3d8,
492 .security = 0x3dc,
493 },
494 },
495 }, {
496 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
497 .name = "nvjpgsrd",
498 .sid = TEGRA186_SID_NVJPG,
499 .regs = {
500 .sid = {
501 .override = 0x3f0,
502 .security = 0x3f4,
503 },
504 },
505 }, {
506 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
507 .name = "nvjpgswr",
508 .sid = TEGRA186_SID_NVJPG,
509 .regs = {
510 .sid = {
511 .override = 0x3f8,
512 .security = 0x3fc,
513 },
514 },
515 }, {
516 .id = TEGRA186_MEMORY_CLIENT_SESRD,
517 .name = "sesrd",
518 .sid = TEGRA186_SID_SE,
519 .regs = {
520 .sid = {
521 .override = 0x400,
522 .security = 0x404,
523 },
524 },
525 }, {
526 .id = TEGRA186_MEMORY_CLIENT_SESWR,
527 .name = "seswr",
528 .sid = TEGRA186_SID_SE,
529 .regs = {
530 .sid = {
531 .override = 0x408,
532 .security = 0x40c,
533 },
534 },
535 }, {
536 .id = TEGRA186_MEMORY_CLIENT_ETRR,
537 .name = "etrr",
538 .sid = TEGRA186_SID_ETR,
539 .regs = {
540 .sid = {
541 .override = 0x420,
542 .security = 0x424,
543 },
544 },
545 }, {
546 .id = TEGRA186_MEMORY_CLIENT_ETRW,
547 .name = "etrw",
548 .sid = TEGRA186_SID_ETR,
549 .regs = {
550 .sid = {
551 .override = 0x428,
552 .security = 0x42c,
553 },
554 },
555 }, {
556 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
557 .name = "tsecsrdb",
558 .sid = TEGRA186_SID_TSECB,
559 .regs = {
560 .sid = {
561 .override = 0x430,
562 .security = 0x434,
563 },
564 },
565 }, {
566 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
567 .name = "tsecswrb",
568 .sid = TEGRA186_SID_TSECB,
569 .regs = {
570 .sid = {
571 .override = 0x438,
572 .security = 0x43c,
573 },
574 },
575 }, {
576 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
577 .name = "gpusrd2",
578 .sid = TEGRA186_SID_GPU,
579 .regs = {
580 .sid = {
581 .override = 0x440,
582 .security = 0x444,
583 },
584 },
585 }, {
586 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
587 .name = "gpuswr2",
588 .sid = TEGRA186_SID_GPU,
589 .regs = {
590 .sid = {
591 .override = 0x448,
592 .security = 0x44c,
593 },
594 },
595 }, {
596 .id = TEGRA186_MEMORY_CLIENT_AXISR,
597 .name = "axisr",
598 .sid = TEGRA186_SID_GPCDMA_0,
599 .regs = {
600 .sid = {
601 .override = 0x460,
602 .security = 0x464,
603 },
604 },
605 }, {
606 .id = TEGRA186_MEMORY_CLIENT_AXISW,
607 .name = "axisw",
608 .sid = TEGRA186_SID_GPCDMA_0,
609 .regs = {
610 .sid = {
611 .override = 0x468,
612 .security = 0x46c,
613 },
614 },
615 }, {
616 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
617 .name = "eqosr",
618 .sid = TEGRA186_SID_EQOS,
619 .regs = {
620 .sid = {
621 .override = 0x470,
622 .security = 0x474,
623 },
624 },
625 }, {
626 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
627 .name = "eqosw",
628 .sid = TEGRA186_SID_EQOS,
629 .regs = {
630 .sid = {
631 .override = 0x478,
632 .security = 0x47c,
633 },
634 },
635 }, {
636 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
637 .name = "ufshcr",
638 .sid = TEGRA186_SID_UFSHC,
639 .regs = {
640 .sid = {
641 .override = 0x480,
642 .security = 0x484,
643 },
644 },
645 }, {
646 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
647 .name = "ufshcw",
648 .sid = TEGRA186_SID_UFSHC,
649 .regs = {
650 .sid = {
651 .override = 0x488,
652 .security = 0x48c,
653 },
654 },
655 }, {
656 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
657 .name = "nvdisplayr",
658 .sid = TEGRA186_SID_NVDISPLAY,
659 .regs = {
660 .sid = {
661 .override = 0x490,
662 .security = 0x494,
663 },
664 },
665 }, {
666 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
667 .name = "bpmpr",
668 .sid = TEGRA186_SID_BPMP,
669 .regs = {
670 .sid = {
671 .override = 0x498,
672 .security = 0x49c,
673 },
674 },
675 }, {
676 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
677 .name = "bpmpw",
678 .sid = TEGRA186_SID_BPMP,
679 .regs = {
680 .sid = {
681 .override = 0x4a0,
682 .security = 0x4a4,
683 },
684 },
685 }, {
686 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
687 .name = "bpmpdmar",
688 .sid = TEGRA186_SID_BPMP,
689 .regs = {
690 .sid = {
691 .override = 0x4a8,
692 .security = 0x4ac,
693 },
694 },
695 }, {
696 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
697 .name = "bpmpdmaw",
698 .sid = TEGRA186_SID_BPMP,
699 .regs = {
700 .sid = {
701 .override = 0x4b0,
702 .security = 0x4b4,
703 },
704 },
705 }, {
706 .id = TEGRA186_MEMORY_CLIENT_AONR,
707 .name = "aonr",
708 .sid = TEGRA186_SID_AON,
709 .regs = {
710 .sid = {
711 .override = 0x4b8,
712 .security = 0x4bc,
713 },
714 },
715 }, {
716 .id = TEGRA186_MEMORY_CLIENT_AONW,
717 .name = "aonw",
718 .sid = TEGRA186_SID_AON,
719 .regs = {
720 .sid = {
721 .override = 0x4c0,
722 .security = 0x4c4,
723 },
724 },
725 }, {
726 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
727 .name = "aondmar",
728 .sid = TEGRA186_SID_AON,
729 .regs = {
730 .sid = {
731 .override = 0x4c8,
732 .security = 0x4cc,
733 },
734 },
735 }, {
736 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
737 .name = "aondmaw",
738 .sid = TEGRA186_SID_AON,
739 .regs = {
740 .sid = {
741 .override = 0x4d0,
742 .security = 0x4d4,
743 },
744 },
745 }, {
746 .id = TEGRA186_MEMORY_CLIENT_SCER,
747 .name = "scer",
748 .sid = TEGRA186_SID_SCE,
749 .regs = {
750 .sid = {
751 .override = 0x4d8,
752 .security = 0x4dc,
753 },
754 },
755 }, {
756 .id = TEGRA186_MEMORY_CLIENT_SCEW,
757 .name = "scew",
758 .sid = TEGRA186_SID_SCE,
759 .regs = {
760 .sid = {
761 .override = 0x4e0,
762 .security = 0x4e4,
763 },
764 },
765 }, {
766 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
767 .name = "scedmar",
768 .sid = TEGRA186_SID_SCE,
769 .regs = {
770 .sid = {
771 .override = 0x4e8,
772 .security = 0x4ec,
773 },
774 },
775 }, {
776 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
777 .name = "scedmaw",
778 .sid = TEGRA186_SID_SCE,
779 .regs = {
780 .sid = {
781 .override = 0x4f0,
782 .security = 0x4f4,
783 },
784 },
785 }, {
786 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
787 .name = "apedmar",
788 .sid = TEGRA186_SID_APE,
789 .regs = {
790 .sid = {
791 .override = 0x4f8,
792 .security = 0x4fc,
793 },
794 },
795 }, {
796 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
797 .name = "apedmaw",
798 .sid = TEGRA186_SID_APE,
799 .regs = {
800 .sid = {
801 .override = 0x500,
802 .security = 0x504,
803 },
804 },
805 }, {
806 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
807 .name = "nvdisplayr1",
808 .sid = TEGRA186_SID_NVDISPLAY,
809 .regs = {
810 .sid = {
811 .override = 0x508,
812 .security = 0x50c,
813 },
814 },
815 }, {
816 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
817 .name = "vicsrd1",
818 .sid = TEGRA186_SID_VIC,
819 .regs = {
820 .sid = {
821 .override = 0x510,
822 .security = 0x514,
823 },
824 },
825 }, {
826 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
827 .name = "nvdecsrd1",
828 .sid = TEGRA186_SID_NVDEC,
829 .regs = {
830 .sid = {
831 .override = 0x518,
832 .security = 0x51c,
833 },
834 },
835 },
836 };
837
838 const struct tegra_mc_soc tegra186_mc_soc = {
839 .num_clients = ARRAY_SIZE(tegra186_mc_clients),
840 .clients = tegra186_mc_clients,
841 .num_address_bits = 40,
842 .ops = &tegra186_mc_ops,
843 };
844 #endif
845