1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Driver for Realtek PCI-Express card reader
3 *
4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 *
6 * Author:
7 * Wei WANG <wei_wang@realsil.com.cn>
8 * Roger Tseng <rogerable@realtek.com>
9 */
10
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/rtsx_pci.h>
14
15 #include "rtsx_pcr.h"
16
rts5227_get_ic_version(struct rtsx_pcr * pcr)17 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
18 {
19 u8 val;
20
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
22 return val & 0x0F;
23 }
24
rts5227_fill_driving(struct rtsx_pcr * pcr,u8 voltage)25 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
26 {
27 u8 driving_3v3[4][3] = {
28 {0x13, 0x13, 0x13},
29 {0x96, 0x96, 0x96},
30 {0x7F, 0x7F, 0x7F},
31 {0x96, 0x96, 0x96},
32 };
33 u8 driving_1v8[4][3] = {
34 {0x99, 0x99, 0x99},
35 {0xAA, 0xAA, 0xAA},
36 {0xFE, 0xFE, 0xFE},
37 {0xB3, 0xB3, 0xB3},
38 };
39 u8 (*driving)[3], drive_sel;
40
41 if (voltage == OUTPUT_3V3) {
42 driving = driving_3v3;
43 drive_sel = pcr->sd30_drive_sel_3v3;
44 } else {
45 driving = driving_1v8;
46 drive_sel = pcr->sd30_drive_sel_1v8;
47 }
48
49 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
50 0xFF, driving[drive_sel][0]);
51 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
52 0xFF, driving[drive_sel][1]);
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
54 0xFF, driving[drive_sel][2]);
55 }
56
rts5227_fetch_vendor_settings(struct rtsx_pcr * pcr)57 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
58 {
59 struct pci_dev *pdev = pcr->pci;
60 u32 reg;
61
62 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
63 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
64
65 if (!rtsx_vendor_setting_valid(reg))
66 return;
67
68 pcr->aspm_en = rtsx_reg_to_aspm(reg);
69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
70 pcr->card_drive_sel &= 0x3F;
71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
72
73 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®);
74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
75 if (rtsx_check_mmc_support(reg))
76 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
77 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
78 if (rtsx_reg_check_reverse_socket(reg))
79 pcr->flags |= PCR_REVERSE_SOCKET;
80 }
81
rts5227_init_from_cfg(struct rtsx_pcr * pcr)82 static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
83 {
84 struct rtsx_cr_option *option = &pcr->option;
85
86 if (CHK_PCI_PID(pcr, 0x522A)) {
87 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
88 | PM_L1_1_EN | PM_L1_2_EN))
89 rtsx_pci_disable_oobs_polling(pcr);
90 else
91 rtsx_pci_enable_oobs_polling(pcr);
92 }
93
94 if (option->ltr_en) {
95 if (option->ltr_enabled)
96 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
97 }
98 }
99
rts5227_extra_init_hw(struct rtsx_pcr * pcr)100 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
101 {
102 u16 cap;
103 struct rtsx_cr_option *option = &pcr->option;
104
105 rts5227_init_from_cfg(pcr);
106 rtsx_pci_init_cmd(pcr);
107
108 /* Configure GPIO as output */
109 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
110 /* Reset ASPM state to default value */
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
112 /* Switch LDO3318 source from DV33 to card_3v3 */
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
115 /* LED shine disabled, set initial shine cycle period */
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
117 /* Configure LTR */
118 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
119 if (cap & PCI_EXP_DEVCTL2_LTR_EN)
120 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
121 /* Configure OBFF */
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
123 /* Configure driving */
124 rts5227_fill_driving(pcr, OUTPUT_3V3);
125 /* Configure force_clock_req */
126 if (pcr->flags & PCR_REVERSE_SOCKET)
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
128 else
129 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
130
131 if (option->force_clkreq_0)
132 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
133 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
134 else
135 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
136 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
137
138 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
139
140 return rtsx_pci_send_cmd(pcr, 100);
141 }
142
rts5227_optimize_phy(struct rtsx_pcr * pcr)143 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
144 {
145 int err;
146
147 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
148 if (err < 0)
149 return err;
150
151 /* Optimize RX sensitivity */
152 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
153 }
154
rts5227_turn_on_led(struct rtsx_pcr * pcr)155 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
156 {
157 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
158 }
159
rts5227_turn_off_led(struct rtsx_pcr * pcr)160 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
161 {
162 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
163 }
164
rts5227_enable_auto_blink(struct rtsx_pcr * pcr)165 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
166 {
167 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
168 }
169
rts5227_disable_auto_blink(struct rtsx_pcr * pcr)170 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
171 {
172 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
173 }
174
rts5227_card_power_on(struct rtsx_pcr * pcr,int card)175 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
176 {
177 int err;
178
179 if (pcr->option.ocp_en)
180 rtsx_pci_enable_ocp(pcr);
181
182 rtsx_pci_init_cmd(pcr);
183 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
184 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
185
186 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
187 LDO3318_PWR_MASK, 0x02);
188
189 err = rtsx_pci_send_cmd(pcr, 100);
190 if (err < 0)
191 return err;
192
193 /* To avoid too large in-rush current */
194 msleep(20);
195 rtsx_pci_init_cmd(pcr);
196 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
197 SD_POWER_MASK, SD_POWER_ON);
198
199 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
200 LDO3318_PWR_MASK, 0x06);
201
202 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
203 SD_OUTPUT_EN, SD_OUTPUT_EN);
204 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
205 MS_OUTPUT_EN, MS_OUTPUT_EN);
206 return rtsx_pci_send_cmd(pcr, 100);
207 }
208
rts5227_card_power_off(struct rtsx_pcr * pcr,int card)209 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
210 {
211 if (pcr->option.ocp_en)
212 rtsx_pci_disable_ocp(pcr);
213
214 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
215 PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
216 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
217
218 return 0;
219 }
220
rts5227_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)221 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
222 {
223 int err;
224
225 if (voltage == OUTPUT_3V3) {
226 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
227 if (err < 0)
228 return err;
229 } else if (voltage == OUTPUT_1V8) {
230 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
231 if (err < 0)
232 return err;
233 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
234 if (err < 0)
235 return err;
236 } else {
237 return -EINVAL;
238 }
239
240 /* set pad drive */
241 rtsx_pci_init_cmd(pcr);
242 rts5227_fill_driving(pcr, voltage);
243 return rtsx_pci_send_cmd(pcr, 100);
244 }
245
246 static const struct pcr_ops rts5227_pcr_ops = {
247 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
248 .extra_init_hw = rts5227_extra_init_hw,
249 .optimize_phy = rts5227_optimize_phy,
250 .turn_on_led = rts5227_turn_on_led,
251 .turn_off_led = rts5227_turn_off_led,
252 .enable_auto_blink = rts5227_enable_auto_blink,
253 .disable_auto_blink = rts5227_disable_auto_blink,
254 .card_power_on = rts5227_card_power_on,
255 .card_power_off = rts5227_card_power_off,
256 .switch_output_voltage = rts5227_switch_output_voltage,
257 .cd_deglitch = NULL,
258 .conv_clk_and_div_n = NULL,
259 };
260
261 /* SD Pull Control Enable:
262 * SD_DAT[3:0] ==> pull up
263 * SD_CD ==> pull up
264 * SD_WP ==> pull up
265 * SD_CMD ==> pull up
266 * SD_CLK ==> pull down
267 */
268 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
269 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
270 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
271 0,
272 };
273
274 /* SD Pull Control Disable:
275 * SD_DAT[3:0] ==> pull down
276 * SD_CD ==> pull up
277 * SD_WP ==> pull down
278 * SD_CMD ==> pull down
279 * SD_CLK ==> pull down
280 */
281 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
282 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
283 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
284 0,
285 };
286
287 /* MS Pull Control Enable:
288 * MS CD ==> pull up
289 * others ==> pull down
290 */
291 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
292 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
293 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
294 0,
295 };
296
297 /* MS Pull Control Disable:
298 * MS CD ==> pull up
299 * others ==> pull down
300 */
301 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
302 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
303 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
304 0,
305 };
306
rts5227_init_params(struct rtsx_pcr * pcr)307 void rts5227_init_params(struct rtsx_pcr *pcr)
308 {
309 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
310 pcr->num_slots = 2;
311 pcr->ops = &rts5227_pcr_ops;
312
313 pcr->flags = 0;
314 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
315 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
316 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
317 pcr->aspm_en = ASPM_L1_EN;
318 pcr->aspm_mode = ASPM_MODE_CFG;
319 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
320 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
321
322 pcr->ic_version = rts5227_get_ic_version(pcr);
323 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
324 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
325 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
326 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
327
328 pcr->reg_pm_ctrl3 = PM_CTRL3;
329 }
330
rts522a_optimize_phy(struct rtsx_pcr * pcr)331 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
332 {
333 int err;
334
335 err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
336 0x00);
337 if (err < 0)
338 return err;
339
340 if (is_version(pcr, 0x522A, IC_VER_A)) {
341 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
342 PHY_RCR2_INIT_27S);
343 if (err)
344 return err;
345
346 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
347 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
348 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
349 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
350 }
351
352 return 0;
353 }
354
rts522a_extra_init_hw(struct rtsx_pcr * pcr)355 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
356 {
357 rts5227_extra_init_hw(pcr);
358
359 /* Power down OCP for power consumption */
360 if (!pcr->card_exist)
361 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
362 OC_POWER_DOWN);
363
364 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
365 FUNC_FORCE_UPME_XMT_DBG);
366 rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
367 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
368 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
369
370 return 0;
371 }
372
rts522a_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)373 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
374 {
375 int err;
376
377 if (voltage == OUTPUT_3V3) {
378 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
379 if (err < 0)
380 return err;
381 } else if (voltage == OUTPUT_1V8) {
382 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
383 if (err < 0)
384 return err;
385 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
386 if (err < 0)
387 return err;
388 } else {
389 return -EINVAL;
390 }
391
392 /* set pad drive */
393 rtsx_pci_init_cmd(pcr);
394 rts5227_fill_driving(pcr, voltage);
395 return rtsx_pci_send_cmd(pcr, 100);
396 }
397
rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr * pcr,int active)398 static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
399 {
400 struct rtsx_cr_option *option = &pcr->option;
401 int aspm_L1_1, aspm_L1_2;
402 u8 val = 0;
403
404 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
405 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
406
407 if (active) {
408 /* run, latency: 60us */
409 if (aspm_L1_1)
410 val = option->ltr_l1off_snooze_sspwrgate;
411 } else {
412 /* l1off, latency: 300us */
413 if (aspm_L1_2)
414 val = option->ltr_l1off_sspwrgate;
415 }
416
417 rtsx_set_l1off_sub(pcr, val);
418 }
419
420 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
421 */
422 static const struct pcr_ops rts522a_pcr_ops = {
423 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
424 .extra_init_hw = rts522a_extra_init_hw,
425 .optimize_phy = rts522a_optimize_phy,
426 .turn_on_led = rts5227_turn_on_led,
427 .turn_off_led = rts5227_turn_off_led,
428 .enable_auto_blink = rts5227_enable_auto_blink,
429 .disable_auto_blink = rts5227_disable_auto_blink,
430 .card_power_on = rts5227_card_power_on,
431 .card_power_off = rts5227_card_power_off,
432 .switch_output_voltage = rts522a_switch_output_voltage,
433 .cd_deglitch = NULL,
434 .conv_clk_and_div_n = NULL,
435 .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
436 };
437
rts522a_init_params(struct rtsx_pcr * pcr)438 void rts522a_init_params(struct rtsx_pcr *pcr)
439 {
440 struct rtsx_cr_option *option = &pcr->option;
441
442 rts5227_init_params(pcr);
443 pcr->ops = &rts522a_pcr_ops;
444 pcr->aspm_mode = ASPM_MODE_REG;
445 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
446 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
447
448 option->dev_flags = LTR_L1SS_PWR_GATE_EN;
449 option->ltr_en = true;
450
451 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
452 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
453 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
454 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
455 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
456 option->ltr_l1off_sspwrgate = 0x7F;
457 option->ltr_l1off_snooze_sspwrgate = 0x78;
458
459 pcr->option.ocp_en = 1;
460 if (pcr->option.ocp_en)
461 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
462 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
463 pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
464
465 }
466