1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/iopoll.h>
12 #include <linux/ioport.h>
13 #include <linux/irq.h>
14 #include <linux/of_address.h>
15 #include <linux/of_device.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_gpio.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include "cqhci.h"
37
38 #define MAX_BD_NUM 1024
39 #define MSDC_NR_CLOCKS 3
40
41 /*--------------------------------------------------------------------------*/
42 /* Common Definition */
43 /*--------------------------------------------------------------------------*/
44 #define MSDC_BUS_1BITS 0x0
45 #define MSDC_BUS_4BITS 0x1
46 #define MSDC_BUS_8BITS 0x2
47
48 #define MSDC_BURST_64B 0x6
49
50 /*--------------------------------------------------------------------------*/
51 /* Register Offset */
52 /*--------------------------------------------------------------------------*/
53 #define MSDC_CFG 0x0
54 #define MSDC_IOCON 0x04
55 #define MSDC_PS 0x08
56 #define MSDC_INT 0x0c
57 #define MSDC_INTEN 0x10
58 #define MSDC_FIFOCS 0x14
59 #define SDC_CFG 0x30
60 #define SDC_CMD 0x34
61 #define SDC_ARG 0x38
62 #define SDC_STS 0x3c
63 #define SDC_RESP0 0x40
64 #define SDC_RESP1 0x44
65 #define SDC_RESP2 0x48
66 #define SDC_RESP3 0x4c
67 #define SDC_BLK_NUM 0x50
68 #define SDC_ADV_CFG0 0x64
69 #define EMMC_IOCON 0x7c
70 #define SDC_ACMD_RESP 0x80
71 #define DMA_SA_H4BIT 0x8c
72 #define MSDC_DMA_SA 0x90
73 #define MSDC_DMA_CTRL 0x98
74 #define MSDC_DMA_CFG 0x9c
75 #define MSDC_PATCH_BIT 0xb0
76 #define MSDC_PATCH_BIT1 0xb4
77 #define MSDC_PATCH_BIT2 0xb8
78 #define MSDC_PAD_TUNE 0xec
79 #define MSDC_PAD_TUNE0 0xf0
80 #define PAD_DS_TUNE 0x188
81 #define PAD_CMD_TUNE 0x18c
82 #define EMMC51_CFG0 0x204
83 #define EMMC50_CFG0 0x208
84 #define EMMC50_CFG1 0x20c
85 #define EMMC50_CFG3 0x220
86 #define SDC_FIFO_CFG 0x228
87 #define CQHCI_SETTING 0x7fc
88
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL 0x00
93 #define EMMC_TOP_CMD 0x04
94 #define EMMC50_PAD_DS_TUNE 0x0c
95
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask */
98 /*--------------------------------------------------------------------------*/
99
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
102 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
103 #define MSDC_CFG_RST (0x1 << 2) /* RW */
104 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
105 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
106 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
107 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
108 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
109 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
110 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
111 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */
113 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */
114 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */
115
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
118 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
119 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
120 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
121 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
122 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
123 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */
124 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
125 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
126 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
127 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
128 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
129 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
130 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
131 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
132 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
133
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
136 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
137 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
138 #define MSDC_PS_DAT (0xff << 16) /* R */
139 #define MSDC_PS_DATA1 (0x1 << 17) /* R */
140 #define MSDC_PS_CMD (0x1 << 24) /* R */
141 #define MSDC_PS_WP (0x1 << 31) /* R */
142
143 /* MSDC_INT mask */
144 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
145 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
146 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
147 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
148 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
149 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
150 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
151 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
152 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
153 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
154 #define MSDC_INT_CSTA (0x1 << 11) /* R */
155 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
156 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
157 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
158 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
159 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
160 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */
161 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */
162 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */
163 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */
164
165 /* MSDC_INTEN mask */
166 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
167 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
168 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
169 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
170 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
171 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
172 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
173 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
174 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
175 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
176 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
177 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
178 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
179 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
180 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
181 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
182 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */
183 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */
184 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */
185
186 /* MSDC_FIFOCS mask */
187 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
188 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
189 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */
190
191 /* SDC_CFG mask */
192 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
193 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
194 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */
195 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
196 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
197 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
198 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
199 #define SDC_CFG_DTOC (0xff << 24) /* RW */
200
201 /* SDC_STS mask */
202 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
203 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
204 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
205
206 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */
207 /* SDC_ADV_CFG0 mask */
208 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
209
210 /* DMA_SA_H4BIT mask */
211 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
212
213 /* MSDC_DMA_CTRL mask */
214 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
215 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
216 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
217 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
218 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
219 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
220
221 /* MSDC_DMA_CFG mask */
222 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
223 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
224 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */
225 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */
226 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */
227
228 /* MSDC_PATCH_BIT mask */
229 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
230 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
231 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10)
232 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
233 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
234 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
235 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
236 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
237 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
238 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
239 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
240 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
241
242 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */
243 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */
244 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */
245
246 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
247 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
248 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
249 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
250 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
251 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
252
253 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */
255 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */
256 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */
257 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */
258 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */
259 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */
260 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */
261
262 #define PAD_DS_TUNE_DLY_SEL (0x1 << 0) /* RW */
263 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */
264 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */
265 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */
266
267 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */
268
269 /* EMMC51_CFG0 mask */
270 #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */
271
272 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */
273 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */
274 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */
275 #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */
276
277 /* EMMC50_CFG1 mask */
278 #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */
279
280 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */
281
282 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
283 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
284
285 /* CQHCI_SETTING */
286 #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */
287 #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */
288
289 /* EMMC_TOP_CONTROL mask */
290 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */
291 #define DELAY_EN (0x1 << 1) /* RW */
292 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
293 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
294 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
295 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
296 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
297 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */
298
299 /* EMMC_TOP_CMD mask */
300 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
301 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */
302 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
303 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
304 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
305
306 /* EMMC50_PAD_DS_TUNE mask */
307 #define PAD_DS_DLY_SEL (0x1 << 16) /* RW */
308 #define PAD_DS_DLY1 (0x1f << 10) /* RW */
309 #define PAD_DS_DLY3 (0x1f << 0) /* RW */
310
311 #define REQ_CMD_EIO (0x1 << 0)
312 #define REQ_CMD_TMO (0x1 << 1)
313 #define REQ_DAT_ERR (0x1 << 2)
314 #define REQ_STOP_EIO (0x1 << 3)
315 #define REQ_STOP_TMO (0x1 << 4)
316 #define REQ_CMD_BUSY (0x1 << 5)
317
318 #define MSDC_PREPARE_FLAG (0x1 << 0)
319 #define MSDC_ASYNC_FLAG (0x1 << 1)
320 #define MSDC_MMAP_FLAG (0x1 << 2)
321
322 #define MTK_MMC_AUTOSUSPEND_DELAY 50
323 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
324 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
325
326 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
327
328 #define PAD_DELAY_MAX 32 /* PAD delay cells */
329 /*--------------------------------------------------------------------------*/
330 /* Descriptor Structure */
331 /*--------------------------------------------------------------------------*/
332 struct mt_gpdma_desc {
333 u32 gpd_info;
334 #define GPDMA_DESC_HWO (0x1 << 0)
335 #define GPDMA_DESC_BDP (0x1 << 1)
336 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
337 #define GPDMA_DESC_INT (0x1 << 16)
338 #define GPDMA_DESC_NEXT_H4 (0xf << 24)
339 #define GPDMA_DESC_PTR_H4 (0xf << 28)
340 u32 next;
341 u32 ptr;
342 u32 gpd_data_len;
343 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
344 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
345 u32 arg;
346 u32 blknum;
347 u32 cmd;
348 };
349
350 struct mt_bdma_desc {
351 u32 bd_info;
352 #define BDMA_DESC_EOL (0x1 << 0)
353 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
354 #define BDMA_DESC_BLKPAD (0x1 << 17)
355 #define BDMA_DESC_DWPAD (0x1 << 18)
356 #define BDMA_DESC_NEXT_H4 (0xf << 24)
357 #define BDMA_DESC_PTR_H4 (0xf << 28)
358 u32 next;
359 u32 ptr;
360 u32 bd_data_len;
361 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
362 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */
363 };
364
365 struct msdc_dma {
366 struct scatterlist *sg; /* I/O scatter list */
367 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
368 struct mt_bdma_desc *bd; /* pointer to bd array */
369 dma_addr_t gpd_addr; /* the physical address of gpd array */
370 dma_addr_t bd_addr; /* the physical address of bd array */
371 };
372
373 struct msdc_save_para {
374 u32 msdc_cfg;
375 u32 iocon;
376 u32 sdc_cfg;
377 u32 pad_tune;
378 u32 patch_bit0;
379 u32 patch_bit1;
380 u32 patch_bit2;
381 u32 pad_ds_tune;
382 u32 pad_cmd_tune;
383 u32 emmc50_cfg0;
384 u32 emmc50_cfg3;
385 u32 sdc_fifo_cfg;
386 u32 emmc_top_control;
387 u32 emmc_top_cmd;
388 u32 emmc50_pad_ds_tune;
389 };
390
391 struct mtk_mmc_compatible {
392 u8 clk_div_bits;
393 bool recheck_sdio_irq;
394 bool hs400_tune; /* only used for MT8173 */
395 u32 pad_tune_reg;
396 bool async_fifo;
397 bool data_tune;
398 bool busy_check;
399 bool stop_clk_fix;
400 bool enhance_rx;
401 bool support_64g;
402 bool use_internal_cd;
403 };
404
405 struct msdc_tune_para {
406 u32 iocon;
407 u32 pad_tune;
408 u32 pad_cmd_tune;
409 u32 emmc_top_control;
410 u32 emmc_top_cmd;
411 };
412
413 struct msdc_delay_phase {
414 u8 maxlen;
415 u8 start;
416 u8 final_phase;
417 };
418
419 struct msdc_host {
420 struct device *dev;
421 const struct mtk_mmc_compatible *dev_comp;
422 int cmd_rsp;
423
424 spinlock_t lock;
425 struct mmc_request *mrq;
426 struct mmc_command *cmd;
427 struct mmc_data *data;
428 int error;
429
430 void __iomem *base; /* host base address */
431 void __iomem *top_base; /* host top register base address */
432
433 struct msdc_dma dma; /* dma channel */
434 u64 dma_mask;
435
436 u32 timeout_ns; /* data timeout ns */
437 u32 timeout_clks; /* data timeout clks */
438
439 struct pinctrl *pinctrl;
440 struct pinctrl_state *pins_default;
441 struct pinctrl_state *pins_uhs;
442 struct delayed_work req_timeout;
443 int irq; /* host interrupt */
444 struct reset_control *reset;
445
446 struct clk *src_clk; /* msdc source clock */
447 struct clk *h_clk; /* msdc h_clk */
448 struct clk *bus_clk; /* bus clock which used to access register */
449 struct clk *src_clk_cg; /* msdc source clock control gate */
450 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
451 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
452 u32 mclk; /* mmc subsystem clock frequency */
453 u32 src_clk_freq; /* source clock frequency */
454 unsigned char timing;
455 bool vqmmc_enabled;
456 u32 latch_ck;
457 u32 hs400_ds_delay;
458 u32 hs400_ds_dly3;
459 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
460 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
461 bool hs400_cmd_resp_sel_rising;
462 /* cmd response sample selection for HS400 */
463 bool hs400_mode; /* current eMMC will run at hs400 mode */
464 bool hs400_tuning; /* hs400 mode online tuning */
465 bool internal_cd; /* Use internal card-detect logic */
466 bool cqhci; /* support eMMC hw cmdq */
467 struct msdc_save_para save_para; /* used when gate HCLK */
468 struct msdc_tune_para def_tune_para; /* default tune setting */
469 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
470 struct cqhci_host *cq_host;
471 };
472
473 static const struct mtk_mmc_compatible mt8135_compat = {
474 .clk_div_bits = 8,
475 .recheck_sdio_irq = true,
476 .hs400_tune = false,
477 .pad_tune_reg = MSDC_PAD_TUNE,
478 .async_fifo = false,
479 .data_tune = false,
480 .busy_check = false,
481 .stop_clk_fix = false,
482 .enhance_rx = false,
483 .support_64g = false,
484 };
485
486 static const struct mtk_mmc_compatible mt8173_compat = {
487 .clk_div_bits = 8,
488 .recheck_sdio_irq = true,
489 .hs400_tune = true,
490 .pad_tune_reg = MSDC_PAD_TUNE,
491 .async_fifo = false,
492 .data_tune = false,
493 .busy_check = false,
494 .stop_clk_fix = false,
495 .enhance_rx = false,
496 .support_64g = false,
497 };
498
499 static const struct mtk_mmc_compatible mt8183_compat = {
500 .clk_div_bits = 12,
501 .recheck_sdio_irq = false,
502 .hs400_tune = false,
503 .pad_tune_reg = MSDC_PAD_TUNE0,
504 .async_fifo = true,
505 .data_tune = true,
506 .busy_check = true,
507 .stop_clk_fix = true,
508 .enhance_rx = true,
509 .support_64g = true,
510 };
511
512 static const struct mtk_mmc_compatible mt2701_compat = {
513 .clk_div_bits = 12,
514 .recheck_sdio_irq = true,
515 .hs400_tune = false,
516 .pad_tune_reg = MSDC_PAD_TUNE0,
517 .async_fifo = true,
518 .data_tune = true,
519 .busy_check = false,
520 .stop_clk_fix = false,
521 .enhance_rx = false,
522 .support_64g = false,
523 };
524
525 static const struct mtk_mmc_compatible mt2712_compat = {
526 .clk_div_bits = 12,
527 .recheck_sdio_irq = false,
528 .hs400_tune = false,
529 .pad_tune_reg = MSDC_PAD_TUNE0,
530 .async_fifo = true,
531 .data_tune = true,
532 .busy_check = true,
533 .stop_clk_fix = true,
534 .enhance_rx = true,
535 .support_64g = true,
536 };
537
538 static const struct mtk_mmc_compatible mt7622_compat = {
539 .clk_div_bits = 12,
540 .recheck_sdio_irq = true,
541 .hs400_tune = false,
542 .pad_tune_reg = MSDC_PAD_TUNE0,
543 .async_fifo = true,
544 .data_tune = true,
545 .busy_check = true,
546 .stop_clk_fix = true,
547 .enhance_rx = true,
548 .support_64g = false,
549 };
550
551 static const struct mtk_mmc_compatible mt8516_compat = {
552 .clk_div_bits = 12,
553 .recheck_sdio_irq = true,
554 .hs400_tune = false,
555 .pad_tune_reg = MSDC_PAD_TUNE0,
556 .async_fifo = true,
557 .data_tune = true,
558 .busy_check = true,
559 .stop_clk_fix = true,
560 };
561
562 static const struct mtk_mmc_compatible mt7620_compat = {
563 .clk_div_bits = 8,
564 .recheck_sdio_irq = true,
565 .hs400_tune = false,
566 .pad_tune_reg = MSDC_PAD_TUNE,
567 .async_fifo = false,
568 .data_tune = false,
569 .busy_check = false,
570 .stop_clk_fix = false,
571 .enhance_rx = false,
572 .use_internal_cd = true,
573 };
574
575 static const struct mtk_mmc_compatible mt6779_compat = {
576 .clk_div_bits = 12,
577 .recheck_sdio_irq = false,
578 .hs400_tune = false,
579 .pad_tune_reg = MSDC_PAD_TUNE0,
580 .async_fifo = true,
581 .data_tune = true,
582 .busy_check = true,
583 .stop_clk_fix = true,
584 .enhance_rx = true,
585 .support_64g = true,
586 };
587
588 static const struct of_device_id msdc_of_ids[] = {
589 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
590 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
591 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
592 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
593 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
594 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
595 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
596 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
597 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
598 {}
599 };
600 MODULE_DEVICE_TABLE(of, msdc_of_ids);
601
sdr_set_bits(void __iomem * reg,u32 bs)602 static void sdr_set_bits(void __iomem *reg, u32 bs)
603 {
604 u32 val = readl(reg);
605
606 val |= bs;
607 writel(val, reg);
608 }
609
sdr_clr_bits(void __iomem * reg,u32 bs)610 static void sdr_clr_bits(void __iomem *reg, u32 bs)
611 {
612 u32 val = readl(reg);
613
614 val &= ~bs;
615 writel(val, reg);
616 }
617
sdr_set_field(void __iomem * reg,u32 field,u32 val)618 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
619 {
620 unsigned int tv = readl(reg);
621
622 tv &= ~field;
623 tv |= ((val) << (ffs((unsigned int)field) - 1));
624 writel(tv, reg);
625 }
626
sdr_get_field(void __iomem * reg,u32 field,u32 * val)627 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
628 {
629 unsigned int tv = readl(reg);
630
631 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
632 }
633
msdc_reset_hw(struct msdc_host * host)634 static void msdc_reset_hw(struct msdc_host *host)
635 {
636 u32 val;
637
638 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
639 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
640
641 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
642 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
643 !(val & MSDC_FIFOCS_CLR), 0, 0);
644
645 val = readl(host->base + MSDC_INT);
646 writel(val, host->base + MSDC_INT);
647 }
648
649 static void msdc_cmd_next(struct msdc_host *host,
650 struct mmc_request *mrq, struct mmc_command *cmd);
651 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
652
653 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
654 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
655 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
656 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
657 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
658 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
659
msdc_dma_calcs(u8 * buf,u32 len)660 static u8 msdc_dma_calcs(u8 *buf, u32 len)
661 {
662 u32 i, sum = 0;
663
664 for (i = 0; i < len; i++)
665 sum += buf[i];
666 return 0xff - (u8) sum;
667 }
668
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)669 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
670 struct mmc_data *data)
671 {
672 unsigned int j, dma_len;
673 dma_addr_t dma_address;
674 u32 dma_ctrl;
675 struct scatterlist *sg;
676 struct mt_gpdma_desc *gpd;
677 struct mt_bdma_desc *bd;
678
679 sg = data->sg;
680
681 gpd = dma->gpd;
682 bd = dma->bd;
683
684 /* modify gpd */
685 gpd->gpd_info |= GPDMA_DESC_HWO;
686 gpd->gpd_info |= GPDMA_DESC_BDP;
687 /* need to clear first. use these bits to calc checksum */
688 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
689 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
690
691 /* modify bd */
692 for_each_sg(data->sg, sg, data->sg_count, j) {
693 dma_address = sg_dma_address(sg);
694 dma_len = sg_dma_len(sg);
695
696 /* init bd */
697 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
698 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
699 bd[j].ptr = lower_32_bits(dma_address);
700 if (host->dev_comp->support_64g) {
701 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
702 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
703 << 28;
704 }
705
706 if (host->dev_comp->support_64g) {
707 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
708 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
709 } else {
710 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
711 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
712 }
713
714 if (j == data->sg_count - 1) /* the last bd */
715 bd[j].bd_info |= BDMA_DESC_EOL;
716 else
717 bd[j].bd_info &= ~BDMA_DESC_EOL;
718
719 /* checksume need to clear first */
720 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
721 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
722 }
723
724 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
725 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
726 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
727 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
728 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
729 if (host->dev_comp->support_64g)
730 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
731 upper_32_bits(dma->gpd_addr) & 0xf);
732 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
733 }
734
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)735 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
736 {
737 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
738 data->host_cookie |= MSDC_PREPARE_FLAG;
739 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
740 mmc_get_dma_dir(data));
741 }
742 }
743
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)744 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
745 {
746 if (data->host_cookie & MSDC_ASYNC_FLAG)
747 return;
748
749 if (data->host_cookie & MSDC_PREPARE_FLAG) {
750 dma_unmap_sg(host->dev, data->sg, data->sg_len,
751 mmc_get_dma_dir(data));
752 data->host_cookie &= ~MSDC_PREPARE_FLAG;
753 }
754 }
755
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)756 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
757 {
758 struct mmc_host *mmc = mmc_from_priv(host);
759 u64 timeout, clk_ns;
760 u32 mode = 0;
761
762 if (mmc->actual_clock == 0) {
763 timeout = 0;
764 } else {
765 clk_ns = 1000000000ULL;
766 do_div(clk_ns, mmc->actual_clock);
767 timeout = ns + clk_ns - 1;
768 do_div(timeout, clk_ns);
769 timeout += clks;
770 /* in 1048576 sclk cycle unit */
771 timeout = DIV_ROUND_UP(timeout, (0x1 << 20));
772 if (host->dev_comp->clk_div_bits == 8)
773 sdr_get_field(host->base + MSDC_CFG,
774 MSDC_CFG_CKMOD, &mode);
775 else
776 sdr_get_field(host->base + MSDC_CFG,
777 MSDC_CFG_CKMOD_EXTRA, &mode);
778 /*DDR mode will double the clk cycles for data timeout */
779 timeout = mode >= 2 ? timeout * 2 : timeout;
780 timeout = timeout > 1 ? timeout - 1 : 0;
781 }
782 return timeout;
783 }
784
785 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)786 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
787 {
788 u64 timeout;
789
790 host->timeout_ns = ns;
791 host->timeout_clks = clks;
792
793 timeout = msdc_timeout_cal(host, ns, clks);
794 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
795 (u32)(timeout > 255 ? 255 : timeout));
796 }
797
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)798 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
799 {
800 u64 timeout;
801
802 timeout = msdc_timeout_cal(host, ns, clks);
803 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
804 (u32)(timeout > 8191 ? 8191 : timeout));
805 }
806
msdc_gate_clock(struct msdc_host * host)807 static void msdc_gate_clock(struct msdc_host *host)
808 {
809 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
810 clk_disable_unprepare(host->src_clk_cg);
811 clk_disable_unprepare(host->src_clk);
812 clk_disable_unprepare(host->bus_clk);
813 clk_disable_unprepare(host->h_clk);
814 }
815
msdc_ungate_clock(struct msdc_host * host)816 static int msdc_ungate_clock(struct msdc_host *host)
817 {
818 u32 val;
819 int ret;
820
821 clk_prepare_enable(host->h_clk);
822 clk_prepare_enable(host->bus_clk);
823 clk_prepare_enable(host->src_clk);
824 clk_prepare_enable(host->src_clk_cg);
825 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
826 if (ret) {
827 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
828 return ret;
829 }
830
831 return readl_poll_timeout(host->base + MSDC_CFG, val,
832 (val & MSDC_CFG_CKSTB), 1, 20000);
833 }
834
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)835 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
836 {
837 struct mmc_host *mmc = mmc_from_priv(host);
838 u32 mode;
839 u32 flags;
840 u32 div;
841 u32 sclk;
842 u32 tune_reg = host->dev_comp->pad_tune_reg;
843 u32 val;
844
845 if (!hz) {
846 dev_dbg(host->dev, "set mclk to 0\n");
847 host->mclk = 0;
848 mmc->actual_clock = 0;
849 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
850 return;
851 }
852
853 flags = readl(host->base + MSDC_INTEN);
854 sdr_clr_bits(host->base + MSDC_INTEN, flags);
855 if (host->dev_comp->clk_div_bits == 8)
856 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
857 else
858 sdr_clr_bits(host->base + MSDC_CFG,
859 MSDC_CFG_HS400_CK_MODE_EXTRA);
860 if (timing == MMC_TIMING_UHS_DDR50 ||
861 timing == MMC_TIMING_MMC_DDR52 ||
862 timing == MMC_TIMING_MMC_HS400) {
863 if (timing == MMC_TIMING_MMC_HS400)
864 mode = 0x3;
865 else
866 mode = 0x2; /* ddr mode and use divisor */
867
868 if (hz >= (host->src_clk_freq >> 2)) {
869 div = 0; /* mean div = 1/4 */
870 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
871 } else {
872 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
873 sclk = (host->src_clk_freq >> 2) / div;
874 div = (div >> 1);
875 }
876
877 if (timing == MMC_TIMING_MMC_HS400 &&
878 hz >= (host->src_clk_freq >> 1)) {
879 if (host->dev_comp->clk_div_bits == 8)
880 sdr_set_bits(host->base + MSDC_CFG,
881 MSDC_CFG_HS400_CK_MODE);
882 else
883 sdr_set_bits(host->base + MSDC_CFG,
884 MSDC_CFG_HS400_CK_MODE_EXTRA);
885 sclk = host->src_clk_freq >> 1;
886 div = 0; /* div is ignore when bit18 is set */
887 }
888 } else if (hz >= host->src_clk_freq) {
889 mode = 0x1; /* no divisor */
890 div = 0;
891 sclk = host->src_clk_freq;
892 } else {
893 mode = 0x0; /* use divisor */
894 if (hz >= (host->src_clk_freq >> 1)) {
895 div = 0; /* mean div = 1/2 */
896 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
897 } else {
898 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
899 sclk = (host->src_clk_freq >> 2) / div;
900 }
901 }
902 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
903 /*
904 * As src_clk/HCLK use the same bit to gate/ungate,
905 * So if want to only gate src_clk, need gate its parent(mux).
906 */
907 if (host->src_clk_cg)
908 clk_disable_unprepare(host->src_clk_cg);
909 else
910 clk_disable_unprepare(clk_get_parent(host->src_clk));
911 if (host->dev_comp->clk_div_bits == 8)
912 sdr_set_field(host->base + MSDC_CFG,
913 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
914 (mode << 8) | div);
915 else
916 sdr_set_field(host->base + MSDC_CFG,
917 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
918 (mode << 12) | div);
919 if (host->src_clk_cg)
920 clk_prepare_enable(host->src_clk_cg);
921 else
922 clk_prepare_enable(clk_get_parent(host->src_clk));
923
924 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
925 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
926 mmc->actual_clock = sclk;
927 host->mclk = hz;
928 host->timing = timing;
929 /* need because clk changed. */
930 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
931 sdr_set_bits(host->base + MSDC_INTEN, flags);
932
933 /*
934 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
935 * tune result of hs200/200Mhz is not suitable for 50Mhz
936 */
937 if (mmc->actual_clock <= 52000000) {
938 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
939 if (host->top_base) {
940 writel(host->def_tune_para.emmc_top_control,
941 host->top_base + EMMC_TOP_CONTROL);
942 writel(host->def_tune_para.emmc_top_cmd,
943 host->top_base + EMMC_TOP_CMD);
944 } else {
945 writel(host->def_tune_para.pad_tune,
946 host->base + tune_reg);
947 }
948 } else {
949 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
950 writel(host->saved_tune_para.pad_cmd_tune,
951 host->base + PAD_CMD_TUNE);
952 if (host->top_base) {
953 writel(host->saved_tune_para.emmc_top_control,
954 host->top_base + EMMC_TOP_CONTROL);
955 writel(host->saved_tune_para.emmc_top_cmd,
956 host->top_base + EMMC_TOP_CMD);
957 } else {
958 writel(host->saved_tune_para.pad_tune,
959 host->base + tune_reg);
960 }
961 }
962
963 if (timing == MMC_TIMING_MMC_HS400 &&
964 host->dev_comp->hs400_tune)
965 sdr_set_field(host->base + tune_reg,
966 MSDC_PAD_TUNE_CMDRRDLY,
967 host->hs400_cmd_int_delay);
968 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
969 timing);
970 }
971
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)972 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
973 struct mmc_request *mrq, struct mmc_command *cmd)
974 {
975 u32 resp;
976
977 switch (mmc_resp_type(cmd)) {
978 /* Actually, R1, R5, R6, R7 are the same */
979 case MMC_RSP_R1:
980 resp = 0x1;
981 break;
982 case MMC_RSP_R1B:
983 resp = 0x7;
984 break;
985 case MMC_RSP_R2:
986 resp = 0x2;
987 break;
988 case MMC_RSP_R3:
989 resp = 0x3;
990 break;
991 case MMC_RSP_NONE:
992 default:
993 resp = 0x0;
994 break;
995 }
996
997 return resp;
998 }
999
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1000 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1001 struct mmc_request *mrq, struct mmc_command *cmd)
1002 {
1003 struct mmc_host *mmc = mmc_from_priv(host);
1004 /* rawcmd :
1005 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1006 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1007 */
1008 u32 opcode = cmd->opcode;
1009 u32 resp = msdc_cmd_find_resp(host, mrq, cmd);
1010 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1011
1012 host->cmd_rsp = resp;
1013
1014 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1015 opcode == MMC_STOP_TRANSMISSION)
1016 rawcmd |= (0x1 << 14);
1017 else if (opcode == SD_SWITCH_VOLTAGE)
1018 rawcmd |= (0x1 << 30);
1019 else if (opcode == SD_APP_SEND_SCR ||
1020 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1021 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1022 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1023 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1024 rawcmd |= (0x1 << 11);
1025
1026 if (cmd->data) {
1027 struct mmc_data *data = cmd->data;
1028
1029 if (mmc_op_multi(opcode)) {
1030 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1031 !(mrq->sbc->arg & 0xFFFF0000))
1032 rawcmd |= 0x2 << 28; /* AutoCMD23 */
1033 }
1034
1035 rawcmd |= ((data->blksz & 0xFFF) << 16);
1036 if (data->flags & MMC_DATA_WRITE)
1037 rawcmd |= (0x1 << 13);
1038 if (data->blocks > 1)
1039 rawcmd |= (0x2 << 11);
1040 else
1041 rawcmd |= (0x1 << 11);
1042 /* Always use dma mode */
1043 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1044
1045 if (host->timeout_ns != data->timeout_ns ||
1046 host->timeout_clks != data->timeout_clks)
1047 msdc_set_timeout(host, data->timeout_ns,
1048 data->timeout_clks);
1049
1050 writel(data->blocks, host->base + SDC_BLK_NUM);
1051 }
1052 return rawcmd;
1053 }
1054
msdc_start_data(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd,struct mmc_data * data)1055 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq,
1056 struct mmc_command *cmd, struct mmc_data *data)
1057 {
1058 bool read;
1059
1060 WARN_ON(host->data);
1061 host->data = data;
1062 read = data->flags & MMC_DATA_READ;
1063
1064 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1065 msdc_dma_setup(host, &host->dma, data);
1066 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1067 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1068 dev_dbg(host->dev, "DMA start\n");
1069 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1070 __func__, cmd->opcode, data->blocks, read);
1071 }
1072
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1073 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1074 struct mmc_command *cmd)
1075 {
1076 u32 *rsp = cmd->resp;
1077
1078 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1079
1080 if (events & MSDC_INT_ACMDRDY) {
1081 cmd->error = 0;
1082 } else {
1083 msdc_reset_hw(host);
1084 if (events & MSDC_INT_ACMDCRCERR) {
1085 cmd->error = -EILSEQ;
1086 host->error |= REQ_STOP_EIO;
1087 } else if (events & MSDC_INT_ACMDTMO) {
1088 cmd->error = -ETIMEDOUT;
1089 host->error |= REQ_STOP_TMO;
1090 }
1091 dev_err(host->dev,
1092 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1093 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1094 }
1095 return cmd->error;
1096 }
1097
1098 /*
1099 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1100 *
1101 * Host controller may lost interrupt in some special case.
1102 * Add SDIO irq recheck mechanism to make sure all interrupts
1103 * can be processed immediately
1104 */
msdc_recheck_sdio_irq(struct msdc_host * host)1105 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1106 {
1107 struct mmc_host *mmc = mmc_from_priv(host);
1108 u32 reg_int, reg_inten, reg_ps;
1109
1110 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1111 reg_inten = readl(host->base + MSDC_INTEN);
1112 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1113 reg_int = readl(host->base + MSDC_INT);
1114 reg_ps = readl(host->base + MSDC_PS);
1115 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1116 reg_ps & MSDC_PS_DATA1)) {
1117 __msdc_enable_sdio_irq(host, 0);
1118 sdio_signal_irq(mmc);
1119 }
1120 }
1121 }
1122 }
1123
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1124 static void msdc_track_cmd_data(struct msdc_host *host,
1125 struct mmc_command *cmd, struct mmc_data *data)
1126 {
1127 if (host->error)
1128 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1129 __func__, cmd->opcode, cmd->arg, host->error);
1130 }
1131
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1132 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1133 {
1134 unsigned long flags;
1135
1136 /*
1137 * No need check the return value of cancel_delayed_work, as only ONE
1138 * path will go here!
1139 */
1140 cancel_delayed_work(&host->req_timeout);
1141
1142 spin_lock_irqsave(&host->lock, flags);
1143 host->mrq = NULL;
1144 spin_unlock_irqrestore(&host->lock, flags);
1145
1146 msdc_track_cmd_data(host, mrq->cmd, mrq->data);
1147 if (mrq->data)
1148 msdc_unprepare_data(host, mrq->data);
1149 if (host->error)
1150 msdc_reset_hw(host);
1151 mmc_request_done(mmc_from_priv(host), mrq);
1152 if (host->dev_comp->recheck_sdio_irq)
1153 msdc_recheck_sdio_irq(host);
1154 }
1155
1156 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1157 static bool msdc_cmd_done(struct msdc_host *host, int events,
1158 struct mmc_request *mrq, struct mmc_command *cmd)
1159 {
1160 bool done = false;
1161 bool sbc_error;
1162 unsigned long flags;
1163 u32 *rsp;
1164
1165 if (mrq->sbc && cmd == mrq->cmd &&
1166 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1167 | MSDC_INT_ACMDTMO)))
1168 msdc_auto_cmd_done(host, events, mrq->sbc);
1169
1170 sbc_error = mrq->sbc && mrq->sbc->error;
1171
1172 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1173 | MSDC_INT_RSPCRCERR
1174 | MSDC_INT_CMDTMO)))
1175 return done;
1176
1177 spin_lock_irqsave(&host->lock, flags);
1178 done = !host->cmd;
1179 host->cmd = NULL;
1180 spin_unlock_irqrestore(&host->lock, flags);
1181
1182 if (done)
1183 return true;
1184 rsp = cmd->resp;
1185
1186 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1187
1188 if (cmd->flags & MMC_RSP_PRESENT) {
1189 if (cmd->flags & MMC_RSP_136) {
1190 rsp[0] = readl(host->base + SDC_RESP3);
1191 rsp[1] = readl(host->base + SDC_RESP2);
1192 rsp[2] = readl(host->base + SDC_RESP1);
1193 rsp[3] = readl(host->base + SDC_RESP0);
1194 } else {
1195 rsp[0] = readl(host->base + SDC_RESP0);
1196 }
1197 }
1198
1199 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1200 if (events & MSDC_INT_CMDTMO ||
1201 (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1202 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
1203 !host->hs400_tuning))
1204 /*
1205 * should not clear fifo/interrupt as the tune data
1206 * may have alreay come when cmd19/cmd21 gets response
1207 * CRC error.
1208 */
1209 msdc_reset_hw(host);
1210 if (events & MSDC_INT_RSPCRCERR) {
1211 cmd->error = -EILSEQ;
1212 host->error |= REQ_CMD_EIO;
1213 } else if (events & MSDC_INT_CMDTMO) {
1214 cmd->error = -ETIMEDOUT;
1215 host->error |= REQ_CMD_TMO;
1216 }
1217 }
1218 if (cmd->error)
1219 dev_dbg(host->dev,
1220 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1221 __func__, cmd->opcode, cmd->arg, rsp[0],
1222 cmd->error);
1223
1224 msdc_cmd_next(host, mrq, cmd);
1225 return true;
1226 }
1227
1228 /* It is the core layer's responsibility to ensure card status
1229 * is correct before issue a request. but host design do below
1230 * checks recommended.
1231 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1232 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1233 struct mmc_request *mrq, struct mmc_command *cmd)
1234 {
1235 u32 val;
1236 int ret;
1237
1238 /* The max busy time we can endure is 20ms */
1239 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1240 !(val & SDC_STS_CMDBUSY), 1, 20000);
1241 if (ret) {
1242 dev_err(host->dev, "CMD bus busy detected\n");
1243 host->error |= REQ_CMD_BUSY;
1244 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1245 return false;
1246 }
1247
1248 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1249 /* R1B or with data, should check SDCBUSY */
1250 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1251 !(val & SDC_STS_SDCBUSY), 1, 20000);
1252 if (ret) {
1253 dev_err(host->dev, "Controller busy detected\n");
1254 host->error |= REQ_CMD_BUSY;
1255 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1256 return false;
1257 }
1258 }
1259 return true;
1260 }
1261
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1262 static void msdc_start_command(struct msdc_host *host,
1263 struct mmc_request *mrq, struct mmc_command *cmd)
1264 {
1265 u32 rawcmd;
1266 unsigned long flags;
1267
1268 WARN_ON(host->cmd);
1269 host->cmd = cmd;
1270
1271 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1272 if (!msdc_cmd_is_ready(host, mrq, cmd))
1273 return;
1274
1275 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1276 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1277 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1278 msdc_reset_hw(host);
1279 }
1280
1281 cmd->error = 0;
1282 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1283
1284 spin_lock_irqsave(&host->lock, flags);
1285 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1286 spin_unlock_irqrestore(&host->lock, flags);
1287
1288 writel(cmd->arg, host->base + SDC_ARG);
1289 writel(rawcmd, host->base + SDC_CMD);
1290 }
1291
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1292 static void msdc_cmd_next(struct msdc_host *host,
1293 struct mmc_request *mrq, struct mmc_command *cmd)
1294 {
1295 if ((cmd->error &&
1296 !(cmd->error == -EILSEQ &&
1297 (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1298 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
1299 host->hs400_tuning))) ||
1300 (mrq->sbc && mrq->sbc->error))
1301 msdc_request_done(host, mrq);
1302 else if (cmd == mrq->sbc)
1303 msdc_start_command(host, mrq, mrq->cmd);
1304 else if (!cmd->data)
1305 msdc_request_done(host, mrq);
1306 else
1307 msdc_start_data(host, mrq, cmd, cmd->data);
1308 }
1309
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1310 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1311 {
1312 struct msdc_host *host = mmc_priv(mmc);
1313
1314 host->error = 0;
1315 WARN_ON(host->mrq);
1316 host->mrq = mrq;
1317
1318 if (mrq->data)
1319 msdc_prepare_data(host, mrq->data);
1320
1321 /* if SBC is required, we have HW option and SW option.
1322 * if HW option is enabled, and SBC does not have "special" flags,
1323 * use HW option, otherwise use SW option
1324 */
1325 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1326 (mrq->sbc->arg & 0xFFFF0000)))
1327 msdc_start_command(host, mrq, mrq->sbc);
1328 else
1329 msdc_start_command(host, mrq, mrq->cmd);
1330 }
1331
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1332 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1333 {
1334 struct msdc_host *host = mmc_priv(mmc);
1335 struct mmc_data *data = mrq->data;
1336
1337 if (!data)
1338 return;
1339
1340 msdc_prepare_data(host, data);
1341 data->host_cookie |= MSDC_ASYNC_FLAG;
1342 }
1343
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1344 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1345 int err)
1346 {
1347 struct msdc_host *host = mmc_priv(mmc);
1348 struct mmc_data *data = mrq->data;
1349
1350 if (!data)
1351 return;
1352
1353 if (data->host_cookie) {
1354 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1355 msdc_unprepare_data(host, data);
1356 }
1357 }
1358
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1359 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1360 {
1361 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1362 !mrq->sbc)
1363 msdc_start_command(host, mrq, mrq->stop);
1364 else
1365 msdc_request_done(host, mrq);
1366 }
1367
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1368 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1369 struct mmc_request *mrq, struct mmc_data *data)
1370 {
1371 struct mmc_command *stop;
1372 unsigned long flags;
1373 bool done;
1374 unsigned int check_data = events &
1375 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1376 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1377 | MSDC_INT_DMA_PROTECT);
1378 u32 val;
1379 int ret;
1380
1381 spin_lock_irqsave(&host->lock, flags);
1382 done = !host->data;
1383 if (check_data)
1384 host->data = NULL;
1385 spin_unlock_irqrestore(&host->lock, flags);
1386
1387 if (done)
1388 return;
1389 stop = data->stop;
1390
1391 if (check_data || (stop && stop->error)) {
1392 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1393 readl(host->base + MSDC_DMA_CFG));
1394 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1395 1);
1396
1397 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1398 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1399 if (ret)
1400 dev_dbg(host->dev, "DMA stop timed out\n");
1401
1402 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1403 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1404 if (ret)
1405 dev_dbg(host->dev, "DMA inactive timed out\n");
1406
1407 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1408 dev_dbg(host->dev, "DMA stop\n");
1409
1410 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1411 data->bytes_xfered = data->blocks * data->blksz;
1412 } else {
1413 dev_dbg(host->dev, "interrupt events: %x\n", events);
1414 msdc_reset_hw(host);
1415 host->error |= REQ_DAT_ERR;
1416 data->bytes_xfered = 0;
1417
1418 if (events & MSDC_INT_DATTMO)
1419 data->error = -ETIMEDOUT;
1420 else if (events & MSDC_INT_DATCRCERR)
1421 data->error = -EILSEQ;
1422
1423 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1424 __func__, mrq->cmd->opcode, data->blocks);
1425 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1426 (int)data->error, data->bytes_xfered);
1427 }
1428
1429 msdc_data_xfer_next(host, mrq);
1430 }
1431 }
1432
msdc_set_buswidth(struct msdc_host * host,u32 width)1433 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1434 {
1435 u32 val = readl(host->base + SDC_CFG);
1436
1437 val &= ~SDC_CFG_BUSWIDTH;
1438
1439 switch (width) {
1440 default:
1441 case MMC_BUS_WIDTH_1:
1442 val |= (MSDC_BUS_1BITS << 16);
1443 break;
1444 case MMC_BUS_WIDTH_4:
1445 val |= (MSDC_BUS_4BITS << 16);
1446 break;
1447 case MMC_BUS_WIDTH_8:
1448 val |= (MSDC_BUS_8BITS << 16);
1449 break;
1450 }
1451
1452 writel(val, host->base + SDC_CFG);
1453 dev_dbg(host->dev, "Bus Width = %d", width);
1454 }
1455
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1456 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1457 {
1458 struct msdc_host *host = mmc_priv(mmc);
1459 int ret;
1460
1461 if (!IS_ERR(mmc->supply.vqmmc)) {
1462 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1463 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1464 dev_err(host->dev, "Unsupported signal voltage!\n");
1465 return -EINVAL;
1466 }
1467
1468 ret = mmc_regulator_set_vqmmc(mmc, ios);
1469 if (ret < 0) {
1470 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1471 ret, ios->signal_voltage);
1472 return ret;
1473 }
1474
1475 /* Apply different pinctrl settings for different signal voltage */
1476 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1477 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1478 else
1479 pinctrl_select_state(host->pinctrl, host->pins_default);
1480 }
1481 return 0;
1482 }
1483
msdc_card_busy(struct mmc_host * mmc)1484 static int msdc_card_busy(struct mmc_host *mmc)
1485 {
1486 struct msdc_host *host = mmc_priv(mmc);
1487 u32 status = readl(host->base + MSDC_PS);
1488
1489 /* only check if data0 is low */
1490 return !(status & BIT(16));
1491 }
1492
msdc_request_timeout(struct work_struct * work)1493 static void msdc_request_timeout(struct work_struct *work)
1494 {
1495 struct msdc_host *host = container_of(work, struct msdc_host,
1496 req_timeout.work);
1497
1498 /* simulate HW timeout status */
1499 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1500 if (host->mrq) {
1501 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1502 host->mrq, host->mrq->cmd->opcode);
1503 if (host->cmd) {
1504 dev_err(host->dev, "%s: aborting cmd=%d\n",
1505 __func__, host->cmd->opcode);
1506 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1507 host->cmd);
1508 } else if (host->data) {
1509 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1510 __func__, host->mrq->cmd->opcode,
1511 host->data->blocks);
1512 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1513 host->data);
1514 }
1515 }
1516 }
1517
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1518 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1519 {
1520 if (enb) {
1521 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1522 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1523 if (host->dev_comp->recheck_sdio_irq)
1524 msdc_recheck_sdio_irq(host);
1525 } else {
1526 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1527 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1528 }
1529 }
1530
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1531 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1532 {
1533 unsigned long flags;
1534 struct msdc_host *host = mmc_priv(mmc);
1535
1536 spin_lock_irqsave(&host->lock, flags);
1537 __msdc_enable_sdio_irq(host, enb);
1538 spin_unlock_irqrestore(&host->lock, flags);
1539
1540 if (enb)
1541 pm_runtime_get_noresume(host->dev);
1542 else
1543 pm_runtime_put_noidle(host->dev);
1544 }
1545
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1546 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1547 {
1548 struct mmc_host *mmc = mmc_from_priv(host);
1549 int cmd_err = 0, dat_err = 0;
1550
1551 if (intsts & MSDC_INT_RSPCRCERR) {
1552 cmd_err = -EILSEQ;
1553 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1554 } else if (intsts & MSDC_INT_CMDTMO) {
1555 cmd_err = -ETIMEDOUT;
1556 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1557 }
1558
1559 if (intsts & MSDC_INT_DATCRCERR) {
1560 dat_err = -EILSEQ;
1561 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1562 } else if (intsts & MSDC_INT_DATTMO) {
1563 dat_err = -ETIMEDOUT;
1564 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1565 }
1566
1567 if (cmd_err || dat_err) {
1568 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1569 cmd_err, dat_err, intsts);
1570 }
1571
1572 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1573 }
1574
msdc_irq(int irq,void * dev_id)1575 static irqreturn_t msdc_irq(int irq, void *dev_id)
1576 {
1577 struct msdc_host *host = (struct msdc_host *) dev_id;
1578 struct mmc_host *mmc = mmc_from_priv(host);
1579
1580 while (true) {
1581 struct mmc_request *mrq;
1582 struct mmc_command *cmd;
1583 struct mmc_data *data;
1584 u32 events, event_mask;
1585
1586 spin_lock(&host->lock);
1587 events = readl(host->base + MSDC_INT);
1588 event_mask = readl(host->base + MSDC_INTEN);
1589 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1590 __msdc_enable_sdio_irq(host, 0);
1591 /* clear interrupts */
1592 writel(events & event_mask, host->base + MSDC_INT);
1593
1594 mrq = host->mrq;
1595 cmd = host->cmd;
1596 data = host->data;
1597 spin_unlock(&host->lock);
1598
1599 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1600 sdio_signal_irq(mmc);
1601
1602 if ((events & event_mask) & MSDC_INT_CDSC) {
1603 if (host->internal_cd)
1604 mmc_detect_change(mmc, msecs_to_jiffies(20));
1605 events &= ~MSDC_INT_CDSC;
1606 }
1607
1608 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1609 break;
1610
1611 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1612 (events & MSDC_INT_CMDQ)) {
1613 msdc_cmdq_irq(host, events);
1614 /* clear interrupts */
1615 writel(events, host->base + MSDC_INT);
1616 return IRQ_HANDLED;
1617 }
1618
1619 if (!mrq) {
1620 dev_err(host->dev,
1621 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1622 __func__, events, event_mask);
1623 WARN_ON(1);
1624 break;
1625 }
1626
1627 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1628
1629 if (cmd)
1630 msdc_cmd_done(host, events, mrq, cmd);
1631 else if (data)
1632 msdc_data_xfer_done(host, events, mrq, data);
1633 }
1634
1635 return IRQ_HANDLED;
1636 }
1637
msdc_init_hw(struct msdc_host * host)1638 static void msdc_init_hw(struct msdc_host *host)
1639 {
1640 u32 val;
1641 u32 tune_reg = host->dev_comp->pad_tune_reg;
1642
1643 if (host->reset) {
1644 reset_control_assert(host->reset);
1645 usleep_range(10, 50);
1646 reset_control_deassert(host->reset);
1647 }
1648
1649 /* Configure to MMC/SD mode, clock free running */
1650 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1651
1652 /* Reset */
1653 msdc_reset_hw(host);
1654
1655 /* Disable and clear all interrupts */
1656 writel(0, host->base + MSDC_INTEN);
1657 val = readl(host->base + MSDC_INT);
1658 writel(val, host->base + MSDC_INT);
1659
1660 /* Configure card detection */
1661 if (host->internal_cd) {
1662 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1663 DEFAULT_DEBOUNCE);
1664 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1665 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1666 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1667 } else {
1668 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1669 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1670 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1671 }
1672
1673 if (host->top_base) {
1674 writel(0, host->top_base + EMMC_TOP_CONTROL);
1675 writel(0, host->top_base + EMMC_TOP_CMD);
1676 } else {
1677 writel(0, host->base + tune_reg);
1678 }
1679 writel(0, host->base + MSDC_IOCON);
1680 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1681 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1682 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1683 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1684 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1685
1686 if (host->dev_comp->stop_clk_fix) {
1687 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1688 MSDC_PATCH_BIT1_STOP_DLY, 3);
1689 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1690 SDC_FIFO_CFG_WRVALIDSEL);
1691 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1692 SDC_FIFO_CFG_RDVALIDSEL);
1693 }
1694
1695 if (host->dev_comp->busy_check)
1696 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7));
1697
1698 if (host->dev_comp->async_fifo) {
1699 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1700 MSDC_PB2_RESPWAIT, 3);
1701 if (host->dev_comp->enhance_rx) {
1702 if (host->top_base)
1703 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1704 SDC_RX_ENH_EN);
1705 else
1706 sdr_set_bits(host->base + SDC_ADV_CFG0,
1707 SDC_RX_ENHANCE_EN);
1708 } else {
1709 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1710 MSDC_PB2_RESPSTSENSEL, 2);
1711 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1712 MSDC_PB2_CRCSTSENSEL, 2);
1713 }
1714 /* use async fifo, then no need tune internal delay */
1715 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1716 MSDC_PATCH_BIT2_CFGRESP);
1717 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1718 MSDC_PATCH_BIT2_CFGCRCSTS);
1719 }
1720
1721 if (host->dev_comp->support_64g)
1722 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1723 MSDC_PB2_SUPPORT_64G);
1724 if (host->dev_comp->data_tune) {
1725 if (host->top_base) {
1726 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1727 PAD_DAT_RD_RXDLY_SEL);
1728 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1729 DATA_K_VALUE_SEL);
1730 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1731 PAD_CMD_RD_RXDLY_SEL);
1732 } else {
1733 sdr_set_bits(host->base + tune_reg,
1734 MSDC_PAD_TUNE_RD_SEL |
1735 MSDC_PAD_TUNE_CMD_SEL);
1736 }
1737 } else {
1738 /* choose clock tune */
1739 if (host->top_base)
1740 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1741 PAD_RXDLY_SEL);
1742 else
1743 sdr_set_bits(host->base + tune_reg,
1744 MSDC_PAD_TUNE_RXDLYSEL);
1745 }
1746
1747 /* Configure to enable SDIO mode.
1748 * it's must otherwise sdio cmd5 failed
1749 */
1750 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1751
1752 /* Config SDIO device detect interrupt function */
1753 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1754 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1755
1756 /* Configure to default data timeout */
1757 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1758
1759 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1760 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1761 if (host->top_base) {
1762 host->def_tune_para.emmc_top_control =
1763 readl(host->top_base + EMMC_TOP_CONTROL);
1764 host->def_tune_para.emmc_top_cmd =
1765 readl(host->top_base + EMMC_TOP_CMD);
1766 host->saved_tune_para.emmc_top_control =
1767 readl(host->top_base + EMMC_TOP_CONTROL);
1768 host->saved_tune_para.emmc_top_cmd =
1769 readl(host->top_base + EMMC_TOP_CMD);
1770 } else {
1771 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1772 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1773 }
1774 dev_dbg(host->dev, "init hardware done!");
1775 }
1776
msdc_deinit_hw(struct msdc_host * host)1777 static void msdc_deinit_hw(struct msdc_host *host)
1778 {
1779 u32 val;
1780
1781 if (host->internal_cd) {
1782 /* Disabled card-detect */
1783 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1784 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1785 }
1786
1787 /* Disable and clear all interrupts */
1788 writel(0, host->base + MSDC_INTEN);
1789
1790 val = readl(host->base + MSDC_INT);
1791 writel(val, host->base + MSDC_INT);
1792 }
1793
1794 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1795 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1796 {
1797 struct mt_gpdma_desc *gpd = dma->gpd;
1798 struct mt_bdma_desc *bd = dma->bd;
1799 dma_addr_t dma_addr;
1800 int i;
1801
1802 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1803
1804 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1805 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1806 /* gpd->next is must set for desc DMA
1807 * That's why must alloc 2 gpd structure.
1808 */
1809 gpd->next = lower_32_bits(dma_addr);
1810 if (host->dev_comp->support_64g)
1811 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1812
1813 dma_addr = dma->bd_addr;
1814 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1815 if (host->dev_comp->support_64g)
1816 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1817
1818 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1819 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1820 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1821 bd[i].next = lower_32_bits(dma_addr);
1822 if (host->dev_comp->support_64g)
1823 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1824 }
1825 }
1826
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1827 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1828 {
1829 struct msdc_host *host = mmc_priv(mmc);
1830 int ret;
1831
1832 msdc_set_buswidth(host, ios->bus_width);
1833
1834 /* Suspend/Resume will do power off/on */
1835 switch (ios->power_mode) {
1836 case MMC_POWER_UP:
1837 if (!IS_ERR(mmc->supply.vmmc)) {
1838 msdc_init_hw(host);
1839 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1840 ios->vdd);
1841 if (ret) {
1842 dev_err(host->dev, "Failed to set vmmc power!\n");
1843 return;
1844 }
1845 }
1846 break;
1847 case MMC_POWER_ON:
1848 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1849 ret = regulator_enable(mmc->supply.vqmmc);
1850 if (ret)
1851 dev_err(host->dev, "Failed to set vqmmc power!\n");
1852 else
1853 host->vqmmc_enabled = true;
1854 }
1855 break;
1856 case MMC_POWER_OFF:
1857 if (!IS_ERR(mmc->supply.vmmc))
1858 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1859
1860 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1861 regulator_disable(mmc->supply.vqmmc);
1862 host->vqmmc_enabled = false;
1863 }
1864 break;
1865 default:
1866 break;
1867 }
1868
1869 if (host->mclk != ios->clock || host->timing != ios->timing)
1870 msdc_set_mclk(host, ios->timing, ios->clock);
1871 }
1872
test_delay_bit(u32 delay,u32 bit)1873 static u32 test_delay_bit(u32 delay, u32 bit)
1874 {
1875 bit %= PAD_DELAY_MAX;
1876 return delay & (1 << bit);
1877 }
1878
get_delay_len(u32 delay,u32 start_bit)1879 static int get_delay_len(u32 delay, u32 start_bit)
1880 {
1881 int i;
1882
1883 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1884 if (test_delay_bit(delay, start_bit + i) == 0)
1885 return i;
1886 }
1887 return PAD_DELAY_MAX - start_bit;
1888 }
1889
get_best_delay(struct msdc_host * host,u32 delay)1890 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1891 {
1892 int start = 0, len = 0;
1893 int start_final = 0, len_final = 0;
1894 u8 final_phase = 0xff;
1895 struct msdc_delay_phase delay_phase = { 0, };
1896
1897 if (delay == 0) {
1898 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1899 delay_phase.final_phase = final_phase;
1900 return delay_phase;
1901 }
1902
1903 while (start < PAD_DELAY_MAX) {
1904 len = get_delay_len(delay, start);
1905 if (len_final < len) {
1906 start_final = start;
1907 len_final = len;
1908 }
1909 start += len ? len : 1;
1910 if (len >= 12 && start_final < 4)
1911 break;
1912 }
1913
1914 /* The rule is that to find the smallest delay cell */
1915 if (start_final == 0)
1916 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1917 else
1918 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1919 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1920 delay, len_final, final_phase);
1921
1922 delay_phase.maxlen = len_final;
1923 delay_phase.start = start_final;
1924 delay_phase.final_phase = final_phase;
1925 return delay_phase;
1926 }
1927
msdc_set_cmd_delay(struct msdc_host * host,u32 value)1928 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1929 {
1930 u32 tune_reg = host->dev_comp->pad_tune_reg;
1931
1932 if (host->top_base)
1933 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1934 value);
1935 else
1936 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1937 value);
1938 }
1939
msdc_set_data_delay(struct msdc_host * host,u32 value)1940 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1941 {
1942 u32 tune_reg = host->dev_comp->pad_tune_reg;
1943
1944 if (host->top_base)
1945 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1946 PAD_DAT_RD_RXDLY, value);
1947 else
1948 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1949 value);
1950 }
1951
msdc_tune_response(struct mmc_host * mmc,u32 opcode)1952 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1953 {
1954 struct msdc_host *host = mmc_priv(mmc);
1955 u32 rise_delay = 0, fall_delay = 0;
1956 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1957 struct msdc_delay_phase internal_delay_phase;
1958 u8 final_delay, final_maxlen;
1959 u32 internal_delay = 0;
1960 u32 tune_reg = host->dev_comp->pad_tune_reg;
1961 int cmd_err;
1962 int i, j;
1963
1964 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1965 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1966 sdr_set_field(host->base + tune_reg,
1967 MSDC_PAD_TUNE_CMDRRDLY,
1968 host->hs200_cmd_int_delay);
1969
1970 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1971 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
1972 msdc_set_cmd_delay(host, i);
1973 /*
1974 * Using the same parameters, it may sometimes pass the test,
1975 * but sometimes it may fail. To make sure the parameters are
1976 * more stable, we test each set of parameters 3 times.
1977 */
1978 for (j = 0; j < 3; j++) {
1979 mmc_send_tuning(mmc, opcode, &cmd_err);
1980 if (!cmd_err) {
1981 rise_delay |= (1 << i);
1982 } else {
1983 rise_delay &= ~(1 << i);
1984 break;
1985 }
1986 }
1987 }
1988 final_rise_delay = get_best_delay(host, rise_delay);
1989 /* if rising edge has enough margin, then do not scan falling edge */
1990 if (final_rise_delay.maxlen >= 12 ||
1991 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
1992 goto skip_fall;
1993
1994 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1995 for (i = 0; i < PAD_DELAY_MAX; i++) {
1996 msdc_set_cmd_delay(host, i);
1997 /*
1998 * Using the same parameters, it may sometimes pass the test,
1999 * but sometimes it may fail. To make sure the parameters are
2000 * more stable, we test each set of parameters 3 times.
2001 */
2002 for (j = 0; j < 3; j++) {
2003 mmc_send_tuning(mmc, opcode, &cmd_err);
2004 if (!cmd_err) {
2005 fall_delay |= (1 << i);
2006 } else {
2007 fall_delay &= ~(1 << i);
2008 break;
2009 }
2010 }
2011 }
2012 final_fall_delay = get_best_delay(host, fall_delay);
2013
2014 skip_fall:
2015 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2016 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2017 final_maxlen = final_fall_delay.maxlen;
2018 if (final_maxlen == final_rise_delay.maxlen) {
2019 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2020 final_delay = final_rise_delay.final_phase;
2021 } else {
2022 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2023 final_delay = final_fall_delay.final_phase;
2024 }
2025 msdc_set_cmd_delay(host, final_delay);
2026
2027 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2028 goto skip_internal;
2029
2030 for (i = 0; i < PAD_DELAY_MAX; i++) {
2031 sdr_set_field(host->base + tune_reg,
2032 MSDC_PAD_TUNE_CMDRRDLY, i);
2033 mmc_send_tuning(mmc, opcode, &cmd_err);
2034 if (!cmd_err)
2035 internal_delay |= (1 << i);
2036 }
2037 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2038 internal_delay_phase = get_best_delay(host, internal_delay);
2039 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2040 internal_delay_phase.final_phase);
2041 skip_internal:
2042 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2043 return final_delay == 0xff ? -EIO : 0;
2044 }
2045
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2046 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2047 {
2048 struct msdc_host *host = mmc_priv(mmc);
2049 u32 cmd_delay = 0;
2050 struct msdc_delay_phase final_cmd_delay = { 0,};
2051 u8 final_delay;
2052 int cmd_err;
2053 int i, j;
2054
2055 /* select EMMC50 PAD CMD tune */
2056 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2057 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2058
2059 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2060 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2061 sdr_set_field(host->base + MSDC_PAD_TUNE,
2062 MSDC_PAD_TUNE_CMDRRDLY,
2063 host->hs200_cmd_int_delay);
2064
2065 if (host->hs400_cmd_resp_sel_rising)
2066 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2067 else
2068 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2069 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2070 sdr_set_field(host->base + PAD_CMD_TUNE,
2071 PAD_CMD_TUNE_RX_DLY3, i);
2072 /*
2073 * Using the same parameters, it may sometimes pass the test,
2074 * but sometimes it may fail. To make sure the parameters are
2075 * more stable, we test each set of parameters 3 times.
2076 */
2077 for (j = 0; j < 3; j++) {
2078 mmc_send_tuning(mmc, opcode, &cmd_err);
2079 if (!cmd_err) {
2080 cmd_delay |= (1 << i);
2081 } else {
2082 cmd_delay &= ~(1 << i);
2083 break;
2084 }
2085 }
2086 }
2087 final_cmd_delay = get_best_delay(host, cmd_delay);
2088 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2089 final_cmd_delay.final_phase);
2090 final_delay = final_cmd_delay.final_phase;
2091
2092 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2093 return final_delay == 0xff ? -EIO : 0;
2094 }
2095
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2096 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2097 {
2098 struct msdc_host *host = mmc_priv(mmc);
2099 u32 rise_delay = 0, fall_delay = 0;
2100 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2101 u8 final_delay, final_maxlen;
2102 int i, ret;
2103
2104 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2105 host->latch_ck);
2106 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2107 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2108 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2109 msdc_set_data_delay(host, i);
2110 ret = mmc_send_tuning(mmc, opcode, NULL);
2111 if (!ret)
2112 rise_delay |= (1 << i);
2113 }
2114 final_rise_delay = get_best_delay(host, rise_delay);
2115 /* if rising edge has enough margin, then do not scan falling edge */
2116 if (final_rise_delay.maxlen >= 12 ||
2117 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2118 goto skip_fall;
2119
2120 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2121 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2122 for (i = 0; i < PAD_DELAY_MAX; i++) {
2123 msdc_set_data_delay(host, i);
2124 ret = mmc_send_tuning(mmc, opcode, NULL);
2125 if (!ret)
2126 fall_delay |= (1 << i);
2127 }
2128 final_fall_delay = get_best_delay(host, fall_delay);
2129
2130 skip_fall:
2131 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2132 if (final_maxlen == final_rise_delay.maxlen) {
2133 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2134 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2135 final_delay = final_rise_delay.final_phase;
2136 } else {
2137 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2138 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2139 final_delay = final_fall_delay.final_phase;
2140 }
2141 msdc_set_data_delay(host, final_delay);
2142
2143 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2144 return final_delay == 0xff ? -EIO : 0;
2145 }
2146
2147 /*
2148 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2149 * together, which can save the tuning time.
2150 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2151 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2152 {
2153 struct msdc_host *host = mmc_priv(mmc);
2154 u32 rise_delay = 0, fall_delay = 0;
2155 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2156 u8 final_delay, final_maxlen;
2157 int i, ret;
2158
2159 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2160 host->latch_ck);
2161
2162 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2163 sdr_clr_bits(host->base + MSDC_IOCON,
2164 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2165 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2166 msdc_set_cmd_delay(host, i);
2167 msdc_set_data_delay(host, i);
2168 ret = mmc_send_tuning(mmc, opcode, NULL);
2169 if (!ret)
2170 rise_delay |= (1 << i);
2171 }
2172 final_rise_delay = get_best_delay(host, rise_delay);
2173 /* if rising edge has enough margin, then do not scan falling edge */
2174 if (final_rise_delay.maxlen >= 12 ||
2175 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2176 goto skip_fall;
2177
2178 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2179 sdr_set_bits(host->base + MSDC_IOCON,
2180 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2181 for (i = 0; i < PAD_DELAY_MAX; i++) {
2182 msdc_set_cmd_delay(host, i);
2183 msdc_set_data_delay(host, i);
2184 ret = mmc_send_tuning(mmc, opcode, NULL);
2185 if (!ret)
2186 fall_delay |= (1 << i);
2187 }
2188 final_fall_delay = get_best_delay(host, fall_delay);
2189
2190 skip_fall:
2191 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2192 if (final_maxlen == final_rise_delay.maxlen) {
2193 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2194 sdr_clr_bits(host->base + MSDC_IOCON,
2195 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2196 final_delay = final_rise_delay.final_phase;
2197 } else {
2198 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2199 sdr_set_bits(host->base + MSDC_IOCON,
2200 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2201 final_delay = final_fall_delay.final_phase;
2202 }
2203
2204 msdc_set_cmd_delay(host, final_delay);
2205 msdc_set_data_delay(host, final_delay);
2206
2207 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2208 return final_delay == 0xff ? -EIO : 0;
2209 }
2210
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2211 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2212 {
2213 struct msdc_host *host = mmc_priv(mmc);
2214 int ret;
2215 u32 tune_reg = host->dev_comp->pad_tune_reg;
2216
2217 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2218 ret = msdc_tune_together(mmc, opcode);
2219 if (host->hs400_mode) {
2220 sdr_clr_bits(host->base + MSDC_IOCON,
2221 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2222 msdc_set_data_delay(host, 0);
2223 }
2224 goto tune_done;
2225 }
2226 if (host->hs400_mode &&
2227 host->dev_comp->hs400_tune)
2228 ret = hs400_tune_response(mmc, opcode);
2229 else
2230 ret = msdc_tune_response(mmc, opcode);
2231 if (ret == -EIO) {
2232 dev_err(host->dev, "Tune response fail!\n");
2233 return ret;
2234 }
2235 if (host->hs400_mode == false) {
2236 ret = msdc_tune_data(mmc, opcode);
2237 if (ret == -EIO)
2238 dev_err(host->dev, "Tune data fail!\n");
2239 }
2240
2241 tune_done:
2242 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2243 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2244 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2245 if (host->top_base) {
2246 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2247 EMMC_TOP_CONTROL);
2248 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2249 EMMC_TOP_CMD);
2250 }
2251 return ret;
2252 }
2253
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2254 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2255 {
2256 struct msdc_host *host = mmc_priv(mmc);
2257 host->hs400_mode = true;
2258
2259 if (host->top_base)
2260 writel(host->hs400_ds_delay,
2261 host->top_base + EMMC50_PAD_DS_TUNE);
2262 else
2263 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2264 /* hs400 mode must set it to 0 */
2265 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2266 /* to improve read performance, set outstanding to 2 */
2267 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2268
2269 return 0;
2270 }
2271
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2272 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2273 {
2274 struct msdc_host *host = mmc_priv(mmc);
2275 struct msdc_delay_phase dly1_delay;
2276 u32 val, result_dly1 = 0;
2277 u8 *ext_csd;
2278 int i, ret;
2279
2280 if (host->top_base) {
2281 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2282 PAD_DS_DLY_SEL);
2283 if (host->hs400_ds_dly3)
2284 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2285 PAD_DS_DLY3, host->hs400_ds_dly3);
2286 } else {
2287 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2288 if (host->hs400_ds_dly3)
2289 sdr_set_field(host->base + PAD_DS_TUNE,
2290 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2291 }
2292
2293 host->hs400_tuning = true;
2294 for (i = 0; i < PAD_DELAY_MAX; i++) {
2295 if (host->top_base)
2296 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2297 PAD_DS_DLY1, i);
2298 else
2299 sdr_set_field(host->base + PAD_DS_TUNE,
2300 PAD_DS_TUNE_DLY1, i);
2301 ret = mmc_get_ext_csd(card, &ext_csd);
2302 if (!ret) {
2303 result_dly1 |= (1 << i);
2304 kfree(ext_csd);
2305 }
2306 }
2307 host->hs400_tuning = false;
2308
2309 dly1_delay = get_best_delay(host, result_dly1);
2310 if (dly1_delay.maxlen == 0) {
2311 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2312 goto fail;
2313 }
2314 if (host->top_base)
2315 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2316 PAD_DS_DLY1, dly1_delay.final_phase);
2317 else
2318 sdr_set_field(host->base + PAD_DS_TUNE,
2319 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2320
2321 if (host->top_base)
2322 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2323 else
2324 val = readl(host->base + PAD_DS_TUNE);
2325
2326 dev_info(host->dev, "Fianl PAD_DS_TUNE: 0x%x\n", val);
2327
2328 return 0;
2329
2330 fail:
2331 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2332 return -EIO;
2333 }
2334
msdc_hw_reset(struct mmc_host * mmc)2335 static void msdc_hw_reset(struct mmc_host *mmc)
2336 {
2337 struct msdc_host *host = mmc_priv(mmc);
2338
2339 sdr_set_bits(host->base + EMMC_IOCON, 1);
2340 udelay(10); /* 10us is enough */
2341 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2342 }
2343
msdc_ack_sdio_irq(struct mmc_host * mmc)2344 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2345 {
2346 unsigned long flags;
2347 struct msdc_host *host = mmc_priv(mmc);
2348
2349 spin_lock_irqsave(&host->lock, flags);
2350 __msdc_enable_sdio_irq(host, 1);
2351 spin_unlock_irqrestore(&host->lock, flags);
2352 }
2353
msdc_get_cd(struct mmc_host * mmc)2354 static int msdc_get_cd(struct mmc_host *mmc)
2355 {
2356 struct msdc_host *host = mmc_priv(mmc);
2357 int val;
2358
2359 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2360 return 1;
2361
2362 if (!host->internal_cd)
2363 return mmc_gpio_get_cd(mmc);
2364
2365 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2366 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2367 return !!val;
2368 else
2369 return !val;
2370 }
2371
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2372 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2373 struct mmc_ios *ios)
2374 {
2375 struct msdc_host *host = mmc_priv(mmc);
2376
2377 if (ios->enhanced_strobe) {
2378 msdc_prepare_hs400_tuning(mmc, ios);
2379 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2380 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2381 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2382
2383 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2384 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2385 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2386 } else {
2387 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2388 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2389 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2390
2391 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2392 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2393 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2394 }
2395 }
2396
msdc_cqe_enable(struct mmc_host * mmc)2397 static void msdc_cqe_enable(struct mmc_host *mmc)
2398 {
2399 struct msdc_host *host = mmc_priv(mmc);
2400
2401 /* enable cmdq irq */
2402 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2403 /* enable busy check */
2404 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2405 /* default write data / busy timeout 20s */
2406 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2407 /* default read data timeout 1s */
2408 msdc_set_timeout(host, 1000000000ULL, 0);
2409 }
2410
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2411 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2412 {
2413 struct msdc_host *host = mmc_priv(mmc);
2414 unsigned int val = 0;
2415
2416 /* disable cmdq irq */
2417 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2418 /* disable busy check */
2419 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2420
2421 val = readl(host->base + MSDC_INT);
2422 writel(val, host->base + MSDC_INT);
2423
2424 if (recovery) {
2425 sdr_set_field(host->base + MSDC_DMA_CTRL,
2426 MSDC_DMA_CTRL_STOP, 1);
2427 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2428 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2429 return;
2430 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2431 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2432 return;
2433 msdc_reset_hw(host);
2434 }
2435 }
2436
msdc_cqe_pre_enable(struct mmc_host * mmc)2437 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2438 {
2439 struct cqhci_host *cq_host = mmc->cqe_private;
2440 u32 reg;
2441
2442 reg = cqhci_readl(cq_host, CQHCI_CFG);
2443 reg |= CQHCI_ENABLE;
2444 cqhci_writel(cq_host, reg, CQHCI_CFG);
2445 }
2446
msdc_cqe_post_disable(struct mmc_host * mmc)2447 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2448 {
2449 struct cqhci_host *cq_host = mmc->cqe_private;
2450 u32 reg;
2451
2452 reg = cqhci_readl(cq_host, CQHCI_CFG);
2453 reg &= ~CQHCI_ENABLE;
2454 cqhci_writel(cq_host, reg, CQHCI_CFG);
2455 }
2456
2457 static const struct mmc_host_ops mt_msdc_ops = {
2458 .post_req = msdc_post_req,
2459 .pre_req = msdc_pre_req,
2460 .request = msdc_ops_request,
2461 .set_ios = msdc_ops_set_ios,
2462 .get_ro = mmc_gpio_get_ro,
2463 .get_cd = msdc_get_cd,
2464 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2465 .enable_sdio_irq = msdc_enable_sdio_irq,
2466 .ack_sdio_irq = msdc_ack_sdio_irq,
2467 .start_signal_voltage_switch = msdc_ops_switch_volt,
2468 .card_busy = msdc_card_busy,
2469 .execute_tuning = msdc_execute_tuning,
2470 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2471 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2472 .hw_reset = msdc_hw_reset,
2473 };
2474
2475 static const struct cqhci_host_ops msdc_cmdq_ops = {
2476 .enable = msdc_cqe_enable,
2477 .disable = msdc_cqe_disable,
2478 .pre_enable = msdc_cqe_pre_enable,
2479 .post_disable = msdc_cqe_post_disable,
2480 };
2481
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2482 static void msdc_of_property_parse(struct platform_device *pdev,
2483 struct msdc_host *host)
2484 {
2485 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2486 &host->latch_ck);
2487
2488 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2489 &host->hs400_ds_delay);
2490
2491 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2492 &host->hs400_ds_dly3);
2493
2494 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2495 &host->hs200_cmd_int_delay);
2496
2497 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2498 &host->hs400_cmd_int_delay);
2499
2500 if (of_property_read_bool(pdev->dev.of_node,
2501 "mediatek,hs400-cmd-resp-sel-rising"))
2502 host->hs400_cmd_resp_sel_rising = true;
2503 else
2504 host->hs400_cmd_resp_sel_rising = false;
2505
2506 if (of_property_read_bool(pdev->dev.of_node,
2507 "supports-cqe"))
2508 host->cqhci = true;
2509 else
2510 host->cqhci = false;
2511 }
2512
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2513 static int msdc_of_clock_parse(struct platform_device *pdev,
2514 struct msdc_host *host)
2515 {
2516 int ret;
2517
2518 host->src_clk = devm_clk_get(&pdev->dev, "source");
2519 if (IS_ERR(host->src_clk))
2520 return PTR_ERR(host->src_clk);
2521
2522 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2523 if (IS_ERR(host->h_clk))
2524 return PTR_ERR(host->h_clk);
2525
2526 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2527 if (IS_ERR(host->bus_clk))
2528 host->bus_clk = NULL;
2529
2530 /*source clock control gate is optional clock*/
2531 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2532 if (IS_ERR(host->src_clk_cg))
2533 host->src_clk_cg = NULL;
2534
2535 /* If present, always enable for this clock gate */
2536 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2537 if (IS_ERR(host->sys_clk_cg))
2538 host->sys_clk_cg = NULL;
2539
2540 host->bulk_clks[0].id = "pclk_cg";
2541 host->bulk_clks[1].id = "axi_cg";
2542 host->bulk_clks[2].id = "ahb_cg";
2543 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2544 host->bulk_clks);
2545 if (ret) {
2546 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2547 return ret;
2548 }
2549
2550 return 0;
2551 }
2552
msdc_drv_probe(struct platform_device * pdev)2553 static int msdc_drv_probe(struct platform_device *pdev)
2554 {
2555 struct mmc_host *mmc;
2556 struct msdc_host *host;
2557 struct resource *res;
2558 int ret;
2559
2560 if (!pdev->dev.of_node) {
2561 dev_err(&pdev->dev, "No DT found\n");
2562 return -EINVAL;
2563 }
2564
2565 /* Allocate MMC host for this device */
2566 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2567 if (!mmc)
2568 return -ENOMEM;
2569
2570 host = mmc_priv(mmc);
2571 ret = mmc_of_parse(mmc);
2572 if (ret)
2573 goto host_free;
2574
2575 host->base = devm_platform_ioremap_resource(pdev, 0);
2576 if (IS_ERR(host->base)) {
2577 ret = PTR_ERR(host->base);
2578 goto host_free;
2579 }
2580
2581 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2582 if (res) {
2583 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2584 if (IS_ERR(host->top_base))
2585 host->top_base = NULL;
2586 }
2587
2588 ret = mmc_regulator_get_supply(mmc);
2589 if (ret)
2590 goto host_free;
2591
2592 ret = msdc_of_clock_parse(pdev, host);
2593 if (ret)
2594 goto host_free;
2595
2596 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2597 "hrst");
2598 if (IS_ERR(host->reset)) {
2599 ret = PTR_ERR(host->reset);
2600 goto host_free;
2601 }
2602
2603 host->irq = platform_get_irq(pdev, 0);
2604 if (host->irq < 0) {
2605 ret = host->irq;
2606 goto host_free;
2607 }
2608
2609 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2610 if (IS_ERR(host->pinctrl)) {
2611 ret = PTR_ERR(host->pinctrl);
2612 dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2613 goto host_free;
2614 }
2615
2616 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2617 if (IS_ERR(host->pins_default)) {
2618 ret = PTR_ERR(host->pins_default);
2619 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2620 goto host_free;
2621 }
2622
2623 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2624 if (IS_ERR(host->pins_uhs)) {
2625 ret = PTR_ERR(host->pins_uhs);
2626 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2627 goto host_free;
2628 }
2629
2630 msdc_of_property_parse(pdev, host);
2631
2632 host->dev = &pdev->dev;
2633 host->dev_comp = of_device_get_match_data(&pdev->dev);
2634 host->src_clk_freq = clk_get_rate(host->src_clk);
2635 /* Set host parameters to mmc */
2636 mmc->ops = &mt_msdc_ops;
2637 if (host->dev_comp->clk_div_bits == 8)
2638 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2639 else
2640 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2641
2642 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2643 !mmc_can_gpio_cd(mmc) &&
2644 host->dev_comp->use_internal_cd) {
2645 /*
2646 * Is removable but no GPIO declared, so
2647 * use internal functionality.
2648 */
2649 host->internal_cd = true;
2650 }
2651
2652 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2653 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2654
2655 mmc->caps |= MMC_CAP_CMD23;
2656 if (host->cqhci)
2657 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2658 /* MMC core transfer sizes tunable parameters */
2659 mmc->max_segs = MAX_BD_NUM;
2660 if (host->dev_comp->support_64g)
2661 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2662 else
2663 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2664 mmc->max_blk_size = 2048;
2665 mmc->max_req_size = 512 * 1024;
2666 mmc->max_blk_count = mmc->max_req_size / 512;
2667 if (host->dev_comp->support_64g)
2668 host->dma_mask = DMA_BIT_MASK(36);
2669 else
2670 host->dma_mask = DMA_BIT_MASK(32);
2671 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2672
2673 host->timeout_clks = 3 * 1048576;
2674 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2675 2 * sizeof(struct mt_gpdma_desc),
2676 &host->dma.gpd_addr, GFP_KERNEL);
2677 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2678 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2679 &host->dma.bd_addr, GFP_KERNEL);
2680 if (!host->dma.gpd || !host->dma.bd) {
2681 ret = -ENOMEM;
2682 goto release_mem;
2683 }
2684 msdc_init_gpd_bd(host, &host->dma);
2685 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2686 spin_lock_init(&host->lock);
2687
2688 platform_set_drvdata(pdev, mmc);
2689 ret = msdc_ungate_clock(host);
2690 if (ret) {
2691 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2692 goto release_mem;
2693 }
2694 msdc_init_hw(host);
2695
2696 if (mmc->caps2 & MMC_CAP2_CQE) {
2697 host->cq_host = devm_kzalloc(mmc->parent,
2698 sizeof(*host->cq_host),
2699 GFP_KERNEL);
2700 if (!host->cq_host) {
2701 ret = -ENOMEM;
2702 goto host_free;
2703 }
2704 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2705 host->cq_host->mmio = host->base + 0x800;
2706 host->cq_host->ops = &msdc_cmdq_ops;
2707 ret = cqhci_init(host->cq_host, mmc, true);
2708 if (ret)
2709 goto host_free;
2710 mmc->max_segs = 128;
2711 /* cqhci 16bit length */
2712 /* 0 size, means 65536 so we don't have to -1 here */
2713 mmc->max_seg_size = 64 * 1024;
2714 }
2715
2716 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2717 IRQF_TRIGGER_NONE, pdev->name, host);
2718 if (ret)
2719 goto release;
2720
2721 pm_runtime_set_active(host->dev);
2722 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2723 pm_runtime_use_autosuspend(host->dev);
2724 pm_runtime_enable(host->dev);
2725 ret = mmc_add_host(mmc);
2726
2727 if (ret)
2728 goto end;
2729
2730 return 0;
2731 end:
2732 pm_runtime_disable(host->dev);
2733 release:
2734 platform_set_drvdata(pdev, NULL);
2735 msdc_deinit_hw(host);
2736 msdc_gate_clock(host);
2737 release_mem:
2738 if (host->dma.gpd)
2739 dma_free_coherent(&pdev->dev,
2740 2 * sizeof(struct mt_gpdma_desc),
2741 host->dma.gpd, host->dma.gpd_addr);
2742 if (host->dma.bd)
2743 dma_free_coherent(&pdev->dev,
2744 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2745 host->dma.bd, host->dma.bd_addr);
2746 host_free:
2747 mmc_free_host(mmc);
2748
2749 return ret;
2750 }
2751
msdc_drv_remove(struct platform_device * pdev)2752 static int msdc_drv_remove(struct platform_device *pdev)
2753 {
2754 struct mmc_host *mmc;
2755 struct msdc_host *host;
2756
2757 mmc = platform_get_drvdata(pdev);
2758 host = mmc_priv(mmc);
2759
2760 pm_runtime_get_sync(host->dev);
2761
2762 platform_set_drvdata(pdev, NULL);
2763 mmc_remove_host(mmc);
2764 msdc_deinit_hw(host);
2765 msdc_gate_clock(host);
2766
2767 pm_runtime_disable(host->dev);
2768 pm_runtime_put_noidle(host->dev);
2769 dma_free_coherent(&pdev->dev,
2770 2 * sizeof(struct mt_gpdma_desc),
2771 host->dma.gpd, host->dma.gpd_addr);
2772 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2773 host->dma.bd, host->dma.bd_addr);
2774
2775 mmc_free_host(mmc);
2776
2777 return 0;
2778 }
2779
msdc_save_reg(struct msdc_host * host)2780 static void msdc_save_reg(struct msdc_host *host)
2781 {
2782 u32 tune_reg = host->dev_comp->pad_tune_reg;
2783
2784 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2785 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2786 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2787 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2788 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2789 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2790 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2791 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2792 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2793 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2794 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2795 if (host->top_base) {
2796 host->save_para.emmc_top_control =
2797 readl(host->top_base + EMMC_TOP_CONTROL);
2798 host->save_para.emmc_top_cmd =
2799 readl(host->top_base + EMMC_TOP_CMD);
2800 host->save_para.emmc50_pad_ds_tune =
2801 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2802 } else {
2803 host->save_para.pad_tune = readl(host->base + tune_reg);
2804 }
2805 }
2806
msdc_restore_reg(struct msdc_host * host)2807 static void msdc_restore_reg(struct msdc_host *host)
2808 {
2809 struct mmc_host *mmc = mmc_from_priv(host);
2810 u32 tune_reg = host->dev_comp->pad_tune_reg;
2811
2812 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2813 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2814 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2815 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2816 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2817 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2818 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2819 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2820 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2821 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2822 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2823 if (host->top_base) {
2824 writel(host->save_para.emmc_top_control,
2825 host->top_base + EMMC_TOP_CONTROL);
2826 writel(host->save_para.emmc_top_cmd,
2827 host->top_base + EMMC_TOP_CMD);
2828 writel(host->save_para.emmc50_pad_ds_tune,
2829 host->top_base + EMMC50_PAD_DS_TUNE);
2830 } else {
2831 writel(host->save_para.pad_tune, host->base + tune_reg);
2832 }
2833
2834 if (sdio_irq_claimed(mmc))
2835 __msdc_enable_sdio_irq(host, 1);
2836 }
2837
msdc_runtime_suspend(struct device * dev)2838 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2839 {
2840 struct mmc_host *mmc = dev_get_drvdata(dev);
2841 struct msdc_host *host = mmc_priv(mmc);
2842
2843 msdc_save_reg(host);
2844 msdc_gate_clock(host);
2845 return 0;
2846 }
2847
msdc_runtime_resume(struct device * dev)2848 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2849 {
2850 struct mmc_host *mmc = dev_get_drvdata(dev);
2851 struct msdc_host *host = mmc_priv(mmc);
2852 int ret;
2853
2854 ret = msdc_ungate_clock(host);
2855 if (ret)
2856 return ret;
2857
2858 msdc_restore_reg(host);
2859 return 0;
2860 }
2861
msdc_suspend(struct device * dev)2862 static int __maybe_unused msdc_suspend(struct device *dev)
2863 {
2864 struct mmc_host *mmc = dev_get_drvdata(dev);
2865 int ret;
2866 u32 val;
2867
2868 if (mmc->caps2 & MMC_CAP2_CQE) {
2869 ret = cqhci_suspend(mmc);
2870 if (ret)
2871 return ret;
2872 val = readl(((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT);
2873 writel(val, ((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT);
2874 }
2875
2876 return pm_runtime_force_suspend(dev);
2877 }
2878
msdc_resume(struct device * dev)2879 static int __maybe_unused msdc_resume(struct device *dev)
2880 {
2881 return pm_runtime_force_resume(dev);
2882 }
2883
2884 static const struct dev_pm_ops msdc_dev_pm_ops = {
2885 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
2886 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2887 };
2888
2889 static struct platform_driver mt_msdc_driver = {
2890 .probe = msdc_drv_probe,
2891 .remove = msdc_drv_remove,
2892 .driver = {
2893 .name = "mtk-msdc",
2894 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2895 .of_match_table = msdc_of_ids,
2896 .pm = &msdc_dev_pm_ops,
2897 },
2898 };
2899
2900 module_platform_driver(mt_msdc_driver);
2901 MODULE_LICENSE("GPL v2");
2902 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
2903