1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2010 Google, Inc.
4 */
5
6 #include <linux/delay.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/err.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/iopoll.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/io.h>
15 #include <linux/of.h>
16 #include <linux/of_device.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/mmc/card.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/slot-gpio.h>
24 #include <linux/gpio/consumer.h>
25 #include <linux/ktime.h>
26
27 #include "sdhci-cqhci.h"
28 #include "sdhci-pltfm.h"
29 #include "cqhci.h"
30
31 /* Tegra SDHOST controller vendor register definitions */
32 #define SDHCI_TEGRA_VENDOR_CLOCK_CTRL 0x100
33 #define SDHCI_CLOCK_CTRL_TAP_MASK 0x00ff0000
34 #define SDHCI_CLOCK_CTRL_TAP_SHIFT 16
35 #define SDHCI_CLOCK_CTRL_TRIM_MASK 0x1f000000
36 #define SDHCI_CLOCK_CTRL_TRIM_SHIFT 24
37 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
38 #define SDHCI_CLOCK_CTRL_PADPIPE_CLKEN_OVERRIDE BIT(3)
39 #define SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE BIT(2)
40
41 #define SDHCI_TEGRA_VENDOR_SYS_SW_CTRL 0x104
42 #define SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE BIT(31)
43
44 #define SDHCI_TEGRA_VENDOR_CAP_OVERRIDES 0x10c
45 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK 0x00003f00
46 #define SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT 8
47
48 #define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
49 #define SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT BIT(0)
50 #define SDHCI_MISC_CTRL_ENABLE_SDR104 0x8
51 #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10
52 #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
53 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200
54
55 #define SDHCI_TEGRA_VENDOR_DLLCAL_CFG 0x1b0
56 #define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31)
57
58 #define SDHCI_TEGRA_VENDOR_DLLCAL_STA 0x1bc
59 #define SDHCI_TEGRA_DLLCAL_STA_ACTIVE BIT(31)
60
61 #define SDHCI_VNDR_TUN_CTRL0_0 0x1c0
62 #define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000
63 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK 0x03fc0000
64 #define SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT 18
65 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK 0x00001fc0
66 #define SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT 6
67 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK 0x000e000
68 #define SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT 13
69 #define TRIES_128 2
70 #define TRIES_256 4
71 #define SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK 0x7
72
73 #define SDHCI_TEGRA_VNDR_TUN_CTRL1_0 0x1c4
74 #define SDHCI_TEGRA_VNDR_TUN_STATUS0 0x1C8
75 #define SDHCI_TEGRA_VNDR_TUN_STATUS1 0x1CC
76 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK 0xFF
77 #define SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT 0x8
78 #define TUNING_WORD_BIT_SIZE 32
79
80 #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4
81 #define SDHCI_AUTO_CAL_START BIT(31)
82 #define SDHCI_AUTO_CAL_ENABLE BIT(29)
83 #define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff
84
85 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0
86 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f
87 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7
88 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31)
89 #define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000
90
91 #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
92 #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
93
94 #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
95 #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
96 #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
97 #define NVQUIRK_ENABLE_SDR50 BIT(3)
98 #define NVQUIRK_ENABLE_SDR104 BIT(4)
99 #define NVQUIRK_ENABLE_DDR50 BIT(5)
100 /*
101 * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads
102 * drive strength.
103 */
104 #define NVQUIRK_HAS_PADCALIB BIT(6)
105 /*
106 * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads.
107 * 3V3/1V8 pad selection happens through pinctrl state selection depending
108 * on the signaling mode.
109 */
110 #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7)
111 #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8)
112 #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9)
113
114 /*
115 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
116 * SDMMC hardware data timeout.
117 */
118 #define NVQUIRK_HAS_TMCLK BIT(10)
119
120 #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11)
121
122 /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */
123 #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000
124
125 #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
126 SDHCI_TRNS_BLK_CNT_EN | \
127 SDHCI_TRNS_DMA)
128
129 struct sdhci_tegra_soc_data {
130 const struct sdhci_pltfm_data *pdata;
131 u64 dma_mask;
132 u32 nvquirks;
133 u8 min_tap_delay;
134 u8 max_tap_delay;
135 };
136
137 /* Magic pull up and pull down pad calibration offsets */
138 struct sdhci_tegra_autocal_offsets {
139 u32 pull_up_3v3;
140 u32 pull_down_3v3;
141 u32 pull_up_3v3_timeout;
142 u32 pull_down_3v3_timeout;
143 u32 pull_up_1v8;
144 u32 pull_down_1v8;
145 u32 pull_up_1v8_timeout;
146 u32 pull_down_1v8_timeout;
147 u32 pull_up_sdr104;
148 u32 pull_down_sdr104;
149 u32 pull_up_hs400;
150 u32 pull_down_hs400;
151 };
152
153 struct sdhci_tegra {
154 const struct sdhci_tegra_soc_data *soc_data;
155 struct gpio_desc *power_gpio;
156 struct clk *tmclk;
157 bool ddr_signaling;
158 bool pad_calib_required;
159 bool pad_control_available;
160
161 struct reset_control *rst;
162 struct pinctrl *pinctrl_sdmmc;
163 struct pinctrl_state *pinctrl_state_3v3;
164 struct pinctrl_state *pinctrl_state_1v8;
165 struct pinctrl_state *pinctrl_state_3v3_drv;
166 struct pinctrl_state *pinctrl_state_1v8_drv;
167
168 struct sdhci_tegra_autocal_offsets autocal_offsets;
169 ktime_t last_calib;
170
171 u32 default_tap;
172 u32 default_trim;
173 u32 dqs_trim;
174 bool enable_hwcq;
175 unsigned long curr_clk_rate;
176 u8 tuned_tap_delay;
177 };
178
tegra_sdhci_readw(struct sdhci_host * host,int reg)179 static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
180 {
181 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
182 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
183 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
184
185 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
186 (reg == SDHCI_HOST_VERSION))) {
187 /* Erratum: Version register is invalid in HW. */
188 return SDHCI_SPEC_200;
189 }
190
191 return readw(host->ioaddr + reg);
192 }
193
tegra_sdhci_writew(struct sdhci_host * host,u16 val,int reg)194 static void tegra_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
195 {
196 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
197
198 switch (reg) {
199 case SDHCI_TRANSFER_MODE:
200 /*
201 * Postpone this write, we must do it together with a
202 * command write that is down below.
203 */
204 pltfm_host->xfer_mode_shadow = val;
205 return;
206 case SDHCI_COMMAND:
207 writel((val << 16) | pltfm_host->xfer_mode_shadow,
208 host->ioaddr + SDHCI_TRANSFER_MODE);
209 return;
210 }
211
212 writew(val, host->ioaddr + reg);
213 }
214
tegra_sdhci_writel(struct sdhci_host * host,u32 val,int reg)215 static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
216 {
217 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
218 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
219 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
220
221 /* Seems like we're getting spurious timeout and crc errors, so
222 * disable signalling of them. In case of real errors software
223 * timers should take care of eventually detecting them.
224 */
225 if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
226 val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
227
228 writel(val, host->ioaddr + reg);
229
230 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
231 (reg == SDHCI_INT_ENABLE))) {
232 /* Erratum: Must enable block gap interrupt detection */
233 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
234 if (val & SDHCI_INT_CARD_INT)
235 gap_ctrl |= 0x8;
236 else
237 gap_ctrl &= ~0x8;
238 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
239 }
240 }
241
tegra_sdhci_configure_card_clk(struct sdhci_host * host,bool enable)242 static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable)
243 {
244 bool status;
245 u32 reg;
246
247 reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
248 status = !!(reg & SDHCI_CLOCK_CARD_EN);
249
250 if (status == enable)
251 return status;
252
253 if (enable)
254 reg |= SDHCI_CLOCK_CARD_EN;
255 else
256 reg &= ~SDHCI_CLOCK_CARD_EN;
257
258 sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL);
259
260 return status;
261 }
262
tegra210_sdhci_writew(struct sdhci_host * host,u16 val,int reg)263 static void tegra210_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
264 {
265 bool is_tuning_cmd = 0;
266 bool clk_enabled;
267 u8 cmd;
268
269 if (reg == SDHCI_COMMAND) {
270 cmd = SDHCI_GET_CMD(val);
271 is_tuning_cmd = cmd == MMC_SEND_TUNING_BLOCK ||
272 cmd == MMC_SEND_TUNING_BLOCK_HS200;
273 }
274
275 if (is_tuning_cmd)
276 clk_enabled = tegra_sdhci_configure_card_clk(host, 0);
277
278 writew(val, host->ioaddr + reg);
279
280 if (is_tuning_cmd) {
281 udelay(1);
282 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
283 tegra_sdhci_configure_card_clk(host, clk_enabled);
284 }
285 }
286
tegra_sdhci_get_ro(struct sdhci_host * host)287 static unsigned int tegra_sdhci_get_ro(struct sdhci_host *host)
288 {
289 /*
290 * Write-enable shall be assumed if GPIO is missing in a board's
291 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
292 * Tegra.
293 */
294 return mmc_gpio_get_ro(host->mmc);
295 }
296
tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host * host)297 static bool tegra_sdhci_is_pad_and_regulator_valid(struct sdhci_host *host)
298 {
299 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
300 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
301 int has_1v8, has_3v3;
302
303 /*
304 * The SoCs which have NVQUIRK_NEEDS_PAD_CONTROL require software pad
305 * voltage configuration in order to perform voltage switching. This
306 * means that valid pinctrl info is required on SDHCI instances capable
307 * of performing voltage switching. Whether or not an SDHCI instance is
308 * capable of voltage switching is determined based on the regulator.
309 */
310
311 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
312 return true;
313
314 if (IS_ERR(host->mmc->supply.vqmmc))
315 return false;
316
317 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
318 1700000, 1950000);
319
320 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
321 2700000, 3600000);
322
323 if (has_1v8 == 1 && has_3v3 == 1)
324 return tegra_host->pad_control_available;
325
326 /* Fixed voltage, no pad control required. */
327 return true;
328 }
329
tegra_sdhci_set_tap(struct sdhci_host * host,unsigned int tap)330 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap)
331 {
332 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
333 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
334 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
335 bool card_clk_enabled = false;
336 u32 reg;
337
338 /*
339 * Touching the tap values is a bit tricky on some SoC generations.
340 * The quirk enables a workaround for a glitch that sometimes occurs if
341 * the tap values are changed.
342 */
343
344 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
345 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
346
347 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
348 reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK;
349 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT;
350 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
351
352 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
353 card_clk_enabled) {
354 udelay(1);
355 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
356 tegra_sdhci_configure_card_clk(host, card_clk_enabled);
357 }
358 }
359
tegra_sdhci_reset(struct sdhci_host * host,u8 mask)360 static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)
361 {
362 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
363 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
364 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
365 u32 misc_ctrl, clk_ctrl, pad_ctrl;
366
367 sdhci_and_cqhci_reset(host, mask);
368
369 if (!(mask & SDHCI_RESET_ALL))
370 return;
371
372 tegra_sdhci_set_tap(host, tegra_host->default_tap);
373
374 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
375 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
376
377 misc_ctrl &= ~(SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 |
378 SDHCI_MISC_CTRL_ENABLE_SDR50 |
379 SDHCI_MISC_CTRL_ENABLE_DDR50 |
380 SDHCI_MISC_CTRL_ENABLE_SDR104);
381
382 clk_ctrl &= ~(SDHCI_CLOCK_CTRL_TRIM_MASK |
383 SDHCI_CLOCK_CTRL_SPI_MODE_CLKEN_OVERRIDE);
384
385 if (tegra_sdhci_is_pad_and_regulator_valid(host)) {
386 /* Erratum: Enable SDHCI spec v3.00 support */
387 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
388 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
389 /* Advertise UHS modes as supported by host */
390 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
391 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR50;
392 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
393 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_DDR50;
394 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
395 misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDR104;
396 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
397 clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE;
398 }
399
400 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
401
402 sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
403 sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
404
405 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
406 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
407 pad_ctrl &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK;
408 pad_ctrl |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL;
409 sdhci_writel(host, pad_ctrl, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
410
411 tegra_host->pad_calib_required = true;
412 }
413
414 tegra_host->ddr_signaling = false;
415 }
416
tegra_sdhci_configure_cal_pad(struct sdhci_host * host,bool enable)417 static void tegra_sdhci_configure_cal_pad(struct sdhci_host *host, bool enable)
418 {
419 u32 val;
420
421 /*
422 * Enable or disable the additional I/O pad used by the drive strength
423 * calibration process.
424 */
425 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
426
427 if (enable)
428 val |= SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
429 else
430 val &= ~SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD;
431
432 sdhci_writel(host, val, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
433
434 if (enable)
435 usleep_range(1, 2);
436 }
437
tegra_sdhci_set_pad_autocal_offset(struct sdhci_host * host,u16 pdpu)438 static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host,
439 u16 pdpu)
440 {
441 u32 reg;
442
443 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
444 reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK;
445 reg |= pdpu;
446 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
447 }
448
tegra_sdhci_set_padctrl(struct sdhci_host * host,int voltage,bool state_drvupdn)449 static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
450 bool state_drvupdn)
451 {
452 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
453 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
454 struct sdhci_tegra_autocal_offsets *offsets =
455 &tegra_host->autocal_offsets;
456 struct pinctrl_state *pinctrl_drvupdn = NULL;
457 int ret = 0;
458 u8 drvup = 0, drvdn = 0;
459 u32 reg;
460
461 if (!state_drvupdn) {
462 /* PADS Drive Strength */
463 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
464 if (tegra_host->pinctrl_state_1v8_drv) {
465 pinctrl_drvupdn =
466 tegra_host->pinctrl_state_1v8_drv;
467 } else {
468 drvup = offsets->pull_up_1v8_timeout;
469 drvdn = offsets->pull_down_1v8_timeout;
470 }
471 } else {
472 if (tegra_host->pinctrl_state_3v3_drv) {
473 pinctrl_drvupdn =
474 tegra_host->pinctrl_state_3v3_drv;
475 } else {
476 drvup = offsets->pull_up_3v3_timeout;
477 drvdn = offsets->pull_down_3v3_timeout;
478 }
479 }
480
481 if (pinctrl_drvupdn != NULL) {
482 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
483 pinctrl_drvupdn);
484 if (ret < 0)
485 dev_err(mmc_dev(host->mmc),
486 "failed pads drvupdn, ret: %d\n", ret);
487 } else if ((drvup) || (drvdn)) {
488 reg = sdhci_readl(host,
489 SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
490 reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
491 reg |= (drvup << 20) | (drvdn << 12);
492 sdhci_writel(host, reg,
493 SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
494 }
495
496 } else {
497 /* Dual Voltage PADS Voltage selection */
498 if (!tegra_host->pad_control_available)
499 return 0;
500
501 if (voltage == MMC_SIGNAL_VOLTAGE_180) {
502 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
503 tegra_host->pinctrl_state_1v8);
504 if (ret < 0)
505 dev_err(mmc_dev(host->mmc),
506 "setting 1.8V failed, ret: %d\n", ret);
507 } else {
508 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
509 tegra_host->pinctrl_state_3v3);
510 if (ret < 0)
511 dev_err(mmc_dev(host->mmc),
512 "setting 3.3V failed, ret: %d\n", ret);
513 }
514 }
515
516 return ret;
517 }
518
tegra_sdhci_pad_autocalib(struct sdhci_host * host)519 static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
520 {
521 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
522 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
523 struct sdhci_tegra_autocal_offsets offsets =
524 tegra_host->autocal_offsets;
525 struct mmc_ios *ios = &host->mmc->ios;
526 bool card_clk_enabled;
527 u16 pdpu;
528 u32 reg;
529 int ret;
530
531 switch (ios->timing) {
532 case MMC_TIMING_UHS_SDR104:
533 pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104;
534 break;
535 case MMC_TIMING_MMC_HS400:
536 pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400;
537 break;
538 default:
539 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
540 pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8;
541 else
542 pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
543 }
544
545 /* Set initial offset before auto-calibration */
546 tegra_sdhci_set_pad_autocal_offset(host, pdpu);
547
548 card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
549
550 tegra_sdhci_configure_cal_pad(host, true);
551
552 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
553 reg |= SDHCI_AUTO_CAL_ENABLE | SDHCI_AUTO_CAL_START;
554 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
555
556 usleep_range(1, 2);
557 /* 10 ms timeout */
558 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
559 reg, !(reg & SDHCI_TEGRA_AUTO_CAL_ACTIVE),
560 1000, 10000);
561
562 tegra_sdhci_configure_cal_pad(host, false);
563
564 tegra_sdhci_configure_card_clk(host, card_clk_enabled);
565
566 if (ret) {
567 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
568
569 /* Disable automatic cal and use fixed Drive Strengths */
570 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
571 reg &= ~SDHCI_AUTO_CAL_ENABLE;
572 sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
573
574 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
575 if (ret < 0)
576 dev_err(mmc_dev(host->mmc),
577 "Setting drive strengths failed: %d\n", ret);
578 }
579 }
580
tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host * host)581 static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host)
582 {
583 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
584 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
585 struct sdhci_tegra_autocal_offsets *autocal =
586 &tegra_host->autocal_offsets;
587 int err;
588
589 err = device_property_read_u32(mmc_dev(host->mmc),
590 "nvidia,pad-autocal-pull-up-offset-3v3",
591 &autocal->pull_up_3v3);
592 if (err)
593 autocal->pull_up_3v3 = 0;
594
595 err = device_property_read_u32(mmc_dev(host->mmc),
596 "nvidia,pad-autocal-pull-down-offset-3v3",
597 &autocal->pull_down_3v3);
598 if (err)
599 autocal->pull_down_3v3 = 0;
600
601 err = device_property_read_u32(mmc_dev(host->mmc),
602 "nvidia,pad-autocal-pull-up-offset-1v8",
603 &autocal->pull_up_1v8);
604 if (err)
605 autocal->pull_up_1v8 = 0;
606
607 err = device_property_read_u32(mmc_dev(host->mmc),
608 "nvidia,pad-autocal-pull-down-offset-1v8",
609 &autocal->pull_down_1v8);
610 if (err)
611 autocal->pull_down_1v8 = 0;
612
613 err = device_property_read_u32(mmc_dev(host->mmc),
614 "nvidia,pad-autocal-pull-up-offset-sdr104",
615 &autocal->pull_up_sdr104);
616 if (err)
617 autocal->pull_up_sdr104 = autocal->pull_up_1v8;
618
619 err = device_property_read_u32(mmc_dev(host->mmc),
620 "nvidia,pad-autocal-pull-down-offset-sdr104",
621 &autocal->pull_down_sdr104);
622 if (err)
623 autocal->pull_down_sdr104 = autocal->pull_down_1v8;
624
625 err = device_property_read_u32(mmc_dev(host->mmc),
626 "nvidia,pad-autocal-pull-up-offset-hs400",
627 &autocal->pull_up_hs400);
628 if (err)
629 autocal->pull_up_hs400 = autocal->pull_up_1v8;
630
631 err = device_property_read_u32(mmc_dev(host->mmc),
632 "nvidia,pad-autocal-pull-down-offset-hs400",
633 &autocal->pull_down_hs400);
634 if (err)
635 autocal->pull_down_hs400 = autocal->pull_down_1v8;
636
637 /*
638 * Different fail-safe drive strength values based on the signaling
639 * voltage are applicable for SoCs supporting 3V3 and 1V8 pad controls.
640 * So, avoid reading below device tree properties for SoCs that don't
641 * have NVQUIRK_NEEDS_PAD_CONTROL.
642 */
643 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
644 return;
645
646 err = device_property_read_u32(mmc_dev(host->mmc),
647 "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
648 &autocal->pull_up_3v3_timeout);
649 if (err) {
650 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
651 (tegra_host->pinctrl_state_3v3_drv == NULL))
652 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
653 mmc_hostname(host->mmc));
654 autocal->pull_up_3v3_timeout = 0;
655 }
656
657 err = device_property_read_u32(mmc_dev(host->mmc),
658 "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
659 &autocal->pull_down_3v3_timeout);
660 if (err) {
661 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
662 (tegra_host->pinctrl_state_3v3_drv == NULL))
663 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
664 mmc_hostname(host->mmc));
665 autocal->pull_down_3v3_timeout = 0;
666 }
667
668 err = device_property_read_u32(mmc_dev(host->mmc),
669 "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
670 &autocal->pull_up_1v8_timeout);
671 if (err) {
672 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
673 (tegra_host->pinctrl_state_1v8_drv == NULL))
674 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
675 mmc_hostname(host->mmc));
676 autocal->pull_up_1v8_timeout = 0;
677 }
678
679 err = device_property_read_u32(mmc_dev(host->mmc),
680 "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
681 &autocal->pull_down_1v8_timeout);
682 if (err) {
683 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
684 (tegra_host->pinctrl_state_1v8_drv == NULL))
685 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
686 mmc_hostname(host->mmc));
687 autocal->pull_down_1v8_timeout = 0;
688 }
689 }
690
tegra_sdhci_request(struct mmc_host * mmc,struct mmc_request * mrq)691 static void tegra_sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
692 {
693 struct sdhci_host *host = mmc_priv(mmc);
694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
695 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
696 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
697
698 /* 100 ms calibration interval is specified in the TRM */
699 if (ktime_to_ms(since_calib) > 100) {
700 tegra_sdhci_pad_autocalib(host);
701 tegra_host->last_calib = ktime_get();
702 }
703
704 sdhci_request(mmc, mrq);
705 }
706
tegra_sdhci_parse_tap_and_trim(struct sdhci_host * host)707 static void tegra_sdhci_parse_tap_and_trim(struct sdhci_host *host)
708 {
709 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
710 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
711 int err;
712
713 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap",
714 &tegra_host->default_tap);
715 if (err)
716 tegra_host->default_tap = 0;
717
718 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim",
719 &tegra_host->default_trim);
720 if (err)
721 tegra_host->default_trim = 0;
722
723 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim",
724 &tegra_host->dqs_trim);
725 if (err)
726 tegra_host->dqs_trim = 0x11;
727 }
728
tegra_sdhci_parse_dt(struct sdhci_host * host)729 static void tegra_sdhci_parse_dt(struct sdhci_host *host)
730 {
731 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
732 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
733
734 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe"))
735 tegra_host->enable_hwcq = true;
736 else
737 tegra_host->enable_hwcq = false;
738
739 tegra_sdhci_parse_pad_autocal_dt(host);
740 tegra_sdhci_parse_tap_and_trim(host);
741 }
742
tegra_sdhci_set_clock(struct sdhci_host * host,unsigned int clock)743 static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
744 {
745 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
746 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
747 unsigned long host_clk;
748
749 if (!clock)
750 return sdhci_set_clock(host, clock);
751
752 /*
753 * In DDR50/52 modes the Tegra SDHCI controllers require the SDHCI
754 * divider to be configured to divided the host clock by two. The SDHCI
755 * clock divider is calculated as part of sdhci_set_clock() by
756 * sdhci_calc_clk(). The divider is calculated from host->max_clk and
757 * the requested clock rate.
758 *
759 * By setting the host->max_clk to clock * 2 the divider calculation
760 * will always result in the correct value for DDR50/52 modes,
761 * regardless of clock rate rounding, which may happen if the value
762 * from clk_get_rate() is used.
763 */
764 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
765 clk_set_rate(pltfm_host->clk, host_clk);
766 tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk);
767 if (tegra_host->ddr_signaling)
768 host->max_clk = host_clk;
769 else
770 host->max_clk = clk_get_rate(pltfm_host->clk);
771
772 sdhci_set_clock(host, clock);
773
774 if (tegra_host->pad_calib_required) {
775 tegra_sdhci_pad_autocalib(host);
776 tegra_host->pad_calib_required = false;
777 }
778 }
779
tegra_sdhci_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)780 static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc,
781 struct mmc_ios *ios)
782 {
783 struct sdhci_host *host = mmc_priv(mmc);
784 u32 val;
785
786 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
787
788 if (ios->enhanced_strobe) {
789 val |= SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
790 /*
791 * When CMD13 is sent from mmc_select_hs400es() after
792 * switching to HS400ES mode, the bus is operating at
793 * either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR.
794 * To meet Tegra SDHCI requirement at HS400ES mode, force SDHCI
795 * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host
796 * controller CAR clock and the interface clock are rate matched.
797 */
798 tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR);
799 } else {
800 val &= ~SDHCI_TEGRA_SYS_SW_CTRL_ENHANCED_STROBE;
801 }
802
803 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);
804 }
805
tegra_sdhci_get_max_clock(struct sdhci_host * host)806 static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host)
807 {
808 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
809
810 return clk_round_rate(pltfm_host->clk, UINT_MAX);
811 }
812
tegra_sdhci_set_dqs_trim(struct sdhci_host * host,u8 trim)813 static void tegra_sdhci_set_dqs_trim(struct sdhci_host *host, u8 trim)
814 {
815 u32 val;
816
817 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
818 val &= ~SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_MASK;
819 val |= trim << SDHCI_TEGRA_CAP_OVERRIDES_DQS_TRIM_SHIFT;
820 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);
821 }
822
tegra_sdhci_hs400_dll_cal(struct sdhci_host * host)823 static void tegra_sdhci_hs400_dll_cal(struct sdhci_host *host)
824 {
825 u32 reg;
826 int err;
827
828 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
829 reg |= SDHCI_TEGRA_DLLCAL_CALIBRATE;
830 sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);
831
832 /* 1 ms sleep, 5 ms timeout */
833 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
834 reg, !(reg & SDHCI_TEGRA_DLLCAL_STA_ACTIVE),
835 1000, 5000);
836 if (err)
837 dev_err(mmc_dev(host->mmc),
838 "HS400 delay line calibration timed out\n");
839 }
840
tegra_sdhci_tap_correction(struct sdhci_host * host,u8 thd_up,u8 thd_low,u8 fixed_tap)841 static void tegra_sdhci_tap_correction(struct sdhci_host *host, u8 thd_up,
842 u8 thd_low, u8 fixed_tap)
843 {
844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
845 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
846 u32 val, tun_status;
847 u8 word, bit, edge1, tap, window;
848 bool tap_result;
849 bool start_fail = false;
850 bool start_pass = false;
851 bool end_pass = false;
852 bool first_fail = false;
853 bool first_pass = false;
854 u8 start_pass_tap = 0;
855 u8 end_pass_tap = 0;
856 u8 first_fail_tap = 0;
857 u8 first_pass_tap = 0;
858 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
859
860 /*
861 * Read auto-tuned results and extract good valid passing window by
862 * filtering out un-wanted bubble/partial/merged windows.
863 */
864 for (word = 0; word < total_tuning_words; word++) {
865 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
866 val &= ~SDHCI_VNDR_TUN_CTRL0_TUN_WORD_SEL_MASK;
867 val |= word;
868 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
869 tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);
870 bit = 0;
871 while (bit < TUNING_WORD_BIT_SIZE) {
872 tap = word * TUNING_WORD_BIT_SIZE + bit;
873 tap_result = tun_status & (1 << bit);
874 if (!tap_result && !start_fail) {
875 start_fail = true;
876 if (!first_fail) {
877 first_fail_tap = tap;
878 first_fail = true;
879 }
880
881 } else if (tap_result && start_fail && !start_pass) {
882 start_pass_tap = tap;
883 start_pass = true;
884 if (!first_pass) {
885 first_pass_tap = tap;
886 first_pass = true;
887 }
888
889 } else if (!tap_result && start_fail && start_pass &&
890 !end_pass) {
891 end_pass_tap = tap - 1;
892 end_pass = true;
893 } else if (tap_result && start_pass && start_fail &&
894 end_pass) {
895 window = end_pass_tap - start_pass_tap;
896 /* discard merged window and bubble window */
897 if (window >= thd_up || window < thd_low) {
898 start_pass_tap = tap;
899 end_pass = false;
900 } else {
901 /* set tap at middle of valid window */
902 tap = start_pass_tap + window / 2;
903 tegra_host->tuned_tap_delay = tap;
904 return;
905 }
906 }
907
908 bit++;
909 }
910 }
911
912 if (!first_fail) {
913 WARN(1, "no edge detected, continue with hw tuned delay.\n");
914 } else if (first_pass) {
915 /* set tap location at fixed tap relative to the first edge */
916 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
917 if (edge1 - 1 > fixed_tap)
918 tegra_host->tuned_tap_delay = edge1 - fixed_tap;
919 else
920 tegra_host->tuned_tap_delay = edge1 + fixed_tap;
921 }
922 }
923
tegra_sdhci_post_tuning(struct sdhci_host * host)924 static void tegra_sdhci_post_tuning(struct sdhci_host *host)
925 {
926 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
927 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
928 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
929 u32 avg_tap_dly, val, min_tap_dly, max_tap_dly;
930 u8 fixed_tap, start_tap, end_tap, window_width;
931 u8 thdupper, thdlower;
932 u8 num_iter;
933 u32 clk_rate_mhz, period_ps, bestcase, worstcase;
934
935 /* retain HW tuned tap to use incase if no correction is needed */
936 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);
937 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
938 SDHCI_CLOCK_CTRL_TAP_SHIFT;
939 if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
940 min_tap_dly = soc_data->min_tap_delay;
941 max_tap_dly = soc_data->max_tap_delay;
942 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
943 period_ps = USEC_PER_SEC / clk_rate_mhz;
944 bestcase = period_ps / min_tap_dly;
945 worstcase = period_ps / max_tap_dly;
946 /*
947 * Upper and Lower bound thresholds used to detect merged and
948 * bubble windows
949 */
950 thdupper = (2 * worstcase + bestcase) / 2;
951 thdlower = worstcase / 4;
952 /*
953 * fixed tap is used when HW tuning result contains single edge
954 * and tap is set at fixed tap delay relative to the first edge
955 */
956 avg_tap_dly = (period_ps * 2) / (min_tap_dly + max_tap_dly);
957 fixed_tap = avg_tap_dly / 2;
958
959 val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);
960 start_tap = val & SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
961 end_tap = (val >> SDHCI_TEGRA_VNDR_TUN_STATUS1_END_TAP_SHIFT) &
962 SDHCI_TEGRA_VNDR_TUN_STATUS1_TAP_MASK;
963 window_width = end_tap - start_tap;
964 num_iter = host->tuning_loop_count;
965 /*
966 * partial window includes edges of the tuning range.
967 * merged window includes more taps so window width is higher
968 * than upper threshold.
969 */
970 if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
971 (end_tap == num_iter - 2) || window_width >= thdupper) {
972 pr_debug("%s: Apply tuning correction\n",
973 mmc_hostname(host->mmc));
974 tegra_sdhci_tap_correction(host, thdupper, thdlower,
975 fixed_tap);
976 }
977 }
978
979 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
980 }
981
tegra_sdhci_execute_hw_tuning(struct mmc_host * mmc,u32 opcode)982 static int tegra_sdhci_execute_hw_tuning(struct mmc_host *mmc, u32 opcode)
983 {
984 struct sdhci_host *host = mmc_priv(mmc);
985 int err;
986
987 err = sdhci_execute_tuning(mmc, opcode);
988 if (!err && !host->tuning_err)
989 tegra_sdhci_post_tuning(host);
990
991 return err;
992 }
993
tegra_sdhci_set_uhs_signaling(struct sdhci_host * host,unsigned timing)994 static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host,
995 unsigned timing)
996 {
997 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
998 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
999 bool set_default_tap = false;
1000 bool set_dqs_trim = false;
1001 bool do_hs400_dll_cal = false;
1002 u8 iter = TRIES_256;
1003 u32 val;
1004
1005 tegra_host->ddr_signaling = false;
1006 switch (timing) {
1007 case MMC_TIMING_UHS_SDR50:
1008 break;
1009 case MMC_TIMING_UHS_SDR104:
1010 case MMC_TIMING_MMC_HS200:
1011 /* Don't set default tap on tunable modes. */
1012 iter = TRIES_128;
1013 break;
1014 case MMC_TIMING_MMC_HS400:
1015 set_dqs_trim = true;
1016 do_hs400_dll_cal = true;
1017 iter = TRIES_128;
1018 break;
1019 case MMC_TIMING_MMC_DDR52:
1020 case MMC_TIMING_UHS_DDR50:
1021 tegra_host->ddr_signaling = true;
1022 set_default_tap = true;
1023 break;
1024 default:
1025 set_default_tap = true;
1026 break;
1027 }
1028
1029 val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);
1030 val &= ~(SDHCI_VNDR_TUN_CTRL0_TUN_ITER_MASK |
1031 SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_MASK |
1032 SDHCI_VNDR_TUN_CTRL0_MUL_M_MASK);
1033 val |= (iter << SDHCI_VNDR_TUN_CTRL0_TUN_ITER_SHIFT |
1034 0 << SDHCI_VNDR_TUN_CTRL0_START_TAP_VAL_SHIFT |
1035 1 << SDHCI_VNDR_TUN_CTRL0_MUL_M_SHIFT);
1036 sdhci_writel(host, val, SDHCI_VNDR_TUN_CTRL0_0);
1037 sdhci_writel(host, 0, SDHCI_TEGRA_VNDR_TUN_CTRL1_0);
1038
1039 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
1040
1041 sdhci_set_uhs_signaling(host, timing);
1042
1043 tegra_sdhci_pad_autocalib(host);
1044
1045 if (tegra_host->tuned_tap_delay && !set_default_tap)
1046 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1047 else
1048 tegra_sdhci_set_tap(host, tegra_host->default_tap);
1049
1050 if (set_dqs_trim)
1051 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
1052
1053 if (do_hs400_dll_cal)
1054 tegra_sdhci_hs400_dll_cal(host);
1055 }
1056
tegra_sdhci_execute_tuning(struct sdhci_host * host,u32 opcode)1057 static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
1058 {
1059 unsigned int min, max;
1060
1061 /*
1062 * Start search for minimum tap value at 10, as smaller values are
1063 * may wrongly be reported as working but fail at higher speeds,
1064 * according to the TRM.
1065 */
1066 min = 10;
1067 while (min < 255) {
1068 tegra_sdhci_set_tap(host, min);
1069 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1070 break;
1071 min++;
1072 }
1073
1074 /* Find the maximum tap value that still passes. */
1075 max = min + 1;
1076 while (max < 255) {
1077 tegra_sdhci_set_tap(host, max);
1078 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1079 max--;
1080 break;
1081 }
1082 max++;
1083 }
1084
1085 /* The TRM states the ideal tap value is at 75% in the passing range. */
1086 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
1087
1088 return mmc_send_tuning(host->mmc, opcode, NULL);
1089 }
1090
sdhci_tegra_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)1091 static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
1092 struct mmc_ios *ios)
1093 {
1094 struct sdhci_host *host = mmc_priv(mmc);
1095 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1096 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1097 int ret = 0;
1098
1099 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1100 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1101 if (ret < 0)
1102 return ret;
1103 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1104 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1105 ret = sdhci_start_signal_voltage_switch(mmc, ios);
1106 if (ret < 0)
1107 return ret;
1108 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1109 }
1110
1111 if (tegra_host->pad_calib_required)
1112 tegra_sdhci_pad_autocalib(host);
1113
1114 return ret;
1115 }
1116
tegra_sdhci_init_pinctrl_info(struct device * dev,struct sdhci_tegra * tegra_host)1117 static int tegra_sdhci_init_pinctrl_info(struct device *dev,
1118 struct sdhci_tegra *tegra_host)
1119 {
1120 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
1121 if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
1122 dev_dbg(dev, "No pinctrl info, err: %ld\n",
1123 PTR_ERR(tegra_host->pinctrl_sdmmc));
1124 return -1;
1125 }
1126
1127 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
1128 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
1129 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
1130 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
1131 tegra_host->pinctrl_state_1v8_drv = NULL;
1132 }
1133
1134 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
1135 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
1136 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
1137 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
1138 tegra_host->pinctrl_state_3v3_drv = NULL;
1139 }
1140
1141 tegra_host->pinctrl_state_3v3 =
1142 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
1143 if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
1144 dev_warn(dev, "Missing 3.3V pad state, err: %ld\n",
1145 PTR_ERR(tegra_host->pinctrl_state_3v3));
1146 return -1;
1147 }
1148
1149 tegra_host->pinctrl_state_1v8 =
1150 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
1151 if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
1152 dev_warn(dev, "Missing 1.8V pad state, err: %ld\n",
1153 PTR_ERR(tegra_host->pinctrl_state_1v8));
1154 return -1;
1155 }
1156
1157 tegra_host->pad_control_available = true;
1158
1159 return 0;
1160 }
1161
tegra_sdhci_voltage_switch(struct sdhci_host * host)1162 static void tegra_sdhci_voltage_switch(struct sdhci_host *host)
1163 {
1164 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1165 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1166 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1167
1168 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1169 tegra_host->pad_calib_required = true;
1170 }
1171
tegra_cqhci_writel(struct cqhci_host * cq_host,u32 val,int reg)1172 static void tegra_cqhci_writel(struct cqhci_host *cq_host, u32 val, int reg)
1173 {
1174 struct mmc_host *mmc = cq_host->mmc;
1175 struct sdhci_host *host = mmc_priv(mmc);
1176 u8 ctrl;
1177 ktime_t timeout;
1178 bool timed_out;
1179
1180 /*
1181 * During CQE resume/unhalt, CQHCI driver unhalts CQE prior to
1182 * cqhci_host_ops enable where SDHCI DMA and BLOCK_SIZE registers need
1183 * to be re-configured.
1184 * Tegra CQHCI/SDHCI prevents write access to block size register when
1185 * CQE is unhalted. So handling CQE resume sequence here to configure
1186 * SDHCI block registers prior to exiting CQE halt state.
1187 */
1188 if (reg == CQHCI_CTL && !(val & CQHCI_HALT) &&
1189 cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) {
1190 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1191 sdhci_cqe_enable(mmc);
1192 writel(val, cq_host->mmio + reg);
1193 timeout = ktime_add_us(ktime_get(), 50);
1194 while (1) {
1195 timed_out = ktime_compare(ktime_get(), timeout) > 0;
1196 ctrl = cqhci_readl(cq_host, CQHCI_CTL);
1197 if (!(ctrl & CQHCI_HALT) || timed_out)
1198 break;
1199 }
1200 /*
1201 * CQE usually resumes very quick, but incase if Tegra CQE
1202 * doesn't resume retry unhalt.
1203 */
1204 if (timed_out)
1205 writel(val, cq_host->mmio + reg);
1206 } else {
1207 writel(val, cq_host->mmio + reg);
1208 }
1209 }
1210
sdhci_tegra_update_dcmd_desc(struct mmc_host * mmc,struct mmc_request * mrq,u64 * data)1211 static void sdhci_tegra_update_dcmd_desc(struct mmc_host *mmc,
1212 struct mmc_request *mrq, u64 *data)
1213 {
1214 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(mmc_priv(mmc));
1215 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1216 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1217
1218 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
1219 mrq->cmd->flags & MMC_RSP_R1B)
1220 *data |= CQHCI_CMD_TIMING(1);
1221 }
1222
sdhci_tegra_cqe_enable(struct mmc_host * mmc)1223 static void sdhci_tegra_cqe_enable(struct mmc_host *mmc)
1224 {
1225 struct cqhci_host *cq_host = mmc->cqe_private;
1226 struct sdhci_host *host = mmc_priv(mmc);
1227 u32 val;
1228
1229 /*
1230 * Tegra CQHCI/SDMMC design prevents write access to sdhci block size
1231 * register when CQE is enabled and unhalted.
1232 * CQHCI driver enables CQE prior to activation, so disable CQE before
1233 * programming block size in sdhci controller and enable it back.
1234 */
1235 if (!cq_host->activated) {
1236 val = cqhci_readl(cq_host, CQHCI_CFG);
1237 if (val & CQHCI_ENABLE)
1238 cqhci_writel(cq_host, (val & ~CQHCI_ENABLE),
1239 CQHCI_CFG);
1240 sdhci_writew(host, SDHCI_TEGRA_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1241 sdhci_cqe_enable(mmc);
1242 if (val & CQHCI_ENABLE)
1243 cqhci_writel(cq_host, val, CQHCI_CFG);
1244 }
1245
1246 /*
1247 * CMD CRC errors are seen sometimes with some eMMC devices when status
1248 * command is sent during transfer of last data block which is the
1249 * default case as send status command block counter (CBC) is 1.
1250 * Recommended fix to set CBC to 0 allowing send status command only
1251 * when data lines are idle.
1252 */
1253 val = cqhci_readl(cq_host, CQHCI_SSC1);
1254 val &= ~CQHCI_SSC1_CBC_MASK;
1255 cqhci_writel(cq_host, val, CQHCI_SSC1);
1256 }
1257
sdhci_tegra_dumpregs(struct mmc_host * mmc)1258 static void sdhci_tegra_dumpregs(struct mmc_host *mmc)
1259 {
1260 sdhci_dumpregs(mmc_priv(mmc));
1261 }
1262
sdhci_tegra_cqhci_irq(struct sdhci_host * host,u32 intmask)1263 static u32 sdhci_tegra_cqhci_irq(struct sdhci_host *host, u32 intmask)
1264 {
1265 int cmd_error = 0;
1266 int data_error = 0;
1267
1268 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1269 return intmask;
1270
1271 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1272
1273 return 0;
1274 }
1275
tegra_sdhci_set_timeout(struct sdhci_host * host,struct mmc_command * cmd)1276 static void tegra_sdhci_set_timeout(struct sdhci_host *host,
1277 struct mmc_command *cmd)
1278 {
1279 u32 val;
1280
1281 /*
1282 * HW busy detection timeout is based on programmed data timeout
1283 * counter and maximum supported timeout is 11s which may not be
1284 * enough for long operations like cache flush, sleep awake, erase.
1285 *
1286 * ERASE_TIMEOUT_LIMIT bit of VENDOR_MISC_CTRL register allows
1287 * host controller to wait for busy state until the card is busy
1288 * without HW timeout.
1289 *
1290 * So, use infinite busy wait mode for operations that may take
1291 * more than maximum HW busy timeout of 11s otherwise use finite
1292 * busy wait mode.
1293 */
1294 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
1295 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC)
1296 val |= SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
1297 else
1298 val &= ~SDHCI_MISC_CTRL_ERASE_TIMEOUT_LIMIT;
1299 sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_MISC_CTRL);
1300
1301 __sdhci_set_timeout(host, cmd);
1302 }
1303
sdhci_tegra_cqe_pre_enable(struct mmc_host * mmc)1304 static void sdhci_tegra_cqe_pre_enable(struct mmc_host *mmc)
1305 {
1306 struct cqhci_host *cq_host = mmc->cqe_private;
1307 u32 reg;
1308
1309 reg = cqhci_readl(cq_host, CQHCI_CFG);
1310 reg |= CQHCI_ENABLE;
1311 cqhci_writel(cq_host, reg, CQHCI_CFG);
1312 }
1313
sdhci_tegra_cqe_post_disable(struct mmc_host * mmc)1314 static void sdhci_tegra_cqe_post_disable(struct mmc_host *mmc)
1315 {
1316 struct cqhci_host *cq_host = mmc->cqe_private;
1317 struct sdhci_host *host = mmc_priv(mmc);
1318 u32 reg;
1319
1320 reg = cqhci_readl(cq_host, CQHCI_CFG);
1321 reg &= ~CQHCI_ENABLE;
1322 cqhci_writel(cq_host, reg, CQHCI_CFG);
1323 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1324 }
1325
1326 static const struct cqhci_host_ops sdhci_tegra_cqhci_ops = {
1327 .write_l = tegra_cqhci_writel,
1328 .enable = sdhci_tegra_cqe_enable,
1329 .disable = sdhci_cqe_disable,
1330 .dumpregs = sdhci_tegra_dumpregs,
1331 .update_dcmd_desc = sdhci_tegra_update_dcmd_desc,
1332 .pre_enable = sdhci_tegra_cqe_pre_enable,
1333 .post_disable = sdhci_tegra_cqe_post_disable,
1334 };
1335
tegra_sdhci_set_dma_mask(struct sdhci_host * host)1336 static int tegra_sdhci_set_dma_mask(struct sdhci_host *host)
1337 {
1338 struct sdhci_pltfm_host *platform = sdhci_priv(host);
1339 struct sdhci_tegra *tegra = sdhci_pltfm_priv(platform);
1340 const struct sdhci_tegra_soc_data *soc = tegra->soc_data;
1341 struct device *dev = mmc_dev(host->mmc);
1342
1343 if (soc->dma_mask)
1344 return dma_set_mask_and_coherent(dev, soc->dma_mask);
1345
1346 return 0;
1347 }
1348
1349 static const struct sdhci_ops tegra_sdhci_ops = {
1350 .get_ro = tegra_sdhci_get_ro,
1351 .read_w = tegra_sdhci_readw,
1352 .write_l = tegra_sdhci_writel,
1353 .set_clock = tegra_sdhci_set_clock,
1354 .set_dma_mask = tegra_sdhci_set_dma_mask,
1355 .set_bus_width = sdhci_set_bus_width,
1356 .reset = tegra_sdhci_reset,
1357 .platform_execute_tuning = tegra_sdhci_execute_tuning,
1358 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1359 .voltage_switch = tegra_sdhci_voltage_switch,
1360 .get_max_clock = tegra_sdhci_get_max_clock,
1361 };
1362
1363 static const struct sdhci_pltfm_data sdhci_tegra20_pdata = {
1364 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1365 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1366 SDHCI_QUIRK_NO_HISPD_BIT |
1367 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1368 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1369 .ops = &tegra_sdhci_ops,
1370 };
1371
1372 static const struct sdhci_tegra_soc_data soc_data_tegra20 = {
1373 .pdata = &sdhci_tegra20_pdata,
1374 .dma_mask = DMA_BIT_MASK(32),
1375 .nvquirks = NVQUIRK_FORCE_SDHCI_SPEC_200 |
1376 NVQUIRK_HAS_ANDROID_GPT_SECTOR |
1377 NVQUIRK_ENABLE_BLOCK_GAP_DET,
1378 };
1379
1380 static const struct sdhci_pltfm_data sdhci_tegra30_pdata = {
1381 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1382 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1383 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1384 SDHCI_QUIRK_NO_HISPD_BIT |
1385 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1386 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1387 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1388 SDHCI_QUIRK2_BROKEN_HS200 |
1389 /*
1390 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1391 * though no command operation was in progress."
1392 *
1393 * The exact reason is unknown, as the same hardware seems
1394 * to support Auto CMD23 on a downstream 3.1 kernel.
1395 */
1396 SDHCI_QUIRK2_ACMD23_BROKEN,
1397 .ops = &tegra_sdhci_ops,
1398 };
1399
1400 static const struct sdhci_tegra_soc_data soc_data_tegra30 = {
1401 .pdata = &sdhci_tegra30_pdata,
1402 .dma_mask = DMA_BIT_MASK(32),
1403 .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300 |
1404 NVQUIRK_ENABLE_SDR50 |
1405 NVQUIRK_ENABLE_SDR104 |
1406 NVQUIRK_HAS_ANDROID_GPT_SECTOR |
1407 NVQUIRK_HAS_PADCALIB,
1408 };
1409
1410 static const struct sdhci_ops tegra114_sdhci_ops = {
1411 .get_ro = tegra_sdhci_get_ro,
1412 .read_w = tegra_sdhci_readw,
1413 .write_w = tegra_sdhci_writew,
1414 .write_l = tegra_sdhci_writel,
1415 .set_clock = tegra_sdhci_set_clock,
1416 .set_dma_mask = tegra_sdhci_set_dma_mask,
1417 .set_bus_width = sdhci_set_bus_width,
1418 .reset = tegra_sdhci_reset,
1419 .platform_execute_tuning = tegra_sdhci_execute_tuning,
1420 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1421 .voltage_switch = tegra_sdhci_voltage_switch,
1422 .get_max_clock = tegra_sdhci_get_max_clock,
1423 };
1424
1425 static const struct sdhci_pltfm_data sdhci_tegra114_pdata = {
1426 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1427 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1428 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1429 SDHCI_QUIRK_NO_HISPD_BIT |
1430 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1431 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1432 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1433 .ops = &tegra114_sdhci_ops,
1434 };
1435
1436 static const struct sdhci_tegra_soc_data soc_data_tegra114 = {
1437 .pdata = &sdhci_tegra114_pdata,
1438 .dma_mask = DMA_BIT_MASK(32),
1439 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR,
1440 };
1441
1442 static const struct sdhci_pltfm_data sdhci_tegra124_pdata = {
1443 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1444 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
1445 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1446 SDHCI_QUIRK_NO_HISPD_BIT |
1447 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1448 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1449 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1450 .ops = &tegra114_sdhci_ops,
1451 };
1452
1453 static const struct sdhci_tegra_soc_data soc_data_tegra124 = {
1454 .pdata = &sdhci_tegra124_pdata,
1455 .dma_mask = DMA_BIT_MASK(34),
1456 .nvquirks = NVQUIRK_HAS_ANDROID_GPT_SECTOR,
1457 };
1458
1459 static const struct sdhci_ops tegra210_sdhci_ops = {
1460 .get_ro = tegra_sdhci_get_ro,
1461 .read_w = tegra_sdhci_readw,
1462 .write_w = tegra210_sdhci_writew,
1463 .write_l = tegra_sdhci_writel,
1464 .set_clock = tegra_sdhci_set_clock,
1465 .set_dma_mask = tegra_sdhci_set_dma_mask,
1466 .set_bus_width = sdhci_set_bus_width,
1467 .reset = tegra_sdhci_reset,
1468 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1469 .voltage_switch = tegra_sdhci_voltage_switch,
1470 .get_max_clock = tegra_sdhci_get_max_clock,
1471 .set_timeout = tegra_sdhci_set_timeout,
1472 };
1473
1474 static const struct sdhci_pltfm_data sdhci_tegra210_pdata = {
1475 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1476 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1477 SDHCI_QUIRK_NO_HISPD_BIT |
1478 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1479 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1480 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1481 .ops = &tegra210_sdhci_ops,
1482 };
1483
1484 static const struct sdhci_tegra_soc_data soc_data_tegra210 = {
1485 .pdata = &sdhci_tegra210_pdata,
1486 .dma_mask = DMA_BIT_MASK(34),
1487 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1488 NVQUIRK_HAS_PADCALIB |
1489 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1490 NVQUIRK_ENABLE_SDR50 |
1491 NVQUIRK_ENABLE_SDR104 |
1492 NVQUIRK_HAS_TMCLK,
1493 .min_tap_delay = 106,
1494 .max_tap_delay = 185,
1495 };
1496
1497 static const struct sdhci_ops tegra186_sdhci_ops = {
1498 .get_ro = tegra_sdhci_get_ro,
1499 .read_w = tegra_sdhci_readw,
1500 .write_l = tegra_sdhci_writel,
1501 .set_clock = tegra_sdhci_set_clock,
1502 .set_dma_mask = tegra_sdhci_set_dma_mask,
1503 .set_bus_width = sdhci_set_bus_width,
1504 .reset = tegra_sdhci_reset,
1505 .set_uhs_signaling = tegra_sdhci_set_uhs_signaling,
1506 .voltage_switch = tegra_sdhci_voltage_switch,
1507 .get_max_clock = tegra_sdhci_get_max_clock,
1508 .irq = sdhci_tegra_cqhci_irq,
1509 .set_timeout = tegra_sdhci_set_timeout,
1510 };
1511
1512 static const struct sdhci_pltfm_data sdhci_tegra186_pdata = {
1513 .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
1514 SDHCI_QUIRK_SINGLE_POWER_WRITE |
1515 SDHCI_QUIRK_NO_HISPD_BIT |
1516 SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
1517 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
1518 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1519 .ops = &tegra186_sdhci_ops,
1520 };
1521
1522 static const struct sdhci_tegra_soc_data soc_data_tegra186 = {
1523 .pdata = &sdhci_tegra186_pdata,
1524 .dma_mask = DMA_BIT_MASK(40),
1525 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1526 NVQUIRK_HAS_PADCALIB |
1527 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1528 NVQUIRK_ENABLE_SDR50 |
1529 NVQUIRK_ENABLE_SDR104 |
1530 NVQUIRK_HAS_TMCLK |
1531 NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING,
1532 .min_tap_delay = 84,
1533 .max_tap_delay = 136,
1534 };
1535
1536 static const struct sdhci_tegra_soc_data soc_data_tegra194 = {
1537 .pdata = &sdhci_tegra186_pdata,
1538 .dma_mask = DMA_BIT_MASK(39),
1539 .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL |
1540 NVQUIRK_HAS_PADCALIB |
1541 NVQUIRK_DIS_CARD_CLK_CONFIG_TAP |
1542 NVQUIRK_ENABLE_SDR50 |
1543 NVQUIRK_ENABLE_SDR104 |
1544 NVQUIRK_HAS_TMCLK,
1545 .min_tap_delay = 96,
1546 .max_tap_delay = 139,
1547 };
1548
1549 static const struct of_device_id sdhci_tegra_dt_match[] = {
1550 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1551 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1552 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1553 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1554 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1555 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1556 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1557 {}
1558 };
1559 MODULE_DEVICE_TABLE(of, sdhci_tegra_dt_match);
1560
sdhci_tegra_add_host(struct sdhci_host * host)1561 static int sdhci_tegra_add_host(struct sdhci_host *host)
1562 {
1563 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1564 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1565 struct cqhci_host *cq_host;
1566 bool dma64;
1567 int ret;
1568
1569 if (!tegra_host->enable_hwcq)
1570 return sdhci_add_host(host);
1571
1572 sdhci_enable_v4_mode(host);
1573
1574 ret = sdhci_setup_host(host);
1575 if (ret)
1576 return ret;
1577
1578 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1579
1580 cq_host = devm_kzalloc(mmc_dev(host->mmc),
1581 sizeof(*cq_host), GFP_KERNEL);
1582 if (!cq_host) {
1583 ret = -ENOMEM;
1584 goto cleanup;
1585 }
1586
1587 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
1588 cq_host->ops = &sdhci_tegra_cqhci_ops;
1589
1590 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1591 if (dma64)
1592 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1593
1594 ret = cqhci_init(cq_host, host->mmc, dma64);
1595 if (ret)
1596 goto cleanup;
1597
1598 ret = __sdhci_add_host(host);
1599 if (ret)
1600 goto cleanup;
1601
1602 return 0;
1603
1604 cleanup:
1605 sdhci_cleanup_host(host);
1606 return ret;
1607 }
1608
sdhci_tegra_probe(struct platform_device * pdev)1609 static int sdhci_tegra_probe(struct platform_device *pdev)
1610 {
1611 const struct of_device_id *match;
1612 const struct sdhci_tegra_soc_data *soc_data;
1613 struct sdhci_host *host;
1614 struct sdhci_pltfm_host *pltfm_host;
1615 struct sdhci_tegra *tegra_host;
1616 struct clk *clk;
1617 int rc;
1618
1619 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev);
1620 if (!match)
1621 return -EINVAL;
1622 soc_data = match->data;
1623
1624 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1625 if (IS_ERR(host))
1626 return PTR_ERR(host);
1627 pltfm_host = sdhci_priv(host);
1628
1629 tegra_host = sdhci_pltfm_priv(pltfm_host);
1630 tegra_host->ddr_signaling = false;
1631 tegra_host->pad_calib_required = false;
1632 tegra_host->pad_control_available = false;
1633 tegra_host->soc_data = soc_data;
1634
1635 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR)
1636 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA;
1637
1638 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1639 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1640 if (rc == 0)
1641 host->mmc_host_ops.start_signal_voltage_switch =
1642 sdhci_tegra_start_signal_voltage_switch;
1643 }
1644
1645 /* Hook to periodically rerun pad calibration */
1646 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1647 host->mmc_host_ops.request = tegra_sdhci_request;
1648
1649 host->mmc_host_ops.hs400_enhanced_strobe =
1650 tegra_sdhci_hs400_enhanced_strobe;
1651
1652 if (!host->ops->platform_execute_tuning)
1653 host->mmc_host_ops.execute_tuning =
1654 tegra_sdhci_execute_hw_tuning;
1655
1656 rc = mmc_of_parse(host->mmc);
1657 if (rc)
1658 goto err_parse_dt;
1659
1660 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1661 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1662
1663 /* HW busy detection is supported, but R1B responses are required. */
1664 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1665
1666 tegra_sdhci_parse_dt(host);
1667
1668 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1669 GPIOD_OUT_HIGH);
1670 if (IS_ERR(tegra_host->power_gpio)) {
1671 rc = PTR_ERR(tegra_host->power_gpio);
1672 goto err_power_req;
1673 }
1674
1675 /*
1676 * Tegra210 has a separate SDMMC_LEGACY_TM clock used for host
1677 * timeout clock and SW can choose TMCLK or SDCLK for hardware
1678 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of
1679 * the register SDHCI_TEGRA_VENDOR_SYS_SW_CTRL.
1680 *
1681 * USE_TMCLK_FOR_DATA_TIMEOUT bit default is set to 1 and SDMMC uses
1682 * 12Mhz TMCLK which is advertised in host capability register.
1683 * With TMCLK of 12Mhz provides maximum data timeout period that can
1684 * be achieved is 11s better than using SDCLK for data timeout.
1685 *
1686 * So, TMCLK is set to 12Mhz and kept enabled all the time on SoC's
1687 * supporting separate TMCLK.
1688 */
1689
1690 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {
1691 clk = devm_clk_get(&pdev->dev, "tmclk");
1692 if (IS_ERR(clk)) {
1693 rc = PTR_ERR(clk);
1694 if (rc == -EPROBE_DEFER)
1695 goto err_power_req;
1696
1697 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
1698 clk = NULL;
1699 }
1700
1701 clk_set_rate(clk, 12000000);
1702 rc = clk_prepare_enable(clk);
1703 if (rc) {
1704 dev_err(&pdev->dev,
1705 "failed to enable tmclk: %d\n", rc);
1706 goto err_power_req;
1707 }
1708
1709 tegra_host->tmclk = clk;
1710 }
1711
1712 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1713 if (IS_ERR(clk)) {
1714 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk),
1715 "failed to get clock\n");
1716 goto err_clk_get;
1717 }
1718 clk_prepare_enable(clk);
1719 pltfm_host->clk = clk;
1720
1721 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1722 "sdhci");
1723 if (IS_ERR(tegra_host->rst)) {
1724 rc = PTR_ERR(tegra_host->rst);
1725 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1726 goto err_rst_get;
1727 }
1728
1729 rc = reset_control_assert(tegra_host->rst);
1730 if (rc)
1731 goto err_rst_get;
1732
1733 usleep_range(2000, 4000);
1734
1735 rc = reset_control_deassert(tegra_host->rst);
1736 if (rc)
1737 goto err_rst_get;
1738
1739 usleep_range(2000, 4000);
1740
1741 rc = sdhci_tegra_add_host(host);
1742 if (rc)
1743 goto err_add_host;
1744
1745 return 0;
1746
1747 err_add_host:
1748 reset_control_assert(tegra_host->rst);
1749 err_rst_get:
1750 clk_disable_unprepare(pltfm_host->clk);
1751 err_clk_get:
1752 clk_disable_unprepare(tegra_host->tmclk);
1753 err_power_req:
1754 err_parse_dt:
1755 sdhci_pltfm_free(pdev);
1756 return rc;
1757 }
1758
sdhci_tegra_remove(struct platform_device * pdev)1759 static int sdhci_tegra_remove(struct platform_device *pdev)
1760 {
1761 struct sdhci_host *host = platform_get_drvdata(pdev);
1762 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1763 struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
1764
1765 sdhci_remove_host(host, 0);
1766
1767 reset_control_assert(tegra_host->rst);
1768 usleep_range(2000, 4000);
1769 clk_disable_unprepare(pltfm_host->clk);
1770 clk_disable_unprepare(tegra_host->tmclk);
1771
1772 sdhci_pltfm_free(pdev);
1773
1774 return 0;
1775 }
1776
1777 #ifdef CONFIG_PM_SLEEP
sdhci_tegra_suspend(struct device * dev)1778 static int __maybe_unused sdhci_tegra_suspend(struct device *dev)
1779 {
1780 struct sdhci_host *host = dev_get_drvdata(dev);
1781 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1782 int ret;
1783
1784 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1785 ret = cqhci_suspend(host->mmc);
1786 if (ret)
1787 return ret;
1788 }
1789
1790 ret = sdhci_suspend_host(host);
1791 if (ret) {
1792 cqhci_resume(host->mmc);
1793 return ret;
1794 }
1795
1796 clk_disable_unprepare(pltfm_host->clk);
1797 return 0;
1798 }
1799
sdhci_tegra_resume(struct device * dev)1800 static int __maybe_unused sdhci_tegra_resume(struct device *dev)
1801 {
1802 struct sdhci_host *host = dev_get_drvdata(dev);
1803 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1804 int ret;
1805
1806 ret = clk_prepare_enable(pltfm_host->clk);
1807 if (ret)
1808 return ret;
1809
1810 ret = sdhci_resume_host(host);
1811 if (ret)
1812 goto disable_clk;
1813
1814 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1815 ret = cqhci_resume(host->mmc);
1816 if (ret)
1817 goto suspend_host;
1818 }
1819
1820 return 0;
1821
1822 suspend_host:
1823 sdhci_suspend_host(host);
1824 disable_clk:
1825 clk_disable_unprepare(pltfm_host->clk);
1826 return ret;
1827 }
1828 #endif
1829
1830 static SIMPLE_DEV_PM_OPS(sdhci_tegra_dev_pm_ops, sdhci_tegra_suspend,
1831 sdhci_tegra_resume);
1832
1833 static struct platform_driver sdhci_tegra_driver = {
1834 .driver = {
1835 .name = "sdhci-tegra",
1836 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1837 .of_match_table = sdhci_tegra_dt_match,
1838 .pm = &sdhci_tegra_dev_pm_ops,
1839 },
1840 .probe = sdhci_tegra_probe,
1841 .remove = sdhci_tegra_remove,
1842 };
1843
1844 module_platform_driver(sdhci_tegra_driver);
1845
1846 MODULE_DESCRIPTION("SDHCI driver for Tegra");
1847 MODULE_AUTHOR("Google, Inc.");
1848 MODULE_LICENSE("GPL v2");
1849