1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
3 *
4 * Copyright (C) 2015 Renesas Electronics Corp.
5 */
6
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
10 *
11 * This driver puts the controller in CAN FD only mode by default. In this
12 * mode, the controller acts as a CAN FD node that can also interoperate with
13 * CAN 2.0 nodes.
14 *
15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
17 * also required to switch modes.
18 *
19 * Note: The h/w manual register naming convention is clumsy and not acceptable
20 * to use as it is in the driver. However, those names are added as comments
21 * wherever it is modified to a readable name.
22 */
23
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kernel.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
29 #include <linux/errno.h>
30 #include <linux/netdevice.h>
31 #include <linux/platform_device.h>
32 #include <linux/can/led.h>
33 #include <linux/can/dev.h>
34 #include <linux/clk.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/bitmap.h>
38 #include <linux/bitops.h>
39 #include <linux/iopoll.h>
40 #include <linux/reset.h>
41
42 #define RCANFD_DRV_NAME "rcar_canfd"
43
44 enum rcanfd_chip_id {
45 RENESAS_RCAR_GEN3 = 0,
46 RENESAS_RZG2L,
47 };
48
49 /* Global register bits */
50
51 /* RSCFDnCFDGRMCFG */
52 #define RCANFD_GRMCFG_RCMC BIT(0)
53
54 /* RSCFDnCFDGCFG / RSCFDnGCFG */
55 #define RCANFD_GCFG_EEFE BIT(6)
56 #define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */
57 #define RCANFD_GCFG_DCS BIT(4)
58 #define RCANFD_GCFG_DCE BIT(1)
59 #define RCANFD_GCFG_TPRI BIT(0)
60
61 /* RSCFDnCFDGCTR / RSCFDnGCTR */
62 #define RCANFD_GCTR_TSRST BIT(16)
63 #define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */
64 #define RCANFD_GCTR_THLEIE BIT(10)
65 #define RCANFD_GCTR_MEIE BIT(9)
66 #define RCANFD_GCTR_DEIE BIT(8)
67 #define RCANFD_GCTR_GSLPR BIT(2)
68 #define RCANFD_GCTR_GMDC_MASK (0x3)
69 #define RCANFD_GCTR_GMDC_GOPM (0x0)
70 #define RCANFD_GCTR_GMDC_GRESET (0x1)
71 #define RCANFD_GCTR_GMDC_GTEST (0x2)
72
73 /* RSCFDnCFDGSTS / RSCFDnGSTS */
74 #define RCANFD_GSTS_GRAMINIT BIT(3)
75 #define RCANFD_GSTS_GSLPSTS BIT(2)
76 #define RCANFD_GSTS_GHLTSTS BIT(1)
77 #define RCANFD_GSTS_GRSTSTS BIT(0)
78 /* Non-operational status */
79 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
80
81 /* RSCFDnCFDGERFL / RSCFDnGERFL */
82 #define RCANFD_GERFL_EEF1 BIT(17)
83 #define RCANFD_GERFL_EEF0 BIT(16)
84 #define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */
85 #define RCANFD_GERFL_THLES BIT(2)
86 #define RCANFD_GERFL_MES BIT(1)
87 #define RCANFD_GERFL_DEF BIT(0)
88
89 #define RCANFD_GERFL_ERR(gpriv, x) ((x) & (RCANFD_GERFL_EEF1 |\
90 RCANFD_GERFL_EEF0 | RCANFD_GERFL_MES |\
91 (gpriv->fdmode ?\
92 RCANFD_GERFL_CMPOF : 0)))
93
94 /* AFL Rx rules registers */
95
96 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
97 #define RCANFD_GAFLCFG_SETRNC(n, x) (((x) & 0xff) << (24 - n * 8))
98 #define RCANFD_GAFLCFG_GETRNC(n, x) (((x) >> (24 - n * 8)) & 0xff)
99
100 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
101 #define RCANFD_GAFLECTR_AFLDAE BIT(8)
102 #define RCANFD_GAFLECTR_AFLPN(x) ((x) & 0x1f)
103
104 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
105 #define RCANFD_GAFLID_GAFLLB BIT(29)
106
107 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
108 #define RCANFD_GAFLP1_GAFLFDP(x) (1 << (x))
109
110 /* Channel register bits */
111
112 /* RSCFDnCmCFG - Classical CAN only */
113 #define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24)
114 #define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20)
115 #define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16)
116 #define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0)
117
118 /* RSCFDnCFDCmNCFG - CAN FD only */
119 #define RCANFD_NCFG_NTSEG2(x) (((x) & 0x1f) << 24)
120 #define RCANFD_NCFG_NTSEG1(x) (((x) & 0x7f) << 16)
121 #define RCANFD_NCFG_NSJW(x) (((x) & 0x1f) << 11)
122 #define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
123
124 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
125 #define RCANFD_CCTR_CTME BIT(24)
126 #define RCANFD_CCTR_ERRD BIT(23)
127 #define RCANFD_CCTR_BOM_MASK (0x3 << 21)
128 #define RCANFD_CCTR_BOM_ISO (0x0 << 21)
129 #define RCANFD_CCTR_BOM_BENTRY (0x1 << 21)
130 #define RCANFD_CCTR_BOM_BEND (0x2 << 21)
131 #define RCANFD_CCTR_TDCVFIE BIT(19)
132 #define RCANFD_CCTR_SOCOIE BIT(18)
133 #define RCANFD_CCTR_EOCOIE BIT(17)
134 #define RCANFD_CCTR_TAIE BIT(16)
135 #define RCANFD_CCTR_ALIE BIT(15)
136 #define RCANFD_CCTR_BLIE BIT(14)
137 #define RCANFD_CCTR_OLIE BIT(13)
138 #define RCANFD_CCTR_BORIE BIT(12)
139 #define RCANFD_CCTR_BOEIE BIT(11)
140 #define RCANFD_CCTR_EPIE BIT(10)
141 #define RCANFD_CCTR_EWIE BIT(9)
142 #define RCANFD_CCTR_BEIE BIT(8)
143 #define RCANFD_CCTR_CSLPR BIT(2)
144 #define RCANFD_CCTR_CHMDC_MASK (0x3)
145 #define RCANFD_CCTR_CHDMC_COPM (0x0)
146 #define RCANFD_CCTR_CHDMC_CRESET (0x1)
147 #define RCANFD_CCTR_CHDMC_CHLT (0x2)
148
149 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
150 #define RCANFD_CSTS_COMSTS BIT(7)
151 #define RCANFD_CSTS_RECSTS BIT(6)
152 #define RCANFD_CSTS_TRMSTS BIT(5)
153 #define RCANFD_CSTS_BOSTS BIT(4)
154 #define RCANFD_CSTS_EPSTS BIT(3)
155 #define RCANFD_CSTS_SLPSTS BIT(2)
156 #define RCANFD_CSTS_HLTSTS BIT(1)
157 #define RCANFD_CSTS_CRSTSTS BIT(0)
158
159 #define RCANFD_CSTS_TECCNT(x) (((x) >> 24) & 0xff)
160 #define RCANFD_CSTS_RECCNT(x) (((x) >> 16) & 0xff)
161
162 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
163 #define RCANFD_CERFL_ADERR BIT(14)
164 #define RCANFD_CERFL_B0ERR BIT(13)
165 #define RCANFD_CERFL_B1ERR BIT(12)
166 #define RCANFD_CERFL_CERR BIT(11)
167 #define RCANFD_CERFL_AERR BIT(10)
168 #define RCANFD_CERFL_FERR BIT(9)
169 #define RCANFD_CERFL_SERR BIT(8)
170 #define RCANFD_CERFL_ALF BIT(7)
171 #define RCANFD_CERFL_BLF BIT(6)
172 #define RCANFD_CERFL_OVLF BIT(5)
173 #define RCANFD_CERFL_BORF BIT(4)
174 #define RCANFD_CERFL_BOEF BIT(3)
175 #define RCANFD_CERFL_EPF BIT(2)
176 #define RCANFD_CERFL_EWF BIT(1)
177 #define RCANFD_CERFL_BEF BIT(0)
178
179 #define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */
180
181 /* RSCFDnCFDCmDCFG */
182 #define RCANFD_DCFG_DSJW(x) (((x) & 0x7) << 24)
183 #define RCANFD_DCFG_DTSEG2(x) (((x) & 0x7) << 20)
184 #define RCANFD_DCFG_DTSEG1(x) (((x) & 0xf) << 16)
185 #define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
186
187 /* RSCFDnCFDCmFDCFG */
188 #define RCANFD_FDCFG_TDCE BIT(9)
189 #define RCANFD_FDCFG_TDCOC BIT(8)
190 #define RCANFD_FDCFG_TDCO(x) (((x) & 0x7f) >> 16)
191
192 /* RSCFDnCFDRFCCx */
193 #define RCANFD_RFCC_RFIM BIT(12)
194 #define RCANFD_RFCC_RFDC(x) (((x) & 0x7) << 8)
195 #define RCANFD_RFCC_RFPLS(x) (((x) & 0x7) << 4)
196 #define RCANFD_RFCC_RFIE BIT(1)
197 #define RCANFD_RFCC_RFE BIT(0)
198
199 /* RSCFDnCFDRFSTSx */
200 #define RCANFD_RFSTS_RFIF BIT(3)
201 #define RCANFD_RFSTS_RFMLT BIT(2)
202 #define RCANFD_RFSTS_RFFLL BIT(1)
203 #define RCANFD_RFSTS_RFEMP BIT(0)
204
205 /* RSCFDnCFDRFIDx */
206 #define RCANFD_RFID_RFIDE BIT(31)
207 #define RCANFD_RFID_RFRTR BIT(30)
208
209 /* RSCFDnCFDRFPTRx */
210 #define RCANFD_RFPTR_RFDLC(x) (((x) >> 28) & 0xf)
211 #define RCANFD_RFPTR_RFPTR(x) (((x) >> 16) & 0xfff)
212 #define RCANFD_RFPTR_RFTS(x) (((x) >> 0) & 0xffff)
213
214 /* RSCFDnCFDRFFDSTSx */
215 #define RCANFD_RFFDSTS_RFFDF BIT(2)
216 #define RCANFD_RFFDSTS_RFBRS BIT(1)
217 #define RCANFD_RFFDSTS_RFESI BIT(0)
218
219 /* Common FIFO bits */
220
221 /* RSCFDnCFDCFCCk */
222 #define RCANFD_CFCC_CFTML(x) (((x) & 0xf) << 20)
223 #define RCANFD_CFCC_CFM(x) (((x) & 0x3) << 16)
224 #define RCANFD_CFCC_CFIM BIT(12)
225 #define RCANFD_CFCC_CFDC(x) (((x) & 0x7) << 8)
226 #define RCANFD_CFCC_CFPLS(x) (((x) & 0x7) << 4)
227 #define RCANFD_CFCC_CFTXIE BIT(2)
228 #define RCANFD_CFCC_CFE BIT(0)
229
230 /* RSCFDnCFDCFSTSk */
231 #define RCANFD_CFSTS_CFMC(x) (((x) >> 8) & 0xff)
232 #define RCANFD_CFSTS_CFTXIF BIT(4)
233 #define RCANFD_CFSTS_CFMLT BIT(2)
234 #define RCANFD_CFSTS_CFFLL BIT(1)
235 #define RCANFD_CFSTS_CFEMP BIT(0)
236
237 /* RSCFDnCFDCFIDk */
238 #define RCANFD_CFID_CFIDE BIT(31)
239 #define RCANFD_CFID_CFRTR BIT(30)
240 #define RCANFD_CFID_CFID_MASK(x) ((x) & 0x1fffffff)
241
242 /* RSCFDnCFDCFPTRk */
243 #define RCANFD_CFPTR_CFDLC(x) (((x) & 0xf) << 28)
244 #define RCANFD_CFPTR_CFPTR(x) (((x) & 0xfff) << 16)
245 #define RCANFD_CFPTR_CFTS(x) (((x) & 0xff) << 0)
246
247 /* RSCFDnCFDCFFDCSTSk */
248 #define RCANFD_CFFDCSTS_CFFDF BIT(2)
249 #define RCANFD_CFFDCSTS_CFBRS BIT(1)
250 #define RCANFD_CFFDCSTS_CFESI BIT(0)
251
252 /* This controller supports either Classical CAN only mode or CAN FD only mode.
253 * These modes are supported in two separate set of register maps & names.
254 * However, some of the register offsets are common for both modes. Those
255 * offsets are listed below as Common registers.
256 *
257 * The CAN FD only mode specific registers & Classical CAN only mode specific
258 * registers are listed separately. Their register names starts with
259 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
260 */
261
262 /* Common registers */
263
264 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
265 #define RCANFD_CCFG(m) (0x0000 + (0x10 * (m)))
266 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
267 #define RCANFD_CCTR(m) (0x0004 + (0x10 * (m)))
268 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
269 #define RCANFD_CSTS(m) (0x0008 + (0x10 * (m)))
270 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
271 #define RCANFD_CERFL(m) (0x000C + (0x10 * (m)))
272
273 /* RSCFDnCFDGCFG / RSCFDnGCFG */
274 #define RCANFD_GCFG (0x0084)
275 /* RSCFDnCFDGCTR / RSCFDnGCTR */
276 #define RCANFD_GCTR (0x0088)
277 /* RSCFDnCFDGCTS / RSCFDnGCTS */
278 #define RCANFD_GSTS (0x008c)
279 /* RSCFDnCFDGERFL / RSCFDnGERFL */
280 #define RCANFD_GERFL (0x0090)
281 /* RSCFDnCFDGTSC / RSCFDnGTSC */
282 #define RCANFD_GTSC (0x0094)
283 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
284 #define RCANFD_GAFLECTR (0x0098)
285 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
286 #define RCANFD_GAFLCFG0 (0x009c)
287 /* RSCFDnCFDGAFLCFG1 / RSCFDnGAFLCFG1 */
288 #define RCANFD_GAFLCFG1 (0x00a0)
289 /* RSCFDnCFDRMNB / RSCFDnRMNB */
290 #define RCANFD_RMNB (0x00a4)
291 /* RSCFDnCFDRMND / RSCFDnRMND */
292 #define RCANFD_RMND(y) (0x00a8 + (0x04 * (y)))
293
294 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
295 #define RCANFD_RFCC(x) (0x00b8 + (0x04 * (x)))
296 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
297 #define RCANFD_RFSTS(x) (0x00d8 + (0x04 * (x)))
298 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
299 #define RCANFD_RFPCTR(x) (0x00f8 + (0x04 * (x)))
300
301 /* Common FIFO Control registers */
302
303 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
304 #define RCANFD_CFCC(ch, idx) (0x0118 + (0x0c * (ch)) + \
305 (0x04 * (idx)))
306 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
307 #define RCANFD_CFSTS(ch, idx) (0x0178 + (0x0c * (ch)) + \
308 (0x04 * (idx)))
309 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
310 #define RCANFD_CFPCTR(ch, idx) (0x01d8 + (0x0c * (ch)) + \
311 (0x04 * (idx)))
312
313 /* RSCFDnCFDFESTS / RSCFDnFESTS */
314 #define RCANFD_FESTS (0x0238)
315 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
316 #define RCANFD_FFSTS (0x023c)
317 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
318 #define RCANFD_FMSTS (0x0240)
319 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
320 #define RCANFD_RFISTS (0x0244)
321 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
322 #define RCANFD_CFRISTS (0x0248)
323 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
324 #define RCANFD_CFTISTS (0x024c)
325
326 /* RSCFDnCFDTMCp / RSCFDnTMCp */
327 #define RCANFD_TMC(p) (0x0250 + (0x01 * (p)))
328 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
329 #define RCANFD_TMSTS(p) (0x02d0 + (0x01 * (p)))
330
331 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
332 #define RCANFD_TMTRSTS(y) (0x0350 + (0x04 * (y)))
333 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
334 #define RCANFD_TMTARSTS(y) (0x0360 + (0x04 * (y)))
335 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
336 #define RCANFD_TMTCSTS(y) (0x0370 + (0x04 * (y)))
337 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
338 #define RCANFD_TMTASTS(y) (0x0380 + (0x04 * (y)))
339 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
340 #define RCANFD_TMIEC(y) (0x0390 + (0x04 * (y)))
341
342 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
343 #define RCANFD_TXQCC(m) (0x03a0 + (0x04 * (m)))
344 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
345 #define RCANFD_TXQSTS(m) (0x03c0 + (0x04 * (m)))
346 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
347 #define RCANFD_TXQPCTR(m) (0x03e0 + (0x04 * (m)))
348
349 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
350 #define RCANFD_THLCC(m) (0x0400 + (0x04 * (m)))
351 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
352 #define RCANFD_THLSTS(m) (0x0420 + (0x04 * (m)))
353 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
354 #define RCANFD_THLPCTR(m) (0x0440 + (0x04 * (m)))
355
356 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
357 #define RCANFD_GTINTSTS0 (0x0460)
358 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
359 #define RCANFD_GTINTSTS1 (0x0464)
360 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
361 #define RCANFD_GTSTCFG (0x0468)
362 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
363 #define RCANFD_GTSTCTR (0x046c)
364 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
365 #define RCANFD_GLOCKK (0x047c)
366 /* RSCFDnCFDGRMCFG */
367 #define RCANFD_GRMCFG (0x04fc)
368
369 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
370 #define RCANFD_GAFLID(offset, j) ((offset) + (0x10 * (j)))
371 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
372 #define RCANFD_GAFLM(offset, j) ((offset) + 0x04 + (0x10 * (j)))
373 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
374 #define RCANFD_GAFLP0(offset, j) ((offset) + 0x08 + (0x10 * (j)))
375 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
376 #define RCANFD_GAFLP1(offset, j) ((offset) + 0x0c + (0x10 * (j)))
377
378 /* Classical CAN only mode register map */
379
380 /* RSCFDnGAFLXXXj offset */
381 #define RCANFD_C_GAFL_OFFSET (0x0500)
382
383 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
384 #define RCANFD_C_RMID(q) (0x0600 + (0x10 * (q)))
385 #define RCANFD_C_RMPTR(q) (0x0604 + (0x10 * (q)))
386 #define RCANFD_C_RMDF0(q) (0x0608 + (0x10 * (q)))
387 #define RCANFD_C_RMDF1(q) (0x060c + (0x10 * (q)))
388
389 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
390 #define RCANFD_C_RFOFFSET (0x0e00)
391 #define RCANFD_C_RFID(x) (RCANFD_C_RFOFFSET + (0x10 * (x)))
392 #define RCANFD_C_RFPTR(x) (RCANFD_C_RFOFFSET + 0x04 + \
393 (0x10 * (x)))
394 #define RCANFD_C_RFDF(x, df) (RCANFD_C_RFOFFSET + 0x08 + \
395 (0x10 * (x)) + (0x04 * (df)))
396
397 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
398 #define RCANFD_C_CFOFFSET (0x0e80)
399 #define RCANFD_C_CFID(ch, idx) (RCANFD_C_CFOFFSET + (0x30 * (ch)) + \
400 (0x10 * (idx)))
401 #define RCANFD_C_CFPTR(ch, idx) (RCANFD_C_CFOFFSET + 0x04 + \
402 (0x30 * (ch)) + (0x10 * (idx)))
403 #define RCANFD_C_CFDF(ch, idx, df) (RCANFD_C_CFOFFSET + 0x08 + \
404 (0x30 * (ch)) + (0x10 * (idx)) + \
405 (0x04 * (df)))
406
407 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
408 #define RCANFD_C_TMID(p) (0x1000 + (0x10 * (p)))
409 #define RCANFD_C_TMPTR(p) (0x1004 + (0x10 * (p)))
410 #define RCANFD_C_TMDF0(p) (0x1008 + (0x10 * (p)))
411 #define RCANFD_C_TMDF1(p) (0x100c + (0x10 * (p)))
412
413 /* RSCFDnTHLACCm */
414 #define RCANFD_C_THLACC(m) (0x1800 + (0x04 * (m)))
415 /* RSCFDnRPGACCr */
416 #define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
417
418 /* CAN FD mode specific register map */
419
420 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
421 #define RCANFD_F_DCFG(m) (0x0500 + (0x20 * (m)))
422 #define RCANFD_F_CFDCFG(m) (0x0504 + (0x20 * (m)))
423 #define RCANFD_F_CFDCTR(m) (0x0508 + (0x20 * (m)))
424 #define RCANFD_F_CFDSTS(m) (0x050c + (0x20 * (m)))
425 #define RCANFD_F_CFDCRC(m) (0x0510 + (0x20 * (m)))
426
427 /* RSCFDnCFDGAFLXXXj offset */
428 #define RCANFD_F_GAFL_OFFSET (0x1000)
429
430 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
431 #define RCANFD_F_RMID(q) (0x2000 + (0x20 * (q)))
432 #define RCANFD_F_RMPTR(q) (0x2004 + (0x20 * (q)))
433 #define RCANFD_F_RMFDSTS(q) (0x2008 + (0x20 * (q)))
434 #define RCANFD_F_RMDF(q, b) (0x200c + (0x04 * (b)) + (0x20 * (q)))
435
436 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
437 #define RCANFD_F_RFOFFSET (0x3000)
438 #define RCANFD_F_RFID(x) (RCANFD_F_RFOFFSET + (0x80 * (x)))
439 #define RCANFD_F_RFPTR(x) (RCANFD_F_RFOFFSET + 0x04 + \
440 (0x80 * (x)))
441 #define RCANFD_F_RFFDSTS(x) (RCANFD_F_RFOFFSET + 0x08 + \
442 (0x80 * (x)))
443 #define RCANFD_F_RFDF(x, df) (RCANFD_F_RFOFFSET + 0x0c + \
444 (0x80 * (x)) + (0x04 * (df)))
445
446 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
447 #define RCANFD_F_CFOFFSET (0x3400)
448 #define RCANFD_F_CFID(ch, idx) (RCANFD_F_CFOFFSET + (0x180 * (ch)) + \
449 (0x80 * (idx)))
450 #define RCANFD_F_CFPTR(ch, idx) (RCANFD_F_CFOFFSET + 0x04 + \
451 (0x180 * (ch)) + (0x80 * (idx)))
452 #define RCANFD_F_CFFDCSTS(ch, idx) (RCANFD_F_CFOFFSET + 0x08 + \
453 (0x180 * (ch)) + (0x80 * (idx)))
454 #define RCANFD_F_CFDF(ch, idx, df) (RCANFD_F_CFOFFSET + 0x0c + \
455 (0x180 * (ch)) + (0x80 * (idx)) + \
456 (0x04 * (df)))
457
458 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
459 #define RCANFD_F_TMID(p) (0x4000 + (0x20 * (p)))
460 #define RCANFD_F_TMPTR(p) (0x4004 + (0x20 * (p)))
461 #define RCANFD_F_TMFDCTR(p) (0x4008 + (0x20 * (p)))
462 #define RCANFD_F_TMDF(p, b) (0x400c + (0x20 * (p)) + (0x04 * (b)))
463
464 /* RSCFDnCFDTHLACCm */
465 #define RCANFD_F_THLACC(m) (0x6000 + (0x04 * (m)))
466 /* RSCFDnCFDRPGACCr */
467 #define RCANFD_F_RPGACC(r) (0x6400 + (0x04 * (r)))
468
469 /* Constants */
470 #define RCANFD_FIFO_DEPTH 8 /* Tx FIFO depth */
471 #define RCANFD_NAPI_WEIGHT 8 /* Rx poll quota */
472
473 #define RCANFD_NUM_CHANNELS 2 /* Two channels max */
474 #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1)
475
476 #define RCANFD_GAFL_PAGENUM(entry) ((entry) / 16)
477 #define RCANFD_CHANNEL_NUMRULES 1 /* only one rule per channel */
478
479 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
480 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
481 * number is added to RFFIFO index.
482 */
483 #define RCANFD_RFFIFO_IDX 0
484
485 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
486 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
487 */
488 #define RCANFD_CFFIFO_IDX 0
489
490 /* fCAN clock select register settings */
491 enum rcar_canfd_fcanclk {
492 RCANFD_CANFDCLK = 0, /* CANFD clock */
493 RCANFD_EXTCLK, /* Externally input clock */
494 };
495
496 struct rcar_canfd_global;
497
498 /* Channel priv data */
499 struct rcar_canfd_channel {
500 struct can_priv can; /* Must be the first member */
501 struct net_device *ndev;
502 struct rcar_canfd_global *gpriv; /* Controller reference */
503 void __iomem *base; /* Register base address */
504 struct napi_struct napi;
505 u8 tx_len[RCANFD_FIFO_DEPTH]; /* For net stats */
506 u32 tx_head; /* Incremented on xmit */
507 u32 tx_tail; /* Incremented on xmit done */
508 u32 channel; /* Channel number */
509 spinlock_t tx_lock; /* To protect tx path */
510 };
511
512 /* Global priv data */
513 struct rcar_canfd_global {
514 struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
515 void __iomem *base; /* Register base address */
516 struct platform_device *pdev; /* Respective platform device */
517 struct clk *clkp; /* Peripheral clock */
518 struct clk *can_clk; /* fCAN clock */
519 enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
520 unsigned long channels_mask; /* Enabled channels mask */
521 bool fdmode; /* CAN FD or Classical CAN only mode */
522 struct reset_control *rstc1;
523 struct reset_control *rstc2;
524 enum rcanfd_chip_id chip_id;
525 };
526
527 /* CAN FD mode nominal rate constants */
528 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
529 .name = RCANFD_DRV_NAME,
530 .tseg1_min = 2,
531 .tseg1_max = 128,
532 .tseg2_min = 2,
533 .tseg2_max = 32,
534 .sjw_max = 32,
535 .brp_min = 1,
536 .brp_max = 1024,
537 .brp_inc = 1,
538 };
539
540 /* CAN FD mode data rate constants */
541 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
542 .name = RCANFD_DRV_NAME,
543 .tseg1_min = 2,
544 .tseg1_max = 16,
545 .tseg2_min = 2,
546 .tseg2_max = 8,
547 .sjw_max = 8,
548 .brp_min = 1,
549 .brp_max = 256,
550 .brp_inc = 1,
551 };
552
553 /* Classical CAN mode bitrate constants */
554 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
555 .name = RCANFD_DRV_NAME,
556 .tseg1_min = 4,
557 .tseg1_max = 16,
558 .tseg2_min = 2,
559 .tseg2_max = 8,
560 .sjw_max = 4,
561 .brp_min = 1,
562 .brp_max = 1024,
563 .brp_inc = 1,
564 };
565
566 /* Helper functions */
rcar_canfd_update(u32 mask,u32 val,u32 __iomem * reg)567 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
568 {
569 u32 data = readl(reg);
570
571 data &= ~mask;
572 data |= (val & mask);
573 writel(data, reg);
574 }
575
rcar_canfd_read(void __iomem * base,u32 offset)576 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
577 {
578 return readl(base + (offset));
579 }
580
rcar_canfd_write(void __iomem * base,u32 offset,u32 val)581 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
582 {
583 writel(val, base + (offset));
584 }
585
rcar_canfd_set_bit(void __iomem * base,u32 reg,u32 val)586 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
587 {
588 rcar_canfd_update(val, val, base + (reg));
589 }
590
rcar_canfd_clear_bit(void __iomem * base,u32 reg,u32 val)591 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
592 {
593 rcar_canfd_update(val, 0, base + (reg));
594 }
595
rcar_canfd_update_bit(void __iomem * base,u32 reg,u32 mask,u32 val)596 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
597 u32 mask, u32 val)
598 {
599 rcar_canfd_update(mask, val, base + (reg));
600 }
601
rcar_canfd_get_data(struct rcar_canfd_channel * priv,struct canfd_frame * cf,u32 off)602 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
603 struct canfd_frame *cf, u32 off)
604 {
605 u32 i, lwords;
606
607 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
608 for (i = 0; i < lwords; i++)
609 *((u32 *)cf->data + i) =
610 rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
611 }
612
rcar_canfd_put_data(struct rcar_canfd_channel * priv,struct canfd_frame * cf,u32 off)613 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
614 struct canfd_frame *cf, u32 off)
615 {
616 u32 i, lwords;
617
618 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
619 for (i = 0; i < lwords; i++)
620 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
621 *((u32 *)cf->data + i));
622 }
623
rcar_canfd_tx_failure_cleanup(struct net_device * ndev)624 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
625 {
626 u32 i;
627
628 for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
629 can_free_echo_skb(ndev, i, NULL);
630 }
631
rcar_canfd_reset_controller(struct rcar_canfd_global * gpriv)632 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
633 {
634 u32 sts, ch;
635 int err;
636
637 /* Check RAMINIT flag as CAN RAM initialization takes place
638 * after the MCU reset
639 */
640 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
641 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
642 if (err) {
643 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
644 return err;
645 }
646
647 /* Transition to Global Reset mode */
648 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
649 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
650 RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
651
652 /* Ensure Global reset mode */
653 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
654 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
655 if (err) {
656 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
657 return err;
658 }
659
660 /* Reset Global error flags */
661 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
662
663 /* Set the controller into appropriate mode */
664 if (gpriv->fdmode)
665 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
666 RCANFD_GRMCFG_RCMC);
667 else
668 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
669 RCANFD_GRMCFG_RCMC);
670
671 /* Transition all Channels to reset mode */
672 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
673 rcar_canfd_clear_bit(gpriv->base,
674 RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
675
676 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
677 RCANFD_CCTR_CHMDC_MASK,
678 RCANFD_CCTR_CHDMC_CRESET);
679
680 /* Ensure Channel reset mode */
681 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
682 (sts & RCANFD_CSTS_CRSTSTS),
683 2, 500000);
684 if (err) {
685 dev_dbg(&gpriv->pdev->dev,
686 "channel %u reset failed\n", ch);
687 return err;
688 }
689 }
690 return 0;
691 }
692
rcar_canfd_configure_controller(struct rcar_canfd_global * gpriv)693 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
694 {
695 u32 cfg, ch;
696
697 /* Global configuration settings */
698
699 /* ECC Error flag Enable */
700 cfg = RCANFD_GCFG_EEFE;
701
702 if (gpriv->fdmode)
703 /* Truncate payload to configured message size RFPLS */
704 cfg |= RCANFD_GCFG_CMPOC;
705
706 /* Set External Clock if selected */
707 if (gpriv->fcan != RCANFD_CANFDCLK)
708 cfg |= RCANFD_GCFG_DCS;
709
710 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
711
712 /* Channel configuration settings */
713 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
714 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
715 RCANFD_CCTR_ERRD);
716 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
717 RCANFD_CCTR_BOM_MASK,
718 RCANFD_CCTR_BOM_BENTRY);
719 }
720 }
721
rcar_canfd_configure_afl_rules(struct rcar_canfd_global * gpriv,u32 ch)722 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
723 u32 ch)
724 {
725 u32 cfg;
726 int offset, start, page, num_rules = RCANFD_CHANNEL_NUMRULES;
727 u32 ridx = ch + RCANFD_RFFIFO_IDX;
728
729 if (ch == 0) {
730 start = 0; /* Channel 0 always starts from 0th rule */
731 } else {
732 /* Get number of Channel 0 rules and adjust */
733 cfg = rcar_canfd_read(gpriv->base, RCANFD_GAFLCFG0);
734 start = RCANFD_GAFLCFG_GETRNC(0, cfg);
735 }
736
737 /* Enable write access to entry */
738 page = RCANFD_GAFL_PAGENUM(start);
739 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
740 (RCANFD_GAFLECTR_AFLPN(page) |
741 RCANFD_GAFLECTR_AFLDAE));
742
743 /* Write number of rules for channel */
744 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG0,
745 RCANFD_GAFLCFG_SETRNC(ch, num_rules));
746 if (gpriv->fdmode)
747 offset = RCANFD_F_GAFL_OFFSET;
748 else
749 offset = RCANFD_C_GAFL_OFFSET;
750
751 /* Accept all IDs */
752 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, start), 0);
753 /* IDE or RTR is not considered for matching */
754 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, start), 0);
755 /* Any data length accepted */
756 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, start), 0);
757 /* Place the msg in corresponding Rx FIFO entry */
758 rcar_canfd_write(gpriv->base, RCANFD_GAFLP1(offset, start),
759 RCANFD_GAFLP1_GAFLFDP(ridx));
760
761 /* Disable write access to page */
762 rcar_canfd_clear_bit(gpriv->base,
763 RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
764 }
765
rcar_canfd_configure_rx(struct rcar_canfd_global * gpriv,u32 ch)766 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
767 {
768 /* Rx FIFO is used for reception */
769 u32 cfg;
770 u16 rfdc, rfpls;
771
772 /* Select Rx FIFO based on channel */
773 u32 ridx = ch + RCANFD_RFFIFO_IDX;
774
775 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
776 if (gpriv->fdmode)
777 rfpls = 7; /* b111 - Max 64 bytes payload */
778 else
779 rfpls = 0; /* b000 - Max 8 bytes payload */
780
781 cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
782 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
783 rcar_canfd_write(gpriv->base, RCANFD_RFCC(ridx), cfg);
784 }
785
rcar_canfd_configure_tx(struct rcar_canfd_global * gpriv,u32 ch)786 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
787 {
788 /* Tx/Rx(Common) FIFO configured in Tx mode is
789 * used for transmission
790 *
791 * Each channel has 3 Common FIFO dedicated to them.
792 * Use the 1st (index 0) out of 3
793 */
794 u32 cfg;
795 u16 cftml, cfm, cfdc, cfpls;
796
797 cftml = 0; /* 0th buffer */
798 cfm = 1; /* b01 - Transmit mode */
799 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
800 if (gpriv->fdmode)
801 cfpls = 7; /* b111 - Max 64 bytes payload */
802 else
803 cfpls = 0; /* b000 - Max 8 bytes payload */
804
805 cfg = (RCANFD_CFCC_CFTML(cftml) | RCANFD_CFCC_CFM(cfm) |
806 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(cfdc) |
807 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
808 rcar_canfd_write(gpriv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX), cfg);
809
810 if (gpriv->fdmode)
811 /* Clear FD mode specific control/status register */
812 rcar_canfd_write(gpriv->base,
813 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), 0);
814 }
815
rcar_canfd_enable_global_interrupts(struct rcar_canfd_global * gpriv)816 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
817 {
818 u32 ctr;
819
820 /* Clear any stray error interrupt flags */
821 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
822
823 /* Global interrupts setup */
824 ctr = RCANFD_GCTR_MEIE;
825 if (gpriv->fdmode)
826 ctr |= RCANFD_GCTR_CFMPOFIE;
827
828 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
829 }
830
rcar_canfd_disable_global_interrupts(struct rcar_canfd_global * gpriv)831 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
832 *gpriv)
833 {
834 /* Disable all interrupts */
835 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
836
837 /* Clear any stray error interrupt flags */
838 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
839 }
840
rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel * priv)841 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
842 *priv)
843 {
844 u32 ctr, ch = priv->channel;
845
846 /* Clear any stray error flags */
847 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
848
849 /* Channel interrupts setup */
850 ctr = (RCANFD_CCTR_TAIE |
851 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
852 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
853 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
854 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
855 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
856 }
857
rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel * priv)858 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
859 *priv)
860 {
861 u32 ctr, ch = priv->channel;
862
863 ctr = (RCANFD_CCTR_TAIE |
864 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
865 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
866 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
867 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
868 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
869
870 /* Clear any stray error flags */
871 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
872 }
873
rcar_canfd_global_error(struct net_device * ndev)874 static void rcar_canfd_global_error(struct net_device *ndev)
875 {
876 struct rcar_canfd_channel *priv = netdev_priv(ndev);
877 struct rcar_canfd_global *gpriv = priv->gpriv;
878 struct net_device_stats *stats = &ndev->stats;
879 u32 ch = priv->channel;
880 u32 gerfl, sts;
881 u32 ridx = ch + RCANFD_RFFIFO_IDX;
882
883 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
884 if ((gerfl & RCANFD_GERFL_EEF0) && (ch == 0)) {
885 netdev_dbg(ndev, "Ch0: ECC Error flag\n");
886 stats->tx_dropped++;
887 }
888 if ((gerfl & RCANFD_GERFL_EEF1) && (ch == 1)) {
889 netdev_dbg(ndev, "Ch1: ECC Error flag\n");
890 stats->tx_dropped++;
891 }
892 if (gerfl & RCANFD_GERFL_MES) {
893 sts = rcar_canfd_read(priv->base,
894 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
895 if (sts & RCANFD_CFSTS_CFMLT) {
896 netdev_dbg(ndev, "Tx Message Lost flag\n");
897 stats->tx_dropped++;
898 rcar_canfd_write(priv->base,
899 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
900 sts & ~RCANFD_CFSTS_CFMLT);
901 }
902
903 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
904 if (sts & RCANFD_RFSTS_RFMLT) {
905 netdev_dbg(ndev, "Rx Message Lost flag\n");
906 stats->rx_dropped++;
907 rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
908 sts & ~RCANFD_RFSTS_RFMLT);
909 }
910 }
911 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
912 /* Message Lost flag will be set for respective channel
913 * when this condition happens with counters and flags
914 * already updated.
915 */
916 netdev_dbg(ndev, "global payload overflow interrupt\n");
917 }
918
919 /* Clear all global error interrupts. Only affected channels bits
920 * get cleared
921 */
922 rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
923 }
924
rcar_canfd_error(struct net_device * ndev,u32 cerfl,u16 txerr,u16 rxerr)925 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
926 u16 txerr, u16 rxerr)
927 {
928 struct rcar_canfd_channel *priv = netdev_priv(ndev);
929 struct net_device_stats *stats = &ndev->stats;
930 struct can_frame *cf;
931 struct sk_buff *skb;
932 u32 ch = priv->channel;
933
934 netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
935
936 /* Propagate the error condition to the CAN stack */
937 skb = alloc_can_err_skb(ndev, &cf);
938 if (!skb) {
939 stats->rx_dropped++;
940 return;
941 }
942
943 /* Channel error interrupts */
944 if (cerfl & RCANFD_CERFL_BEF) {
945 netdev_dbg(ndev, "Bus error\n");
946 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
947 cf->data[2] = CAN_ERR_PROT_UNSPEC;
948 priv->can.can_stats.bus_error++;
949 }
950 if (cerfl & RCANFD_CERFL_ADERR) {
951 netdev_dbg(ndev, "ACK Delimiter Error\n");
952 stats->tx_errors++;
953 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
954 }
955 if (cerfl & RCANFD_CERFL_B0ERR) {
956 netdev_dbg(ndev, "Bit Error (dominant)\n");
957 stats->tx_errors++;
958 cf->data[2] |= CAN_ERR_PROT_BIT0;
959 }
960 if (cerfl & RCANFD_CERFL_B1ERR) {
961 netdev_dbg(ndev, "Bit Error (recessive)\n");
962 stats->tx_errors++;
963 cf->data[2] |= CAN_ERR_PROT_BIT1;
964 }
965 if (cerfl & RCANFD_CERFL_CERR) {
966 netdev_dbg(ndev, "CRC Error\n");
967 stats->rx_errors++;
968 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
969 }
970 if (cerfl & RCANFD_CERFL_AERR) {
971 netdev_dbg(ndev, "ACK Error\n");
972 stats->tx_errors++;
973 cf->can_id |= CAN_ERR_ACK;
974 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
975 }
976 if (cerfl & RCANFD_CERFL_FERR) {
977 netdev_dbg(ndev, "Form Error\n");
978 stats->rx_errors++;
979 cf->data[2] |= CAN_ERR_PROT_FORM;
980 }
981 if (cerfl & RCANFD_CERFL_SERR) {
982 netdev_dbg(ndev, "Stuff Error\n");
983 stats->rx_errors++;
984 cf->data[2] |= CAN_ERR_PROT_STUFF;
985 }
986 if (cerfl & RCANFD_CERFL_ALF) {
987 netdev_dbg(ndev, "Arbitration lost Error\n");
988 priv->can.can_stats.arbitration_lost++;
989 cf->can_id |= CAN_ERR_LOSTARB;
990 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
991 }
992 if (cerfl & RCANFD_CERFL_BLF) {
993 netdev_dbg(ndev, "Bus Lock Error\n");
994 stats->rx_errors++;
995 cf->can_id |= CAN_ERR_BUSERROR;
996 }
997 if (cerfl & RCANFD_CERFL_EWF) {
998 netdev_dbg(ndev, "Error warning interrupt\n");
999 priv->can.state = CAN_STATE_ERROR_WARNING;
1000 priv->can.can_stats.error_warning++;
1001 cf->can_id |= CAN_ERR_CRTL;
1002 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1003 CAN_ERR_CRTL_RX_WARNING;
1004 cf->data[6] = txerr;
1005 cf->data[7] = rxerr;
1006 }
1007 if (cerfl & RCANFD_CERFL_EPF) {
1008 netdev_dbg(ndev, "Error passive interrupt\n");
1009 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1010 priv->can.can_stats.error_passive++;
1011 cf->can_id |= CAN_ERR_CRTL;
1012 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1013 CAN_ERR_CRTL_RX_PASSIVE;
1014 cf->data[6] = txerr;
1015 cf->data[7] = rxerr;
1016 }
1017 if (cerfl & RCANFD_CERFL_BOEF) {
1018 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1019 rcar_canfd_tx_failure_cleanup(ndev);
1020 priv->can.state = CAN_STATE_BUS_OFF;
1021 priv->can.can_stats.bus_off++;
1022 can_bus_off(ndev);
1023 cf->can_id |= CAN_ERR_BUSOFF;
1024 }
1025 if (cerfl & RCANFD_CERFL_OVLF) {
1026 netdev_dbg(ndev,
1027 "Overload Frame Transmission error interrupt\n");
1028 stats->tx_errors++;
1029 cf->can_id |= CAN_ERR_PROT;
1030 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1031 }
1032
1033 /* Clear channel error interrupts that are handled */
1034 rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1035 RCANFD_CERFL_ERR(~cerfl));
1036 stats->rx_packets++;
1037 stats->rx_bytes += cf->len;
1038 netif_rx(skb);
1039 }
1040
rcar_canfd_tx_done(struct net_device * ndev)1041 static void rcar_canfd_tx_done(struct net_device *ndev)
1042 {
1043 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1044 struct net_device_stats *stats = &ndev->stats;
1045 u32 sts;
1046 unsigned long flags;
1047 u32 ch = priv->channel;
1048
1049 do {
1050 u8 unsent, sent;
1051
1052 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1053 stats->tx_packets++;
1054 stats->tx_bytes += priv->tx_len[sent];
1055 priv->tx_len[sent] = 0;
1056 can_get_echo_skb(ndev, sent, NULL);
1057
1058 spin_lock_irqsave(&priv->tx_lock, flags);
1059 priv->tx_tail++;
1060 sts = rcar_canfd_read(priv->base,
1061 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1062 unsent = RCANFD_CFSTS_CFMC(sts);
1063
1064 /* Wake producer only when there is room */
1065 if (unsent != RCANFD_FIFO_DEPTH)
1066 netif_wake_queue(ndev);
1067
1068 if (priv->tx_head - priv->tx_tail <= unsent) {
1069 spin_unlock_irqrestore(&priv->tx_lock, flags);
1070 break;
1071 }
1072 spin_unlock_irqrestore(&priv->tx_lock, flags);
1073
1074 } while (1);
1075
1076 /* Clear interrupt */
1077 rcar_canfd_write(priv->base, RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX),
1078 sts & ~RCANFD_CFSTS_CFTXIF);
1079 can_led_event(ndev, CAN_LED_EVENT_TX);
1080 }
1081
rcar_canfd_handle_global_err(struct rcar_canfd_global * gpriv,u32 ch)1082 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1083 {
1084 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1085 struct net_device *ndev = priv->ndev;
1086 u32 gerfl;
1087
1088 /* Handle global error interrupts */
1089 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1090 if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1091 rcar_canfd_global_error(ndev);
1092 }
1093
rcar_canfd_global_err_interrupt(int irq,void * dev_id)1094 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1095 {
1096 struct rcar_canfd_global *gpriv = dev_id;
1097 u32 ch;
1098
1099 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1100 rcar_canfd_handle_global_err(gpriv, ch);
1101
1102 return IRQ_HANDLED;
1103 }
1104
rcar_canfd_handle_global_receive(struct rcar_canfd_global * gpriv,u32 ch)1105 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1106 {
1107 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1108 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1109 u32 sts, cc;
1110
1111 /* Handle Rx interrupts */
1112 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1113 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(ridx));
1114 if (likely(sts & RCANFD_RFSTS_RFIF &&
1115 cc & RCANFD_RFCC_RFIE)) {
1116 if (napi_schedule_prep(&priv->napi)) {
1117 /* Disable Rx FIFO interrupts */
1118 rcar_canfd_clear_bit(priv->base,
1119 RCANFD_RFCC(ridx),
1120 RCANFD_RFCC_RFIE);
1121 __napi_schedule(&priv->napi);
1122 }
1123 }
1124 }
1125
rcar_canfd_global_receive_fifo_interrupt(int irq,void * dev_id)1126 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1127 {
1128 struct rcar_canfd_global *gpriv = dev_id;
1129 u32 ch;
1130
1131 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1132 rcar_canfd_handle_global_receive(gpriv, ch);
1133
1134 return IRQ_HANDLED;
1135 }
1136
rcar_canfd_global_interrupt(int irq,void * dev_id)1137 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1138 {
1139 struct rcar_canfd_global *gpriv = dev_id;
1140 u32 ch;
1141
1142 /* Global error interrupts still indicate a condition specific
1143 * to a channel. RxFIFO interrupt is a global interrupt.
1144 */
1145 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1146 rcar_canfd_handle_global_err(gpriv, ch);
1147 rcar_canfd_handle_global_receive(gpriv, ch);
1148 }
1149 return IRQ_HANDLED;
1150 }
1151
rcar_canfd_state_change(struct net_device * ndev,u16 txerr,u16 rxerr)1152 static void rcar_canfd_state_change(struct net_device *ndev,
1153 u16 txerr, u16 rxerr)
1154 {
1155 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1156 struct net_device_stats *stats = &ndev->stats;
1157 enum can_state rx_state, tx_state, state = priv->can.state;
1158 struct can_frame *cf;
1159 struct sk_buff *skb;
1160
1161 /* Handle transition from error to normal states */
1162 if (txerr < 96 && rxerr < 96)
1163 state = CAN_STATE_ERROR_ACTIVE;
1164 else if (txerr < 128 && rxerr < 128)
1165 state = CAN_STATE_ERROR_WARNING;
1166
1167 if (state != priv->can.state) {
1168 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1169 state, priv->can.state, txerr, rxerr);
1170 skb = alloc_can_err_skb(ndev, &cf);
1171 if (!skb) {
1172 stats->rx_dropped++;
1173 return;
1174 }
1175 tx_state = txerr >= rxerr ? state : 0;
1176 rx_state = txerr <= rxerr ? state : 0;
1177
1178 can_change_state(ndev, cf, tx_state, rx_state);
1179 stats->rx_packets++;
1180 stats->rx_bytes += cf->len;
1181 netif_rx(skb);
1182 }
1183 }
1184
rcar_canfd_handle_channel_tx(struct rcar_canfd_global * gpriv,u32 ch)1185 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1186 {
1187 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1188 struct net_device *ndev = priv->ndev;
1189 u32 sts;
1190
1191 /* Handle Tx interrupts */
1192 sts = rcar_canfd_read(priv->base,
1193 RCANFD_CFSTS(ch, RCANFD_CFFIFO_IDX));
1194 if (likely(sts & RCANFD_CFSTS_CFTXIF))
1195 rcar_canfd_tx_done(ndev);
1196 }
1197
rcar_canfd_channel_tx_interrupt(int irq,void * dev_id)1198 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1199 {
1200 struct rcar_canfd_channel *priv = dev_id;
1201
1202 rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1203
1204 return IRQ_HANDLED;
1205 }
1206
rcar_canfd_handle_channel_err(struct rcar_canfd_global * gpriv,u32 ch)1207 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1208 {
1209 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1210 struct net_device *ndev = priv->ndev;
1211 u16 txerr, rxerr;
1212 u32 sts, cerfl;
1213
1214 /* Handle channel error interrupts */
1215 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1216 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1217 txerr = RCANFD_CSTS_TECCNT(sts);
1218 rxerr = RCANFD_CSTS_RECCNT(sts);
1219 if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1220 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1221
1222 /* Handle state change to lower states */
1223 if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1224 priv->can.state != CAN_STATE_BUS_OFF))
1225 rcar_canfd_state_change(ndev, txerr, rxerr);
1226 }
1227
rcar_canfd_channel_err_interrupt(int irq,void * dev_id)1228 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1229 {
1230 struct rcar_canfd_channel *priv = dev_id;
1231
1232 rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1233
1234 return IRQ_HANDLED;
1235 }
1236
rcar_canfd_channel_interrupt(int irq,void * dev_id)1237 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1238 {
1239 struct rcar_canfd_global *gpriv = dev_id;
1240 u32 ch;
1241
1242 /* Common FIFO is a per channel resource */
1243 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1244 rcar_canfd_handle_channel_err(gpriv, ch);
1245 rcar_canfd_handle_channel_tx(gpriv, ch);
1246 }
1247
1248 return IRQ_HANDLED;
1249 }
1250
rcar_canfd_set_bittiming(struct net_device * dev)1251 static void rcar_canfd_set_bittiming(struct net_device *dev)
1252 {
1253 struct rcar_canfd_channel *priv = netdev_priv(dev);
1254 const struct can_bittiming *bt = &priv->can.bittiming;
1255 const struct can_bittiming *dbt = &priv->can.data_bittiming;
1256 u16 brp, sjw, tseg1, tseg2;
1257 u32 cfg;
1258 u32 ch = priv->channel;
1259
1260 /* Nominal bit timing settings */
1261 brp = bt->brp - 1;
1262 sjw = bt->sjw - 1;
1263 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1264 tseg2 = bt->phase_seg2 - 1;
1265
1266 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1267 /* CAN FD only mode */
1268 cfg = (RCANFD_NCFG_NTSEG1(tseg1) | RCANFD_NCFG_NBRP(brp) |
1269 RCANFD_NCFG_NSJW(sjw) | RCANFD_NCFG_NTSEG2(tseg2));
1270
1271 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1272 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1273 brp, sjw, tseg1, tseg2);
1274
1275 /* Data bit timing settings */
1276 brp = dbt->brp - 1;
1277 sjw = dbt->sjw - 1;
1278 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1279 tseg2 = dbt->phase_seg2 - 1;
1280
1281 cfg = (RCANFD_DCFG_DTSEG1(tseg1) | RCANFD_DCFG_DBRP(brp) |
1282 RCANFD_DCFG_DSJW(sjw) | RCANFD_DCFG_DTSEG2(tseg2));
1283
1284 rcar_canfd_write(priv->base, RCANFD_F_DCFG(ch), cfg);
1285 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1286 brp, sjw, tseg1, tseg2);
1287 } else {
1288 /* Classical CAN only mode */
1289 cfg = (RCANFD_CFG_TSEG1(tseg1) | RCANFD_CFG_BRP(brp) |
1290 RCANFD_CFG_SJW(sjw) | RCANFD_CFG_TSEG2(tseg2));
1291
1292 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1293 netdev_dbg(priv->ndev,
1294 "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1295 brp, sjw, tseg1, tseg2);
1296 }
1297 }
1298
rcar_canfd_start(struct net_device * ndev)1299 static int rcar_canfd_start(struct net_device *ndev)
1300 {
1301 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1302 int err = -EOPNOTSUPP;
1303 u32 sts, ch = priv->channel;
1304 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1305
1306 rcar_canfd_set_bittiming(ndev);
1307
1308 rcar_canfd_enable_channel_interrupts(priv);
1309
1310 /* Set channel to Operational mode */
1311 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1312 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1313
1314 /* Verify channel mode change */
1315 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1316 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1317 if (err) {
1318 netdev_err(ndev, "channel %u communication state failed\n", ch);
1319 goto fail_mode_change;
1320 }
1321
1322 /* Enable Common & Rx FIFO */
1323 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1324 RCANFD_CFCC_CFE);
1325 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1326
1327 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1328 return 0;
1329
1330 fail_mode_change:
1331 rcar_canfd_disable_channel_interrupts(priv);
1332 return err;
1333 }
1334
rcar_canfd_open(struct net_device * ndev)1335 static int rcar_canfd_open(struct net_device *ndev)
1336 {
1337 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1338 struct rcar_canfd_global *gpriv = priv->gpriv;
1339 int err;
1340
1341 /* Peripheral clock is already enabled in probe */
1342 err = clk_prepare_enable(gpriv->can_clk);
1343 if (err) {
1344 netdev_err(ndev, "failed to enable CAN clock, error %d\n", err);
1345 goto out_clock;
1346 }
1347
1348 err = open_candev(ndev);
1349 if (err) {
1350 netdev_err(ndev, "open_candev() failed, error %d\n", err);
1351 goto out_can_clock;
1352 }
1353
1354 napi_enable(&priv->napi);
1355 err = rcar_canfd_start(ndev);
1356 if (err)
1357 goto out_close;
1358 netif_start_queue(ndev);
1359 can_led_event(ndev, CAN_LED_EVENT_OPEN);
1360 return 0;
1361 out_close:
1362 napi_disable(&priv->napi);
1363 close_candev(ndev);
1364 out_can_clock:
1365 clk_disable_unprepare(gpriv->can_clk);
1366 out_clock:
1367 return err;
1368 }
1369
rcar_canfd_stop(struct net_device * ndev)1370 static void rcar_canfd_stop(struct net_device *ndev)
1371 {
1372 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1373 int err;
1374 u32 sts, ch = priv->channel;
1375 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1376
1377 /* Transition to channel reset mode */
1378 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1379 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1380
1381 /* Check Channel reset mode */
1382 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1383 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1384 if (err)
1385 netdev_err(ndev, "channel %u reset failed\n", ch);
1386
1387 rcar_canfd_disable_channel_interrupts(priv);
1388
1389 /* Disable Common & Rx FIFO */
1390 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(ch, RCANFD_CFFIFO_IDX),
1391 RCANFD_CFCC_CFE);
1392 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(ridx), RCANFD_RFCC_RFE);
1393
1394 /* Set the state as STOPPED */
1395 priv->can.state = CAN_STATE_STOPPED;
1396 }
1397
rcar_canfd_close(struct net_device * ndev)1398 static int rcar_canfd_close(struct net_device *ndev)
1399 {
1400 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1401 struct rcar_canfd_global *gpriv = priv->gpriv;
1402
1403 netif_stop_queue(ndev);
1404 rcar_canfd_stop(ndev);
1405 napi_disable(&priv->napi);
1406 clk_disable_unprepare(gpriv->can_clk);
1407 close_candev(ndev);
1408 can_led_event(ndev, CAN_LED_EVENT_STOP);
1409 return 0;
1410 }
1411
rcar_canfd_start_xmit(struct sk_buff * skb,struct net_device * ndev)1412 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1413 struct net_device *ndev)
1414 {
1415 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1416 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1417 u32 sts = 0, id, dlc;
1418 unsigned long flags;
1419 u32 ch = priv->channel;
1420
1421 if (can_dropped_invalid_skb(ndev, skb))
1422 return NETDEV_TX_OK;
1423
1424 if (cf->can_id & CAN_EFF_FLAG) {
1425 id = cf->can_id & CAN_EFF_MASK;
1426 id |= RCANFD_CFID_CFIDE;
1427 } else {
1428 id = cf->can_id & CAN_SFF_MASK;
1429 }
1430
1431 if (cf->can_id & CAN_RTR_FLAG)
1432 id |= RCANFD_CFID_CFRTR;
1433
1434 dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1435
1436 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1437 rcar_canfd_write(priv->base,
1438 RCANFD_F_CFID(ch, RCANFD_CFFIFO_IDX), id);
1439 rcar_canfd_write(priv->base,
1440 RCANFD_F_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1441
1442 if (can_is_canfd_skb(skb)) {
1443 /* CAN FD frame format */
1444 sts |= RCANFD_CFFDCSTS_CFFDF;
1445 if (cf->flags & CANFD_BRS)
1446 sts |= RCANFD_CFFDCSTS_CFBRS;
1447
1448 if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1449 sts |= RCANFD_CFFDCSTS_CFESI;
1450 }
1451
1452 rcar_canfd_write(priv->base,
1453 RCANFD_F_CFFDCSTS(ch, RCANFD_CFFIFO_IDX), sts);
1454
1455 rcar_canfd_put_data(priv, cf,
1456 RCANFD_F_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1457 } else {
1458 rcar_canfd_write(priv->base,
1459 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1460 rcar_canfd_write(priv->base,
1461 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1462 rcar_canfd_put_data(priv, cf,
1463 RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1464 }
1465
1466 priv->tx_len[priv->tx_head % RCANFD_FIFO_DEPTH] = cf->len;
1467 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1468
1469 spin_lock_irqsave(&priv->tx_lock, flags);
1470 priv->tx_head++;
1471
1472 /* Stop the queue if we've filled all FIFO entries */
1473 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1474 netif_stop_queue(ndev);
1475
1476 /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1477 * pointer for the Common FIFO
1478 */
1479 rcar_canfd_write(priv->base,
1480 RCANFD_CFPCTR(ch, RCANFD_CFFIFO_IDX), 0xff);
1481
1482 spin_unlock_irqrestore(&priv->tx_lock, flags);
1483 return NETDEV_TX_OK;
1484 }
1485
rcar_canfd_rx_pkt(struct rcar_canfd_channel * priv)1486 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1487 {
1488 struct net_device_stats *stats = &priv->ndev->stats;
1489 struct canfd_frame *cf;
1490 struct sk_buff *skb;
1491 u32 sts = 0, id, dlc;
1492 u32 ch = priv->channel;
1493 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1494
1495 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1496 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(ridx));
1497 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(ridx));
1498
1499 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(ridx));
1500 if (sts & RCANFD_RFFDSTS_RFFDF)
1501 skb = alloc_canfd_skb(priv->ndev, &cf);
1502 else
1503 skb = alloc_can_skb(priv->ndev,
1504 (struct can_frame **)&cf);
1505 } else {
1506 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1507 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1508 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1509 }
1510
1511 if (!skb) {
1512 stats->rx_dropped++;
1513 return;
1514 }
1515
1516 if (id & RCANFD_RFID_RFIDE)
1517 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1518 else
1519 cf->can_id = id & CAN_SFF_MASK;
1520
1521 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1522 if (sts & RCANFD_RFFDSTS_RFFDF)
1523 cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1524 else
1525 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1526
1527 if (sts & RCANFD_RFFDSTS_RFESI) {
1528 cf->flags |= CANFD_ESI;
1529 netdev_dbg(priv->ndev, "ESI Error\n");
1530 }
1531
1532 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1533 cf->can_id |= CAN_RTR_FLAG;
1534 } else {
1535 if (sts & RCANFD_RFFDSTS_RFBRS)
1536 cf->flags |= CANFD_BRS;
1537
1538 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(ridx, 0));
1539 }
1540 } else {
1541 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1542 if (id & RCANFD_RFID_RFRTR)
1543 cf->can_id |= CAN_RTR_FLAG;
1544 else
1545 rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1546 }
1547
1548 /* Write 0xff to RFPC to increment the CPU-side
1549 * pointer of the Rx FIFO
1550 */
1551 rcar_canfd_write(priv->base, RCANFD_RFPCTR(ridx), 0xff);
1552
1553 can_led_event(priv->ndev, CAN_LED_EVENT_RX);
1554
1555 stats->rx_bytes += cf->len;
1556 stats->rx_packets++;
1557 netif_receive_skb(skb);
1558 }
1559
rcar_canfd_rx_poll(struct napi_struct * napi,int quota)1560 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1561 {
1562 struct rcar_canfd_channel *priv =
1563 container_of(napi, struct rcar_canfd_channel, napi);
1564 int num_pkts;
1565 u32 sts;
1566 u32 ch = priv->channel;
1567 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1568
1569 for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1570 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(ridx));
1571 /* Check FIFO empty condition */
1572 if (sts & RCANFD_RFSTS_RFEMP)
1573 break;
1574
1575 rcar_canfd_rx_pkt(priv);
1576
1577 /* Clear interrupt bit */
1578 if (sts & RCANFD_RFSTS_RFIF)
1579 rcar_canfd_write(priv->base, RCANFD_RFSTS(ridx),
1580 sts & ~RCANFD_RFSTS_RFIF);
1581 }
1582
1583 /* All packets processed */
1584 if (num_pkts < quota) {
1585 if (napi_complete_done(napi, num_pkts)) {
1586 /* Enable Rx FIFO interrupts */
1587 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(ridx),
1588 RCANFD_RFCC_RFIE);
1589 }
1590 }
1591 return num_pkts;
1592 }
1593
rcar_canfd_do_set_mode(struct net_device * ndev,enum can_mode mode)1594 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1595 {
1596 int err;
1597
1598 switch (mode) {
1599 case CAN_MODE_START:
1600 err = rcar_canfd_start(ndev);
1601 if (err)
1602 return err;
1603 netif_wake_queue(ndev);
1604 return 0;
1605 default:
1606 return -EOPNOTSUPP;
1607 }
1608 }
1609
rcar_canfd_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)1610 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1611 struct can_berr_counter *bec)
1612 {
1613 struct rcar_canfd_channel *priv = netdev_priv(dev);
1614 u32 val, ch = priv->channel;
1615
1616 /* Peripheral clock is already enabled in probe */
1617 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1618 bec->txerr = RCANFD_CSTS_TECCNT(val);
1619 bec->rxerr = RCANFD_CSTS_RECCNT(val);
1620 return 0;
1621 }
1622
1623 static const struct net_device_ops rcar_canfd_netdev_ops = {
1624 .ndo_open = rcar_canfd_open,
1625 .ndo_stop = rcar_canfd_close,
1626 .ndo_start_xmit = rcar_canfd_start_xmit,
1627 .ndo_change_mtu = can_change_mtu,
1628 };
1629
rcar_canfd_channel_probe(struct rcar_canfd_global * gpriv,u32 ch,u32 fcan_freq)1630 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1631 u32 fcan_freq)
1632 {
1633 struct platform_device *pdev = gpriv->pdev;
1634 struct rcar_canfd_channel *priv;
1635 struct net_device *ndev;
1636 int err = -ENODEV;
1637
1638 ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1639 if (!ndev) {
1640 dev_err(&pdev->dev, "alloc_candev() failed\n");
1641 return -ENOMEM;
1642 }
1643 priv = netdev_priv(ndev);
1644
1645 ndev->netdev_ops = &rcar_canfd_netdev_ops;
1646 ndev->flags |= IFF_ECHO;
1647 priv->ndev = ndev;
1648 priv->base = gpriv->base;
1649 priv->channel = ch;
1650 priv->gpriv = gpriv;
1651 priv->can.clock.freq = fcan_freq;
1652 dev_info(&pdev->dev, "can_clk rate is %u\n", priv->can.clock.freq);
1653
1654 if (gpriv->chip_id == RENESAS_RZG2L) {
1655 char *irq_name;
1656 int err_irq;
1657 int tx_irq;
1658
1659 err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1660 if (err_irq < 0) {
1661 err = err_irq;
1662 goto fail;
1663 }
1664
1665 tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1666 if (tx_irq < 0) {
1667 err = tx_irq;
1668 goto fail;
1669 }
1670
1671 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1672 "canfd.ch%d_err", ch);
1673 if (!irq_name) {
1674 err = -ENOMEM;
1675 goto fail;
1676 }
1677 err = devm_request_irq(&pdev->dev, err_irq,
1678 rcar_canfd_channel_err_interrupt, 0,
1679 irq_name, priv);
1680 if (err) {
1681 dev_err(&pdev->dev, "devm_request_irq CH Err(%d) failed, error %d\n",
1682 err_irq, err);
1683 goto fail;
1684 }
1685 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
1686 "canfd.ch%d_trx", ch);
1687 if (!irq_name) {
1688 err = -ENOMEM;
1689 goto fail;
1690 }
1691 err = devm_request_irq(&pdev->dev, tx_irq,
1692 rcar_canfd_channel_tx_interrupt, 0,
1693 irq_name, priv);
1694 if (err) {
1695 dev_err(&pdev->dev, "devm_request_irq Tx (%d) failed, error %d\n",
1696 tx_irq, err);
1697 goto fail;
1698 }
1699 }
1700
1701 if (gpriv->fdmode) {
1702 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1703 priv->can.data_bittiming_const =
1704 &rcar_canfd_data_bittiming_const;
1705
1706 /* Controller starts in CAN FD only mode */
1707 can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1708 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1709 } else {
1710 /* Controller starts in Classical CAN only mode */
1711 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1712 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1713 }
1714
1715 priv->can.do_set_mode = rcar_canfd_do_set_mode;
1716 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1717 SET_NETDEV_DEV(ndev, &pdev->dev);
1718
1719 netif_napi_add(ndev, &priv->napi, rcar_canfd_rx_poll,
1720 RCANFD_NAPI_WEIGHT);
1721 spin_lock_init(&priv->tx_lock);
1722 devm_can_led_init(ndev);
1723 gpriv->ch[priv->channel] = priv;
1724 err = register_candev(ndev);
1725 if (err) {
1726 dev_err(&pdev->dev,
1727 "register_candev() failed, error %d\n", err);
1728 goto fail_candev;
1729 }
1730 dev_info(&pdev->dev, "device registered (channel %u)\n", priv->channel);
1731 return 0;
1732
1733 fail_candev:
1734 netif_napi_del(&priv->napi);
1735 fail:
1736 free_candev(ndev);
1737 return err;
1738 }
1739
rcar_canfd_channel_remove(struct rcar_canfd_global * gpriv,u32 ch)1740 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1741 {
1742 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1743
1744 if (priv) {
1745 unregister_candev(priv->ndev);
1746 netif_napi_del(&priv->napi);
1747 free_candev(priv->ndev);
1748 }
1749 }
1750
rcar_canfd_probe(struct platform_device * pdev)1751 static int rcar_canfd_probe(struct platform_device *pdev)
1752 {
1753 void __iomem *addr;
1754 u32 sts, ch, fcan_freq;
1755 struct rcar_canfd_global *gpriv;
1756 struct device_node *of_child;
1757 unsigned long channels_mask = 0;
1758 int err, ch_irq, g_irq;
1759 int g_err_irq, g_recc_irq;
1760 bool fdmode = true; /* CAN FD only mode - default */
1761 enum rcanfd_chip_id chip_id;
1762
1763 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1764
1765 if (of_property_read_bool(pdev->dev.of_node, "renesas,no-can-fd"))
1766 fdmode = false; /* Classical CAN only mode */
1767
1768 of_child = of_get_child_by_name(pdev->dev.of_node, "channel0");
1769 if (of_child && of_device_is_available(of_child))
1770 channels_mask |= BIT(0); /* Channel 0 */
1771
1772 of_child = of_get_child_by_name(pdev->dev.of_node, "channel1");
1773 if (of_child && of_device_is_available(of_child))
1774 channels_mask |= BIT(1); /* Channel 1 */
1775
1776 if (chip_id == RENESAS_RCAR_GEN3) {
1777 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1778 if (ch_irq < 0) {
1779 /* For backward compatibility get irq by index */
1780 ch_irq = platform_get_irq(pdev, 0);
1781 if (ch_irq < 0)
1782 return ch_irq;
1783 }
1784
1785 g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1786 if (g_irq < 0) {
1787 /* For backward compatibility get irq by index */
1788 g_irq = platform_get_irq(pdev, 1);
1789 if (g_irq < 0)
1790 return g_irq;
1791 }
1792 } else {
1793 g_err_irq = platform_get_irq_byname(pdev, "g_err");
1794 if (g_err_irq < 0)
1795 return g_err_irq;
1796
1797 g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1798 if (g_recc_irq < 0)
1799 return g_recc_irq;
1800 }
1801
1802 /* Global controller context */
1803 gpriv = devm_kzalloc(&pdev->dev, sizeof(*gpriv), GFP_KERNEL);
1804 if (!gpriv) {
1805 err = -ENOMEM;
1806 goto fail_dev;
1807 }
1808 gpriv->pdev = pdev;
1809 gpriv->channels_mask = channels_mask;
1810 gpriv->fdmode = fdmode;
1811 gpriv->chip_id = chip_id;
1812
1813 if (gpriv->chip_id == RENESAS_RZG2L) {
1814 gpriv->rstc1 = devm_reset_control_get_exclusive(&pdev->dev, "rstp_n");
1815 if (IS_ERR(gpriv->rstc1))
1816 return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc1),
1817 "failed to get rstp_n\n");
1818
1819 gpriv->rstc2 = devm_reset_control_get_exclusive(&pdev->dev, "rstc_n");
1820 if (IS_ERR(gpriv->rstc2))
1821 return dev_err_probe(&pdev->dev, PTR_ERR(gpriv->rstc2),
1822 "failed to get rstc_n\n");
1823 }
1824
1825 /* Peripheral clock */
1826 gpriv->clkp = devm_clk_get(&pdev->dev, "fck");
1827 if (IS_ERR(gpriv->clkp)) {
1828 err = PTR_ERR(gpriv->clkp);
1829 dev_err(&pdev->dev, "cannot get peripheral clock, error %d\n",
1830 err);
1831 goto fail_dev;
1832 }
1833
1834 /* fCAN clock: Pick External clock. If not available fallback to
1835 * CANFD clock
1836 */
1837 gpriv->can_clk = devm_clk_get(&pdev->dev, "can_clk");
1838 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1839 gpriv->can_clk = devm_clk_get(&pdev->dev, "canfd");
1840 if (IS_ERR(gpriv->can_clk)) {
1841 err = PTR_ERR(gpriv->can_clk);
1842 dev_err(&pdev->dev,
1843 "cannot get canfd clock, error %d\n", err);
1844 goto fail_dev;
1845 }
1846 gpriv->fcan = RCANFD_CANFDCLK;
1847
1848 } else {
1849 gpriv->fcan = RCANFD_EXTCLK;
1850 }
1851 fcan_freq = clk_get_rate(gpriv->can_clk);
1852
1853 if (gpriv->fcan == RCANFD_CANFDCLK && gpriv->chip_id == RENESAS_RCAR_GEN3)
1854 /* CANFD clock is further divided by (1/2) within the IP */
1855 fcan_freq /= 2;
1856
1857 addr = devm_platform_ioremap_resource(pdev, 0);
1858 if (IS_ERR(addr)) {
1859 err = PTR_ERR(addr);
1860 goto fail_dev;
1861 }
1862 gpriv->base = addr;
1863
1864 /* Request IRQ that's common for both channels */
1865 if (gpriv->chip_id == RENESAS_RCAR_GEN3) {
1866 err = devm_request_irq(&pdev->dev, ch_irq,
1867 rcar_canfd_channel_interrupt, 0,
1868 "canfd.ch_int", gpriv);
1869 if (err) {
1870 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1871 ch_irq, err);
1872 goto fail_dev;
1873 }
1874
1875 err = devm_request_irq(&pdev->dev, g_irq,
1876 rcar_canfd_global_interrupt, 0,
1877 "canfd.g_int", gpriv);
1878 if (err) {
1879 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1880 g_irq, err);
1881 goto fail_dev;
1882 }
1883 } else {
1884 err = devm_request_irq(&pdev->dev, g_recc_irq,
1885 rcar_canfd_global_receive_fifo_interrupt, 0,
1886 "canfd.g_recc", gpriv);
1887
1888 if (err) {
1889 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1890 g_recc_irq, err);
1891 goto fail_dev;
1892 }
1893
1894 err = devm_request_irq(&pdev->dev, g_err_irq,
1895 rcar_canfd_global_err_interrupt, 0,
1896 "canfd.g_err", gpriv);
1897 if (err) {
1898 dev_err(&pdev->dev, "devm_request_irq(%d) failed, error %d\n",
1899 g_err_irq, err);
1900 goto fail_dev;
1901 }
1902 }
1903
1904 err = reset_control_reset(gpriv->rstc1);
1905 if (err)
1906 goto fail_dev;
1907 err = reset_control_reset(gpriv->rstc2);
1908 if (err) {
1909 reset_control_assert(gpriv->rstc1);
1910 goto fail_dev;
1911 }
1912
1913 /* Enable peripheral clock for register access */
1914 err = clk_prepare_enable(gpriv->clkp);
1915 if (err) {
1916 dev_err(&pdev->dev,
1917 "failed to enable peripheral clock, error %d\n", err);
1918 goto fail_reset;
1919 }
1920
1921 err = rcar_canfd_reset_controller(gpriv);
1922 if (err) {
1923 dev_err(&pdev->dev, "reset controller failed\n");
1924 goto fail_clk;
1925 }
1926
1927 /* Controller in Global reset & Channel reset mode */
1928 rcar_canfd_configure_controller(gpriv);
1929
1930 /* Configure per channel attributes */
1931 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1932 /* Configure Channel's Rx fifo */
1933 rcar_canfd_configure_rx(gpriv, ch);
1934
1935 /* Configure Channel's Tx (Common) fifo */
1936 rcar_canfd_configure_tx(gpriv, ch);
1937
1938 /* Configure receive rules */
1939 rcar_canfd_configure_afl_rules(gpriv, ch);
1940 }
1941
1942 /* Configure common interrupts */
1943 rcar_canfd_enable_global_interrupts(gpriv);
1944
1945 /* Start Global operation mode */
1946 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
1947 RCANFD_GCTR_GMDC_GOPM);
1948
1949 /* Verify mode change */
1950 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
1951 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
1952 if (err) {
1953 dev_err(&pdev->dev, "global operational mode failed\n");
1954 goto fail_mode;
1955 }
1956
1957 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1958 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq);
1959 if (err)
1960 goto fail_channel;
1961 }
1962
1963 platform_set_drvdata(pdev, gpriv);
1964 dev_info(&pdev->dev, "global operational state (clk %d, fdmode %d)\n",
1965 gpriv->fcan, gpriv->fdmode);
1966 return 0;
1967
1968 fail_channel:
1969 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS)
1970 rcar_canfd_channel_remove(gpriv, ch);
1971 fail_mode:
1972 rcar_canfd_disable_global_interrupts(gpriv);
1973 fail_clk:
1974 clk_disable_unprepare(gpriv->clkp);
1975 fail_reset:
1976 reset_control_assert(gpriv->rstc1);
1977 reset_control_assert(gpriv->rstc2);
1978 fail_dev:
1979 return err;
1980 }
1981
rcar_canfd_remove(struct platform_device * pdev)1982 static int rcar_canfd_remove(struct platform_device *pdev)
1983 {
1984 struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
1985 u32 ch;
1986
1987 rcar_canfd_reset_controller(gpriv);
1988 rcar_canfd_disable_global_interrupts(gpriv);
1989
1990 for_each_set_bit(ch, &gpriv->channels_mask, RCANFD_NUM_CHANNELS) {
1991 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
1992 rcar_canfd_channel_remove(gpriv, ch);
1993 }
1994
1995 /* Enter global sleep mode */
1996 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
1997 clk_disable_unprepare(gpriv->clkp);
1998 reset_control_assert(gpriv->rstc1);
1999 reset_control_assert(gpriv->rstc2);
2000
2001 return 0;
2002 }
2003
rcar_canfd_suspend(struct device * dev)2004 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2005 {
2006 return 0;
2007 }
2008
rcar_canfd_resume(struct device * dev)2009 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2010 {
2011 return 0;
2012 }
2013
2014 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2015 rcar_canfd_resume);
2016
2017 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2018 { .compatible = "renesas,rcar-gen3-canfd", .data = (void *)RENESAS_RCAR_GEN3 },
2019 { .compatible = "renesas,rzg2l-canfd", .data = (void *)RENESAS_RZG2L },
2020 { }
2021 };
2022
2023 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2024
2025 static struct platform_driver rcar_canfd_driver = {
2026 .driver = {
2027 .name = RCANFD_DRV_NAME,
2028 .of_match_table = of_match_ptr(rcar_canfd_of_table),
2029 .pm = &rcar_canfd_pm_ops,
2030 },
2031 .probe = rcar_canfd_probe,
2032 .remove = rcar_canfd_remove,
2033 };
2034
2035 module_platform_driver(rcar_canfd_driver);
2036
2037 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
2038 MODULE_LICENSE("GPL");
2039 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2040 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
2041