1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2021 Broadcom Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 */
9 #include <linux/kernel.h>
10 #include <linux/errno.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ptp_clock_kernel.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/timecounter.h>
17 #include <linux/timekeeping.h>
18 #include <linux/ptp_classify.h>
19 #include "bnxt_hsi.h"
20 #include "bnxt.h"
21 #include "bnxt_hwrm.h"
22 #include "bnxt_ptp.h"
23
bnxt_ptp_parse(struct sk_buff * skb,u16 * seq_id,u16 * hdr_off)24 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off)
25 {
26 unsigned int ptp_class;
27 struct ptp_header *hdr;
28
29 ptp_class = ptp_classify_raw(skb);
30
31 switch (ptp_class & PTP_CLASS_VMASK) {
32 case PTP_CLASS_V1:
33 case PTP_CLASS_V2:
34 hdr = ptp_parse_header(skb, ptp_class);
35 if (!hdr)
36 return -EINVAL;
37
38 *hdr_off = (u8 *)hdr - skb->data;
39 *seq_id = ntohs(hdr->sequence_id);
40 return 0;
41 default:
42 return -ERANGE;
43 }
44 }
45
bnxt_ptp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)46 static int bnxt_ptp_settime(struct ptp_clock_info *ptp_info,
47 const struct timespec64 *ts)
48 {
49 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
50 ptp_info);
51 u64 ns = timespec64_to_ns(ts);
52
53 spin_lock_bh(&ptp->ptp_lock);
54 timecounter_init(&ptp->tc, &ptp->cc, ns);
55 spin_unlock_bh(&ptp->ptp_lock);
56 return 0;
57 }
58
59 /* Caller holds ptp_lock */
bnxt_refclk_read(struct bnxt * bp,struct ptp_system_timestamp * sts,u64 * ns)60 static int bnxt_refclk_read(struct bnxt *bp, struct ptp_system_timestamp *sts,
61 u64 *ns)
62 {
63 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
64 u32 high_before, high_now, low;
65
66 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
67 return -EIO;
68
69 high_before = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
70 ptp_read_system_prets(sts);
71 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
72 ptp_read_system_postts(sts);
73 high_now = readl(bp->bar0 + ptp->refclk_mapped_regs[1]);
74 if (high_now != high_before) {
75 ptp_read_system_prets(sts);
76 low = readl(bp->bar0 + ptp->refclk_mapped_regs[0]);
77 ptp_read_system_postts(sts);
78 }
79 *ns = ((u64)high_now << 32) | low;
80
81 return 0;
82 }
83
bnxt_ptp_get_current_time(struct bnxt * bp)84 static void bnxt_ptp_get_current_time(struct bnxt *bp)
85 {
86 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
87
88 if (!ptp)
89 return;
90 spin_lock_bh(&ptp->ptp_lock);
91 WRITE_ONCE(ptp->old_time, ptp->current_time);
92 bnxt_refclk_read(bp, NULL, &ptp->current_time);
93 spin_unlock_bh(&ptp->ptp_lock);
94 }
95
bnxt_hwrm_port_ts_query(struct bnxt * bp,u32 flags,u64 * ts)96 static int bnxt_hwrm_port_ts_query(struct bnxt *bp, u32 flags, u64 *ts)
97 {
98 struct hwrm_port_ts_query_output *resp;
99 struct hwrm_port_ts_query_input *req;
100 int rc;
101
102 rc = hwrm_req_init(bp, req, HWRM_PORT_TS_QUERY);
103 if (rc)
104 return rc;
105
106 req->flags = cpu_to_le32(flags);
107 if ((flags & PORT_TS_QUERY_REQ_FLAGS_PATH) ==
108 PORT_TS_QUERY_REQ_FLAGS_PATH_TX) {
109 req->enables = cpu_to_le16(BNXT_PTP_QTS_TX_ENABLES);
110 req->ptp_seq_id = cpu_to_le32(bp->ptp_cfg->tx_seqid);
111 req->ptp_hdr_offset = cpu_to_le16(bp->ptp_cfg->tx_hdr_off);
112 req->ts_req_timeout = cpu_to_le16(BNXT_PTP_QTS_TIMEOUT);
113 }
114 resp = hwrm_req_hold(bp, req);
115
116 rc = hwrm_req_send(bp, req);
117 if (!rc)
118 *ts = le64_to_cpu(resp->ptp_msg_ts);
119 hwrm_req_drop(bp, req);
120 return rc;
121 }
122
bnxt_ptp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)123 static int bnxt_ptp_gettimex(struct ptp_clock_info *ptp_info,
124 struct timespec64 *ts,
125 struct ptp_system_timestamp *sts)
126 {
127 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
128 ptp_info);
129 u64 ns, cycles;
130 int rc;
131
132 spin_lock_bh(&ptp->ptp_lock);
133 rc = bnxt_refclk_read(ptp->bp, sts, &cycles);
134 if (rc) {
135 spin_unlock_bh(&ptp->ptp_lock);
136 return rc;
137 }
138 ns = timecounter_cyc2time(&ptp->tc, cycles);
139 spin_unlock_bh(&ptp->ptp_lock);
140 *ts = ns_to_timespec64(ns);
141
142 return 0;
143 }
144
bnxt_ptp_adjtime(struct ptp_clock_info * ptp_info,s64 delta)145 static int bnxt_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
146 {
147 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
148 ptp_info);
149
150 spin_lock_bh(&ptp->ptp_lock);
151 timecounter_adjtime(&ptp->tc, delta);
152 spin_unlock_bh(&ptp->ptp_lock);
153 return 0;
154 }
155
bnxt_ptp_adjfreq(struct ptp_clock_info * ptp_info,s32 ppb)156 static int bnxt_ptp_adjfreq(struct ptp_clock_info *ptp_info, s32 ppb)
157 {
158 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
159 ptp_info);
160 struct hwrm_port_mac_cfg_input *req;
161 struct bnxt *bp = ptp->bp;
162 int rc;
163
164 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
165 if (rc)
166 return rc;
167
168 req->ptp_freq_adj_ppb = cpu_to_le32(ppb);
169 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB);
170 rc = hwrm_req_send(ptp->bp, req);
171 if (rc)
172 netdev_err(ptp->bp->dev,
173 "ptp adjfreq failed. rc = %d\n", rc);
174 return rc;
175 }
176
bnxt_ptp_pps_event(struct bnxt * bp,u32 data1,u32 data2)177 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2)
178 {
179 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
180 struct ptp_clock_event event;
181 u64 ns, pps_ts;
182
183 pps_ts = EVENT_PPS_TS(data2, data1);
184 spin_lock_bh(&ptp->ptp_lock);
185 ns = timecounter_cyc2time(&ptp->tc, pps_ts);
186 spin_unlock_bh(&ptp->ptp_lock);
187
188 switch (EVENT_DATA2_PPS_EVENT_TYPE(data2)) {
189 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL:
190 event.pps_times.ts_real = ns_to_timespec64(ns);
191 event.type = PTP_CLOCK_PPSUSR;
192 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
193 break;
194 case ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL:
195 event.timestamp = ns;
196 event.type = PTP_CLOCK_EXTTS;
197 event.index = EVENT_DATA2_PPS_PIN_NUM(data2);
198 break;
199 }
200
201 ptp_clock_event(bp->ptp_cfg->ptp_clock, &event);
202 }
203
bnxt_ptp_cfg_pin(struct bnxt * bp,u8 pin,u8 usage)204 static int bnxt_ptp_cfg_pin(struct bnxt *bp, u8 pin, u8 usage)
205 {
206 struct hwrm_func_ptp_pin_cfg_input *req;
207 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
208 u8 state = usage != BNXT_PPS_PIN_NONE;
209 u8 *pin_state, *pin_usg;
210 u32 enables;
211 int rc;
212
213 if (!TSIO_PIN_VALID(pin)) {
214 netdev_err(ptp->bp->dev, "1PPS: Invalid pin. Check pin-function configuration\n");
215 return -EOPNOTSUPP;
216 }
217
218 rc = hwrm_req_init(ptp->bp, req, HWRM_FUNC_PTP_PIN_CFG);
219 if (rc)
220 return rc;
221
222 enables = (FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE |
223 FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE) << (pin * 2);
224 req->enables = cpu_to_le32(enables);
225
226 pin_state = &req->pin0_state;
227 pin_usg = &req->pin0_usage;
228
229 *(pin_state + (pin * 2)) = state;
230 *(pin_usg + (pin * 2)) = usage;
231
232 rc = hwrm_req_send(ptp->bp, req);
233 if (rc)
234 return rc;
235
236 ptp->pps_info.pins[pin].usage = usage;
237 ptp->pps_info.pins[pin].state = state;
238
239 return 0;
240 }
241
bnxt_ptp_cfg_event(struct bnxt * bp,u8 event)242 static int bnxt_ptp_cfg_event(struct bnxt *bp, u8 event)
243 {
244 struct hwrm_func_ptp_cfg_input *req;
245 int rc;
246
247 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
248 if (rc)
249 return rc;
250
251 req->enables = cpu_to_le16(FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT);
252 req->ptp_pps_event = event;
253 return hwrm_req_send(bp, req);
254 }
255
bnxt_ptp_reapply_pps(struct bnxt * bp)256 void bnxt_ptp_reapply_pps(struct bnxt *bp)
257 {
258 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
259 struct bnxt_pps *pps;
260 u32 pin = 0;
261 int rc;
262
263 if (!ptp || !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) ||
264 !(ptp->ptp_info.pin_config))
265 return;
266 pps = &ptp->pps_info;
267 for (pin = 0; pin < BNXT_MAX_TSIO_PINS; pin++) {
268 if (pps->pins[pin].state) {
269 rc = bnxt_ptp_cfg_pin(bp, pin, pps->pins[pin].usage);
270 if (!rc && pps->pins[pin].event)
271 rc = bnxt_ptp_cfg_event(bp,
272 pps->pins[pin].event);
273 if (rc)
274 netdev_err(bp->dev, "1PPS: Failed to configure pin%d\n",
275 pin);
276 }
277 }
278 }
279
bnxt_get_target_cycles(struct bnxt_ptp_cfg * ptp,u64 target_ns,u64 * cycles_delta)280 static int bnxt_get_target_cycles(struct bnxt_ptp_cfg *ptp, u64 target_ns,
281 u64 *cycles_delta)
282 {
283 u64 cycles_now;
284 u64 nsec_now, nsec_delta;
285 int rc;
286
287 spin_lock_bh(&ptp->ptp_lock);
288 rc = bnxt_refclk_read(ptp->bp, NULL, &cycles_now);
289 if (rc) {
290 spin_unlock_bh(&ptp->ptp_lock);
291 return rc;
292 }
293 nsec_now = timecounter_cyc2time(&ptp->tc, cycles_now);
294 spin_unlock_bh(&ptp->ptp_lock);
295
296 nsec_delta = target_ns - nsec_now;
297 *cycles_delta = div64_u64(nsec_delta << ptp->cc.shift, ptp->cc.mult);
298 return 0;
299 }
300
bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg * ptp,struct ptp_clock_request * rq)301 static int bnxt_ptp_perout_cfg(struct bnxt_ptp_cfg *ptp,
302 struct ptp_clock_request *rq)
303 {
304 struct hwrm_func_ptp_cfg_input *req;
305 struct bnxt *bp = ptp->bp;
306 struct timespec64 ts;
307 u64 target_ns, delta;
308 u16 enables;
309 int rc;
310
311 ts.tv_sec = rq->perout.start.sec;
312 ts.tv_nsec = rq->perout.start.nsec;
313 target_ns = timespec64_to_ns(&ts);
314
315 rc = bnxt_get_target_cycles(ptp, target_ns, &delta);
316 if (rc)
317 return rc;
318
319 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_CFG);
320 if (rc)
321 return rc;
322
323 enables = FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD |
324 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP |
325 FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE;
326 req->enables = cpu_to_le16(enables);
327 req->ptp_pps_event = 0;
328 req->ptp_freq_adj_dll_source = 0;
329 req->ptp_freq_adj_dll_phase = 0;
330 req->ptp_freq_adj_ext_period = cpu_to_le32(NSEC_PER_SEC);
331 req->ptp_freq_adj_ext_up = 0;
332 req->ptp_freq_adj_ext_phase_lower = cpu_to_le32(delta);
333
334 return hwrm_req_send(bp, req);
335 }
336
bnxt_ptp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)337 static int bnxt_ptp_enable(struct ptp_clock_info *ptp_info,
338 struct ptp_clock_request *rq, int on)
339 {
340 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
341 ptp_info);
342 struct bnxt *bp = ptp->bp;
343 int pin_id;
344 int rc;
345
346 switch (rq->type) {
347 case PTP_CLK_REQ_EXTTS:
348 /* Configure an External PPS IN */
349 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_EXTTS,
350 rq->extts.index);
351 if (!TSIO_PIN_VALID(pin_id))
352 return -EOPNOTSUPP;
353 if (!on)
354 break;
355 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_IN);
356 if (rc)
357 return rc;
358 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_EXTERNAL);
359 if (!rc)
360 ptp->pps_info.pins[pin_id].event = BNXT_PPS_EVENT_EXTERNAL;
361 return rc;
362 case PTP_CLK_REQ_PEROUT:
363 /* Configure a Periodic PPS OUT */
364 pin_id = ptp_find_pin(ptp->ptp_clock, PTP_PF_PEROUT,
365 rq->perout.index);
366 if (!TSIO_PIN_VALID(pin_id))
367 return -EOPNOTSUPP;
368 if (!on)
369 break;
370
371 rc = bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_PPS_OUT);
372 if (!rc)
373 rc = bnxt_ptp_perout_cfg(ptp, rq);
374
375 return rc;
376 case PTP_CLK_REQ_PPS:
377 /* Configure PHC PPS IN */
378 rc = bnxt_ptp_cfg_pin(bp, 0, BNXT_PPS_PIN_PPS_IN);
379 if (rc)
380 return rc;
381 rc = bnxt_ptp_cfg_event(bp, BNXT_PPS_EVENT_INTERNAL);
382 if (!rc)
383 ptp->pps_info.pins[0].event = BNXT_PPS_EVENT_INTERNAL;
384 return rc;
385 default:
386 netdev_err(ptp->bp->dev, "Unrecognized PIN function\n");
387 return -EOPNOTSUPP;
388 }
389
390 return bnxt_ptp_cfg_pin(bp, pin_id, BNXT_PPS_PIN_NONE);
391 }
392
bnxt_hwrm_ptp_cfg(struct bnxt * bp)393 static int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
394 {
395 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
396 struct hwrm_port_mac_cfg_input *req;
397 u32 flags = 0;
398 int rc;
399
400 rc = hwrm_req_init(bp, req, HWRM_PORT_MAC_CFG);
401 if (rc)
402 return rc;
403
404 if (ptp->rx_filter)
405 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
406 else
407 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
408 if (ptp->tx_tstamp_en)
409 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
410 else
411 flags |= PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
412 req->flags = cpu_to_le32(flags);
413 req->enables = cpu_to_le32(PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
414 req->rx_ts_capture_ptp_msg_type = cpu_to_le16(ptp->rxctl);
415
416 return hwrm_req_send(bp, req);
417 }
418
bnxt_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)419 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
420 {
421 struct bnxt *bp = netdev_priv(dev);
422 struct hwtstamp_config stmpconf;
423 struct bnxt_ptp_cfg *ptp;
424 u16 old_rxctl;
425 int old_rx_filter, rc;
426 u8 old_tx_tstamp_en;
427
428 ptp = bp->ptp_cfg;
429 if (!ptp)
430 return -EOPNOTSUPP;
431
432 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
433 return -EFAULT;
434
435 if (stmpconf.flags)
436 return -EINVAL;
437
438 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
439 stmpconf.tx_type != HWTSTAMP_TX_OFF)
440 return -ERANGE;
441
442 old_rx_filter = ptp->rx_filter;
443 old_rxctl = ptp->rxctl;
444 old_tx_tstamp_en = ptp->tx_tstamp_en;
445 switch (stmpconf.rx_filter) {
446 case HWTSTAMP_FILTER_NONE:
447 ptp->rxctl = 0;
448 ptp->rx_filter = HWTSTAMP_FILTER_NONE;
449 break;
450 case HWTSTAMP_FILTER_PTP_V2_EVENT:
451 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
452 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
453 ptp->rxctl = BNXT_PTP_MSG_EVENTS;
454 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
455 break;
456 case HWTSTAMP_FILTER_PTP_V2_SYNC:
457 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
458 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
459 ptp->rxctl = BNXT_PTP_MSG_SYNC;
460 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
461 break;
462 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
463 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
464 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
465 ptp->rxctl = BNXT_PTP_MSG_DELAY_REQ;
466 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
467 break;
468 default:
469 return -ERANGE;
470 }
471
472 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
473 ptp->tx_tstamp_en = 1;
474 else
475 ptp->tx_tstamp_en = 0;
476
477 rc = bnxt_hwrm_ptp_cfg(bp);
478 if (rc)
479 goto ts_set_err;
480
481 stmpconf.rx_filter = ptp->rx_filter;
482 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
483 -EFAULT : 0;
484
485 ts_set_err:
486 ptp->rx_filter = old_rx_filter;
487 ptp->rxctl = old_rxctl;
488 ptp->tx_tstamp_en = old_tx_tstamp_en;
489 return rc;
490 }
491
bnxt_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)492 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
493 {
494 struct bnxt *bp = netdev_priv(dev);
495 struct hwtstamp_config stmpconf;
496 struct bnxt_ptp_cfg *ptp;
497
498 ptp = bp->ptp_cfg;
499 if (!ptp)
500 return -EOPNOTSUPP;
501
502 stmpconf.flags = 0;
503 stmpconf.tx_type = ptp->tx_tstamp_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
504
505 stmpconf.rx_filter = ptp->rx_filter;
506 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
507 -EFAULT : 0;
508 }
509
bnxt_map_regs(struct bnxt * bp,u32 * reg_arr,int count,int reg_win)510 static int bnxt_map_regs(struct bnxt *bp, u32 *reg_arr, int count, int reg_win)
511 {
512 u32 reg_base = *reg_arr & BNXT_GRC_BASE_MASK;
513 u32 win_off;
514 int i;
515
516 for (i = 0; i < count; i++) {
517 if ((reg_arr[i] & BNXT_GRC_BASE_MASK) != reg_base)
518 return -ERANGE;
519 }
520 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4;
521 writel(reg_base, bp->bar0 + win_off);
522 return 0;
523 }
524
bnxt_map_ptp_regs(struct bnxt * bp)525 static int bnxt_map_ptp_regs(struct bnxt *bp)
526 {
527 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
528 u32 *reg_arr;
529 int rc, i;
530
531 reg_arr = ptp->refclk_regs;
532 if (bp->flags & BNXT_FLAG_CHIP_P5) {
533 rc = bnxt_map_regs(bp, reg_arr, 2, BNXT_PTP_GRC_WIN);
534 if (rc)
535 return rc;
536 for (i = 0; i < 2; i++)
537 ptp->refclk_mapped_regs[i] = BNXT_PTP_GRC_WIN_BASE +
538 (ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
539 return 0;
540 }
541 return -ENODEV;
542 }
543
bnxt_unmap_ptp_regs(struct bnxt * bp)544 static void bnxt_unmap_ptp_regs(struct bnxt *bp)
545 {
546 writel(0, bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT +
547 (BNXT_PTP_GRC_WIN - 1) * 4);
548 }
549
bnxt_cc_read(const struct cyclecounter * cc)550 static u64 bnxt_cc_read(const struct cyclecounter *cc)
551 {
552 struct bnxt_ptp_cfg *ptp = container_of(cc, struct bnxt_ptp_cfg, cc);
553 u64 ns = 0;
554
555 bnxt_refclk_read(ptp->bp, NULL, &ns);
556 return ns;
557 }
558
bnxt_stamp_tx_skb(struct bnxt * bp,struct sk_buff * skb)559 static void bnxt_stamp_tx_skb(struct bnxt *bp, struct sk_buff *skb)
560 {
561 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
562 struct skb_shared_hwtstamps timestamp;
563 u64 ts = 0, ns = 0;
564 int rc;
565
566 rc = bnxt_hwrm_port_ts_query(bp, PORT_TS_QUERY_REQ_FLAGS_PATH_TX, &ts);
567 if (!rc) {
568 memset(×tamp, 0, sizeof(timestamp));
569 spin_lock_bh(&ptp->ptp_lock);
570 ns = timecounter_cyc2time(&ptp->tc, ts);
571 spin_unlock_bh(&ptp->ptp_lock);
572 timestamp.hwtstamp = ns_to_ktime(ns);
573 skb_tstamp_tx(ptp->tx_skb, ×tamp);
574 } else {
575 netdev_err(bp->dev, "TS query for TX timer failed rc = %x\n",
576 rc);
577 }
578
579 dev_kfree_skb_any(ptp->tx_skb);
580 ptp->tx_skb = NULL;
581 atomic_inc(&ptp->tx_avail);
582 }
583
bnxt_ptp_ts_aux_work(struct ptp_clock_info * ptp_info)584 static long bnxt_ptp_ts_aux_work(struct ptp_clock_info *ptp_info)
585 {
586 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
587 ptp_info);
588 unsigned long now = jiffies;
589 struct bnxt *bp = ptp->bp;
590
591 if (ptp->tx_skb)
592 bnxt_stamp_tx_skb(bp, ptp->tx_skb);
593
594 if (!time_after_eq(now, ptp->next_period))
595 return ptp->next_period - now;
596
597 bnxt_ptp_get_current_time(bp);
598 ptp->next_period = now + HZ;
599 if (time_after_eq(now, ptp->next_overflow_check)) {
600 spin_lock_bh(&ptp->ptp_lock);
601 timecounter_read(&ptp->tc);
602 spin_unlock_bh(&ptp->ptp_lock);
603 ptp->next_overflow_check = now + BNXT_PHC_OVERFLOW_PERIOD;
604 }
605 return HZ;
606 }
607
bnxt_get_tx_ts_p5(struct bnxt * bp,struct sk_buff * skb)608 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb)
609 {
610 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
611
612 if (ptp->tx_skb) {
613 netdev_err(bp->dev, "deferring skb:one SKB is still outstanding\n");
614 return -EBUSY;
615 }
616 ptp->tx_skb = skb;
617 ptp_schedule_worker(ptp->ptp_clock, 0);
618 return 0;
619 }
620
bnxt_get_rx_ts_p5(struct bnxt * bp,u64 * ts,u32 pkt_ts)621 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts)
622 {
623 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
624 u64 time;
625
626 if (!ptp)
627 return -ENODEV;
628
629 BNXT_READ_TIME64(ptp, time, ptp->old_time);
630 *ts = (time & BNXT_HI_TIMER_MASK) | pkt_ts;
631 if (pkt_ts < (time & BNXT_LO_TIMER_MASK))
632 *ts += BNXT_LO_TIMER_MASK + 1;
633
634 return 0;
635 }
636
637 static const struct ptp_clock_info bnxt_ptp_caps = {
638 .owner = THIS_MODULE,
639 .name = "bnxt clock",
640 .max_adj = BNXT_MAX_PHC_DRIFT,
641 .n_alarm = 0,
642 .n_ext_ts = 0,
643 .n_per_out = 0,
644 .n_pins = 0,
645 .pps = 0,
646 .adjfreq = bnxt_ptp_adjfreq,
647 .adjtime = bnxt_ptp_adjtime,
648 .do_aux_work = bnxt_ptp_ts_aux_work,
649 .gettimex64 = bnxt_ptp_gettimex,
650 .settime64 = bnxt_ptp_settime,
651 .enable = bnxt_ptp_enable,
652 };
653
bnxt_ptp_verify(struct ptp_clock_info * ptp_info,unsigned int pin,enum ptp_pin_function func,unsigned int chan)654 static int bnxt_ptp_verify(struct ptp_clock_info *ptp_info, unsigned int pin,
655 enum ptp_pin_function func, unsigned int chan)
656 {
657 struct bnxt_ptp_cfg *ptp = container_of(ptp_info, struct bnxt_ptp_cfg,
658 ptp_info);
659 /* Allow only PPS pin function configuration */
660 if (ptp->pps_info.pins[pin].usage <= BNXT_PPS_PIN_PPS_OUT &&
661 func != PTP_PF_PHYSYNC)
662 return 0;
663 else
664 return -EOPNOTSUPP;
665 }
666
bnxt_ptp_pps_init(struct bnxt * bp)667 static int bnxt_ptp_pps_init(struct bnxt *bp)
668 {
669 struct hwrm_func_ptp_pin_qcfg_output *resp;
670 struct hwrm_func_ptp_pin_qcfg_input *req;
671 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
672 struct ptp_clock_info *ptp_info;
673 struct bnxt_pps *pps_info;
674 u8 *pin_usg;
675 u32 i, rc;
676
677 /* Query current/default PIN CFG */
678 rc = hwrm_req_init(bp, req, HWRM_FUNC_PTP_PIN_QCFG);
679 if (rc)
680 return rc;
681
682 resp = hwrm_req_hold(bp, req);
683 rc = hwrm_req_send(bp, req);
684 if (rc || !resp->num_pins) {
685 hwrm_req_drop(bp, req);
686 return -EOPNOTSUPP;
687 }
688
689 ptp_info = &ptp->ptp_info;
690 pps_info = &ptp->pps_info;
691 pps_info->num_pins = resp->num_pins;
692 ptp_info->n_pins = pps_info->num_pins;
693 ptp_info->pin_config = kcalloc(ptp_info->n_pins,
694 sizeof(*ptp_info->pin_config),
695 GFP_KERNEL);
696 if (!ptp_info->pin_config) {
697 hwrm_req_drop(bp, req);
698 return -ENOMEM;
699 }
700
701 /* Report the TSIO capability to kernel */
702 pin_usg = &resp->pin0_usage;
703 for (i = 0; i < pps_info->num_pins; i++, pin_usg++) {
704 snprintf(ptp_info->pin_config[i].name,
705 sizeof(ptp_info->pin_config[i].name), "bnxt_pps%d", i);
706 ptp_info->pin_config[i].index = i;
707 ptp_info->pin_config[i].chan = i;
708 if (*pin_usg == BNXT_PPS_PIN_PPS_IN)
709 ptp_info->pin_config[i].func = PTP_PF_EXTTS;
710 else if (*pin_usg == BNXT_PPS_PIN_PPS_OUT)
711 ptp_info->pin_config[i].func = PTP_PF_PEROUT;
712 else
713 ptp_info->pin_config[i].func = PTP_PF_NONE;
714
715 pps_info->pins[i].usage = *pin_usg;
716 }
717 hwrm_req_drop(bp, req);
718
719 /* Only 1 each of ext_ts and per_out pins is available in HW */
720 ptp_info->n_ext_ts = 1;
721 ptp_info->n_per_out = 1;
722 ptp_info->pps = 1;
723 ptp_info->verify = bnxt_ptp_verify;
724
725 return 0;
726 }
727
bnxt_pps_config_ok(struct bnxt * bp)728 static bool bnxt_pps_config_ok(struct bnxt *bp)
729 {
730 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
731
732 return !(bp->fw_cap & BNXT_FW_CAP_PTP_PPS) == !ptp->ptp_info.pin_config;
733 }
734
bnxt_ptp_init(struct bnxt * bp)735 int bnxt_ptp_init(struct bnxt *bp)
736 {
737 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
738 int rc;
739
740 if (!ptp)
741 return 0;
742
743 rc = bnxt_map_ptp_regs(bp);
744 if (rc)
745 return rc;
746
747 if (ptp->ptp_clock && bnxt_pps_config_ok(bp))
748 return 0;
749
750 if (ptp->ptp_clock) {
751 ptp_clock_unregister(ptp->ptp_clock);
752 ptp->ptp_clock = NULL;
753 kfree(ptp->ptp_info.pin_config);
754 ptp->ptp_info.pin_config = NULL;
755 }
756 atomic_set(&ptp->tx_avail, BNXT_MAX_TX_TS);
757 spin_lock_init(&ptp->ptp_lock);
758
759 memset(&ptp->cc, 0, sizeof(ptp->cc));
760 ptp->cc.read = bnxt_cc_read;
761 ptp->cc.mask = CYCLECOUNTER_MASK(48);
762 ptp->cc.shift = 0;
763 ptp->cc.mult = 1;
764
765 ptp->next_overflow_check = jiffies + BNXT_PHC_OVERFLOW_PERIOD;
766 timecounter_init(&ptp->tc, &ptp->cc, ktime_to_ns(ktime_get_real()));
767
768 ptp->ptp_info = bnxt_ptp_caps;
769 if ((bp->fw_cap & BNXT_FW_CAP_PTP_PPS)) {
770 if (bnxt_ptp_pps_init(bp))
771 netdev_err(bp->dev, "1pps not initialized, continuing without 1pps support\n");
772 }
773 ptp->ptp_clock = ptp_clock_register(&ptp->ptp_info, &bp->pdev->dev);
774 if (IS_ERR(ptp->ptp_clock)) {
775 int err = PTR_ERR(ptp->ptp_clock);
776
777 ptp->ptp_clock = NULL;
778 bnxt_unmap_ptp_regs(bp);
779 return err;
780 }
781 if (bp->flags & BNXT_FLAG_CHIP_P5) {
782 spin_lock_bh(&ptp->ptp_lock);
783 bnxt_refclk_read(bp, NULL, &ptp->current_time);
784 WRITE_ONCE(ptp->old_time, ptp->current_time);
785 spin_unlock_bh(&ptp->ptp_lock);
786 ptp_schedule_worker(ptp->ptp_clock, 0);
787 }
788 return 0;
789 }
790
bnxt_ptp_clear(struct bnxt * bp)791 void bnxt_ptp_clear(struct bnxt *bp)
792 {
793 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
794
795 if (!ptp)
796 return;
797
798 if (ptp->ptp_clock)
799 ptp_clock_unregister(ptp->ptp_clock);
800
801 ptp->ptp_clock = NULL;
802 kfree(ptp->ptp_info.pin_config);
803 ptp->ptp_info.pin_config = NULL;
804
805 if (ptp->tx_skb) {
806 dev_kfree_skb_any(ptp->tx_skb);
807 ptp->tx_skb = NULL;
808 }
809 bnxt_unmap_ptp_regs(bp);
810 }
811