1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #ifndef _IGC_H_
5 #define _IGC_H_
6
7 #include <linux/kobject.h>
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/vmalloc.h>
11 #include <linux/ethtool.h>
12 #include <linux/sctp.h>
13 #include <linux/ptp_clock_kernel.h>
14 #include <linux/timecounter.h>
15 #include <linux/net_tstamp.h>
16 #include <linux/bitfield.h>
17
18 #include "igc_hw.h"
19
20 void igc_ethtool_set_ops(struct net_device *);
21
22 /* Transmit and receive queues */
23 #define IGC_MAX_RX_QUEUES 4
24 #define IGC_MAX_TX_QUEUES 4
25
26 #define MAX_Q_VECTORS 8
27 #define MAX_STD_JUMBO_FRAME_SIZE 9216
28
29 #define MAX_ETYPE_FILTER 8
30 #define IGC_RETA_SIZE 128
31
32 /* SDP support */
33 #define IGC_N_EXTTS 2
34 #define IGC_N_PEROUT 2
35 #define IGC_N_SDP 4
36
37 #define MAX_FLEX_FILTER 32
38
39 enum igc_mac_filter_type {
40 IGC_MAC_FILTER_TYPE_DST = 0,
41 IGC_MAC_FILTER_TYPE_SRC
42 };
43
44 struct igc_tx_queue_stats {
45 u64 packets;
46 u64 bytes;
47 u64 restart_queue;
48 u64 restart_queue2;
49 };
50
51 struct igc_rx_queue_stats {
52 u64 packets;
53 u64 bytes;
54 u64 drops;
55 u64 csum_err;
56 u64 alloc_failed;
57 };
58
59 struct igc_rx_packet_stats {
60 u64 ipv4_packets; /* IPv4 headers processed */
61 u64 ipv4e_packets; /* IPv4E headers with extensions processed */
62 u64 ipv6_packets; /* IPv6 headers processed */
63 u64 ipv6e_packets; /* IPv6E headers with extensions processed */
64 u64 tcp_packets; /* TCP headers processed */
65 u64 udp_packets; /* UDP headers processed */
66 u64 sctp_packets; /* SCTP headers processed */
67 u64 nfs_packets; /* NFS headers processe */
68 u64 other_packets;
69 };
70
71 struct igc_ring_container {
72 struct igc_ring *ring; /* pointer to linked list of rings */
73 unsigned int total_bytes; /* total bytes processed this int */
74 unsigned int total_packets; /* total packets processed this int */
75 u16 work_limit; /* total work allowed per interrupt */
76 u8 count; /* total number of rings in vector */
77 u8 itr; /* current ITR setting for ring */
78 };
79
80 struct igc_ring {
81 struct igc_q_vector *q_vector; /* backlink to q_vector */
82 struct net_device *netdev; /* back pointer to net_device */
83 struct device *dev; /* device for dma mapping */
84 union { /* array of buffer info structs */
85 struct igc_tx_buffer *tx_buffer_info;
86 struct igc_rx_buffer *rx_buffer_info;
87 };
88 void *desc; /* descriptor ring memory */
89 unsigned long flags; /* ring specific flags */
90 void __iomem *tail; /* pointer to ring tail register */
91 dma_addr_t dma; /* phys address of the ring */
92 unsigned int size; /* length of desc. ring in bytes */
93
94 u16 count; /* number of desc. in the ring */
95 u8 queue_index; /* logical index of the ring*/
96 u8 reg_idx; /* physical index of the ring */
97 bool launchtime_enable; /* true if LaunchTime is enabled */
98 ktime_t last_tx_cycle; /* end of the cycle with a launchtime transmission */
99 ktime_t last_ff_cycle; /* Last cycle with an active first flag */
100
101 u32 start_time;
102 u32 end_time;
103
104 /* CBS parameters */
105 bool cbs_enable; /* indicates if CBS is enabled */
106 s32 idleslope; /* idleSlope in kbps */
107 s32 sendslope; /* sendSlope in kbps */
108 s32 hicredit; /* hiCredit in bytes */
109 s32 locredit; /* loCredit in bytes */
110
111 /* everything past this point are written often */
112 u16 next_to_clean;
113 u16 next_to_use;
114 u16 next_to_alloc;
115
116 union {
117 /* TX */
118 struct {
119 struct igc_tx_queue_stats tx_stats;
120 struct u64_stats_sync tx_syncp;
121 struct u64_stats_sync tx_syncp2;
122 };
123 /* RX */
124 struct {
125 struct igc_rx_queue_stats rx_stats;
126 struct igc_rx_packet_stats pkt_stats;
127 struct u64_stats_sync rx_syncp;
128 struct sk_buff *skb;
129 };
130 };
131
132 struct xdp_rxq_info xdp_rxq;
133 struct xsk_buff_pool *xsk_pool;
134 } ____cacheline_internodealigned_in_smp;
135
136 /* Board specific private data structure */
137 struct igc_adapter {
138 struct net_device *netdev;
139
140 struct ethtool_eee eee;
141 u16 eee_advert;
142
143 unsigned long state;
144 unsigned int flags;
145 unsigned int num_q_vectors;
146
147 struct msix_entry *msix_entries;
148
149 /* TX */
150 u16 tx_work_limit;
151 u32 tx_timeout_count;
152 int num_tx_queues;
153 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES];
154
155 /* RX */
156 int num_rx_queues;
157 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES];
158
159 struct timer_list watchdog_timer;
160 struct timer_list dma_err_timer;
161 struct timer_list phy_info_timer;
162
163 u32 wol;
164 u32 en_mng_pt;
165 u16 link_speed;
166 u16 link_duplex;
167
168 u8 port_num;
169
170 u8 __iomem *io_addr;
171 /* Interrupt Throttle Rate */
172 u32 rx_itr_setting;
173 u32 tx_itr_setting;
174
175 struct work_struct reset_task;
176 struct work_struct watchdog_task;
177 struct work_struct dma_err_task;
178 bool fc_autoneg;
179
180 u8 tx_timeout_factor;
181
182 int msg_enable;
183 u32 max_frame_size;
184 u32 min_frame_size;
185
186 ktime_t base_time;
187 ktime_t cycle_time;
188 bool qbv_enable;
189
190 /* OS defined structs */
191 struct pci_dev *pdev;
192 /* lock for statistics */
193 spinlock_t stats64_lock;
194 struct rtnl_link_stats64 stats64;
195
196 /* structs defined in igc_hw.h */
197 struct igc_hw hw;
198 struct igc_hw_stats stats;
199
200 struct igc_q_vector *q_vector[MAX_Q_VECTORS];
201 u32 eims_enable_mask;
202 u32 eims_other;
203
204 u16 tx_ring_count;
205 u16 rx_ring_count;
206
207 u32 tx_hwtstamp_timeouts;
208 u32 tx_hwtstamp_skipped;
209 u32 rx_hwtstamp_cleared;
210
211 u32 rss_queues;
212 u32 rss_indir_tbl_init;
213
214 /* Any access to elements in nfc_rule_list is protected by the
215 * nfc_rule_lock.
216 */
217 struct mutex nfc_rule_lock;
218 struct list_head nfc_rule_list;
219 unsigned int nfc_rule_count;
220
221 u8 rss_indir_tbl[IGC_RETA_SIZE];
222
223 unsigned long link_check_timeout;
224 struct igc_info ei;
225
226 u32 test_icr;
227
228 struct ptp_clock *ptp_clock;
229 struct ptp_clock_info ptp_caps;
230 struct work_struct ptp_tx_work;
231 /* Access to ptp_tx_skb and ptp_tx_start are protected by the
232 * ptp_tx_lock.
233 */
234 spinlock_t ptp_tx_lock;
235 struct sk_buff *ptp_tx_skb;
236 struct hwtstamp_config tstamp_config;
237 unsigned long ptp_tx_start;
238 unsigned int ptp_flags;
239 /* System time value lock */
240 spinlock_t tmreg_lock;
241 struct cyclecounter cc;
242 struct timecounter tc;
243 struct timespec64 prev_ptp_time; /* Pre-reset PTP clock */
244 ktime_t ptp_reset_start; /* Reset time in clock mono */
245 struct system_time_snapshot snapshot;
246
247 char fw_version[32];
248
249 struct bpf_prog *xdp_prog;
250
251 bool pps_sys_wrap_on;
252
253 struct ptp_pin_desc sdp_config[IGC_N_SDP];
254 struct {
255 struct timespec64 start;
256 struct timespec64 period;
257 } perout[IGC_N_PEROUT];
258 };
259
260 void igc_up(struct igc_adapter *adapter);
261 void igc_down(struct igc_adapter *adapter);
262 int igc_open(struct net_device *netdev);
263 int igc_close(struct net_device *netdev);
264 int igc_setup_tx_resources(struct igc_ring *ring);
265 int igc_setup_rx_resources(struct igc_ring *ring);
266 void igc_free_tx_resources(struct igc_ring *ring);
267 void igc_free_rx_resources(struct igc_ring *ring);
268 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter);
269 void igc_set_flag_queue_pairs(struct igc_adapter *adapter,
270 const u32 max_rss_queues);
271 int igc_reinit_queues(struct igc_adapter *adapter);
272 void igc_write_rss_indir_tbl(struct igc_adapter *adapter);
273 bool igc_has_link(struct igc_adapter *adapter);
274 void igc_reset(struct igc_adapter *adapter);
275 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx);
276 void igc_update_stats(struct igc_adapter *adapter);
277 void igc_disable_rx_ring(struct igc_ring *ring);
278 void igc_enable_rx_ring(struct igc_ring *ring);
279 void igc_disable_tx_ring(struct igc_ring *ring);
280 void igc_enable_tx_ring(struct igc_ring *ring);
281 int igc_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
282
283 /* igc_dump declarations */
284 void igc_rings_dump(struct igc_adapter *adapter);
285 void igc_regs_dump(struct igc_adapter *adapter);
286
287 extern char igc_driver_name[];
288
289 #define IGC_REGS_LEN 740
290
291 /* flags controlling PTP/1588 function */
292 #define IGC_PTP_ENABLED BIT(0)
293
294 /* Flags definitions */
295 #define IGC_FLAG_HAS_MSI BIT(0)
296 #define IGC_FLAG_QUEUE_PAIRS BIT(3)
297 #define IGC_FLAG_DMAC BIT(4)
298 #define IGC_FLAG_PTP BIT(8)
299 #define IGC_FLAG_WOL_SUPPORTED BIT(8)
300 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9)
301 #define IGC_FLAG_MEDIA_RESET BIT(10)
302 #define IGC_FLAG_MAS_ENABLE BIT(12)
303 #define IGC_FLAG_HAS_MSIX BIT(13)
304 #define IGC_FLAG_EEE BIT(14)
305 #define IGC_FLAG_VLAN_PROMISC BIT(15)
306 #define IGC_FLAG_RX_LEGACY BIT(16)
307 #define IGC_FLAG_TSN_QBV_ENABLED BIT(17)
308 #define IGC_FLAG_TSN_QAV_ENABLED BIT(18)
309
310 #define IGC_FLAG_TSN_ANY_ENABLED \
311 (IGC_FLAG_TSN_QBV_ENABLED | IGC_FLAG_TSN_QAV_ENABLED)
312
313 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
314 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
315
316 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002
317 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
318 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
319
320 /* RX-desc Write-Back format RSS Type's */
321 enum igc_rss_type_num {
322 IGC_RSS_TYPE_NO_HASH = 0,
323 IGC_RSS_TYPE_HASH_TCP_IPV4 = 1,
324 IGC_RSS_TYPE_HASH_IPV4 = 2,
325 IGC_RSS_TYPE_HASH_TCP_IPV6 = 3,
326 IGC_RSS_TYPE_HASH_IPV6_EX = 4,
327 IGC_RSS_TYPE_HASH_IPV6 = 5,
328 IGC_RSS_TYPE_HASH_TCP_IPV6_EX = 6,
329 IGC_RSS_TYPE_HASH_UDP_IPV4 = 7,
330 IGC_RSS_TYPE_HASH_UDP_IPV6 = 8,
331 IGC_RSS_TYPE_HASH_UDP_IPV6_EX = 9,
332 IGC_RSS_TYPE_MAX = 10,
333 };
334 #define IGC_RSS_TYPE_MAX_TABLE 16
335 #define IGC_RSS_TYPE_MASK GENMASK(3,0) /* 4-bits (3:0) = mask 0x0F */
336
337 /* igc_rss_type - Rx descriptor RSS type field */
igc_rss_type(const union igc_adv_rx_desc * rx_desc)338 static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
339 {
340 /* RSS Type 4-bits (3:0) number: 0-9 (above 9 is reserved)
341 * Accessing the same bits via u16 (wb.lower.lo_dword.hs_rss.pkt_info)
342 * is slightly slower than via u32 (wb.lower.lo_dword.data)
343 */
344 return le32_get_bits(rx_desc->wb.lower.lo_dword.data, IGC_RSS_TYPE_MASK);
345 }
346
347 /* Interrupt defines */
348 #define IGC_START_ITR 648 /* ~6000 ints/sec */
349 #define IGC_4K_ITR 980
350 #define IGC_20K_ITR 196
351 #define IGC_70K_ITR 56
352
353 #define IGC_DEFAULT_ITR 3 /* dynamic */
354 #define IGC_MAX_ITR_USECS 10000
355 #define IGC_MIN_ITR_USECS 10
356 #define NON_Q_VECTORS 1
357 #define MAX_MSIX_ENTRIES 10
358
359 /* TX/RX descriptor defines */
360 #define IGC_DEFAULT_TXD 256
361 #define IGC_DEFAULT_TX_WORK 128
362 #define IGC_MIN_TXD 64
363 #define IGC_MAX_TXD 4096
364
365 #define IGC_DEFAULT_RXD 256
366 #define IGC_MIN_RXD 64
367 #define IGC_MAX_RXD 4096
368
369 /* Supported Rx Buffer Sizes */
370 #define IGC_RXBUFFER_256 256
371 #define IGC_RXBUFFER_2048 2048
372 #define IGC_RXBUFFER_3072 3072
373
374 #define AUTO_ALL_MODES 0
375 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256
376
377 /* Transmit and receive latency (for PTP timestamps) */
378 #define IGC_I225_TX_LATENCY_10 240
379 #define IGC_I225_TX_LATENCY_100 58
380 #define IGC_I225_TX_LATENCY_1000 80
381 #define IGC_I225_TX_LATENCY_2500 1325
382 #define IGC_I225_RX_LATENCY_10 6450
383 #define IGC_I225_RX_LATENCY_100 185
384 #define IGC_I225_RX_LATENCY_1000 300
385 #define IGC_I225_RX_LATENCY_2500 1485
386
387 /* RX and TX descriptor control thresholds.
388 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
389 * descriptors available in its onboard memory.
390 * Setting this to 0 disables RX descriptor prefetch.
391 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
392 * available in host memory.
393 * If PTHRESH is 0, this should also be 0.
394 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
395 * descriptors until either it has this many to write back, or the
396 * ITR timer expires.
397 */
398 #define IGC_RX_PTHRESH 8
399 #define IGC_RX_HTHRESH 8
400 #define IGC_TX_PTHRESH 8
401 #define IGC_TX_HTHRESH 1
402 #define IGC_RX_WTHRESH 4
403 #define IGC_TX_WTHRESH 16
404
405 #define IGC_RX_DMA_ATTR \
406 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
407
408 #define IGC_TS_HDR_LEN 16
409
410 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
411
412 #if (PAGE_SIZE < 8192)
413 #define IGC_MAX_FRAME_BUILD_SKB \
414 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN)
415 #else
416 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN)
417 #endif
418
419 /* How many Rx Buffers do we bundle into one write to the hardware ? */
420 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */
421
422 /* VLAN info */
423 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000
424 #define IGC_TX_FLAGS_VLAN_SHIFT 16
425
426 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */
igc_test_staterr(union igc_adv_rx_desc * rx_desc,const u32 stat_err_bits)427 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc,
428 const u32 stat_err_bits)
429 {
430 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
431 }
432
433 enum igc_state_t {
434 __IGC_TESTING,
435 __IGC_RESETTING,
436 __IGC_DOWN,
437 };
438
439 enum igc_tx_flags {
440 /* cmd_type flags */
441 IGC_TX_FLAGS_VLAN = 0x01,
442 IGC_TX_FLAGS_TSO = 0x02,
443 IGC_TX_FLAGS_TSTAMP = 0x04,
444
445 /* olinfo flags */
446 IGC_TX_FLAGS_IPV4 = 0x10,
447 IGC_TX_FLAGS_CSUM = 0x20,
448 };
449
450 enum igc_boards {
451 board_base,
452 };
453
454 /* The largest size we can write to the descriptor is 65535. In order to
455 * maintain a power of two alignment we have to limit ourselves to 32K.
456 */
457 #define IGC_MAX_TXD_PWR 15
458 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR)
459
460 /* Tx Descriptors needed, worst case */
461 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD)
462 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
463
464 enum igc_tx_buffer_type {
465 IGC_TX_BUFFER_TYPE_SKB,
466 IGC_TX_BUFFER_TYPE_XDP,
467 IGC_TX_BUFFER_TYPE_XSK,
468 };
469
470 /* wrapper around a pointer to a socket buffer,
471 * so a DMA handle can be stored along with the buffer
472 */
473 struct igc_tx_buffer {
474 union igc_adv_tx_desc *next_to_watch;
475 unsigned long time_stamp;
476 enum igc_tx_buffer_type type;
477 union {
478 struct sk_buff *skb;
479 struct xdp_frame *xdpf;
480 };
481 unsigned int bytecount;
482 u16 gso_segs;
483 __be16 protocol;
484
485 DEFINE_DMA_UNMAP_ADDR(dma);
486 DEFINE_DMA_UNMAP_LEN(len);
487 u32 tx_flags;
488 };
489
490 struct igc_rx_buffer {
491 union {
492 struct {
493 dma_addr_t dma;
494 struct page *page;
495 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
496 __u32 page_offset;
497 #else
498 __u16 page_offset;
499 #endif
500 __u16 pagecnt_bias;
501 };
502 struct xdp_buff *xdp;
503 };
504 };
505
506 struct igc_q_vector {
507 struct igc_adapter *adapter; /* backlink */
508 void __iomem *itr_register;
509 u32 eims_value; /* EIMS mask value */
510
511 u16 itr_val;
512 u8 set_itr;
513
514 struct igc_ring_container rx, tx;
515
516 struct napi_struct napi;
517
518 struct rcu_head rcu; /* to avoid race with update stats on free */
519 char name[IFNAMSIZ + 9];
520 struct net_device poll_dev;
521
522 /* for dynamic allocation of rings associated with this q_vector */
523 struct igc_ring ring[] ____cacheline_internodealigned_in_smp;
524 };
525
526 enum igc_filter_match_flags {
527 IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
528 IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
529 IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
530 IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
531 IGC_FILTER_FLAG_USER_DATA = BIT(4),
532 IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
533 };
534
535 struct igc_nfc_filter {
536 u8 match_flags;
537 u16 etype;
538 __be16 vlan_etype;
539 u16 vlan_tci;
540 u16 vlan_tci_mask;
541 u8 src_addr[ETH_ALEN];
542 u8 dst_addr[ETH_ALEN];
543 u8 user_data[8];
544 u8 user_mask[8];
545 u8 flex_index;
546 u8 rx_queue;
547 u8 prio;
548 u8 immediate_irq;
549 u8 drop;
550 };
551
552 struct igc_nfc_rule {
553 struct list_head list;
554 struct igc_nfc_filter filter;
555 u32 location;
556 u16 action;
557 bool flex;
558 };
559
560 /* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
561 * based, 8 ethertype based and 32 Flex filter based rules.
562 */
563 #define IGC_MAX_RXNFC_RULES 64
564
565 struct igc_flex_filter {
566 u8 index;
567 u8 data[128];
568 u8 mask[16];
569 u8 length;
570 u8 rx_queue;
571 u8 prio;
572 u8 immediate_irq;
573 u8 drop;
574 };
575
576 /* igc_desc_unused - calculate if we have unused descriptors */
igc_desc_unused(const struct igc_ring * ring)577 static inline u16 igc_desc_unused(const struct igc_ring *ring)
578 {
579 u16 ntc = ring->next_to_clean;
580 u16 ntu = ring->next_to_use;
581
582 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
583 }
584
igc_get_phy_info(struct igc_hw * hw)585 static inline s32 igc_get_phy_info(struct igc_hw *hw)
586 {
587 if (hw->phy.ops.get_phy_info)
588 return hw->phy.ops.get_phy_info(hw);
589
590 return 0;
591 }
592
igc_reset_phy(struct igc_hw * hw)593 static inline s32 igc_reset_phy(struct igc_hw *hw)
594 {
595 if (hw->phy.ops.reset)
596 return hw->phy.ops.reset(hw);
597
598 return 0;
599 }
600
txring_txq(const struct igc_ring * tx_ring)601 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring)
602 {
603 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
604 }
605
606 enum igc_ring_flags_t {
607 IGC_RING_FLAG_RX_3K_BUFFER,
608 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED,
609 IGC_RING_FLAG_RX_SCTP_CSUM,
610 IGC_RING_FLAG_RX_LB_VLAN_BSWAP,
611 IGC_RING_FLAG_TX_CTX_IDX,
612 IGC_RING_FLAG_TX_DETECT_HANG,
613 IGC_RING_FLAG_AF_XDP_ZC,
614 };
615
616 #define ring_uses_large_buffer(ring) \
617 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
618 #define set_ring_uses_large_buffer(ring) \
619 set_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
620 #define clear_ring_uses_large_buffer(ring) \
621 clear_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
622
623 #define ring_uses_build_skb(ring) \
624 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
625
igc_rx_bufsz(struct igc_ring * ring)626 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring)
627 {
628 #if (PAGE_SIZE < 8192)
629 if (ring_uses_large_buffer(ring))
630 return IGC_RXBUFFER_3072;
631
632 if (ring_uses_build_skb(ring))
633 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN;
634 #endif
635 return IGC_RXBUFFER_2048;
636 }
637
igc_rx_pg_order(struct igc_ring * ring)638 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring)
639 {
640 #if (PAGE_SIZE < 8192)
641 if (ring_uses_large_buffer(ring))
642 return 1;
643 #endif
644 return 0;
645 }
646
igc_read_phy_reg(struct igc_hw * hw,u32 offset,u16 * data)647 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data)
648 {
649 if (hw->phy.ops.read_reg)
650 return hw->phy.ops.read_reg(hw, offset, data);
651
652 return -EOPNOTSUPP;
653 }
654
655 void igc_reinit_locked(struct igc_adapter *);
656 struct igc_nfc_rule *igc_get_nfc_rule(struct igc_adapter *adapter,
657 u32 location);
658 int igc_add_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
659 void igc_del_nfc_rule(struct igc_adapter *adapter, struct igc_nfc_rule *rule);
660
661 void igc_ptp_init(struct igc_adapter *adapter);
662 void igc_ptp_reset(struct igc_adapter *adapter);
663 void igc_ptp_suspend(struct igc_adapter *adapter);
664 void igc_ptp_stop(struct igc_adapter *adapter);
665 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf);
666 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
667 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
668 void igc_ptp_tx_hang(struct igc_adapter *adapter);
669 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts);
670
671 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring))
672
673 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS)
674
675 #define IGC_RX_DESC(R, i) \
676 (&(((union igc_adv_rx_desc *)((R)->desc))[i]))
677 #define IGC_TX_DESC(R, i) \
678 (&(((union igc_adv_tx_desc *)((R)->desc))[i]))
679 #define IGC_TX_CTXTDESC(R, i) \
680 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i]))
681
682 #endif /* _IGC_H_ */
683