• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Admin Function driver
3  *
4  * Copyright (C) 2018 Marvell.
5  *
6  */
7 
8 #include <linux/types.h>
9 #include <linux/module.h>
10 #include <linux/pci.h>
11 
12 #include "rvu.h"
13 #include "cgx.h"
14 #include "lmac_common.h"
15 #include "rvu_reg.h"
16 #include "rvu_trace.h"
17 
18 struct cgx_evq_entry {
19 	struct list_head evq_node;
20 	struct cgx_link_event link_event;
21 };
22 
23 #define M(_name, _id, _fn_name, _req_type, _rsp_type)			\
24 static struct _req_type __maybe_unused					\
25 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid)		\
26 {									\
27 	struct _req_type *req;						\
28 									\
29 	req = (struct _req_type *)otx2_mbox_alloc_msg_rsp(		\
30 		&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
31 		sizeof(struct _rsp_type));				\
32 	if (!req)							\
33 		return NULL;						\
34 	req->hdr.sig = OTX2_MBOX_REQ_SIG;				\
35 	req->hdr.id = _id;						\
36 	trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req));		\
37 	return req;							\
38 }
39 
40 MBOX_UP_CGX_MESSAGES
41 #undef M
42 
is_mac_feature_supported(struct rvu * rvu,int pf,int feature)43 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
44 {
45 	u8 cgx_id, lmac_id;
46 	void *cgxd;
47 
48 	if (!is_pf_cgxmapped(rvu, pf))
49 		return 0;
50 
51 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
52 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
53 
54 	return  (cgx_features_get(cgxd) & feature);
55 }
56 
57 /* Returns bitmap of mapped PFs */
cgxlmac_to_pfmap(struct rvu * rvu,u8 cgx_id,u8 lmac_id)58 static u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
59 {
60 	return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
61 }
62 
cgxlmac_to_pf(struct rvu * rvu,int cgx_id,int lmac_id)63 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
64 {
65 	unsigned long pfmap;
66 
67 	pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
68 
69 	/* Assumes only one pf mapped to a cgx lmac port */
70 	if (!pfmap)
71 		return -ENODEV;
72 	else
73 		return find_first_bit(&pfmap, 16);
74 }
75 
cgxlmac_id_to_bmap(u8 cgx_id,u8 lmac_id)76 static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
77 {
78 	return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
79 }
80 
rvu_cgx_pdata(u8 cgx_id,struct rvu * rvu)81 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
82 {
83 	if (cgx_id >= rvu->cgx_cnt_max)
84 		return NULL;
85 
86 	return rvu->cgx_idmap[cgx_id];
87 }
88 
89 /* Return first enabled CGX instance if none are enabled then return NULL */
rvu_first_cgx_pdata(struct rvu * rvu)90 void *rvu_first_cgx_pdata(struct rvu *rvu)
91 {
92 	int first_enabled_cgx = 0;
93 	void *cgxd = NULL;
94 
95 	for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
96 		cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
97 		if (cgxd)
98 			break;
99 	}
100 
101 	return cgxd;
102 }
103 
104 /* Based on P2X connectivity find mapped NIX block for a PF */
rvu_map_cgx_nix_block(struct rvu * rvu,int pf,int cgx_id,int lmac_id)105 static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
106 				  int cgx_id, int lmac_id)
107 {
108 	struct rvu_pfvf *pfvf = &rvu->pf[pf];
109 	u8 p2x;
110 
111 	p2x = cgx_lmac_get_p2x(cgx_id, lmac_id);
112 	/* Firmware sets P2X_SELECT as either NIX0 or NIX1 */
113 	pfvf->nix_blkaddr = BLKADDR_NIX0;
114 	if (is_rvu_supports_nix1(rvu) && p2x == CMR_P2X_SEL_NIX1)
115 		pfvf->nix_blkaddr = BLKADDR_NIX1;
116 }
117 
rvu_map_cgx_lmac_pf(struct rvu * rvu)118 static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
119 {
120 	struct npc_pkind *pkind = &rvu->hw->pkind;
121 	int cgx_cnt_max = rvu->cgx_cnt_max;
122 	int pf = PF_CGXMAP_BASE;
123 	unsigned long lmac_bmap;
124 	int size, free_pkind;
125 	int cgx, lmac, iter;
126 	int numvfs, hwvfs;
127 
128 	if (!cgx_cnt_max)
129 		return 0;
130 
131 	if (cgx_cnt_max > 0xF || MAX_LMAC_PER_CGX > 0xF)
132 		return -EINVAL;
133 
134 	/* Alloc map table
135 	 * An additional entry is required since PF id starts from 1 and
136 	 * hence entry at offset 0 is invalid.
137 	 */
138 	size = (cgx_cnt_max * MAX_LMAC_PER_CGX + 1) * sizeof(u8);
139 	rvu->pf2cgxlmac_map = devm_kmalloc(rvu->dev, size, GFP_KERNEL);
140 	if (!rvu->pf2cgxlmac_map)
141 		return -ENOMEM;
142 
143 	/* Initialize all entries with an invalid cgx and lmac id */
144 	memset(rvu->pf2cgxlmac_map, 0xFF, size);
145 
146 	/* Reverse map table */
147 	rvu->cgxlmac2pf_map = devm_kzalloc(rvu->dev,
148 				  cgx_cnt_max * MAX_LMAC_PER_CGX * sizeof(u16),
149 				  GFP_KERNEL);
150 	if (!rvu->cgxlmac2pf_map)
151 		return -ENOMEM;
152 
153 	rvu->cgx_mapped_pfs = 0;
154 	for (cgx = 0; cgx < cgx_cnt_max; cgx++) {
155 		if (!rvu_cgx_pdata(cgx, rvu))
156 			continue;
157 		lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu));
158 		for_each_set_bit(iter, &lmac_bmap, MAX_LMAC_PER_CGX) {
159 			lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu),
160 					      iter);
161 			rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
162 			rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
163 			free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
164 			pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
165 			rvu_map_cgx_nix_block(rvu, pf, cgx, lmac);
166 			rvu->cgx_mapped_pfs++;
167 			rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvfs);
168 			rvu->cgx_mapped_vfs += numvfs;
169 			pf++;
170 		}
171 	}
172 	return 0;
173 }
174 
rvu_cgx_send_link_info(int cgx_id,int lmac_id,struct rvu * rvu)175 static int rvu_cgx_send_link_info(int cgx_id, int lmac_id, struct rvu *rvu)
176 {
177 	struct cgx_evq_entry *qentry;
178 	unsigned long flags;
179 	int err;
180 
181 	qentry = kmalloc(sizeof(*qentry), GFP_KERNEL);
182 	if (!qentry)
183 		return -ENOMEM;
184 
185 	/* Lock the event queue before we read the local link status */
186 	spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
187 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
188 				&qentry->link_event.link_uinfo);
189 	qentry->link_event.cgx_id = cgx_id;
190 	qentry->link_event.lmac_id = lmac_id;
191 	if (err) {
192 		kfree(qentry);
193 		goto skip_add;
194 	}
195 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
196 skip_add:
197 	spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
198 
199 	/* start worker to process the events */
200 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
201 
202 	return 0;
203 }
204 
205 /* This is called from interrupt context and is expected to be atomic */
cgx_lmac_postevent(struct cgx_link_event * event,void * data)206 static int cgx_lmac_postevent(struct cgx_link_event *event, void *data)
207 {
208 	struct cgx_evq_entry *qentry;
209 	struct rvu *rvu = data;
210 
211 	/* post event to the event queue */
212 	qentry = kmalloc(sizeof(*qentry), GFP_ATOMIC);
213 	if (!qentry)
214 		return -ENOMEM;
215 	qentry->link_event = *event;
216 	spin_lock(&rvu->cgx_evq_lock);
217 	list_add_tail(&qentry->evq_node, &rvu->cgx_evq_head);
218 	spin_unlock(&rvu->cgx_evq_lock);
219 
220 	/* start worker to process the events */
221 	queue_work(rvu->cgx_evh_wq, &rvu->cgx_evh_work);
222 
223 	return 0;
224 }
225 
cgx_notify_pfs(struct cgx_link_event * event,struct rvu * rvu)226 static void cgx_notify_pfs(struct cgx_link_event *event, struct rvu *rvu)
227 {
228 	struct cgx_link_user_info *linfo;
229 	struct cgx_link_info_msg *msg;
230 	unsigned long pfmap;
231 	int err, pfid;
232 
233 	linfo = &event->link_uinfo;
234 	pfmap = cgxlmac_to_pfmap(rvu, event->cgx_id, event->lmac_id);
235 
236 	do {
237 		pfid = find_first_bit(&pfmap, 16);
238 		clear_bit(pfid, &pfmap);
239 
240 		/* check if notification is enabled */
241 		if (!test_bit(pfid, &rvu->pf_notify_bmap)) {
242 			dev_info(rvu->dev, "cgx %d: lmac %d Link status %s\n",
243 				 event->cgx_id, event->lmac_id,
244 				 linfo->link_up ? "UP" : "DOWN");
245 			continue;
246 		}
247 
248 		/* Send mbox message to PF */
249 		msg = otx2_mbox_alloc_msg_cgx_link_event(rvu, pfid);
250 		if (!msg)
251 			continue;
252 		msg->link_info = *linfo;
253 		otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, pfid);
254 		err = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, pfid);
255 		if (err)
256 			dev_warn(rvu->dev, "notification to pf %d failed\n",
257 				 pfid);
258 	} while (pfmap);
259 }
260 
cgx_evhandler_task(struct work_struct * work)261 static void cgx_evhandler_task(struct work_struct *work)
262 {
263 	struct rvu *rvu = container_of(work, struct rvu, cgx_evh_work);
264 	struct cgx_evq_entry *qentry;
265 	struct cgx_link_event *event;
266 	unsigned long flags;
267 
268 	do {
269 		/* Dequeue an event */
270 		spin_lock_irqsave(&rvu->cgx_evq_lock, flags);
271 		qentry = list_first_entry_or_null(&rvu->cgx_evq_head,
272 						  struct cgx_evq_entry,
273 						  evq_node);
274 		if (qentry)
275 			list_del(&qentry->evq_node);
276 		spin_unlock_irqrestore(&rvu->cgx_evq_lock, flags);
277 		if (!qentry)
278 			break; /* nothing more to process */
279 
280 		event = &qentry->link_event;
281 
282 		/* process event */
283 		cgx_notify_pfs(event, rvu);
284 		kfree(qentry);
285 	} while (1);
286 }
287 
cgx_lmac_event_handler_init(struct rvu * rvu)288 static int cgx_lmac_event_handler_init(struct rvu *rvu)
289 {
290 	unsigned long lmac_bmap;
291 	struct cgx_event_cb cb;
292 	int cgx, lmac, err;
293 	void *cgxd;
294 
295 	spin_lock_init(&rvu->cgx_evq_lock);
296 	INIT_LIST_HEAD(&rvu->cgx_evq_head);
297 	INIT_WORK(&rvu->cgx_evh_work, cgx_evhandler_task);
298 	rvu->cgx_evh_wq = alloc_workqueue("rvu_evh_wq", 0, 0);
299 	if (!rvu->cgx_evh_wq) {
300 		dev_err(rvu->dev, "alloc workqueue failed");
301 		return -ENOMEM;
302 	}
303 
304 	cb.notify_link_chg = cgx_lmac_postevent; /* link change call back */
305 	cb.data = rvu;
306 
307 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
308 		cgxd = rvu_cgx_pdata(cgx, rvu);
309 		if (!cgxd)
310 			continue;
311 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
312 		for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX) {
313 			err = cgx_lmac_evh_register(&cb, cgxd, lmac);
314 			if (err)
315 				dev_err(rvu->dev,
316 					"%d:%d handler register failed\n",
317 					cgx, lmac);
318 		}
319 	}
320 
321 	return 0;
322 }
323 
rvu_cgx_wq_destroy(struct rvu * rvu)324 static void rvu_cgx_wq_destroy(struct rvu *rvu)
325 {
326 	if (rvu->cgx_evh_wq) {
327 		flush_workqueue(rvu->cgx_evh_wq);
328 		destroy_workqueue(rvu->cgx_evh_wq);
329 		rvu->cgx_evh_wq = NULL;
330 	}
331 }
332 
rvu_cgx_init(struct rvu * rvu)333 int rvu_cgx_init(struct rvu *rvu)
334 {
335 	int cgx, err;
336 	void *cgxd;
337 
338 	/* CGX port id starts from 0 and are not necessarily contiguous
339 	 * Hence we allocate resources based on the maximum port id value.
340 	 */
341 	rvu->cgx_cnt_max = cgx_get_cgxcnt_max();
342 	if (!rvu->cgx_cnt_max) {
343 		dev_info(rvu->dev, "No CGX devices found!\n");
344 		return -ENODEV;
345 	}
346 
347 	rvu->cgx_idmap = devm_kzalloc(rvu->dev, rvu->cgx_cnt_max *
348 				      sizeof(void *), GFP_KERNEL);
349 	if (!rvu->cgx_idmap)
350 		return -ENOMEM;
351 
352 	/* Initialize the cgxdata table */
353 	for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++)
354 		rvu->cgx_idmap[cgx] = cgx_get_pdata(cgx);
355 
356 	/* Map CGX LMAC interfaces to RVU PFs */
357 	err = rvu_map_cgx_lmac_pf(rvu);
358 	if (err)
359 		return err;
360 
361 	/* Register for CGX events */
362 	err = cgx_lmac_event_handler_init(rvu);
363 	if (err)
364 		return err;
365 
366 	mutex_init(&rvu->cgx_cfg_lock);
367 
368 	/* Ensure event handler registration is completed, before
369 	 * we turn on the links
370 	 */
371 	mb();
372 
373 	/* Do link up for all CGX ports */
374 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
375 		cgxd = rvu_cgx_pdata(cgx, rvu);
376 		if (!cgxd)
377 			continue;
378 		err = cgx_lmac_linkup_start(cgxd);
379 		if (err)
380 			dev_err(rvu->dev,
381 				"Link up process failed to start on cgx %d\n",
382 				cgx);
383 	}
384 
385 	return 0;
386 }
387 
rvu_cgx_exit(struct rvu * rvu)388 int rvu_cgx_exit(struct rvu *rvu)
389 {
390 	unsigned long lmac_bmap;
391 	int cgx, lmac;
392 	void *cgxd;
393 
394 	for (cgx = 0; cgx <= rvu->cgx_cnt_max; cgx++) {
395 		cgxd = rvu_cgx_pdata(cgx, rvu);
396 		if (!cgxd)
397 			continue;
398 		lmac_bmap = cgx_get_lmac_bmap(cgxd);
399 		for_each_set_bit(lmac, &lmac_bmap, MAX_LMAC_PER_CGX)
400 			cgx_lmac_evh_unregister(cgxd, lmac);
401 	}
402 
403 	/* Ensure event handler unregister is completed */
404 	mb();
405 
406 	rvu_cgx_wq_destroy(rvu);
407 	return 0;
408 }
409 
410 /* Most of the CGX configuration is restricted to the mapped PF only,
411  * VF's of mapped PF and other PFs are not allowed. This fn() checks
412  * whether a PFFUNC is permitted to do the config or not.
413  */
is_cgx_config_permitted(struct rvu * rvu,u16 pcifunc)414 inline bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc)
415 {
416 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
417 	    !is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
418 		return false;
419 	return true;
420 }
421 
rvu_cgx_enadis_rx_bp(struct rvu * rvu,int pf,bool enable)422 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable)
423 {
424 	struct mac_ops *mac_ops;
425 	u8 cgx_id, lmac_id;
426 	void *cgxd;
427 
428 	if (!is_pf_cgxmapped(rvu, pf))
429 		return;
430 
431 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
432 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
433 
434 	mac_ops = get_mac_ops(cgxd);
435 	/* Set / clear CTL_BCK to control pause frame forwarding to NIX */
436 	if (enable)
437 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true);
438 	else
439 		mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false);
440 }
441 
rvu_cgx_config_rxtx(struct rvu * rvu,u16 pcifunc,bool start)442 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start)
443 {
444 	int pf = rvu_get_pf(pcifunc);
445 	struct mac_ops *mac_ops;
446 	u8 cgx_id, lmac_id;
447 	void *cgxd;
448 
449 	if (!is_cgx_config_permitted(rvu, pcifunc))
450 		return LMAC_AF_ERR_PERM_DENIED;
451 
452 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
453 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
454 	mac_ops = get_mac_ops(cgxd);
455 
456 	return mac_ops->mac_rx_tx_enable(cgxd, lmac_id, start);
457 }
458 
rvu_cgx_tx_enable(struct rvu * rvu,u16 pcifunc,bool enable)459 int rvu_cgx_tx_enable(struct rvu *rvu, u16 pcifunc, bool enable)
460 {
461 	int pf = rvu_get_pf(pcifunc);
462 	struct mac_ops *mac_ops;
463 	u8 cgx_id, lmac_id;
464 	void *cgxd;
465 
466 	if (!is_cgx_config_permitted(rvu, pcifunc))
467 		return LMAC_AF_ERR_PERM_DENIED;
468 
469 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
470 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
471 	mac_ops = get_mac_ops(cgxd);
472 
473 	return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);
474 }
475 
rvu_cgx_config_tx(void * cgxd,int lmac_id,bool enable)476 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable)
477 {
478 	struct mac_ops *mac_ops;
479 
480 	mac_ops = get_mac_ops(cgxd);
481 	return mac_ops->mac_tx_enable(cgxd, lmac_id, enable);
482 }
483 
rvu_cgx_disable_dmac_entries(struct rvu * rvu,u16 pcifunc)484 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc)
485 {
486 	int pf = rvu_get_pf(pcifunc);
487 	int i = 0, lmac_count = 0;
488 	u8 max_dmac_filters;
489 	u8 cgx_id, lmac_id;
490 	void *cgx_dev;
491 
492 	if (!is_cgx_config_permitted(rvu, pcifunc))
493 		return;
494 
495 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
496 	cgx_dev = cgx_get_pdata(cgx_id);
497 	lmac_count = cgx_get_lmac_cnt(cgx_dev);
498 	max_dmac_filters = MAX_DMAC_ENTRIES_PER_CGX / lmac_count;
499 
500 	for (i = 0; i < max_dmac_filters; i++)
501 		cgx_lmac_addr_del(cgx_id, lmac_id, i);
502 
503 	/* As cgx_lmac_addr_del does not clear entry for index 0
504 	 * so it needs to be done explicitly
505 	 */
506 	cgx_lmac_addr_reset(cgx_id, lmac_id);
507 }
508 
rvu_mbox_handler_cgx_start_rxtx(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)509 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
510 				    struct msg_rsp *rsp)
511 {
512 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, true);
513 	return 0;
514 }
515 
rvu_mbox_handler_cgx_stop_rxtx(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)516 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
517 				   struct msg_rsp *rsp)
518 {
519 	rvu_cgx_config_rxtx(rvu, req->hdr.pcifunc, false);
520 	return 0;
521 }
522 
rvu_lmac_get_stats(struct rvu * rvu,struct msg_req * req,void * rsp)523 static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req,
524 			      void *rsp)
525 {
526 	int pf = rvu_get_pf(req->hdr.pcifunc);
527 	struct mac_ops *mac_ops;
528 	int stat = 0, err = 0;
529 	u64 tx_stat, rx_stat;
530 	u8 cgx_idx, lmac;
531 	void *cgxd;
532 
533 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
534 		return LMAC_AF_ERR_PERM_DENIED;
535 
536 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
537 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
538 	mac_ops = get_mac_ops(cgxd);
539 
540 	/* Rx stats */
541 	while (stat < mac_ops->rx_stats_cnt) {
542 		err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat);
543 		if (err)
544 			return err;
545 		if (mac_ops->rx_stats_cnt == RPM_RX_STATS_COUNT)
546 			((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
547 		else
548 			((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat;
549 		stat++;
550 	}
551 
552 	/* Tx stats */
553 	stat = 0;
554 	while (stat < mac_ops->tx_stats_cnt) {
555 		err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat);
556 		if (err)
557 			return err;
558 		if (mac_ops->tx_stats_cnt == RPM_TX_STATS_COUNT)
559 			((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
560 		else
561 			((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat;
562 		stat++;
563 	}
564 	return 0;
565 }
566 
rvu_mbox_handler_cgx_stats(struct rvu * rvu,struct msg_req * req,struct cgx_stats_rsp * rsp)567 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
568 			       struct cgx_stats_rsp *rsp)
569 {
570 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
571 }
572 
rvu_mbox_handler_rpm_stats(struct rvu * rvu,struct msg_req * req,struct rpm_stats_rsp * rsp)573 int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req,
574 			       struct rpm_stats_rsp *rsp)
575 {
576 	return rvu_lmac_get_stats(rvu, req, (void *)rsp);
577 }
578 
rvu_mbox_handler_cgx_fec_stats(struct rvu * rvu,struct msg_req * req,struct cgx_fec_stats_rsp * rsp)579 int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu,
580 				   struct msg_req *req,
581 				   struct cgx_fec_stats_rsp *rsp)
582 {
583 	int pf = rvu_get_pf(req->hdr.pcifunc);
584 	u8 cgx_idx, lmac;
585 	void *cgxd;
586 
587 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
588 		return LMAC_AF_ERR_PERM_DENIED;
589 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
590 
591 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
592 	return cgx_get_fec_stats(cgxd, lmac, rsp);
593 }
594 
rvu_mbox_handler_cgx_mac_addr_set(struct rvu * rvu,struct cgx_mac_addr_set_or_get * req,struct cgx_mac_addr_set_or_get * rsp)595 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
596 				      struct cgx_mac_addr_set_or_get *req,
597 				      struct cgx_mac_addr_set_or_get *rsp)
598 {
599 	int pf = rvu_get_pf(req->hdr.pcifunc);
600 	u8 cgx_id, lmac_id;
601 
602 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
603 		return -EPERM;
604 
605 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
606 
607 	cgx_lmac_addr_set(cgx_id, lmac_id, req->mac_addr);
608 
609 	return 0;
610 }
611 
rvu_mbox_handler_cgx_mac_addr_add(struct rvu * rvu,struct cgx_mac_addr_add_req * req,struct cgx_mac_addr_add_rsp * rsp)612 int rvu_mbox_handler_cgx_mac_addr_add(struct rvu *rvu,
613 				      struct cgx_mac_addr_add_req *req,
614 				      struct cgx_mac_addr_add_rsp *rsp)
615 {
616 	int pf = rvu_get_pf(req->hdr.pcifunc);
617 	u8 cgx_id, lmac_id;
618 	int rc = 0;
619 
620 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
621 		return -EPERM;
622 
623 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
624 	rc = cgx_lmac_addr_add(cgx_id, lmac_id, req->mac_addr);
625 	if (rc >= 0) {
626 		rsp->index = rc;
627 		return 0;
628 	}
629 
630 	return rc;
631 }
632 
rvu_mbox_handler_cgx_mac_addr_del(struct rvu * rvu,struct cgx_mac_addr_del_req * req,struct msg_rsp * rsp)633 int rvu_mbox_handler_cgx_mac_addr_del(struct rvu *rvu,
634 				      struct cgx_mac_addr_del_req *req,
635 				      struct msg_rsp *rsp)
636 {
637 	int pf = rvu_get_pf(req->hdr.pcifunc);
638 	u8 cgx_id, lmac_id;
639 
640 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
641 		return -EPERM;
642 
643 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
644 	return cgx_lmac_addr_del(cgx_id, lmac_id, req->index);
645 }
646 
rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu * rvu,struct msg_req * req,struct cgx_max_dmac_entries_get_rsp * rsp)647 int rvu_mbox_handler_cgx_mac_max_entries_get(struct rvu *rvu,
648 					     struct msg_req *req,
649 					     struct cgx_max_dmac_entries_get_rsp
650 					     *rsp)
651 {
652 	int pf = rvu_get_pf(req->hdr.pcifunc);
653 	u8 cgx_id, lmac_id;
654 
655 	/* If msg is received from PFs(which are not mapped to CGX LMACs)
656 	 * or VF then no entries are allocated for DMAC filters at CGX level.
657 	 * So returning zero.
658 	 */
659 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) {
660 		rsp->max_dmac_filters = 0;
661 		return 0;
662 	}
663 
664 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
665 	rsp->max_dmac_filters = cgx_lmac_addr_max_entries_get(cgx_id, lmac_id);
666 	return 0;
667 }
668 
rvu_mbox_handler_cgx_mac_addr_get(struct rvu * rvu,struct cgx_mac_addr_set_or_get * req,struct cgx_mac_addr_set_or_get * rsp)669 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
670 				      struct cgx_mac_addr_set_or_get *req,
671 				      struct cgx_mac_addr_set_or_get *rsp)
672 {
673 	int pf = rvu_get_pf(req->hdr.pcifunc);
674 	u8 cgx_id, lmac_id;
675 	int rc = 0, i;
676 	u64 cfg;
677 
678 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
679 		return -EPERM;
680 
681 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
682 
683 	rsp->hdr.rc = rc;
684 	cfg = cgx_lmac_addr_get(cgx_id, lmac_id);
685 	/* copy 48 bit mac address to req->mac_addr */
686 	for (i = 0; i < ETH_ALEN; i++)
687 		rsp->mac_addr[i] = cfg >> (ETH_ALEN - 1 - i) * 8;
688 	return 0;
689 }
690 
rvu_mbox_handler_cgx_promisc_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)691 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
692 					struct msg_rsp *rsp)
693 {
694 	u16 pcifunc = req->hdr.pcifunc;
695 	int pf = rvu_get_pf(pcifunc);
696 	u8 cgx_id, lmac_id;
697 
698 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
699 		return -EPERM;
700 
701 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
702 
703 	cgx_lmac_promisc_config(cgx_id, lmac_id, true);
704 	return 0;
705 }
706 
rvu_mbox_handler_cgx_promisc_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)707 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
708 					 struct msg_rsp *rsp)
709 {
710 	int pf = rvu_get_pf(req->hdr.pcifunc);
711 	u8 cgx_id, lmac_id;
712 
713 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
714 		return -EPERM;
715 
716 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
717 
718 	cgx_lmac_promisc_config(cgx_id, lmac_id, false);
719 	return 0;
720 }
721 
rvu_cgx_ptp_rx_cfg(struct rvu * rvu,u16 pcifunc,bool enable)722 static int rvu_cgx_ptp_rx_cfg(struct rvu *rvu, u16 pcifunc, bool enable)
723 {
724 	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
725 	int pf = rvu_get_pf(pcifunc);
726 	struct mac_ops *mac_ops;
727 	u8 cgx_id, lmac_id;
728 	void *cgxd;
729 
730 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_PTP))
731 		return 0;
732 
733 	/* This msg is expected only from PFs that are mapped to CGX LMACs,
734 	 * if received from other PF/VF simply ACK, nothing to do.
735 	 */
736 	if ((pcifunc & RVU_PFVF_FUNC_MASK) ||
737 	    !is_pf_cgxmapped(rvu, pf))
738 		return -ENODEV;
739 
740 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
741 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
742 
743 	mac_ops = get_mac_ops(cgxd);
744 	mac_ops->mac_enadis_ptp_config(cgxd, lmac_id, enable);
745 	/* If PTP is enabled then inform NPC that packets to be
746 	 * parsed by this PF will have their data shifted by 8 bytes
747 	 * and if PTP is disabled then no shift is required
748 	 */
749 	if (npc_config_ts_kpuaction(rvu, pf, pcifunc, enable))
750 		return -EINVAL;
751 	/* This flag is required to clean up CGX conf if app gets killed */
752 	pfvf->hw_rx_tstamp_en = enable;
753 
754 	return 0;
755 }
756 
rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)757 int rvu_mbox_handler_cgx_ptp_rx_enable(struct rvu *rvu, struct msg_req *req,
758 				       struct msg_rsp *rsp)
759 {
760 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, true);
761 }
762 
rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)763 int rvu_mbox_handler_cgx_ptp_rx_disable(struct rvu *rvu, struct msg_req *req,
764 					struct msg_rsp *rsp)
765 {
766 	return rvu_cgx_ptp_rx_cfg(rvu, req->hdr.pcifunc, false);
767 }
768 
rvu_cgx_config_linkevents(struct rvu * rvu,u16 pcifunc,bool en)769 static int rvu_cgx_config_linkevents(struct rvu *rvu, u16 pcifunc, bool en)
770 {
771 	int pf = rvu_get_pf(pcifunc);
772 	u8 cgx_id, lmac_id;
773 
774 	if (!is_cgx_config_permitted(rvu, pcifunc))
775 		return -EPERM;
776 
777 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
778 
779 	if (en) {
780 		set_bit(pf, &rvu->pf_notify_bmap);
781 		/* Send the current link status to PF */
782 		rvu_cgx_send_link_info(cgx_id, lmac_id, rvu);
783 	} else {
784 		clear_bit(pf, &rvu->pf_notify_bmap);
785 	}
786 
787 	return 0;
788 }
789 
rvu_mbox_handler_cgx_start_linkevents(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)790 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
791 					  struct msg_rsp *rsp)
792 {
793 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, true);
794 	return 0;
795 }
796 
rvu_mbox_handler_cgx_stop_linkevents(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)797 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
798 					 struct msg_rsp *rsp)
799 {
800 	rvu_cgx_config_linkevents(rvu, req->hdr.pcifunc, false);
801 	return 0;
802 }
803 
rvu_mbox_handler_cgx_get_linkinfo(struct rvu * rvu,struct msg_req * req,struct cgx_link_info_msg * rsp)804 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
805 				      struct cgx_link_info_msg *rsp)
806 {
807 	u8 cgx_id, lmac_id;
808 	int pf, err;
809 
810 	pf = rvu_get_pf(req->hdr.pcifunc);
811 
812 	if (!is_pf_cgxmapped(rvu, pf))
813 		return -ENODEV;
814 
815 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
816 
817 	err = cgx_get_link_info(rvu_cgx_pdata(cgx_id, rvu), lmac_id,
818 				&rsp->link_info);
819 	return err;
820 }
821 
rvu_mbox_handler_cgx_features_get(struct rvu * rvu,struct msg_req * req,struct cgx_features_info_msg * rsp)822 int rvu_mbox_handler_cgx_features_get(struct rvu *rvu,
823 				      struct msg_req *req,
824 				      struct cgx_features_info_msg *rsp)
825 {
826 	int pf = rvu_get_pf(req->hdr.pcifunc);
827 	u8 cgx_idx, lmac;
828 	void *cgxd;
829 
830 	if (!is_pf_cgxmapped(rvu, pf))
831 		return 0;
832 
833 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
834 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
835 	rsp->lmac_features = cgx_features_get(cgxd);
836 
837 	return 0;
838 }
839 
rvu_cgx_get_fifolen(struct rvu * rvu)840 u32 rvu_cgx_get_fifolen(struct rvu *rvu)
841 {
842 	struct mac_ops *mac_ops;
843 	u32 fifo_len;
844 
845 	mac_ops = get_mac_ops(rvu_first_cgx_pdata(rvu));
846 	fifo_len = mac_ops ? mac_ops->fifo_len : 0;
847 
848 	return fifo_len;
849 }
850 
rvu_cgx_get_lmac_fifolen(struct rvu * rvu,int cgx,int lmac)851 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac)
852 {
853 	struct mac_ops *mac_ops;
854 	void *cgxd;
855 
856 	cgxd = rvu_cgx_pdata(cgx, rvu);
857 	if (!cgxd)
858 		return 0;
859 
860 	mac_ops = get_mac_ops(cgxd);
861 	if (!mac_ops->lmac_fifo_len)
862 		return 0;
863 
864 	return mac_ops->lmac_fifo_len(cgxd, lmac);
865 }
866 
rvu_cgx_config_intlbk(struct rvu * rvu,u16 pcifunc,bool en)867 static int rvu_cgx_config_intlbk(struct rvu *rvu, u16 pcifunc, bool en)
868 {
869 	int pf = rvu_get_pf(pcifunc);
870 	struct mac_ops *mac_ops;
871 	u8 cgx_id, lmac_id;
872 
873 	if (!is_cgx_config_permitted(rvu, pcifunc))
874 		return -EPERM;
875 
876 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
877 	mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu));
878 
879 	return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
880 					  lmac_id, en);
881 }
882 
rvu_mbox_handler_cgx_intlbk_enable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)883 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
884 				       struct msg_rsp *rsp)
885 {
886 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, true);
887 	return 0;
888 }
889 
rvu_mbox_handler_cgx_intlbk_disable(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)890 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
891 					struct msg_rsp *rsp)
892 {
893 	rvu_cgx_config_intlbk(rvu, req->hdr.pcifunc, false);
894 	return 0;
895 }
896 
rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu * rvu,struct cgx_pause_frm_cfg * req,struct cgx_pause_frm_cfg * rsp)897 int rvu_mbox_handler_cgx_cfg_pause_frm(struct rvu *rvu,
898 				       struct cgx_pause_frm_cfg *req,
899 				       struct cgx_pause_frm_cfg *rsp)
900 {
901 	int pf = rvu_get_pf(req->hdr.pcifunc);
902 	struct mac_ops *mac_ops;
903 	u8 cgx_id, lmac_id;
904 	void *cgxd;
905 
906 	if (!is_mac_feature_supported(rvu, pf, RVU_LMAC_FEAT_FC))
907 		return 0;
908 
909 	/* This msg is expected only from PF/VFs that are mapped to CGX LMACs,
910 	 * if received from other PF/VF simply ACK, nothing to do.
911 	 */
912 	if (!is_pf_cgxmapped(rvu, pf))
913 		return -ENODEV;
914 
915 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
916 	cgxd = rvu_cgx_pdata(cgx_id, rvu);
917 	mac_ops = get_mac_ops(cgxd);
918 
919 	if (req->set)
920 		mac_ops->mac_enadis_pause_frm(cgxd, lmac_id,
921 					      req->tx_pause, req->rx_pause);
922 	else
923 		mac_ops->mac_get_pause_frm_status(cgxd, lmac_id,
924 						  &rsp->tx_pause,
925 						  &rsp->rx_pause);
926 	return 0;
927 }
928 
rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)929 int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req,
930 					   struct msg_rsp *rsp)
931 {
932 	int pf = rvu_get_pf(req->hdr.pcifunc);
933 	u8 cgx_id, lmac_id;
934 
935 	if (!is_pf_cgxmapped(rvu, pf))
936 		return LMAC_AF_ERR_PF_NOT_MAPPED;
937 
938 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
939 	return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id);
940 }
941 
942 /* Finds cumulative status of NIX rx/tx counters from LF of a PF and those
943  * from its VFs as well. ie. NIX rx/tx counters at the CGX port level
944  */
rvu_cgx_nix_cuml_stats(struct rvu * rvu,void * cgxd,int lmac_id,int index,int rxtxflag,u64 * stat)945 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id,
946 			   int index, int rxtxflag, u64 *stat)
947 {
948 	struct rvu_block *block;
949 	int blkaddr;
950 	u16 pcifunc;
951 	int pf, lf;
952 
953 	*stat = 0;
954 
955 	if (!cgxd || !rvu)
956 		return -EINVAL;
957 
958 	pf = cgxlmac_to_pf(rvu, cgx_get_cgxid(cgxd), lmac_id);
959 	if (pf < 0)
960 		return pf;
961 
962 	/* Assumes LF of a PF and all of its VF belongs to the same
963 	 * NIX block
964 	 */
965 	pcifunc = pf << RVU_PFVF_PF_SHIFT;
966 	blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
967 	if (blkaddr < 0)
968 		return 0;
969 	block = &rvu->hw->block[blkaddr];
970 
971 	for (lf = 0; lf < block->lf.max; lf++) {
972 		/* Check if a lf is attached to this PF or one of its VFs */
973 		if (!((block->fn_map[lf] & ~RVU_PFVF_FUNC_MASK) == (pcifunc &
974 			 ~RVU_PFVF_FUNC_MASK)))
975 			continue;
976 		if (rxtxflag == NIX_STATS_RX)
977 			*stat += rvu_read64(rvu, blkaddr,
978 					    NIX_AF_LFX_RX_STATX(lf, index));
979 		else
980 			*stat += rvu_read64(rvu, blkaddr,
981 					    NIX_AF_LFX_TX_STATX(lf, index));
982 	}
983 
984 	return 0;
985 }
986 
rvu_cgx_start_stop_io(struct rvu * rvu,u16 pcifunc,bool start)987 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start)
988 {
989 	struct rvu_pfvf *parent_pf, *pfvf;
990 	int cgx_users, err = 0;
991 
992 	if (!is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)))
993 		return 0;
994 
995 	parent_pf = &rvu->pf[rvu_get_pf(pcifunc)];
996 	pfvf = rvu_get_pfvf(rvu, pcifunc);
997 
998 	mutex_lock(&rvu->cgx_cfg_lock);
999 
1000 	if (start && pfvf->cgx_in_use)
1001 		goto exit;  /* CGX is already started hence nothing to do */
1002 	if (!start && !pfvf->cgx_in_use)
1003 		goto exit; /* CGX is already stopped hence nothing to do */
1004 
1005 	if (start) {
1006 		cgx_users = parent_pf->cgx_users;
1007 		parent_pf->cgx_users++;
1008 	} else {
1009 		parent_pf->cgx_users--;
1010 		cgx_users = parent_pf->cgx_users;
1011 	}
1012 
1013 	/* Start CGX when first of all NIXLFs is started.
1014 	 * Stop CGX when last of all NIXLFs is stopped.
1015 	 */
1016 	if (!cgx_users) {
1017 		err = rvu_cgx_config_rxtx(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK,
1018 					  start);
1019 		if (err) {
1020 			dev_err(rvu->dev, "Unable to %s CGX\n",
1021 				start ? "start" : "stop");
1022 			/* Revert the usage count in case of error */
1023 			parent_pf->cgx_users = start ? parent_pf->cgx_users  - 1
1024 					       : parent_pf->cgx_users  + 1;
1025 			goto exit;
1026 		}
1027 	}
1028 	pfvf->cgx_in_use = start;
1029 exit:
1030 	mutex_unlock(&rvu->cgx_cfg_lock);
1031 	return err;
1032 }
1033 
rvu_mbox_handler_cgx_set_fec_param(struct rvu * rvu,struct fec_mode * req,struct fec_mode * rsp)1034 int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu,
1035 				       struct fec_mode *req,
1036 				       struct fec_mode *rsp)
1037 {
1038 	int pf = rvu_get_pf(req->hdr.pcifunc);
1039 	u8 cgx_id, lmac_id;
1040 
1041 	if (!is_pf_cgxmapped(rvu, pf))
1042 		return -EPERM;
1043 
1044 	if (req->fec == OTX2_FEC_OFF)
1045 		req->fec = OTX2_FEC_NONE;
1046 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1047 	rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id);
1048 	return 0;
1049 }
1050 
rvu_mbox_handler_cgx_get_aux_link_info(struct rvu * rvu,struct msg_req * req,struct cgx_fw_data * rsp)1051 int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req,
1052 					   struct cgx_fw_data *rsp)
1053 {
1054 	int pf = rvu_get_pf(req->hdr.pcifunc);
1055 	u8 cgx_id, lmac_id;
1056 
1057 	if (!rvu->fwdata)
1058 		return -ENXIO;
1059 
1060 	if (!is_pf_cgxmapped(rvu, pf))
1061 		return -EPERM;
1062 
1063 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1064 
1065 	memcpy(&rsp->fwdata, &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id],
1066 	       sizeof(struct cgx_lmac_fwdata_s));
1067 	return 0;
1068 }
1069 
rvu_mbox_handler_cgx_set_link_mode(struct rvu * rvu,struct cgx_set_link_mode_req * req,struct cgx_set_link_mode_rsp * rsp)1070 int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu,
1071 				       struct cgx_set_link_mode_req *req,
1072 				       struct cgx_set_link_mode_rsp *rsp)
1073 {
1074 	int pf = rvu_get_pf(req->hdr.pcifunc);
1075 	u8 cgx_idx, lmac;
1076 	void *cgxd;
1077 
1078 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1079 		return -EPERM;
1080 
1081 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac);
1082 	cgxd = rvu_cgx_pdata(cgx_idx, rvu);
1083 	rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac);
1084 	return 0;
1085 }
1086 
rvu_mbox_handler_cgx_mac_addr_reset(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1087 int rvu_mbox_handler_cgx_mac_addr_reset(struct rvu *rvu, struct msg_req *req,
1088 					struct msg_rsp *rsp)
1089 {
1090 	int pf = rvu_get_pf(req->hdr.pcifunc);
1091 	u8 cgx_id, lmac_id;
1092 
1093 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1094 		return LMAC_AF_ERR_PERM_DENIED;
1095 
1096 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1097 	return cgx_lmac_addr_reset(cgx_id, lmac_id);
1098 }
1099 
rvu_mbox_handler_cgx_mac_addr_update(struct rvu * rvu,struct cgx_mac_addr_update_req * req,struct msg_rsp * rsp)1100 int rvu_mbox_handler_cgx_mac_addr_update(struct rvu *rvu,
1101 					 struct cgx_mac_addr_update_req *req,
1102 					 struct msg_rsp *rsp)
1103 {
1104 	int pf = rvu_get_pf(req->hdr.pcifunc);
1105 	u8 cgx_id, lmac_id;
1106 
1107 	if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc))
1108 		return LMAC_AF_ERR_PERM_DENIED;
1109 
1110 	rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
1111 	return cgx_lmac_addr_update(cgx_id, lmac_id, req->mac_addr, req->index);
1112 }
1113