1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
4 * Ethernet adapters. Based on earlier sk98lin, e100 and
5 * FreeBSD if_sk drivers.
6 *
7 * This driver intentionally does not support all the features
8 * of the original driver such as link fail-over and link management because
9 * those should be done at higher levels.
10 *
11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 */
13
14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16 #include <linux/in.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/netdevice.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/pci.h>
24 #include <linux/if_vlan.h>
25 #include <linux/ip.h>
26 #include <linux/delay.h>
27 #include <linux/crc32.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/debugfs.h>
30 #include <linux/sched.h>
31 #include <linux/seq_file.h>
32 #include <linux/mii.h>
33 #include <linux/slab.h>
34 #include <linux/dmi.h>
35 #include <linux/prefetch.h>
36 #include <asm/irq.h>
37
38 #include "skge.h"
39
40 #define DRV_NAME "skge"
41 #define DRV_VERSION "1.14"
42
43 #define DEFAULT_TX_RING_SIZE 128
44 #define DEFAULT_RX_RING_SIZE 512
45 #define MAX_TX_RING_SIZE 1024
46 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
47 #define MAX_RX_RING_SIZE 4096
48 #define RX_COPY_THRESHOLD 128
49 #define RX_BUF_SIZE 1536
50 #define PHY_RETRIES 1000
51 #define ETH_JUMBO_MTU 9000
52 #define TX_WATCHDOG (5 * HZ)
53 #define BLINK_MS 250
54 #define LINK_HZ HZ
55
56 #define SKGE_EEPROM_MAGIC 0x9933aabb
57
58
59 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
61 MODULE_LICENSE("GPL");
62 MODULE_VERSION(DRV_VERSION);
63
64 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
65 NETIF_MSG_LINK | NETIF_MSG_IFUP |
66 NETIF_MSG_IFDOWN);
67
68 static int debug = -1; /* defaults above */
69 module_param(debug, int, 0);
70 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72 static const struct pci_device_id skge_id_table[] = {
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
75 #ifdef CONFIG_SKGE_GENESIS
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
77 #endif
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct net_device *dev);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102 static void skge_set_multicast(struct net_device *dev);
103 static irqreturn_t skge_intr(int irq, void *dev_id);
104
105 /* Avoid conditionals by using array */
106 static const int txqaddr[] = { Q_XA1, Q_XA2 };
107 static const int rxqaddr[] = { Q_R1, Q_R2 };
108 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
109 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
110 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
111 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
112
is_genesis(const struct skge_hw * hw)113 static inline bool is_genesis(const struct skge_hw *hw)
114 {
115 #ifdef CONFIG_SKGE_GENESIS
116 return hw->chip_id == CHIP_ID_GENESIS;
117 #else
118 return false;
119 #endif
120 }
121
skge_get_regs_len(struct net_device * dev)122 static int skge_get_regs_len(struct net_device *dev)
123 {
124 return 0x4000;
125 }
126
127 /*
128 * Returns copy of whole control register region
129 * Note: skip RAM address register because accessing it will
130 * cause bus hangs!
131 */
skge_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)132 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
133 void *p)
134 {
135 const struct skge_port *skge = netdev_priv(dev);
136 const void __iomem *io = skge->hw->regs;
137
138 regs->version = 1;
139 memset(p, 0, regs->len);
140 memcpy_fromio(p, io, B3_RAM_ADDR);
141
142 if (regs->len > B3_RI_WTO_R1) {
143 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
144 regs->len - B3_RI_WTO_R1);
145 }
146 }
147
148 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
wol_supported(const struct skge_hw * hw)149 static u32 wol_supported(const struct skge_hw *hw)
150 {
151 if (is_genesis(hw))
152 return 0;
153
154 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
155 return 0;
156
157 return WAKE_MAGIC | WAKE_PHY;
158 }
159
skge_wol_init(struct skge_port * skge)160 static void skge_wol_init(struct skge_port *skge)
161 {
162 struct skge_hw *hw = skge->hw;
163 int port = skge->port;
164 u16 ctrl;
165
166 skge_write16(hw, B0_CTST, CS_RST_CLR);
167 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
168
169 /* Turn on Vaux */
170 skge_write8(hw, B0_POWER_CTRL,
171 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
172
173 /* WA code for COMA mode -- clear PHY reset */
174 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
175 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
176 u32 reg = skge_read32(hw, B2_GP_IO);
177 reg |= GP_DIR_9;
178 reg &= ~GP_IO_9;
179 skge_write32(hw, B2_GP_IO, reg);
180 }
181
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
183 GPC_DIS_SLEEP |
184 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
185 GPC_ANEG_1 | GPC_RST_SET);
186
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_CLR);
191
192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
193
194 /* Force to 10/100 skge_reset will re-enable on resume */
195 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
196 (PHY_AN_100FULL | PHY_AN_100HALF |
197 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
198 /* no 1000 HD/FD */
199 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
200 gm_phy_write(hw, port, PHY_MARV_CTRL,
201 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
202 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
203
204
205 /* Set GMAC to no flow control and auto update for speed/duplex */
206 gma_write16(hw, port, GM_GP_CTRL,
207 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
208 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
209
210 /* Set WOL address */
211 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
212 skge->netdev->dev_addr, ETH_ALEN);
213
214 /* Turn on appropriate WOL control bits */
215 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
216 ctrl = 0;
217 if (skge->wol & WAKE_PHY)
218 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
219 else
220 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
221
222 if (skge->wol & WAKE_MAGIC)
223 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
226
227 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
228 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
229
230 /* block receiver */
231 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
232 }
233
skge_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)234 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
235 {
236 struct skge_port *skge = netdev_priv(dev);
237
238 wol->supported = wol_supported(skge->hw);
239 wol->wolopts = skge->wol;
240 }
241
skge_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)242 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
243 {
244 struct skge_port *skge = netdev_priv(dev);
245 struct skge_hw *hw = skge->hw;
246
247 if ((wol->wolopts & ~wol_supported(hw)) ||
248 !device_can_wakeup(&hw->pdev->dev))
249 return -EOPNOTSUPP;
250
251 skge->wol = wol->wolopts;
252
253 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
254
255 return 0;
256 }
257
258 /* Determine supported/advertised modes based on hardware.
259 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
260 */
skge_supported_modes(const struct skge_hw * hw)261 static u32 skge_supported_modes(const struct skge_hw *hw)
262 {
263 u32 supported;
264
265 if (hw->copper) {
266 supported = (SUPPORTED_10baseT_Half |
267 SUPPORTED_10baseT_Full |
268 SUPPORTED_100baseT_Half |
269 SUPPORTED_100baseT_Full |
270 SUPPORTED_1000baseT_Half |
271 SUPPORTED_1000baseT_Full |
272 SUPPORTED_Autoneg |
273 SUPPORTED_TP);
274
275 if (is_genesis(hw))
276 supported &= ~(SUPPORTED_10baseT_Half |
277 SUPPORTED_10baseT_Full |
278 SUPPORTED_100baseT_Half |
279 SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
284 supported = (SUPPORTED_1000baseT_Full |
285 SUPPORTED_1000baseT_Half |
286 SUPPORTED_FIBRE |
287 SUPPORTED_Autoneg);
288
289 return supported;
290 }
291
skge_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)292 static int skge_get_link_ksettings(struct net_device *dev,
293 struct ethtool_link_ksettings *cmd)
294 {
295 struct skge_port *skge = netdev_priv(dev);
296 struct skge_hw *hw = skge->hw;
297 u32 supported, advertising;
298
299 supported = skge_supported_modes(hw);
300
301 if (hw->copper) {
302 cmd->base.port = PORT_TP;
303 cmd->base.phy_address = hw->phy_addr;
304 } else
305 cmd->base.port = PORT_FIBRE;
306
307 advertising = skge->advertising;
308 cmd->base.autoneg = skge->autoneg;
309 cmd->base.speed = skge->speed;
310 cmd->base.duplex = skge->duplex;
311
312 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
313 supported);
314 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
315 advertising);
316
317 return 0;
318 }
319
skge_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)320 static int skge_set_link_ksettings(struct net_device *dev,
321 const struct ethtool_link_ksettings *cmd)
322 {
323 struct skge_port *skge = netdev_priv(dev);
324 const struct skge_hw *hw = skge->hw;
325 u32 supported = skge_supported_modes(hw);
326 int err = 0;
327 u32 advertising;
328
329 ethtool_convert_link_mode_to_legacy_u32(&advertising,
330 cmd->link_modes.advertising);
331
332 if (cmd->base.autoneg == AUTONEG_ENABLE) {
333 advertising = supported;
334 skge->duplex = -1;
335 skge->speed = -1;
336 } else {
337 u32 setting;
338 u32 speed = cmd->base.speed;
339
340 switch (speed) {
341 case SPEED_1000:
342 if (cmd->base.duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (cmd->base.duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
346 else
347 return -EINVAL;
348 break;
349 case SPEED_100:
350 if (cmd->base.duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (cmd->base.duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
354 else
355 return -EINVAL;
356 break;
357
358 case SPEED_10:
359 if (cmd->base.duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (cmd->base.duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
363 else
364 return -EINVAL;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 if ((setting & supported) == 0)
371 return -EINVAL;
372
373 skge->speed = speed;
374 skge->duplex = cmd->base.duplex;
375 }
376
377 skge->autoneg = cmd->base.autoneg;
378 skge->advertising = advertising;
379
380 if (netif_running(dev)) {
381 skge_down(dev);
382 err = skge_up(dev);
383 if (err) {
384 dev_close(dev);
385 return err;
386 }
387 }
388
389 return 0;
390 }
391
skge_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)392 static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
394 {
395 struct skge_port *skge = netdev_priv(dev);
396
397 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
398 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
399 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
400 sizeof(info->bus_info));
401 }
402
403 static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
405 u16 xmac_offset;
406 u16 gma_offset;
407 } skge_stats[] = {
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
410
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
419
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
426
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
432 };
433
skge_get_sset_count(struct net_device * dev,int sset)434 static int skge_get_sset_count(struct net_device *dev, int sset)
435 {
436 switch (sset) {
437 case ETH_SS_STATS:
438 return ARRAY_SIZE(skge_stats);
439 default:
440 return -EOPNOTSUPP;
441 }
442 }
443
skge_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)444 static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
446 {
447 struct skge_port *skge = netdev_priv(dev);
448
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453 }
454
455 /* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
458 */
skge_get_stats(struct net_device * dev)459 static struct net_device_stats *skge_get_stats(struct net_device *dev)
460 {
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
463
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
466 else
467 yukon_get_stats(skge, data);
468
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
476
477 return &dev->stats;
478 }
479
skge_get_strings(struct net_device * dev,u32 stringset,u8 * data)480 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
481 {
482 int i;
483
484 switch (stringset) {
485 case ETH_SS_STATS:
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 memcpy(data + i * ETH_GSTRING_LEN,
488 skge_stats[i].name, ETH_GSTRING_LEN);
489 break;
490 }
491 }
492
skge_get_ring_param(struct net_device * dev,struct ethtool_ringparam * p)493 static void skge_get_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495 {
496 struct skge_port *skge = netdev_priv(dev);
497
498 p->rx_max_pending = MAX_RX_RING_SIZE;
499 p->tx_max_pending = MAX_TX_RING_SIZE;
500
501 p->rx_pending = skge->rx_ring.count;
502 p->tx_pending = skge->tx_ring.count;
503 }
504
skge_set_ring_param(struct net_device * dev,struct ethtool_ringparam * p)505 static int skge_set_ring_param(struct net_device *dev,
506 struct ethtool_ringparam *p)
507 {
508 struct skge_port *skge = netdev_priv(dev);
509 int err = 0;
510
511 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
512 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
513 return -EINVAL;
514
515 skge->rx_ring.count = p->rx_pending;
516 skge->tx_ring.count = p->tx_pending;
517
518 if (netif_running(dev)) {
519 skge_down(dev);
520 err = skge_up(dev);
521 if (err)
522 dev_close(dev);
523 }
524
525 return err;
526 }
527
skge_get_msglevel(struct net_device * netdev)528 static u32 skge_get_msglevel(struct net_device *netdev)
529 {
530 struct skge_port *skge = netdev_priv(netdev);
531 return skge->msg_enable;
532 }
533
skge_set_msglevel(struct net_device * netdev,u32 value)534 static void skge_set_msglevel(struct net_device *netdev, u32 value)
535 {
536 struct skge_port *skge = netdev_priv(netdev);
537 skge->msg_enable = value;
538 }
539
skge_nway_reset(struct net_device * dev)540 static int skge_nway_reset(struct net_device *dev)
541 {
542 struct skge_port *skge = netdev_priv(dev);
543
544 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
545 return -EINVAL;
546
547 skge_phy_reset(skge);
548 return 0;
549 }
550
skge_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * ecmd)551 static void skge_get_pauseparam(struct net_device *dev,
552 struct ethtool_pauseparam *ecmd)
553 {
554 struct skge_port *skge = netdev_priv(dev);
555
556 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
557 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
558 ecmd->tx_pause = (ecmd->rx_pause ||
559 (skge->flow_control == FLOW_MODE_LOC_SEND));
560
561 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
562 }
563
skge_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * ecmd)564 static int skge_set_pauseparam(struct net_device *dev,
565 struct ethtool_pauseparam *ecmd)
566 {
567 struct skge_port *skge = netdev_priv(dev);
568 struct ethtool_pauseparam old;
569 int err = 0;
570
571 skge_get_pauseparam(dev, &old);
572
573 if (ecmd->autoneg != old.autoneg)
574 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
575 else {
576 if (ecmd->rx_pause && ecmd->tx_pause)
577 skge->flow_control = FLOW_MODE_SYMMETRIC;
578 else if (ecmd->rx_pause && !ecmd->tx_pause)
579 skge->flow_control = FLOW_MODE_SYM_OR_REM;
580 else if (!ecmd->rx_pause && ecmd->tx_pause)
581 skge->flow_control = FLOW_MODE_LOC_SEND;
582 else
583 skge->flow_control = FLOW_MODE_NONE;
584 }
585
586 if (netif_running(dev)) {
587 skge_down(dev);
588 err = skge_up(dev);
589 if (err) {
590 dev_close(dev);
591 return err;
592 }
593 }
594
595 return 0;
596 }
597
598 /* Chip internal frequency for clock calculations */
hwkhz(const struct skge_hw * hw)599 static inline u32 hwkhz(const struct skge_hw *hw)
600 {
601 return is_genesis(hw) ? 53125 : 78125;
602 }
603
604 /* Chip HZ to microseconds */
skge_clk2usec(const struct skge_hw * hw,u32 ticks)605 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
606 {
607 return (ticks * 1000) / hwkhz(hw);
608 }
609
610 /* Microseconds to chip HZ */
skge_usecs2clk(const struct skge_hw * hw,u32 usec)611 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
612 {
613 return hwkhz(hw) * usec / 1000;
614 }
615
skge_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)616 static int skge_get_coalesce(struct net_device *dev,
617 struct ethtool_coalesce *ecmd,
618 struct kernel_ethtool_coalesce *kernel_coal,
619 struct netlink_ext_ack *extack)
620 {
621 struct skge_port *skge = netdev_priv(dev);
622 struct skge_hw *hw = skge->hw;
623 int port = skge->port;
624
625 ecmd->rx_coalesce_usecs = 0;
626 ecmd->tx_coalesce_usecs = 0;
627
628 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
629 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
630 u32 msk = skge_read32(hw, B2_IRQM_MSK);
631
632 if (msk & rxirqmask[port])
633 ecmd->rx_coalesce_usecs = delay;
634 if (msk & txirqmask[port])
635 ecmd->tx_coalesce_usecs = delay;
636 }
637
638 return 0;
639 }
640
641 /* Note: interrupt timer is per board, but can turn on/off per port */
skge_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ecmd,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)642 static int skge_set_coalesce(struct net_device *dev,
643 struct ethtool_coalesce *ecmd,
644 struct kernel_ethtool_coalesce *kernel_coal,
645 struct netlink_ext_ack *extack)
646 {
647 struct skge_port *skge = netdev_priv(dev);
648 struct skge_hw *hw = skge->hw;
649 int port = skge->port;
650 u32 msk = skge_read32(hw, B2_IRQM_MSK);
651 u32 delay = 25;
652
653 if (ecmd->rx_coalesce_usecs == 0)
654 msk &= ~rxirqmask[port];
655 else if (ecmd->rx_coalesce_usecs < 25 ||
656 ecmd->rx_coalesce_usecs > 33333)
657 return -EINVAL;
658 else {
659 msk |= rxirqmask[port];
660 delay = ecmd->rx_coalesce_usecs;
661 }
662
663 if (ecmd->tx_coalesce_usecs == 0)
664 msk &= ~txirqmask[port];
665 else if (ecmd->tx_coalesce_usecs < 25 ||
666 ecmd->tx_coalesce_usecs > 33333)
667 return -EINVAL;
668 else {
669 msk |= txirqmask[port];
670 delay = min(delay, ecmd->rx_coalesce_usecs);
671 }
672
673 skge_write32(hw, B2_IRQM_MSK, msk);
674 if (msk == 0)
675 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
676 else {
677 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
678 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
679 }
680 return 0;
681 }
682
683 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
skge_led(struct skge_port * skge,enum led_mode mode)684 static void skge_led(struct skge_port *skge, enum led_mode mode)
685 {
686 struct skge_hw *hw = skge->hw;
687 int port = skge->port;
688
689 spin_lock_bh(&hw->phy_lock);
690 if (is_genesis(hw)) {
691 switch (mode) {
692 case LED_MODE_OFF:
693 if (hw->phy_type == SK_PHY_BCOM)
694 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
695 else {
696 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
697 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
698 }
699 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
700 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
701 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
702 break;
703
704 case LED_MODE_ON:
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
706 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
707
708 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
709 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
710
711 break;
712
713 case LED_MODE_TST:
714 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
715 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
716 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
717
718 if (hw->phy_type == SK_PHY_BCOM)
719 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
720 else {
721 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
722 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
723 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
724 }
725
726 }
727 } else {
728 switch (mode) {
729 case LED_MODE_OFF:
730 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
732 PHY_M_LED_MO_DUP(MO_LED_OFF) |
733 PHY_M_LED_MO_10(MO_LED_OFF) |
734 PHY_M_LED_MO_100(MO_LED_OFF) |
735 PHY_M_LED_MO_1000(MO_LED_OFF) |
736 PHY_M_LED_MO_RX(MO_LED_OFF));
737 break;
738 case LED_MODE_ON:
739 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
740 PHY_M_LED_PULS_DUR(PULS_170MS) |
741 PHY_M_LED_BLINK_RT(BLINK_84MS) |
742 PHY_M_LEDC_TX_CTRL |
743 PHY_M_LEDC_DP_CTRL);
744
745 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
746 PHY_M_LED_MO_RX(MO_LED_OFF) |
747 (skge->speed == SPEED_100 ?
748 PHY_M_LED_MO_100(MO_LED_ON) : 0));
749 break;
750 case LED_MODE_TST:
751 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
752 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
753 PHY_M_LED_MO_DUP(MO_LED_ON) |
754 PHY_M_LED_MO_10(MO_LED_ON) |
755 PHY_M_LED_MO_100(MO_LED_ON) |
756 PHY_M_LED_MO_1000(MO_LED_ON) |
757 PHY_M_LED_MO_RX(MO_LED_ON));
758 }
759 }
760 spin_unlock_bh(&hw->phy_lock);
761 }
762
763 /* blink LED's for finding board */
skge_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)764 static int skge_set_phys_id(struct net_device *dev,
765 enum ethtool_phys_id_state state)
766 {
767 struct skge_port *skge = netdev_priv(dev);
768
769 switch (state) {
770 case ETHTOOL_ID_ACTIVE:
771 return 2; /* cycle on/off twice per second */
772
773 case ETHTOOL_ID_ON:
774 skge_led(skge, LED_MODE_TST);
775 break;
776
777 case ETHTOOL_ID_OFF:
778 skge_led(skge, LED_MODE_OFF);
779 break;
780
781 case ETHTOOL_ID_INACTIVE:
782 /* back to regular LED state */
783 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
784 }
785
786 return 0;
787 }
788
skge_get_eeprom_len(struct net_device * dev)789 static int skge_get_eeprom_len(struct net_device *dev)
790 {
791 struct skge_port *skge = netdev_priv(dev);
792 u32 reg2;
793
794 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
795 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
796 }
797
skge_vpd_read(struct pci_dev * pdev,int cap,u16 offset)798 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
799 {
800 u32 val;
801
802 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
803
804 do {
805 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
806 } while (!(offset & PCI_VPD_ADDR_F));
807
808 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
809 return val;
810 }
811
skge_vpd_write(struct pci_dev * pdev,int cap,u16 offset,u32 val)812 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
813 {
814 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
815 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
816 offset | PCI_VPD_ADDR_F);
817
818 do {
819 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
820 } while (offset & PCI_VPD_ADDR_F);
821 }
822
skge_get_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)823 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
824 u8 *data)
825 {
826 struct skge_port *skge = netdev_priv(dev);
827 struct pci_dev *pdev = skge->hw->pdev;
828 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
829 int length = eeprom->len;
830 u16 offset = eeprom->offset;
831
832 if (!cap)
833 return -EINVAL;
834
835 eeprom->magic = SKGE_EEPROM_MAGIC;
836
837 while (length > 0) {
838 u32 val = skge_vpd_read(pdev, cap, offset);
839 int n = min_t(int, length, sizeof(val));
840
841 memcpy(data, &val, n);
842 length -= n;
843 data += n;
844 offset += n;
845 }
846 return 0;
847 }
848
skge_set_eeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data)849 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
850 u8 *data)
851 {
852 struct skge_port *skge = netdev_priv(dev);
853 struct pci_dev *pdev = skge->hw->pdev;
854 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
855 int length = eeprom->len;
856 u16 offset = eeprom->offset;
857
858 if (!cap)
859 return -EINVAL;
860
861 if (eeprom->magic != SKGE_EEPROM_MAGIC)
862 return -EINVAL;
863
864 while (length > 0) {
865 u32 val;
866 int n = min_t(int, length, sizeof(val));
867
868 if (n < sizeof(val))
869 val = skge_vpd_read(pdev, cap, offset);
870 memcpy(&val, data, n);
871
872 skge_vpd_write(pdev, cap, offset, val);
873
874 length -= n;
875 data += n;
876 offset += n;
877 }
878 return 0;
879 }
880
881 static const struct ethtool_ops skge_ethtool_ops = {
882 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
883 .get_drvinfo = skge_get_drvinfo,
884 .get_regs_len = skge_get_regs_len,
885 .get_regs = skge_get_regs,
886 .get_wol = skge_get_wol,
887 .set_wol = skge_set_wol,
888 .get_msglevel = skge_get_msglevel,
889 .set_msglevel = skge_set_msglevel,
890 .nway_reset = skge_nway_reset,
891 .get_link = ethtool_op_get_link,
892 .get_eeprom_len = skge_get_eeprom_len,
893 .get_eeprom = skge_get_eeprom,
894 .set_eeprom = skge_set_eeprom,
895 .get_ringparam = skge_get_ring_param,
896 .set_ringparam = skge_set_ring_param,
897 .get_pauseparam = skge_get_pauseparam,
898 .set_pauseparam = skge_set_pauseparam,
899 .get_coalesce = skge_get_coalesce,
900 .set_coalesce = skge_set_coalesce,
901 .get_strings = skge_get_strings,
902 .set_phys_id = skge_set_phys_id,
903 .get_sset_count = skge_get_sset_count,
904 .get_ethtool_stats = skge_get_ethtool_stats,
905 .get_link_ksettings = skge_get_link_ksettings,
906 .set_link_ksettings = skge_set_link_ksettings,
907 };
908
909 /*
910 * Allocate ring elements and chain them together
911 * One-to-one association of board descriptors with ring elements
912 */
skge_ring_alloc(struct skge_ring * ring,void * vaddr,u32 base)913 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
914 {
915 struct skge_tx_desc *d;
916 struct skge_element *e;
917 int i;
918
919 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
920 if (!ring->start)
921 return -ENOMEM;
922
923 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
924 e->desc = d;
925 if (i == ring->count - 1) {
926 e->next = ring->start;
927 d->next_offset = base;
928 } else {
929 e->next = e + 1;
930 d->next_offset = base + (i+1) * sizeof(*d);
931 }
932 }
933 ring->to_use = ring->to_clean = ring->start;
934
935 return 0;
936 }
937
938 /* Allocate and setup a new buffer for receiving */
skge_rx_setup(struct skge_port * skge,struct skge_element * e,struct sk_buff * skb,unsigned int bufsize)939 static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
940 struct sk_buff *skb, unsigned int bufsize)
941 {
942 struct skge_rx_desc *rd = e->desc;
943 dma_addr_t map;
944
945 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize,
946 DMA_FROM_DEVICE);
947
948 if (dma_mapping_error(&skge->hw->pdev->dev, map))
949 return -1;
950
951 rd->dma_lo = lower_32_bits(map);
952 rd->dma_hi = upper_32_bits(map);
953 e->skb = skb;
954 rd->csum1_start = ETH_HLEN;
955 rd->csum2_start = ETH_HLEN;
956 rd->csum1 = 0;
957 rd->csum2 = 0;
958
959 wmb();
960
961 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
962 dma_unmap_addr_set(e, mapaddr, map);
963 dma_unmap_len_set(e, maplen, bufsize);
964 return 0;
965 }
966
967 /* Resume receiving using existing skb,
968 * Note: DMA address is not changed by chip.
969 * MTU not changed while receiver active.
970 */
skge_rx_reuse(struct skge_element * e,unsigned int size)971 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
972 {
973 struct skge_rx_desc *rd = e->desc;
974
975 rd->csum2 = 0;
976 rd->csum2_start = ETH_HLEN;
977
978 wmb();
979
980 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
981 }
982
983
984 /* Free all buffers in receive ring, assumes receiver stopped */
skge_rx_clean(struct skge_port * skge)985 static void skge_rx_clean(struct skge_port *skge)
986 {
987 struct skge_hw *hw = skge->hw;
988 struct skge_ring *ring = &skge->rx_ring;
989 struct skge_element *e;
990
991 e = ring->start;
992 do {
993 struct skge_rx_desc *rd = e->desc;
994 rd->control = 0;
995 if (e->skb) {
996 dma_unmap_single(&hw->pdev->dev,
997 dma_unmap_addr(e, mapaddr),
998 dma_unmap_len(e, maplen),
999 DMA_FROM_DEVICE);
1000 dev_kfree_skb(e->skb);
1001 e->skb = NULL;
1002 }
1003 } while ((e = e->next) != ring->start);
1004 }
1005
1006
1007 /* Allocate buffers for receive ring
1008 * For receive: to_clean is next received frame.
1009 */
skge_rx_fill(struct net_device * dev)1010 static int skge_rx_fill(struct net_device *dev)
1011 {
1012 struct skge_port *skge = netdev_priv(dev);
1013 struct skge_ring *ring = &skge->rx_ring;
1014 struct skge_element *e;
1015
1016 e = ring->start;
1017 do {
1018 struct sk_buff *skb;
1019
1020 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1021 GFP_KERNEL);
1022 if (!skb)
1023 return -ENOMEM;
1024
1025 skb_reserve(skb, NET_IP_ALIGN);
1026 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1027 dev_kfree_skb(skb);
1028 return -EIO;
1029 }
1030 } while ((e = e->next) != ring->start);
1031
1032 ring->to_clean = ring->start;
1033 return 0;
1034 }
1035
skge_pause(enum pause_status status)1036 static const char *skge_pause(enum pause_status status)
1037 {
1038 switch (status) {
1039 case FLOW_STAT_NONE:
1040 return "none";
1041 case FLOW_STAT_REM_SEND:
1042 return "rx only";
1043 case FLOW_STAT_LOC_SEND:
1044 return "tx_only";
1045 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1046 return "both";
1047 default:
1048 return "indeterminated";
1049 }
1050 }
1051
1052
skge_link_up(struct skge_port * skge)1053 static void skge_link_up(struct skge_port *skge)
1054 {
1055 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1056 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1057
1058 netif_carrier_on(skge->netdev);
1059 netif_wake_queue(skge->netdev);
1060
1061 netif_info(skge, link, skge->netdev,
1062 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1063 skge->speed,
1064 skge->duplex == DUPLEX_FULL ? "full" : "half",
1065 skge_pause(skge->flow_status));
1066 }
1067
skge_link_down(struct skge_port * skge)1068 static void skge_link_down(struct skge_port *skge)
1069 {
1070 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1071 netif_carrier_off(skge->netdev);
1072 netif_stop_queue(skge->netdev);
1073
1074 netif_info(skge, link, skge->netdev, "Link is down\n");
1075 }
1076
xm_link_down(struct skge_hw * hw,int port)1077 static void xm_link_down(struct skge_hw *hw, int port)
1078 {
1079 struct net_device *dev = hw->dev[port];
1080 struct skge_port *skge = netdev_priv(dev);
1081
1082 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1083
1084 if (netif_carrier_ok(dev))
1085 skge_link_down(skge);
1086 }
1087
__xm_phy_read(struct skge_hw * hw,int port,u16 reg,u16 * val)1088 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1089 {
1090 int i;
1091
1092 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1093 *val = xm_read16(hw, port, XM_PHY_DATA);
1094
1095 if (hw->phy_type == SK_PHY_XMAC)
1096 goto ready;
1097
1098 for (i = 0; i < PHY_RETRIES; i++) {
1099 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1100 goto ready;
1101 udelay(1);
1102 }
1103
1104 return -ETIMEDOUT;
1105 ready:
1106 *val = xm_read16(hw, port, XM_PHY_DATA);
1107
1108 return 0;
1109 }
1110
xm_phy_read(struct skge_hw * hw,int port,u16 reg)1111 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1112 {
1113 u16 v = 0;
1114 if (__xm_phy_read(hw, port, reg, &v))
1115 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1116 return v;
1117 }
1118
xm_phy_write(struct skge_hw * hw,int port,u16 reg,u16 val)1119 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1120 {
1121 int i;
1122
1123 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1124 for (i = 0; i < PHY_RETRIES; i++) {
1125 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1126 goto ready;
1127 udelay(1);
1128 }
1129 return -EIO;
1130
1131 ready:
1132 xm_write16(hw, port, XM_PHY_DATA, val);
1133 for (i = 0; i < PHY_RETRIES; i++) {
1134 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1135 return 0;
1136 udelay(1);
1137 }
1138 return -ETIMEDOUT;
1139 }
1140
genesis_init(struct skge_hw * hw)1141 static void genesis_init(struct skge_hw *hw)
1142 {
1143 /* set blink source counter */
1144 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1145 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1146
1147 /* configure mac arbiter */
1148 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1149
1150 /* configure mac arbiter timeout values */
1151 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1152 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1153 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1154 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1155
1156 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1157 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1158 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1159 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1160
1161 /* configure packet arbiter timeout */
1162 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1163 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1164 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1165 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1166 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1167 }
1168
genesis_reset(struct skge_hw * hw,int port)1169 static void genesis_reset(struct skge_hw *hw, int port)
1170 {
1171 static const u8 zero[8] = { 0 };
1172 u32 reg;
1173
1174 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1175
1176 /* reset the statistics module */
1177 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1178 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1179 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1180 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1181 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1182
1183 /* disable Broadcom PHY IRQ */
1184 if (hw->phy_type == SK_PHY_BCOM)
1185 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1186
1187 xm_outhash(hw, port, XM_HSM, zero);
1188
1189 /* Flush TX and RX fifo */
1190 reg = xm_read32(hw, port, XM_MODE);
1191 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1192 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1193 }
1194
1195 /* Convert mode to MII values */
1196 static const u16 phy_pause_map[] = {
1197 [FLOW_MODE_NONE] = 0,
1198 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1199 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1200 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1201 };
1202
1203 /* special defines for FIBER (88E1011S only) */
1204 static const u16 fiber_pause_map[] = {
1205 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1206 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1207 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1208 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1209 };
1210
1211
1212 /* Check status of Broadcom phy link */
bcom_check_link(struct skge_hw * hw,int port)1213 static void bcom_check_link(struct skge_hw *hw, int port)
1214 {
1215 struct net_device *dev = hw->dev[port];
1216 struct skge_port *skge = netdev_priv(dev);
1217 u16 status;
1218
1219 /* read twice because of latch */
1220 xm_phy_read(hw, port, PHY_BCOM_STAT);
1221 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1222
1223 if ((status & PHY_ST_LSYNC) == 0) {
1224 xm_link_down(hw, port);
1225 return;
1226 }
1227
1228 if (skge->autoneg == AUTONEG_ENABLE) {
1229 u16 lpa, aux;
1230
1231 if (!(status & PHY_ST_AN_OVER))
1232 return;
1233
1234 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1235 if (lpa & PHY_B_AN_RF) {
1236 netdev_notice(dev, "remote fault\n");
1237 return;
1238 }
1239
1240 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1241
1242 /* Check Duplex mismatch */
1243 switch (aux & PHY_B_AS_AN_RES_MSK) {
1244 case PHY_B_RES_1000FD:
1245 skge->duplex = DUPLEX_FULL;
1246 break;
1247 case PHY_B_RES_1000HD:
1248 skge->duplex = DUPLEX_HALF;
1249 break;
1250 default:
1251 netdev_notice(dev, "duplex mismatch\n");
1252 return;
1253 }
1254
1255 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1256 switch (aux & PHY_B_AS_PAUSE_MSK) {
1257 case PHY_B_AS_PAUSE_MSK:
1258 skge->flow_status = FLOW_STAT_SYMMETRIC;
1259 break;
1260 case PHY_B_AS_PRR:
1261 skge->flow_status = FLOW_STAT_REM_SEND;
1262 break;
1263 case PHY_B_AS_PRT:
1264 skge->flow_status = FLOW_STAT_LOC_SEND;
1265 break;
1266 default:
1267 skge->flow_status = FLOW_STAT_NONE;
1268 }
1269 skge->speed = SPEED_1000;
1270 }
1271
1272 if (!netif_carrier_ok(dev))
1273 genesis_link_up(skge);
1274 }
1275
1276 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1277 * Phy on for 100 or 10Mbit operation
1278 */
bcom_phy_init(struct skge_port * skge)1279 static void bcom_phy_init(struct skge_port *skge)
1280 {
1281 struct skge_hw *hw = skge->hw;
1282 int port = skge->port;
1283 int i;
1284 u16 id1, r, ext, ctl;
1285
1286 /* magic workaround patterns for Broadcom */
1287 static const struct {
1288 u16 reg;
1289 u16 val;
1290 } A1hack[] = {
1291 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1292 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1293 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1294 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1295 }, C0hack[] = {
1296 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1297 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1298 };
1299
1300 /* read Id from external PHY (all have the same address) */
1301 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1302
1303 /* Optimize MDIO transfer by suppressing preamble. */
1304 r = xm_read16(hw, port, XM_MMU_CMD);
1305 r |= XM_MMU_NO_PRE;
1306 xm_write16(hw, port, XM_MMU_CMD, r);
1307
1308 switch (id1) {
1309 case PHY_BCOM_ID1_C0:
1310 /*
1311 * Workaround BCOM Errata for the C0 type.
1312 * Write magic patterns to reserved registers.
1313 */
1314 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1315 xm_phy_write(hw, port,
1316 C0hack[i].reg, C0hack[i].val);
1317
1318 break;
1319 case PHY_BCOM_ID1_A1:
1320 /*
1321 * Workaround BCOM Errata for the A1 type.
1322 * Write magic patterns to reserved registers.
1323 */
1324 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1325 xm_phy_write(hw, port,
1326 A1hack[i].reg, A1hack[i].val);
1327 break;
1328 }
1329
1330 /*
1331 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1332 * Disable Power Management after reset.
1333 */
1334 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1335 r |= PHY_B_AC_DIS_PM;
1336 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1337
1338 /* Dummy read */
1339 xm_read16(hw, port, XM_ISRC);
1340
1341 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1342 ctl = PHY_CT_SP1000; /* always 1000mbit */
1343
1344 if (skge->autoneg == AUTONEG_ENABLE) {
1345 /*
1346 * Workaround BCOM Errata #1 for the C5 type.
1347 * 1000Base-T Link Acquisition Failure in Slave Mode
1348 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1349 */
1350 u16 adv = PHY_B_1000C_RD;
1351 if (skge->advertising & ADVERTISED_1000baseT_Half)
1352 adv |= PHY_B_1000C_AHD;
1353 if (skge->advertising & ADVERTISED_1000baseT_Full)
1354 adv |= PHY_B_1000C_AFD;
1355 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1356
1357 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1358 } else {
1359 if (skge->duplex == DUPLEX_FULL)
1360 ctl |= PHY_CT_DUP_MD;
1361 /* Force to slave */
1362 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1363 }
1364
1365 /* Set autonegotiation pause parameters */
1366 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1367 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1368
1369 /* Handle Jumbo frames */
1370 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1371 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1372 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1373
1374 ext |= PHY_B_PEC_HIGH_LA;
1375
1376 }
1377
1378 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1379 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1380
1381 /* Use link status change interrupt */
1382 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1383 }
1384
xm_phy_init(struct skge_port * skge)1385 static void xm_phy_init(struct skge_port *skge)
1386 {
1387 struct skge_hw *hw = skge->hw;
1388 int port = skge->port;
1389 u16 ctrl = 0;
1390
1391 if (skge->autoneg == AUTONEG_ENABLE) {
1392 if (skge->advertising & ADVERTISED_1000baseT_Half)
1393 ctrl |= PHY_X_AN_HD;
1394 if (skge->advertising & ADVERTISED_1000baseT_Full)
1395 ctrl |= PHY_X_AN_FD;
1396
1397 ctrl |= fiber_pause_map[skge->flow_control];
1398
1399 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1400
1401 /* Restart Auto-negotiation */
1402 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1403 } else {
1404 /* Set DuplexMode in Config register */
1405 if (skge->duplex == DUPLEX_FULL)
1406 ctrl |= PHY_CT_DUP_MD;
1407 /*
1408 * Do NOT enable Auto-negotiation here. This would hold
1409 * the link down because no IDLEs are transmitted
1410 */
1411 }
1412
1413 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1414
1415 /* Poll PHY for status changes */
1416 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1417 }
1418
xm_check_link(struct net_device * dev)1419 static int xm_check_link(struct net_device *dev)
1420 {
1421 struct skge_port *skge = netdev_priv(dev);
1422 struct skge_hw *hw = skge->hw;
1423 int port = skge->port;
1424 u16 status;
1425
1426 /* read twice because of latch */
1427 xm_phy_read(hw, port, PHY_XMAC_STAT);
1428 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1429
1430 if ((status & PHY_ST_LSYNC) == 0) {
1431 xm_link_down(hw, port);
1432 return 0;
1433 }
1434
1435 if (skge->autoneg == AUTONEG_ENABLE) {
1436 u16 lpa, res;
1437
1438 if (!(status & PHY_ST_AN_OVER))
1439 return 0;
1440
1441 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1442 if (lpa & PHY_B_AN_RF) {
1443 netdev_notice(dev, "remote fault\n");
1444 return 0;
1445 }
1446
1447 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1448
1449 /* Check Duplex mismatch */
1450 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1451 case PHY_X_RS_FD:
1452 skge->duplex = DUPLEX_FULL;
1453 break;
1454 case PHY_X_RS_HD:
1455 skge->duplex = DUPLEX_HALF;
1456 break;
1457 default:
1458 netdev_notice(dev, "duplex mismatch\n");
1459 return 0;
1460 }
1461
1462 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1463 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1464 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1465 (lpa & PHY_X_P_SYM_MD))
1466 skge->flow_status = FLOW_STAT_SYMMETRIC;
1467 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1468 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1469 /* Enable PAUSE receive, disable PAUSE transmit */
1470 skge->flow_status = FLOW_STAT_REM_SEND;
1471 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1472 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1473 /* Disable PAUSE receive, enable PAUSE transmit */
1474 skge->flow_status = FLOW_STAT_LOC_SEND;
1475 else
1476 skge->flow_status = FLOW_STAT_NONE;
1477
1478 skge->speed = SPEED_1000;
1479 }
1480
1481 if (!netif_carrier_ok(dev))
1482 genesis_link_up(skge);
1483 return 1;
1484 }
1485
1486 /* Poll to check for link coming up.
1487 *
1488 * Since internal PHY is wired to a level triggered pin, can't
1489 * get an interrupt when carrier is detected, need to poll for
1490 * link coming up.
1491 */
xm_link_timer(struct timer_list * t)1492 static void xm_link_timer(struct timer_list *t)
1493 {
1494 struct skge_port *skge = from_timer(skge, t, link_timer);
1495 struct net_device *dev = skge->netdev;
1496 struct skge_hw *hw = skge->hw;
1497 int port = skge->port;
1498 int i;
1499 unsigned long flags;
1500
1501 if (!netif_running(dev))
1502 return;
1503
1504 spin_lock_irqsave(&hw->phy_lock, flags);
1505
1506 /*
1507 * Verify that the link by checking GPIO register three times.
1508 * This pin has the signal from the link_sync pin connected to it.
1509 */
1510 for (i = 0; i < 3; i++) {
1511 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1512 goto link_down;
1513 }
1514
1515 /* Re-enable interrupt to detect link down */
1516 if (xm_check_link(dev)) {
1517 u16 msk = xm_read16(hw, port, XM_IMSK);
1518 msk &= ~XM_IS_INP_ASS;
1519 xm_write16(hw, port, XM_IMSK, msk);
1520 xm_read16(hw, port, XM_ISRC);
1521 } else {
1522 link_down:
1523 mod_timer(&skge->link_timer,
1524 round_jiffies(jiffies + LINK_HZ));
1525 }
1526 spin_unlock_irqrestore(&hw->phy_lock, flags);
1527 }
1528
genesis_mac_init(struct skge_hw * hw,int port)1529 static void genesis_mac_init(struct skge_hw *hw, int port)
1530 {
1531 struct net_device *dev = hw->dev[port];
1532 struct skge_port *skge = netdev_priv(dev);
1533 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1534 int i;
1535 u32 r;
1536 static const u8 zero[6] = { 0 };
1537
1538 for (i = 0; i < 10; i++) {
1539 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1540 MFF_SET_MAC_RST);
1541 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1542 goto reset_ok;
1543 udelay(1);
1544 }
1545
1546 netdev_warn(dev, "genesis reset failed\n");
1547
1548 reset_ok:
1549 /* Unreset the XMAC. */
1550 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1551
1552 /*
1553 * Perform additional initialization for external PHYs,
1554 * namely for the 1000baseTX cards that use the XMAC's
1555 * GMII mode.
1556 */
1557 if (hw->phy_type != SK_PHY_XMAC) {
1558 /* Take external Phy out of reset */
1559 r = skge_read32(hw, B2_GP_IO);
1560 if (port == 0)
1561 r |= GP_DIR_0|GP_IO_0;
1562 else
1563 r |= GP_DIR_2|GP_IO_2;
1564
1565 skge_write32(hw, B2_GP_IO, r);
1566
1567 /* Enable GMII interface */
1568 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1569 }
1570
1571
1572 switch (hw->phy_type) {
1573 case SK_PHY_XMAC:
1574 xm_phy_init(skge);
1575 break;
1576 case SK_PHY_BCOM:
1577 bcom_phy_init(skge);
1578 bcom_check_link(hw, port);
1579 }
1580
1581 /* Set Station Address */
1582 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1583
1584 /* We don't use match addresses so clear */
1585 for (i = 1; i < 16; i++)
1586 xm_outaddr(hw, port, XM_EXM(i), zero);
1587
1588 /* Clear MIB counters */
1589 xm_write16(hw, port, XM_STAT_CMD,
1590 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1591 /* Clear two times according to Errata #3 */
1592 xm_write16(hw, port, XM_STAT_CMD,
1593 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1594
1595 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1596 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1597
1598 /* We don't need the FCS appended to the packet. */
1599 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1600 if (jumbo)
1601 r |= XM_RX_BIG_PK_OK;
1602
1603 if (skge->duplex == DUPLEX_HALF) {
1604 /*
1605 * If in manual half duplex mode the other side might be in
1606 * full duplex mode, so ignore if a carrier extension is not seen
1607 * on frames received
1608 */
1609 r |= XM_RX_DIS_CEXT;
1610 }
1611 xm_write16(hw, port, XM_RX_CMD, r);
1612
1613 /* We want short frames padded to 60 bytes. */
1614 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1615
1616 /* Increase threshold for jumbo frames on dual port */
1617 if (hw->ports > 1 && jumbo)
1618 xm_write16(hw, port, XM_TX_THR, 1020);
1619 else
1620 xm_write16(hw, port, XM_TX_THR, 512);
1621
1622 /*
1623 * Enable the reception of all error frames. This is
1624 * a necessary evil due to the design of the XMAC. The
1625 * XMAC's receive FIFO is only 8K in size, however jumbo
1626 * frames can be up to 9000 bytes in length. When bad
1627 * frame filtering is enabled, the XMAC's RX FIFO operates
1628 * in 'store and forward' mode. For this to work, the
1629 * entire frame has to fit into the FIFO, but that means
1630 * that jumbo frames larger than 8192 bytes will be
1631 * truncated. Disabling all bad frame filtering causes
1632 * the RX FIFO to operate in streaming mode, in which
1633 * case the XMAC will start transferring frames out of the
1634 * RX FIFO as soon as the FIFO threshold is reached.
1635 */
1636 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1637
1638
1639 /*
1640 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1641 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1642 * and 'Octets Rx OK Hi Cnt Ov'.
1643 */
1644 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1645
1646 /*
1647 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1648 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1649 * and 'Octets Tx OK Hi Cnt Ov'.
1650 */
1651 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1652
1653 /* Configure MAC arbiter */
1654 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1655
1656 /* configure timeout values */
1657 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1658 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1659 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1660 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1661
1662 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1663 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1664 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1665 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1666
1667 /* Configure Rx MAC FIFO */
1668 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1669 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1670 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1671
1672 /* Configure Tx MAC FIFO */
1673 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1674 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1675 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1676
1677 if (jumbo) {
1678 /* Enable frame flushing if jumbo frames used */
1679 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1680 } else {
1681 /* enable timeout timers if normal frames */
1682 skge_write16(hw, B3_PA_CTRL,
1683 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1684 }
1685 }
1686
genesis_stop(struct skge_port * skge)1687 static void genesis_stop(struct skge_port *skge)
1688 {
1689 struct skge_hw *hw = skge->hw;
1690 int port = skge->port;
1691 unsigned retries = 1000;
1692 u16 cmd;
1693
1694 /* Disable Tx and Rx */
1695 cmd = xm_read16(hw, port, XM_MMU_CMD);
1696 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1697 xm_write16(hw, port, XM_MMU_CMD, cmd);
1698
1699 genesis_reset(hw, port);
1700
1701 /* Clear Tx packet arbiter timeout IRQ */
1702 skge_write16(hw, B3_PA_CTRL,
1703 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1704
1705 /* Reset the MAC */
1706 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1707 do {
1708 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1709 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1710 break;
1711 } while (--retries > 0);
1712
1713 /* For external PHYs there must be special handling */
1714 if (hw->phy_type != SK_PHY_XMAC) {
1715 u32 reg = skge_read32(hw, B2_GP_IO);
1716 if (port == 0) {
1717 reg |= GP_DIR_0;
1718 reg &= ~GP_IO_0;
1719 } else {
1720 reg |= GP_DIR_2;
1721 reg &= ~GP_IO_2;
1722 }
1723 skge_write32(hw, B2_GP_IO, reg);
1724 skge_read32(hw, B2_GP_IO);
1725 }
1726
1727 xm_write16(hw, port, XM_MMU_CMD,
1728 xm_read16(hw, port, XM_MMU_CMD)
1729 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1730
1731 xm_read16(hw, port, XM_MMU_CMD);
1732 }
1733
1734
genesis_get_stats(struct skge_port * skge,u64 * data)1735 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1736 {
1737 struct skge_hw *hw = skge->hw;
1738 int port = skge->port;
1739 int i;
1740 unsigned long timeout = jiffies + HZ;
1741
1742 xm_write16(hw, port,
1743 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1744
1745 /* wait for update to complete */
1746 while (xm_read16(hw, port, XM_STAT_CMD)
1747 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1748 if (time_after(jiffies, timeout))
1749 break;
1750 udelay(10);
1751 }
1752
1753 /* special case for 64 bit octet counter */
1754 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1755 | xm_read32(hw, port, XM_TXO_OK_LO);
1756 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1757 | xm_read32(hw, port, XM_RXO_OK_LO);
1758
1759 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1760 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1761 }
1762
genesis_mac_intr(struct skge_hw * hw,int port)1763 static void genesis_mac_intr(struct skge_hw *hw, int port)
1764 {
1765 struct net_device *dev = hw->dev[port];
1766 struct skge_port *skge = netdev_priv(dev);
1767 u16 status = xm_read16(hw, port, XM_ISRC);
1768
1769 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1770 "mac interrupt status 0x%x\n", status);
1771
1772 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1773 xm_link_down(hw, port);
1774 mod_timer(&skge->link_timer, jiffies + 1);
1775 }
1776
1777 if (status & XM_IS_TXF_UR) {
1778 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1779 ++dev->stats.tx_fifo_errors;
1780 }
1781 }
1782
genesis_link_up(struct skge_port * skge)1783 static void genesis_link_up(struct skge_port *skge)
1784 {
1785 struct skge_hw *hw = skge->hw;
1786 int port = skge->port;
1787 u16 cmd, msk;
1788 u32 mode;
1789
1790 cmd = xm_read16(hw, port, XM_MMU_CMD);
1791
1792 /*
1793 * enabling pause frame reception is required for 1000BT
1794 * because the XMAC is not reset if the link is going down
1795 */
1796 if (skge->flow_status == FLOW_STAT_NONE ||
1797 skge->flow_status == FLOW_STAT_LOC_SEND)
1798 /* Disable Pause Frame Reception */
1799 cmd |= XM_MMU_IGN_PF;
1800 else
1801 /* Enable Pause Frame Reception */
1802 cmd &= ~XM_MMU_IGN_PF;
1803
1804 xm_write16(hw, port, XM_MMU_CMD, cmd);
1805
1806 mode = xm_read32(hw, port, XM_MODE);
1807 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1808 skge->flow_status == FLOW_STAT_LOC_SEND) {
1809 /*
1810 * Configure Pause Frame Generation
1811 * Use internal and external Pause Frame Generation.
1812 * Sending pause frames is edge triggered.
1813 * Send a Pause frame with the maximum pause time if
1814 * internal oder external FIFO full condition occurs.
1815 * Send a zero pause time frame to re-start transmission.
1816 */
1817 /* XM_PAUSE_DA = '010000C28001' (default) */
1818 /* XM_MAC_PTIME = 0xffff (maximum) */
1819 /* remember this value is defined in big endian (!) */
1820 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1821
1822 mode |= XM_PAUSE_MODE;
1823 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1824 } else {
1825 /*
1826 * disable pause frame generation is required for 1000BT
1827 * because the XMAC is not reset if the link is going down
1828 */
1829 /* Disable Pause Mode in Mode Register */
1830 mode &= ~XM_PAUSE_MODE;
1831
1832 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1833 }
1834
1835 xm_write32(hw, port, XM_MODE, mode);
1836
1837 /* Turn on detection of Tx underrun */
1838 msk = xm_read16(hw, port, XM_IMSK);
1839 msk &= ~XM_IS_TXF_UR;
1840 xm_write16(hw, port, XM_IMSK, msk);
1841
1842 xm_read16(hw, port, XM_ISRC);
1843
1844 /* get MMU Command Reg. */
1845 cmd = xm_read16(hw, port, XM_MMU_CMD);
1846 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1847 cmd |= XM_MMU_GMII_FD;
1848
1849 /*
1850 * Workaround BCOM Errata (#10523) for all BCom Phys
1851 * Enable Power Management after link up
1852 */
1853 if (hw->phy_type == SK_PHY_BCOM) {
1854 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1855 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1856 & ~PHY_B_AC_DIS_PM);
1857 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1858 }
1859
1860 /* enable Rx/Tx */
1861 xm_write16(hw, port, XM_MMU_CMD,
1862 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1863 skge_link_up(skge);
1864 }
1865
1866
bcom_phy_intr(struct skge_port * skge)1867 static inline void bcom_phy_intr(struct skge_port *skge)
1868 {
1869 struct skge_hw *hw = skge->hw;
1870 int port = skge->port;
1871 u16 isrc;
1872
1873 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1874 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1875 "phy interrupt status 0x%x\n", isrc);
1876
1877 if (isrc & PHY_B_IS_PSE)
1878 pr_err("%s: uncorrectable pair swap error\n",
1879 hw->dev[port]->name);
1880
1881 /* Workaround BCom Errata:
1882 * enable and disable loopback mode if "NO HCD" occurs.
1883 */
1884 if (isrc & PHY_B_IS_NO_HDCL) {
1885 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1886 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1887 ctrl | PHY_CT_LOOP);
1888 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1889 ctrl & ~PHY_CT_LOOP);
1890 }
1891
1892 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1893 bcom_check_link(hw, port);
1894
1895 }
1896
gm_phy_write(struct skge_hw * hw,int port,u16 reg,u16 val)1897 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1898 {
1899 int i;
1900
1901 gma_write16(hw, port, GM_SMI_DATA, val);
1902 gma_write16(hw, port, GM_SMI_CTRL,
1903 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1904 for (i = 0; i < PHY_RETRIES; i++) {
1905 udelay(1);
1906
1907 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1908 return 0;
1909 }
1910
1911 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1912 return -EIO;
1913 }
1914
__gm_phy_read(struct skge_hw * hw,int port,u16 reg,u16 * val)1915 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1916 {
1917 int i;
1918
1919 gma_write16(hw, port, GM_SMI_CTRL,
1920 GM_SMI_CT_PHY_AD(hw->phy_addr)
1921 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1922
1923 for (i = 0; i < PHY_RETRIES; i++) {
1924 udelay(1);
1925 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1926 goto ready;
1927 }
1928
1929 return -ETIMEDOUT;
1930 ready:
1931 *val = gma_read16(hw, port, GM_SMI_DATA);
1932 return 0;
1933 }
1934
gm_phy_read(struct skge_hw * hw,int port,u16 reg)1935 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1936 {
1937 u16 v = 0;
1938 if (__gm_phy_read(hw, port, reg, &v))
1939 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1940 return v;
1941 }
1942
1943 /* Marvell Phy Initialization */
yukon_init(struct skge_hw * hw,int port)1944 static void yukon_init(struct skge_hw *hw, int port)
1945 {
1946 struct skge_port *skge = netdev_priv(hw->dev[port]);
1947 u16 ctrl, ct1000, adv;
1948
1949 if (skge->autoneg == AUTONEG_ENABLE) {
1950 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1951
1952 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1953 PHY_M_EC_MAC_S_MSK);
1954 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1955
1956 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1957
1958 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1959 }
1960
1961 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1962 if (skge->autoneg == AUTONEG_DISABLE)
1963 ctrl &= ~PHY_CT_ANE;
1964
1965 ctrl |= PHY_CT_RESET;
1966 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1967
1968 ctrl = 0;
1969 ct1000 = 0;
1970 adv = PHY_AN_CSMA;
1971
1972 if (skge->autoneg == AUTONEG_ENABLE) {
1973 if (hw->copper) {
1974 if (skge->advertising & ADVERTISED_1000baseT_Full)
1975 ct1000 |= PHY_M_1000C_AFD;
1976 if (skge->advertising & ADVERTISED_1000baseT_Half)
1977 ct1000 |= PHY_M_1000C_AHD;
1978 if (skge->advertising & ADVERTISED_100baseT_Full)
1979 adv |= PHY_M_AN_100_FD;
1980 if (skge->advertising & ADVERTISED_100baseT_Half)
1981 adv |= PHY_M_AN_100_HD;
1982 if (skge->advertising & ADVERTISED_10baseT_Full)
1983 adv |= PHY_M_AN_10_FD;
1984 if (skge->advertising & ADVERTISED_10baseT_Half)
1985 adv |= PHY_M_AN_10_HD;
1986
1987 /* Set Flow-control capabilities */
1988 adv |= phy_pause_map[skge->flow_control];
1989 } else {
1990 if (skge->advertising & ADVERTISED_1000baseT_Full)
1991 adv |= PHY_M_AN_1000X_AFD;
1992 if (skge->advertising & ADVERTISED_1000baseT_Half)
1993 adv |= PHY_M_AN_1000X_AHD;
1994
1995 adv |= fiber_pause_map[skge->flow_control];
1996 }
1997
1998 /* Restart Auto-negotiation */
1999 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2000 } else {
2001 /* forced speed/duplex settings */
2002 ct1000 = PHY_M_1000C_MSE;
2003
2004 if (skge->duplex == DUPLEX_FULL)
2005 ctrl |= PHY_CT_DUP_MD;
2006
2007 switch (skge->speed) {
2008 case SPEED_1000:
2009 ctrl |= PHY_CT_SP1000;
2010 break;
2011 case SPEED_100:
2012 ctrl |= PHY_CT_SP100;
2013 break;
2014 }
2015
2016 ctrl |= PHY_CT_RESET;
2017 }
2018
2019 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2020
2021 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2022 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2023
2024 /* Enable phy interrupt on autonegotiation complete (or link up) */
2025 if (skge->autoneg == AUTONEG_ENABLE)
2026 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2027 else
2028 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2029 }
2030
yukon_reset(struct skge_hw * hw,int port)2031 static void yukon_reset(struct skge_hw *hw, int port)
2032 {
2033 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2034 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2035 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2036 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2037 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2038
2039 gma_write16(hw, port, GM_RX_CTRL,
2040 gma_read16(hw, port, GM_RX_CTRL)
2041 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2042 }
2043
2044 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
is_yukon_lite_a0(struct skge_hw * hw)2045 static int is_yukon_lite_a0(struct skge_hw *hw)
2046 {
2047 u32 reg;
2048 int ret;
2049
2050 if (hw->chip_id != CHIP_ID_YUKON)
2051 return 0;
2052
2053 reg = skge_read32(hw, B2_FAR);
2054 skge_write8(hw, B2_FAR + 3, 0xff);
2055 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2056 skge_write32(hw, B2_FAR, reg);
2057 return ret;
2058 }
2059
yukon_mac_init(struct skge_hw * hw,int port)2060 static void yukon_mac_init(struct skge_hw *hw, int port)
2061 {
2062 struct skge_port *skge = netdev_priv(hw->dev[port]);
2063 int i;
2064 u32 reg;
2065 const u8 *addr = hw->dev[port]->dev_addr;
2066
2067 /* WA code for COMA mode -- set PHY reset */
2068 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2069 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2070 reg = skge_read32(hw, B2_GP_IO);
2071 reg |= GP_DIR_9 | GP_IO_9;
2072 skge_write32(hw, B2_GP_IO, reg);
2073 }
2074
2075 /* hard reset */
2076 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2077 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2078
2079 /* WA code for COMA mode -- clear PHY reset */
2080 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2081 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2082 reg = skge_read32(hw, B2_GP_IO);
2083 reg |= GP_DIR_9;
2084 reg &= ~GP_IO_9;
2085 skge_write32(hw, B2_GP_IO, reg);
2086 }
2087
2088 /* Set hardware config mode */
2089 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2090 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2091 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2092
2093 /* Clear GMC reset */
2094 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2095 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2096 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2097
2098 if (skge->autoneg == AUTONEG_DISABLE) {
2099 reg = GM_GPCR_AU_ALL_DIS;
2100 gma_write16(hw, port, GM_GP_CTRL,
2101 gma_read16(hw, port, GM_GP_CTRL) | reg);
2102
2103 switch (skge->speed) {
2104 case SPEED_1000:
2105 reg &= ~GM_GPCR_SPEED_100;
2106 reg |= GM_GPCR_SPEED_1000;
2107 break;
2108 case SPEED_100:
2109 reg &= ~GM_GPCR_SPEED_1000;
2110 reg |= GM_GPCR_SPEED_100;
2111 break;
2112 case SPEED_10:
2113 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2114 break;
2115 }
2116
2117 if (skge->duplex == DUPLEX_FULL)
2118 reg |= GM_GPCR_DUP_FULL;
2119 } else
2120 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2121
2122 switch (skge->flow_control) {
2123 case FLOW_MODE_NONE:
2124 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2125 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2126 break;
2127 case FLOW_MODE_LOC_SEND:
2128 /* disable Rx flow-control */
2129 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2130 break;
2131 case FLOW_MODE_SYMMETRIC:
2132 case FLOW_MODE_SYM_OR_REM:
2133 /* enable Tx & Rx flow-control */
2134 break;
2135 }
2136
2137 gma_write16(hw, port, GM_GP_CTRL, reg);
2138 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2139
2140 yukon_init(hw, port);
2141
2142 /* MIB clear */
2143 reg = gma_read16(hw, port, GM_PHY_ADDR);
2144 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2145
2146 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2147 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2148 gma_write16(hw, port, GM_PHY_ADDR, reg);
2149
2150 /* transmit control */
2151 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2152
2153 /* receive control reg: unicast + multicast + no FCS */
2154 gma_write16(hw, port, GM_RX_CTRL,
2155 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2156
2157 /* transmit flow control */
2158 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2159
2160 /* transmit parameter */
2161 gma_write16(hw, port, GM_TX_PARAM,
2162 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2163 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2164 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2165
2166 /* configure the Serial Mode Register */
2167 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2168 | GM_SMOD_VLAN_ENA
2169 | IPG_DATA_VAL(IPG_DATA_DEF);
2170
2171 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2172 reg |= GM_SMOD_JUMBO_ENA;
2173
2174 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2175
2176 /* physical address: used for pause frames */
2177 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2178 /* virtual address for data */
2179 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2180
2181 /* enable interrupt mask for counter overflows */
2182 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2183 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2184 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2185
2186 /* Initialize Mac Fifo */
2187
2188 /* Configure Rx MAC FIFO */
2189 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2190 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2191
2192 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2193 if (is_yukon_lite_a0(hw))
2194 reg &= ~GMF_RX_F_FL_ON;
2195
2196 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2197 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2198 /*
2199 * because Pause Packet Truncation in GMAC is not working
2200 * we have to increase the Flush Threshold to 64 bytes
2201 * in order to flush pause packets in Rx FIFO on Yukon-1
2202 */
2203 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2204
2205 /* Configure Tx MAC FIFO */
2206 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2207 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2208 }
2209
2210 /* Go into power down mode */
yukon_suspend(struct skge_hw * hw,int port)2211 static void yukon_suspend(struct skge_hw *hw, int port)
2212 {
2213 u16 ctrl;
2214
2215 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2216 ctrl |= PHY_M_PC_POL_R_DIS;
2217 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2218
2219 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2220 ctrl |= PHY_CT_RESET;
2221 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2222
2223 /* switch IEEE compatible power down mode on */
2224 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2225 ctrl |= PHY_CT_PDOWN;
2226 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2227 }
2228
yukon_stop(struct skge_port * skge)2229 static void yukon_stop(struct skge_port *skge)
2230 {
2231 struct skge_hw *hw = skge->hw;
2232 int port = skge->port;
2233
2234 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2235 yukon_reset(hw, port);
2236
2237 gma_write16(hw, port, GM_GP_CTRL,
2238 gma_read16(hw, port, GM_GP_CTRL)
2239 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2240 gma_read16(hw, port, GM_GP_CTRL);
2241
2242 yukon_suspend(hw, port);
2243
2244 /* set GPHY Control reset */
2245 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2246 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2247 }
2248
yukon_get_stats(struct skge_port * skge,u64 * data)2249 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2250 {
2251 struct skge_hw *hw = skge->hw;
2252 int port = skge->port;
2253 int i;
2254
2255 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2256 | gma_read32(hw, port, GM_TXO_OK_LO);
2257 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2258 | gma_read32(hw, port, GM_RXO_OK_LO);
2259
2260 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2261 data[i] = gma_read32(hw, port,
2262 skge_stats[i].gma_offset);
2263 }
2264
yukon_mac_intr(struct skge_hw * hw,int port)2265 static void yukon_mac_intr(struct skge_hw *hw, int port)
2266 {
2267 struct net_device *dev = hw->dev[port];
2268 struct skge_port *skge = netdev_priv(dev);
2269 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2270
2271 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2272 "mac interrupt status 0x%x\n", status);
2273
2274 if (status & GM_IS_RX_FF_OR) {
2275 ++dev->stats.rx_fifo_errors;
2276 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2277 }
2278
2279 if (status & GM_IS_TX_FF_UR) {
2280 ++dev->stats.tx_fifo_errors;
2281 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2282 }
2283
2284 }
2285
yukon_speed(const struct skge_hw * hw,u16 aux)2286 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2287 {
2288 switch (aux & PHY_M_PS_SPEED_MSK) {
2289 case PHY_M_PS_SPEED_1000:
2290 return SPEED_1000;
2291 case PHY_M_PS_SPEED_100:
2292 return SPEED_100;
2293 default:
2294 return SPEED_10;
2295 }
2296 }
2297
yukon_link_up(struct skge_port * skge)2298 static void yukon_link_up(struct skge_port *skge)
2299 {
2300 struct skge_hw *hw = skge->hw;
2301 int port = skge->port;
2302 u16 reg;
2303
2304 /* Enable Transmit FIFO Underrun */
2305 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2306
2307 reg = gma_read16(hw, port, GM_GP_CTRL);
2308 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2309 reg |= GM_GPCR_DUP_FULL;
2310
2311 /* enable Rx/Tx */
2312 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2313 gma_write16(hw, port, GM_GP_CTRL, reg);
2314
2315 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2316 skge_link_up(skge);
2317 }
2318
yukon_link_down(struct skge_port * skge)2319 static void yukon_link_down(struct skge_port *skge)
2320 {
2321 struct skge_hw *hw = skge->hw;
2322 int port = skge->port;
2323 u16 ctrl;
2324
2325 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2326 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2327 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2328
2329 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2330 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2331 ctrl |= PHY_M_AN_ASP;
2332 /* restore Asymmetric Pause bit */
2333 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2334 }
2335
2336 skge_link_down(skge);
2337
2338 yukon_init(hw, port);
2339 }
2340
yukon_phy_intr(struct skge_port * skge)2341 static void yukon_phy_intr(struct skge_port *skge)
2342 {
2343 struct skge_hw *hw = skge->hw;
2344 int port = skge->port;
2345 const char *reason = NULL;
2346 u16 istatus, phystat;
2347
2348 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2349 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2350
2351 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2352 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2353
2354 if (istatus & PHY_M_IS_AN_COMPL) {
2355 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2356 & PHY_M_AN_RF) {
2357 reason = "remote fault";
2358 goto failed;
2359 }
2360
2361 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2362 reason = "master/slave fault";
2363 goto failed;
2364 }
2365
2366 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2367 reason = "speed/duplex";
2368 goto failed;
2369 }
2370
2371 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2372 ? DUPLEX_FULL : DUPLEX_HALF;
2373 skge->speed = yukon_speed(hw, phystat);
2374
2375 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2376 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2377 case PHY_M_PS_PAUSE_MSK:
2378 skge->flow_status = FLOW_STAT_SYMMETRIC;
2379 break;
2380 case PHY_M_PS_RX_P_EN:
2381 skge->flow_status = FLOW_STAT_REM_SEND;
2382 break;
2383 case PHY_M_PS_TX_P_EN:
2384 skge->flow_status = FLOW_STAT_LOC_SEND;
2385 break;
2386 default:
2387 skge->flow_status = FLOW_STAT_NONE;
2388 }
2389
2390 if (skge->flow_status == FLOW_STAT_NONE ||
2391 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2392 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2393 else
2394 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2395 yukon_link_up(skge);
2396 return;
2397 }
2398
2399 if (istatus & PHY_M_IS_LSP_CHANGE)
2400 skge->speed = yukon_speed(hw, phystat);
2401
2402 if (istatus & PHY_M_IS_DUP_CHANGE)
2403 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2404 if (istatus & PHY_M_IS_LST_CHANGE) {
2405 if (phystat & PHY_M_PS_LINK_UP)
2406 yukon_link_up(skge);
2407 else
2408 yukon_link_down(skge);
2409 }
2410 return;
2411 failed:
2412 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2413
2414 /* XXX restart autonegotiation? */
2415 }
2416
skge_phy_reset(struct skge_port * skge)2417 static void skge_phy_reset(struct skge_port *skge)
2418 {
2419 struct skge_hw *hw = skge->hw;
2420 int port = skge->port;
2421 struct net_device *dev = hw->dev[port];
2422
2423 netif_stop_queue(skge->netdev);
2424 netif_carrier_off(skge->netdev);
2425
2426 spin_lock_bh(&hw->phy_lock);
2427 if (is_genesis(hw)) {
2428 genesis_reset(hw, port);
2429 genesis_mac_init(hw, port);
2430 } else {
2431 yukon_reset(hw, port);
2432 yukon_init(hw, port);
2433 }
2434 spin_unlock_bh(&hw->phy_lock);
2435
2436 skge_set_multicast(dev);
2437 }
2438
2439 /* Basic MII support */
skge_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)2440 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2441 {
2442 struct mii_ioctl_data *data = if_mii(ifr);
2443 struct skge_port *skge = netdev_priv(dev);
2444 struct skge_hw *hw = skge->hw;
2445 int err = -EOPNOTSUPP;
2446
2447 if (!netif_running(dev))
2448 return -ENODEV; /* Phy still in reset */
2449
2450 switch (cmd) {
2451 case SIOCGMIIPHY:
2452 data->phy_id = hw->phy_addr;
2453
2454 fallthrough;
2455 case SIOCGMIIREG: {
2456 u16 val = 0;
2457 spin_lock_bh(&hw->phy_lock);
2458
2459 if (is_genesis(hw))
2460 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2461 else
2462 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2463 spin_unlock_bh(&hw->phy_lock);
2464 data->val_out = val;
2465 break;
2466 }
2467
2468 case SIOCSMIIREG:
2469 spin_lock_bh(&hw->phy_lock);
2470 if (is_genesis(hw))
2471 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2472 data->val_in);
2473 else
2474 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2475 data->val_in);
2476 spin_unlock_bh(&hw->phy_lock);
2477 break;
2478 }
2479 return err;
2480 }
2481
skge_ramset(struct skge_hw * hw,u16 q,u32 start,size_t len)2482 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2483 {
2484 u32 end;
2485
2486 start /= 8;
2487 len /= 8;
2488 end = start + len - 1;
2489
2490 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2491 skge_write32(hw, RB_ADDR(q, RB_START), start);
2492 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2493 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2494 skge_write32(hw, RB_ADDR(q, RB_END), end);
2495
2496 if (q == Q_R1 || q == Q_R2) {
2497 /* Set thresholds on receive queue's */
2498 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2499 start + (2*len)/3);
2500 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2501 start + (len/3));
2502 } else {
2503 /* Enable store & forward on Tx queue's because
2504 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2505 */
2506 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2507 }
2508
2509 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2510 }
2511
2512 /* Setup Bus Memory Interface */
skge_qset(struct skge_port * skge,u16 q,const struct skge_element * e)2513 static void skge_qset(struct skge_port *skge, u16 q,
2514 const struct skge_element *e)
2515 {
2516 struct skge_hw *hw = skge->hw;
2517 u32 watermark = 0x600;
2518 u64 base = skge->dma + (e->desc - skge->mem);
2519
2520 /* optimization to reduce window on 32bit/33mhz */
2521 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2522 watermark /= 2;
2523
2524 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2525 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2526 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2527 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2528 }
2529
skge_up(struct net_device * dev)2530 static int skge_up(struct net_device *dev)
2531 {
2532 struct skge_port *skge = netdev_priv(dev);
2533 struct skge_hw *hw = skge->hw;
2534 int port = skge->port;
2535 u32 chunk, ram_addr;
2536 size_t rx_size, tx_size;
2537 int err;
2538
2539 if (!is_valid_ether_addr(dev->dev_addr))
2540 return -EINVAL;
2541
2542 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2543
2544 if (dev->mtu > RX_BUF_SIZE)
2545 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2546 else
2547 skge->rx_buf_size = RX_BUF_SIZE;
2548
2549
2550 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2551 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2552 skge->mem_size = tx_size + rx_size;
2553 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size,
2554 &skge->dma, GFP_KERNEL);
2555 if (!skge->mem)
2556 return -ENOMEM;
2557
2558 BUG_ON(skge->dma & 7);
2559
2560 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2561 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n");
2562 err = -EINVAL;
2563 goto free_pci_mem;
2564 }
2565
2566 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2567 if (err)
2568 goto free_pci_mem;
2569
2570 err = skge_rx_fill(dev);
2571 if (err)
2572 goto free_rx_ring;
2573
2574 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2575 skge->dma + rx_size);
2576 if (err)
2577 goto free_rx_ring;
2578
2579 if (hw->ports == 1) {
2580 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2581 dev->name, hw);
2582 if (err) {
2583 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2584 hw->pdev->irq, err);
2585 goto free_tx_ring;
2586 }
2587 }
2588
2589 /* Initialize MAC */
2590 netif_carrier_off(dev);
2591 spin_lock_bh(&hw->phy_lock);
2592 if (is_genesis(hw))
2593 genesis_mac_init(hw, port);
2594 else
2595 yukon_mac_init(hw, port);
2596 spin_unlock_bh(&hw->phy_lock);
2597
2598 /* Configure RAMbuffers - equally between ports and tx/rx */
2599 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2600 ram_addr = hw->ram_offset + 2 * chunk * port;
2601
2602 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2603 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2604
2605 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2606 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2607 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2608
2609 /* Start receiver BMU */
2610 wmb();
2611 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2612 skge_led(skge, LED_MODE_ON);
2613
2614 spin_lock_irq(&hw->hw_lock);
2615 hw->intr_mask |= portmask[port];
2616 skge_write32(hw, B0_IMSK, hw->intr_mask);
2617 skge_read32(hw, B0_IMSK);
2618 spin_unlock_irq(&hw->hw_lock);
2619
2620 napi_enable(&skge->napi);
2621
2622 skge_set_multicast(dev);
2623
2624 return 0;
2625
2626 free_tx_ring:
2627 kfree(skge->tx_ring.start);
2628 free_rx_ring:
2629 skge_rx_clean(skge);
2630 kfree(skge->rx_ring.start);
2631 free_pci_mem:
2632 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2633 skge->dma);
2634 skge->mem = NULL;
2635
2636 return err;
2637 }
2638
2639 /* stop receiver */
skge_rx_stop(struct skge_hw * hw,int port)2640 static void skge_rx_stop(struct skge_hw *hw, int port)
2641 {
2642 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2643 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2644 RB_RST_SET|RB_DIS_OP_MD);
2645 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2646 }
2647
skge_down(struct net_device * dev)2648 static int skge_down(struct net_device *dev)
2649 {
2650 struct skge_port *skge = netdev_priv(dev);
2651 struct skge_hw *hw = skge->hw;
2652 int port = skge->port;
2653
2654 if (!skge->mem)
2655 return 0;
2656
2657 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2658
2659 netif_tx_disable(dev);
2660
2661 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2662 del_timer_sync(&skge->link_timer);
2663
2664 napi_disable(&skge->napi);
2665 netif_carrier_off(dev);
2666
2667 spin_lock_irq(&hw->hw_lock);
2668 hw->intr_mask &= ~portmask[port];
2669 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2670 skge_read32(hw, B0_IMSK);
2671 spin_unlock_irq(&hw->hw_lock);
2672
2673 if (hw->ports == 1)
2674 free_irq(hw->pdev->irq, hw);
2675
2676 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2677 if (is_genesis(hw))
2678 genesis_stop(skge);
2679 else
2680 yukon_stop(skge);
2681
2682 /* Stop transmitter */
2683 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2684 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2685 RB_RST_SET|RB_DIS_OP_MD);
2686
2687
2688 /* Disable Force Sync bit and Enable Alloc bit */
2689 skge_write8(hw, SK_REG(port, TXA_CTRL),
2690 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2691
2692 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2693 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2694 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2695
2696 /* Reset PCI FIFO */
2697 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2698 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2699
2700 /* Reset the RAM Buffer async Tx queue */
2701 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2702
2703 skge_rx_stop(hw, port);
2704
2705 if (is_genesis(hw)) {
2706 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2707 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2708 } else {
2709 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2710 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2711 }
2712
2713 skge_led(skge, LED_MODE_OFF);
2714
2715 netif_tx_lock_bh(dev);
2716 skge_tx_clean(dev);
2717 netif_tx_unlock_bh(dev);
2718
2719 skge_rx_clean(skge);
2720
2721 kfree(skge->rx_ring.start);
2722 kfree(skge->tx_ring.start);
2723 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2724 skge->dma);
2725 skge->mem = NULL;
2726 return 0;
2727 }
2728
skge_avail(const struct skge_ring * ring)2729 static inline int skge_avail(const struct skge_ring *ring)
2730 {
2731 smp_mb();
2732 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2733 + (ring->to_clean - ring->to_use) - 1;
2734 }
2735
skge_xmit_frame(struct sk_buff * skb,struct net_device * dev)2736 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2737 struct net_device *dev)
2738 {
2739 struct skge_port *skge = netdev_priv(dev);
2740 struct skge_hw *hw = skge->hw;
2741 struct skge_element *e;
2742 struct skge_tx_desc *td;
2743 int i;
2744 u32 control, len;
2745 dma_addr_t map;
2746
2747 if (skb_padto(skb, ETH_ZLEN))
2748 return NETDEV_TX_OK;
2749
2750 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2751 return NETDEV_TX_BUSY;
2752
2753 e = skge->tx_ring.to_use;
2754 td = e->desc;
2755 BUG_ON(td->control & BMU_OWN);
2756 e->skb = skb;
2757 len = skb_headlen(skb);
2758 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2759 if (dma_mapping_error(&hw->pdev->dev, map))
2760 goto mapping_error;
2761
2762 dma_unmap_addr_set(e, mapaddr, map);
2763 dma_unmap_len_set(e, maplen, len);
2764
2765 td->dma_lo = lower_32_bits(map);
2766 td->dma_hi = upper_32_bits(map);
2767
2768 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2769 const int offset = skb_checksum_start_offset(skb);
2770
2771 /* This seems backwards, but it is what the sk98lin
2772 * does. Looks like hardware is wrong?
2773 */
2774 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2775 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2776 control = BMU_TCP_CHECK;
2777 else
2778 control = BMU_UDP_CHECK;
2779
2780 td->csum_offs = 0;
2781 td->csum_start = offset;
2782 td->csum_write = offset + skb->csum_offset;
2783 } else
2784 control = BMU_CHECK;
2785
2786 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2787 control |= BMU_EOF | BMU_IRQ_EOF;
2788 else {
2789 struct skge_tx_desc *tf = td;
2790
2791 control |= BMU_STFWD;
2792 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2793 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2794
2795 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2796 skb_frag_size(frag), DMA_TO_DEVICE);
2797 if (dma_mapping_error(&hw->pdev->dev, map))
2798 goto mapping_unwind;
2799
2800 e = e->next;
2801 e->skb = skb;
2802 tf = e->desc;
2803 BUG_ON(tf->control & BMU_OWN);
2804
2805 tf->dma_lo = lower_32_bits(map);
2806 tf->dma_hi = upper_32_bits(map);
2807 dma_unmap_addr_set(e, mapaddr, map);
2808 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2809
2810 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2811 }
2812 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2813 }
2814 /* Make sure all the descriptors written */
2815 wmb();
2816 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2817 wmb();
2818
2819 netdev_sent_queue(dev, skb->len);
2820
2821 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2822
2823 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2824 "tx queued, slot %td, len %d\n",
2825 e - skge->tx_ring.start, skb->len);
2826
2827 skge->tx_ring.to_use = e->next;
2828 smp_wmb();
2829
2830 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2831 netdev_dbg(dev, "transmit queue full\n");
2832 netif_stop_queue(dev);
2833 }
2834
2835 return NETDEV_TX_OK;
2836
2837 mapping_unwind:
2838 e = skge->tx_ring.to_use;
2839 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2840 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2841 while (i-- > 0) {
2842 e = e->next;
2843 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2844 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2845 }
2846
2847 mapping_error:
2848 if (net_ratelimit())
2849 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2850 dev_kfree_skb_any(skb);
2851 return NETDEV_TX_OK;
2852 }
2853
2854
2855 /* Free resources associated with this reing element */
skge_tx_unmap(struct pci_dev * pdev,struct skge_element * e,u32 control)2856 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2857 u32 control)
2858 {
2859 /* skb header vs. fragment */
2860 if (control & BMU_STF)
2861 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr),
2862 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2863 else
2864 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr),
2865 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2866 }
2867
2868 /* Free all buffers in transmit ring */
skge_tx_clean(struct net_device * dev)2869 static void skge_tx_clean(struct net_device *dev)
2870 {
2871 struct skge_port *skge = netdev_priv(dev);
2872 struct skge_element *e;
2873
2874 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2875 struct skge_tx_desc *td = e->desc;
2876
2877 skge_tx_unmap(skge->hw->pdev, e, td->control);
2878
2879 if (td->control & BMU_EOF)
2880 dev_kfree_skb(e->skb);
2881 td->control = 0;
2882 }
2883
2884 netdev_reset_queue(dev);
2885 skge->tx_ring.to_clean = e;
2886 }
2887
skge_tx_timeout(struct net_device * dev,unsigned int txqueue)2888 static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue)
2889 {
2890 struct skge_port *skge = netdev_priv(dev);
2891
2892 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2893
2894 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2895 skge_tx_clean(dev);
2896 netif_wake_queue(dev);
2897 }
2898
skge_change_mtu(struct net_device * dev,int new_mtu)2899 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2900 {
2901 int err;
2902
2903 if (!netif_running(dev)) {
2904 dev->mtu = new_mtu;
2905 return 0;
2906 }
2907
2908 skge_down(dev);
2909
2910 dev->mtu = new_mtu;
2911
2912 err = skge_up(dev);
2913 if (err)
2914 dev_close(dev);
2915
2916 return err;
2917 }
2918
2919 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2920
genesis_add_filter(u8 filter[8],const u8 * addr)2921 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2922 {
2923 u32 crc, bit;
2924
2925 crc = ether_crc_le(ETH_ALEN, addr);
2926 bit = ~crc & 0x3f;
2927 filter[bit/8] |= 1 << (bit%8);
2928 }
2929
genesis_set_multicast(struct net_device * dev)2930 static void genesis_set_multicast(struct net_device *dev)
2931 {
2932 struct skge_port *skge = netdev_priv(dev);
2933 struct skge_hw *hw = skge->hw;
2934 int port = skge->port;
2935 struct netdev_hw_addr *ha;
2936 u32 mode;
2937 u8 filter[8];
2938
2939 mode = xm_read32(hw, port, XM_MODE);
2940 mode |= XM_MD_ENA_HASH;
2941 if (dev->flags & IFF_PROMISC)
2942 mode |= XM_MD_ENA_PROM;
2943 else
2944 mode &= ~XM_MD_ENA_PROM;
2945
2946 if (dev->flags & IFF_ALLMULTI)
2947 memset(filter, 0xff, sizeof(filter));
2948 else {
2949 memset(filter, 0, sizeof(filter));
2950
2951 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2952 skge->flow_status == FLOW_STAT_SYMMETRIC)
2953 genesis_add_filter(filter, pause_mc_addr);
2954
2955 netdev_for_each_mc_addr(ha, dev)
2956 genesis_add_filter(filter, ha->addr);
2957 }
2958
2959 xm_write32(hw, port, XM_MODE, mode);
2960 xm_outhash(hw, port, XM_HSM, filter);
2961 }
2962
yukon_add_filter(u8 filter[8],const u8 * addr)2963 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2964 {
2965 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2966
2967 filter[bit / 8] |= 1 << (bit % 8);
2968 }
2969
yukon_set_multicast(struct net_device * dev)2970 static void yukon_set_multicast(struct net_device *dev)
2971 {
2972 struct skge_port *skge = netdev_priv(dev);
2973 struct skge_hw *hw = skge->hw;
2974 int port = skge->port;
2975 struct netdev_hw_addr *ha;
2976 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2977 skge->flow_status == FLOW_STAT_SYMMETRIC);
2978 u16 reg;
2979 u8 filter[8];
2980
2981 memset(filter, 0, sizeof(filter));
2982
2983 reg = gma_read16(hw, port, GM_RX_CTRL);
2984 reg |= GM_RXCR_UCF_ENA;
2985
2986 if (dev->flags & IFF_PROMISC) /* promiscuous */
2987 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2988 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2989 memset(filter, 0xff, sizeof(filter));
2990 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2991 reg &= ~GM_RXCR_MCF_ENA;
2992 else {
2993 reg |= GM_RXCR_MCF_ENA;
2994
2995 if (rx_pause)
2996 yukon_add_filter(filter, pause_mc_addr);
2997
2998 netdev_for_each_mc_addr(ha, dev)
2999 yukon_add_filter(filter, ha->addr);
3000 }
3001
3002
3003 gma_write16(hw, port, GM_MC_ADDR_H1,
3004 (u16)filter[0] | ((u16)filter[1] << 8));
3005 gma_write16(hw, port, GM_MC_ADDR_H2,
3006 (u16)filter[2] | ((u16)filter[3] << 8));
3007 gma_write16(hw, port, GM_MC_ADDR_H3,
3008 (u16)filter[4] | ((u16)filter[5] << 8));
3009 gma_write16(hw, port, GM_MC_ADDR_H4,
3010 (u16)filter[6] | ((u16)filter[7] << 8));
3011
3012 gma_write16(hw, port, GM_RX_CTRL, reg);
3013 }
3014
phy_length(const struct skge_hw * hw,u32 status)3015 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3016 {
3017 if (is_genesis(hw))
3018 return status >> XMR_FS_LEN_SHIFT;
3019 else
3020 return status >> GMR_FS_LEN_SHIFT;
3021 }
3022
bad_phy_status(const struct skge_hw * hw,u32 status)3023 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3024 {
3025 if (is_genesis(hw))
3026 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3027 else
3028 return (status & GMR_FS_ANY_ERR) ||
3029 (status & GMR_FS_RX_OK) == 0;
3030 }
3031
skge_set_multicast(struct net_device * dev)3032 static void skge_set_multicast(struct net_device *dev)
3033 {
3034 struct skge_port *skge = netdev_priv(dev);
3035
3036 if (is_genesis(skge->hw))
3037 genesis_set_multicast(dev);
3038 else
3039 yukon_set_multicast(dev);
3040
3041 }
3042
3043
3044 /* Get receive buffer from descriptor.
3045 * Handles copy of small buffers and reallocation failures
3046 */
skge_rx_get(struct net_device * dev,struct skge_element * e,u32 control,u32 status,u16 csum)3047 static struct sk_buff *skge_rx_get(struct net_device *dev,
3048 struct skge_element *e,
3049 u32 control, u32 status, u16 csum)
3050 {
3051 struct skge_port *skge = netdev_priv(dev);
3052 struct sk_buff *skb;
3053 u16 len = control & BMU_BBC;
3054
3055 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3056 "rx slot %td status 0x%x len %d\n",
3057 e - skge->rx_ring.start, status, len);
3058
3059 if (len > skge->rx_buf_size)
3060 goto error;
3061
3062 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3063 goto error;
3064
3065 if (bad_phy_status(skge->hw, status))
3066 goto error;
3067
3068 if (phy_length(skge->hw, status) != len)
3069 goto error;
3070
3071 if (len < RX_COPY_THRESHOLD) {
3072 skb = netdev_alloc_skb_ip_align(dev, len);
3073 if (!skb)
3074 goto resubmit;
3075
3076 dma_sync_single_for_cpu(&skge->hw->pdev->dev,
3077 dma_unmap_addr(e, mapaddr),
3078 dma_unmap_len(e, maplen),
3079 DMA_FROM_DEVICE);
3080 skb_copy_from_linear_data(e->skb, skb->data, len);
3081 dma_sync_single_for_device(&skge->hw->pdev->dev,
3082 dma_unmap_addr(e, mapaddr),
3083 dma_unmap_len(e, maplen),
3084 DMA_FROM_DEVICE);
3085 skge_rx_reuse(e, skge->rx_buf_size);
3086 } else {
3087 struct skge_element ee;
3088 struct sk_buff *nskb;
3089
3090 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3091 if (!nskb)
3092 goto resubmit;
3093
3094 ee = *e;
3095
3096 skb = ee.skb;
3097 prefetch(skb->data);
3098
3099 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3100 dev_kfree_skb(nskb);
3101 goto resubmit;
3102 }
3103
3104 dma_unmap_single(&skge->hw->pdev->dev,
3105 dma_unmap_addr(&ee, mapaddr),
3106 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE);
3107 }
3108
3109 skb_put(skb, len);
3110
3111 if (dev->features & NETIF_F_RXCSUM) {
3112 skb->csum = le16_to_cpu(csum);
3113 skb->ip_summed = CHECKSUM_COMPLETE;
3114 }
3115
3116 skb->protocol = eth_type_trans(skb, dev);
3117
3118 return skb;
3119 error:
3120
3121 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3122 "rx err, slot %td control 0x%x status 0x%x\n",
3123 e - skge->rx_ring.start, control, status);
3124
3125 if (is_genesis(skge->hw)) {
3126 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3127 dev->stats.rx_length_errors++;
3128 if (status & XMR_FS_FRA_ERR)
3129 dev->stats.rx_frame_errors++;
3130 if (status & XMR_FS_FCS_ERR)
3131 dev->stats.rx_crc_errors++;
3132 } else {
3133 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3134 dev->stats.rx_length_errors++;
3135 if (status & GMR_FS_FRAGMENT)
3136 dev->stats.rx_frame_errors++;
3137 if (status & GMR_FS_CRC_ERR)
3138 dev->stats.rx_crc_errors++;
3139 }
3140
3141 resubmit:
3142 skge_rx_reuse(e, skge->rx_buf_size);
3143 return NULL;
3144 }
3145
3146 /* Free all buffers in Tx ring which are no longer owned by device */
skge_tx_done(struct net_device * dev)3147 static void skge_tx_done(struct net_device *dev)
3148 {
3149 struct skge_port *skge = netdev_priv(dev);
3150 struct skge_ring *ring = &skge->tx_ring;
3151 struct skge_element *e;
3152 unsigned int bytes_compl = 0, pkts_compl = 0;
3153
3154 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3155
3156 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3157 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3158
3159 if (control & BMU_OWN)
3160 break;
3161
3162 skge_tx_unmap(skge->hw->pdev, e, control);
3163
3164 if (control & BMU_EOF) {
3165 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3166 "tx done slot %td\n",
3167 e - skge->tx_ring.start);
3168
3169 pkts_compl++;
3170 bytes_compl += e->skb->len;
3171
3172 dev_consume_skb_any(e->skb);
3173 }
3174 }
3175 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3176 skge->tx_ring.to_clean = e;
3177
3178 /* Can run lockless until we need to synchronize to restart queue. */
3179 smp_mb();
3180
3181 if (unlikely(netif_queue_stopped(dev) &&
3182 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3183 netif_tx_lock(dev);
3184 if (unlikely(netif_queue_stopped(dev) &&
3185 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3186 netif_wake_queue(dev);
3187
3188 }
3189 netif_tx_unlock(dev);
3190 }
3191 }
3192
skge_poll(struct napi_struct * napi,int budget)3193 static int skge_poll(struct napi_struct *napi, int budget)
3194 {
3195 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3196 struct net_device *dev = skge->netdev;
3197 struct skge_hw *hw = skge->hw;
3198 struct skge_ring *ring = &skge->rx_ring;
3199 struct skge_element *e;
3200 int work_done = 0;
3201
3202 skge_tx_done(dev);
3203
3204 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3205
3206 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3207 struct skge_rx_desc *rd = e->desc;
3208 struct sk_buff *skb;
3209 u32 control;
3210
3211 rmb();
3212 control = rd->control;
3213 if (control & BMU_OWN)
3214 break;
3215
3216 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3217 if (likely(skb)) {
3218 napi_gro_receive(napi, skb);
3219 ++work_done;
3220 }
3221 }
3222 ring->to_clean = e;
3223
3224 /* restart receiver */
3225 wmb();
3226 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3227
3228 if (work_done < budget && napi_complete_done(napi, work_done)) {
3229 unsigned long flags;
3230
3231 spin_lock_irqsave(&hw->hw_lock, flags);
3232 hw->intr_mask |= napimask[skge->port];
3233 skge_write32(hw, B0_IMSK, hw->intr_mask);
3234 skge_read32(hw, B0_IMSK);
3235 spin_unlock_irqrestore(&hw->hw_lock, flags);
3236 }
3237
3238 return work_done;
3239 }
3240
3241 /* Parity errors seem to happen when Genesis is connected to a switch
3242 * with no other ports present. Heartbeat error??
3243 */
skge_mac_parity(struct skge_hw * hw,int port)3244 static void skge_mac_parity(struct skge_hw *hw, int port)
3245 {
3246 struct net_device *dev = hw->dev[port];
3247
3248 ++dev->stats.tx_heartbeat_errors;
3249
3250 if (is_genesis(hw))
3251 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3252 MFF_CLR_PERR);
3253 else
3254 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3255 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3256 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3257 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3258 }
3259
skge_mac_intr(struct skge_hw * hw,int port)3260 static void skge_mac_intr(struct skge_hw *hw, int port)
3261 {
3262 if (is_genesis(hw))
3263 genesis_mac_intr(hw, port);
3264 else
3265 yukon_mac_intr(hw, port);
3266 }
3267
3268 /* Handle device specific framing and timeout interrupts */
skge_error_irq(struct skge_hw * hw)3269 static void skge_error_irq(struct skge_hw *hw)
3270 {
3271 struct pci_dev *pdev = hw->pdev;
3272 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3273
3274 if (is_genesis(hw)) {
3275 /* clear xmac errors */
3276 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3277 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3278 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3279 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3280 } else {
3281 /* Timestamp (unused) overflow */
3282 if (hwstatus & IS_IRQ_TIST_OV)
3283 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3284 }
3285
3286 if (hwstatus & IS_RAM_RD_PAR) {
3287 dev_err(&pdev->dev, "Ram read data parity error\n");
3288 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3289 }
3290
3291 if (hwstatus & IS_RAM_WR_PAR) {
3292 dev_err(&pdev->dev, "Ram write data parity error\n");
3293 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3294 }
3295
3296 if (hwstatus & IS_M1_PAR_ERR)
3297 skge_mac_parity(hw, 0);
3298
3299 if (hwstatus & IS_M2_PAR_ERR)
3300 skge_mac_parity(hw, 1);
3301
3302 if (hwstatus & IS_R1_PAR_ERR) {
3303 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3304 hw->dev[0]->name);
3305 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3306 }
3307
3308 if (hwstatus & IS_R2_PAR_ERR) {
3309 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3310 hw->dev[1]->name);
3311 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3312 }
3313
3314 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3315 u16 pci_status, pci_cmd;
3316
3317 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3318 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3319
3320 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3321 pci_cmd, pci_status);
3322
3323 /* Write the error bits back to clear them. */
3324 pci_status &= PCI_STATUS_ERROR_BITS;
3325 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3326 pci_write_config_word(pdev, PCI_COMMAND,
3327 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3328 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3329 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3330
3331 /* if error still set then just ignore it */
3332 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3333 if (hwstatus & IS_IRQ_STAT) {
3334 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3335 hw->intr_mask &= ~IS_HW_ERR;
3336 }
3337 }
3338 }
3339
3340 /*
3341 * Interrupt from PHY are handled in tasklet (softirq)
3342 * because accessing phy registers requires spin wait which might
3343 * cause excess interrupt latency.
3344 */
skge_extirq(struct tasklet_struct * t)3345 static void skge_extirq(struct tasklet_struct *t)
3346 {
3347 struct skge_hw *hw = from_tasklet(hw, t, phy_task);
3348 int port;
3349
3350 for (port = 0; port < hw->ports; port++) {
3351 struct net_device *dev = hw->dev[port];
3352
3353 if (netif_running(dev)) {
3354 struct skge_port *skge = netdev_priv(dev);
3355
3356 spin_lock(&hw->phy_lock);
3357 if (!is_genesis(hw))
3358 yukon_phy_intr(skge);
3359 else if (hw->phy_type == SK_PHY_BCOM)
3360 bcom_phy_intr(skge);
3361 spin_unlock(&hw->phy_lock);
3362 }
3363 }
3364
3365 spin_lock_irq(&hw->hw_lock);
3366 hw->intr_mask |= IS_EXT_REG;
3367 skge_write32(hw, B0_IMSK, hw->intr_mask);
3368 skge_read32(hw, B0_IMSK);
3369 spin_unlock_irq(&hw->hw_lock);
3370 }
3371
skge_intr(int irq,void * dev_id)3372 static irqreturn_t skge_intr(int irq, void *dev_id)
3373 {
3374 struct skge_hw *hw = dev_id;
3375 u32 status;
3376 int handled = 0;
3377
3378 spin_lock(&hw->hw_lock);
3379 /* Reading this register masks IRQ */
3380 status = skge_read32(hw, B0_SP_ISRC);
3381 if (status == 0 || status == ~0)
3382 goto out;
3383
3384 handled = 1;
3385 status &= hw->intr_mask;
3386 if (status & IS_EXT_REG) {
3387 hw->intr_mask &= ~IS_EXT_REG;
3388 tasklet_schedule(&hw->phy_task);
3389 }
3390
3391 if (status & (IS_XA1_F|IS_R1_F)) {
3392 struct skge_port *skge = netdev_priv(hw->dev[0]);
3393 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3394 napi_schedule(&skge->napi);
3395 }
3396
3397 if (status & IS_PA_TO_TX1)
3398 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3399
3400 if (status & IS_PA_TO_RX1) {
3401 ++hw->dev[0]->stats.rx_over_errors;
3402 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3403 }
3404
3405
3406 if (status & IS_MAC1)
3407 skge_mac_intr(hw, 0);
3408
3409 if (hw->dev[1]) {
3410 struct skge_port *skge = netdev_priv(hw->dev[1]);
3411
3412 if (status & (IS_XA2_F|IS_R2_F)) {
3413 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3414 napi_schedule(&skge->napi);
3415 }
3416
3417 if (status & IS_PA_TO_RX2) {
3418 ++hw->dev[1]->stats.rx_over_errors;
3419 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3420 }
3421
3422 if (status & IS_PA_TO_TX2)
3423 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3424
3425 if (status & IS_MAC2)
3426 skge_mac_intr(hw, 1);
3427 }
3428
3429 if (status & IS_HW_ERR)
3430 skge_error_irq(hw);
3431 out:
3432 skge_write32(hw, B0_IMSK, hw->intr_mask);
3433 skge_read32(hw, B0_IMSK);
3434 spin_unlock(&hw->hw_lock);
3435
3436 return IRQ_RETVAL(handled);
3437 }
3438
3439 #ifdef CONFIG_NET_POLL_CONTROLLER
skge_netpoll(struct net_device * dev)3440 static void skge_netpoll(struct net_device *dev)
3441 {
3442 struct skge_port *skge = netdev_priv(dev);
3443
3444 disable_irq(dev->irq);
3445 skge_intr(dev->irq, skge->hw);
3446 enable_irq(dev->irq);
3447 }
3448 #endif
3449
skge_set_mac_address(struct net_device * dev,void * p)3450 static int skge_set_mac_address(struct net_device *dev, void *p)
3451 {
3452 struct skge_port *skge = netdev_priv(dev);
3453 struct skge_hw *hw = skge->hw;
3454 unsigned port = skge->port;
3455 const struct sockaddr *addr = p;
3456 u16 ctrl;
3457
3458 if (!is_valid_ether_addr(addr->sa_data))
3459 return -EADDRNOTAVAIL;
3460
3461 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3462
3463 if (!netif_running(dev)) {
3464 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3465 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3466 } else {
3467 /* disable Rx */
3468 spin_lock_bh(&hw->phy_lock);
3469 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3470 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3471
3472 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3473 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3474
3475 if (is_genesis(hw))
3476 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3477 else {
3478 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3479 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3480 }
3481
3482 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3483 spin_unlock_bh(&hw->phy_lock);
3484 }
3485
3486 return 0;
3487 }
3488
3489 static const struct {
3490 u8 id;
3491 const char *name;
3492 } skge_chips[] = {
3493 { CHIP_ID_GENESIS, "Genesis" },
3494 { CHIP_ID_YUKON, "Yukon" },
3495 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3496 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3497 };
3498
skge_board_name(const struct skge_hw * hw)3499 static const char *skge_board_name(const struct skge_hw *hw)
3500 {
3501 int i;
3502 static char buf[16];
3503
3504 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3505 if (skge_chips[i].id == hw->chip_id)
3506 return skge_chips[i].name;
3507
3508 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3509 return buf;
3510 }
3511
3512
3513 /*
3514 * Setup the board data structure, but don't bring up
3515 * the port(s)
3516 */
skge_reset(struct skge_hw * hw)3517 static int skge_reset(struct skge_hw *hw)
3518 {
3519 u32 reg;
3520 u16 ctst, pci_status;
3521 u8 t8, mac_cfg, pmd_type;
3522 int i;
3523
3524 ctst = skge_read16(hw, B0_CTST);
3525
3526 /* do a SW reset */
3527 skge_write8(hw, B0_CTST, CS_RST_SET);
3528 skge_write8(hw, B0_CTST, CS_RST_CLR);
3529
3530 /* clear PCI errors, if any */
3531 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3532 skge_write8(hw, B2_TST_CTRL2, 0);
3533
3534 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3535 pci_write_config_word(hw->pdev, PCI_STATUS,
3536 pci_status | PCI_STATUS_ERROR_BITS);
3537 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3538 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3539
3540 /* restore CLK_RUN bits (for Yukon-Lite) */
3541 skge_write16(hw, B0_CTST,
3542 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3543
3544 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3545 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3546 pmd_type = skge_read8(hw, B2_PMD_TYP);
3547 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3548
3549 switch (hw->chip_id) {
3550 case CHIP_ID_GENESIS:
3551 #ifdef CONFIG_SKGE_GENESIS
3552 switch (hw->phy_type) {
3553 case SK_PHY_XMAC:
3554 hw->phy_addr = PHY_ADDR_XMAC;
3555 break;
3556 case SK_PHY_BCOM:
3557 hw->phy_addr = PHY_ADDR_BCOM;
3558 break;
3559 default:
3560 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3561 hw->phy_type);
3562 return -EOPNOTSUPP;
3563 }
3564 break;
3565 #else
3566 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3567 return -EOPNOTSUPP;
3568 #endif
3569
3570 case CHIP_ID_YUKON:
3571 case CHIP_ID_YUKON_LITE:
3572 case CHIP_ID_YUKON_LP:
3573 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3574 hw->copper = 1;
3575
3576 hw->phy_addr = PHY_ADDR_MARV;
3577 break;
3578
3579 default:
3580 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3581 hw->chip_id);
3582 return -EOPNOTSUPP;
3583 }
3584
3585 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3586 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3587 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3588
3589 /* read the adapters RAM size */
3590 t8 = skge_read8(hw, B2_E_0);
3591 if (is_genesis(hw)) {
3592 if (t8 == 3) {
3593 /* special case: 4 x 64k x 36, offset = 0x80000 */
3594 hw->ram_size = 0x100000;
3595 hw->ram_offset = 0x80000;
3596 } else
3597 hw->ram_size = t8 * 512;
3598 } else if (t8 == 0)
3599 hw->ram_size = 0x20000;
3600 else
3601 hw->ram_size = t8 * 4096;
3602
3603 hw->intr_mask = IS_HW_ERR;
3604
3605 /* Use PHY IRQ for all but fiber based Genesis board */
3606 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3607 hw->intr_mask |= IS_EXT_REG;
3608
3609 if (is_genesis(hw))
3610 genesis_init(hw);
3611 else {
3612 /* switch power to VCC (WA for VAUX problem) */
3613 skge_write8(hw, B0_POWER_CTRL,
3614 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3615
3616 /* avoid boards with stuck Hardware error bits */
3617 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3618 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3619 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3620 hw->intr_mask &= ~IS_HW_ERR;
3621 }
3622
3623 /* Clear PHY COMA */
3624 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3625 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3626 reg &= ~PCI_PHY_COMA;
3627 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3628 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3629
3630
3631 for (i = 0; i < hw->ports; i++) {
3632 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3633 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3634 }
3635 }
3636
3637 /* turn off hardware timer (unused) */
3638 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3639 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3640 skge_write8(hw, B0_LED, LED_STAT_ON);
3641
3642 /* enable the Tx Arbiters */
3643 for (i = 0; i < hw->ports; i++)
3644 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3645
3646 /* Initialize ram interface */
3647 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3648
3649 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3650 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3651 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3661
3662 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3663
3664 /* Set interrupt moderation for Transmit only
3665 * Receive interrupts avoided by NAPI
3666 */
3667 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3668 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3669 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3670
3671 /* Leave irq disabled until first port is brought up. */
3672 skge_write32(hw, B0_IMSK, 0);
3673
3674 for (i = 0; i < hw->ports; i++) {
3675 if (is_genesis(hw))
3676 genesis_reset(hw, i);
3677 else
3678 yukon_reset(hw, i);
3679 }
3680
3681 return 0;
3682 }
3683
3684
3685 #ifdef CONFIG_SKGE_DEBUG
3686
3687 static struct dentry *skge_debug;
3688
skge_debug_show(struct seq_file * seq,void * v)3689 static int skge_debug_show(struct seq_file *seq, void *v)
3690 {
3691 struct net_device *dev = seq->private;
3692 const struct skge_port *skge = netdev_priv(dev);
3693 const struct skge_hw *hw = skge->hw;
3694 const struct skge_element *e;
3695
3696 if (!netif_running(dev))
3697 return -ENETDOWN;
3698
3699 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3700 skge_read32(hw, B0_IMSK));
3701
3702 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3703 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3704 const struct skge_tx_desc *t = e->desc;
3705 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3706 t->control, t->dma_hi, t->dma_lo, t->status,
3707 t->csum_offs, t->csum_write, t->csum_start);
3708 }
3709
3710 seq_puts(seq, "\nRx Ring:\n");
3711 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3712 const struct skge_rx_desc *r = e->desc;
3713
3714 if (r->control & BMU_OWN)
3715 break;
3716
3717 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3718 r->control, r->dma_hi, r->dma_lo, r->status,
3719 r->timestamp, r->csum1, r->csum1_start);
3720 }
3721
3722 return 0;
3723 }
3724 DEFINE_SHOW_ATTRIBUTE(skge_debug);
3725
3726 /*
3727 * Use network device events to create/remove/rename
3728 * debugfs file entries
3729 */
skge_device_event(struct notifier_block * unused,unsigned long event,void * ptr)3730 static int skge_device_event(struct notifier_block *unused,
3731 unsigned long event, void *ptr)
3732 {
3733 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3734 struct skge_port *skge;
3735
3736 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3737 goto done;
3738
3739 skge = netdev_priv(dev);
3740 switch (event) {
3741 case NETDEV_CHANGENAME:
3742 if (skge->debugfs)
3743 skge->debugfs = debugfs_rename(skge_debug,
3744 skge->debugfs,
3745 skge_debug, dev->name);
3746 break;
3747
3748 case NETDEV_GOING_DOWN:
3749 debugfs_remove(skge->debugfs);
3750 skge->debugfs = NULL;
3751 break;
3752
3753 case NETDEV_UP:
3754 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug,
3755 dev, &skge_debug_fops);
3756 break;
3757 }
3758
3759 done:
3760 return NOTIFY_DONE;
3761 }
3762
3763 static struct notifier_block skge_notifier = {
3764 .notifier_call = skge_device_event,
3765 };
3766
3767
skge_debug_init(void)3768 static __init void skge_debug_init(void)
3769 {
3770 skge_debug = debugfs_create_dir("skge", NULL);
3771
3772 register_netdevice_notifier(&skge_notifier);
3773 }
3774
skge_debug_cleanup(void)3775 static __exit void skge_debug_cleanup(void)
3776 {
3777 if (skge_debug) {
3778 unregister_netdevice_notifier(&skge_notifier);
3779 debugfs_remove(skge_debug);
3780 skge_debug = NULL;
3781 }
3782 }
3783
3784 #else
3785 #define skge_debug_init()
3786 #define skge_debug_cleanup()
3787 #endif
3788
3789 static const struct net_device_ops skge_netdev_ops = {
3790 .ndo_open = skge_up,
3791 .ndo_stop = skge_down,
3792 .ndo_start_xmit = skge_xmit_frame,
3793 .ndo_eth_ioctl = skge_ioctl,
3794 .ndo_get_stats = skge_get_stats,
3795 .ndo_tx_timeout = skge_tx_timeout,
3796 .ndo_change_mtu = skge_change_mtu,
3797 .ndo_validate_addr = eth_validate_addr,
3798 .ndo_set_rx_mode = skge_set_multicast,
3799 .ndo_set_mac_address = skge_set_mac_address,
3800 #ifdef CONFIG_NET_POLL_CONTROLLER
3801 .ndo_poll_controller = skge_netpoll,
3802 #endif
3803 };
3804
3805
3806 /* Initialize network device */
skge_devinit(struct skge_hw * hw,int port,int highmem)3807 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3808 int highmem)
3809 {
3810 struct skge_port *skge;
3811 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3812
3813 if (!dev)
3814 return NULL;
3815
3816 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3817 dev->netdev_ops = &skge_netdev_ops;
3818 dev->ethtool_ops = &skge_ethtool_ops;
3819 dev->watchdog_timeo = TX_WATCHDOG;
3820 dev->irq = hw->pdev->irq;
3821
3822 /* MTU range: 60 - 9000 */
3823 dev->min_mtu = ETH_ZLEN;
3824 dev->max_mtu = ETH_JUMBO_MTU;
3825
3826 if (highmem)
3827 dev->features |= NETIF_F_HIGHDMA;
3828
3829 skge = netdev_priv(dev);
3830 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_POLL_WEIGHT);
3831 skge->netdev = dev;
3832 skge->hw = hw;
3833 skge->msg_enable = netif_msg_init(debug, default_msg);
3834
3835 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3836 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3837
3838 /* Auto speed and flow control */
3839 skge->autoneg = AUTONEG_ENABLE;
3840 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3841 skge->duplex = -1;
3842 skge->speed = -1;
3843 skge->advertising = skge_supported_modes(hw);
3844
3845 if (device_can_wakeup(&hw->pdev->dev)) {
3846 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3847 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3848 }
3849
3850 hw->dev[port] = dev;
3851
3852 skge->port = port;
3853
3854 /* Only used for Genesis XMAC */
3855 if (is_genesis(hw))
3856 timer_setup(&skge->link_timer, xm_link_timer, 0);
3857 else {
3858 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3859 NETIF_F_RXCSUM;
3860 dev->features |= dev->hw_features;
3861 }
3862
3863 /* read the mac address */
3864 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3865
3866 return dev;
3867 }
3868
skge_show_addr(struct net_device * dev)3869 static void skge_show_addr(struct net_device *dev)
3870 {
3871 const struct skge_port *skge = netdev_priv(dev);
3872
3873 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3874 }
3875
3876 static int only_32bit_dma;
3877
skge_probe(struct pci_dev * pdev,const struct pci_device_id * ent)3878 static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3879 {
3880 struct net_device *dev, *dev1;
3881 struct skge_hw *hw;
3882 int err, using_dac = 0;
3883
3884 err = pci_enable_device(pdev);
3885 if (err) {
3886 dev_err(&pdev->dev, "cannot enable PCI device\n");
3887 goto err_out;
3888 }
3889
3890 err = pci_request_regions(pdev, DRV_NAME);
3891 if (err) {
3892 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3893 goto err_out_disable_pdev;
3894 }
3895
3896 pci_set_master(pdev);
3897
3898 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3899 using_dac = 1;
3900 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
3901 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
3902 using_dac = 0;
3903 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3904 }
3905
3906 if (err) {
3907 dev_err(&pdev->dev, "no usable DMA configuration\n");
3908 goto err_out_free_regions;
3909 }
3910
3911 #ifdef __BIG_ENDIAN
3912 /* byte swap descriptors in hardware */
3913 {
3914 u32 reg;
3915
3916 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3917 reg |= PCI_REV_DESC;
3918 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3919 }
3920 #endif
3921
3922 err = -ENOMEM;
3923 /* space for skge@pci:0000:04:00.0 */
3924 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3925 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3926 if (!hw)
3927 goto err_out_free_regions;
3928
3929 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3930
3931 hw->pdev = pdev;
3932 spin_lock_init(&hw->hw_lock);
3933 spin_lock_init(&hw->phy_lock);
3934 tasklet_setup(&hw->phy_task, skge_extirq);
3935
3936 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
3937 if (!hw->regs) {
3938 dev_err(&pdev->dev, "cannot map device registers\n");
3939 goto err_out_free_hw;
3940 }
3941
3942 err = skge_reset(hw);
3943 if (err)
3944 goto err_out_iounmap;
3945
3946 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3947 DRV_VERSION,
3948 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3949 skge_board_name(hw), hw->chip_rev);
3950
3951 dev = skge_devinit(hw, 0, using_dac);
3952 if (!dev) {
3953 err = -ENOMEM;
3954 goto err_out_led_off;
3955 }
3956
3957 /* Some motherboards are broken and has zero in ROM. */
3958 if (!is_valid_ether_addr(dev->dev_addr))
3959 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3960
3961 err = register_netdev(dev);
3962 if (err) {
3963 dev_err(&pdev->dev, "cannot register net device\n");
3964 goto err_out_free_netdev;
3965 }
3966
3967 skge_show_addr(dev);
3968
3969 if (hw->ports > 1) {
3970 dev1 = skge_devinit(hw, 1, using_dac);
3971 if (!dev1) {
3972 err = -ENOMEM;
3973 goto err_out_unregister;
3974 }
3975
3976 err = register_netdev(dev1);
3977 if (err) {
3978 dev_err(&pdev->dev, "cannot register second net device\n");
3979 goto err_out_free_dev1;
3980 }
3981
3982 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3983 hw->irq_name, hw);
3984 if (err) {
3985 dev_err(&pdev->dev, "cannot assign irq %d\n",
3986 pdev->irq);
3987 goto err_out_unregister_dev1;
3988 }
3989
3990 skge_show_addr(dev1);
3991 }
3992 pci_set_drvdata(pdev, hw);
3993
3994 return 0;
3995
3996 err_out_unregister_dev1:
3997 unregister_netdev(dev1);
3998 err_out_free_dev1:
3999 free_netdev(dev1);
4000 err_out_unregister:
4001 unregister_netdev(dev);
4002 err_out_free_netdev:
4003 free_netdev(dev);
4004 err_out_led_off:
4005 skge_write16(hw, B0_LED, LED_STAT_OFF);
4006 err_out_iounmap:
4007 iounmap(hw->regs);
4008 err_out_free_hw:
4009 kfree(hw);
4010 err_out_free_regions:
4011 pci_release_regions(pdev);
4012 err_out_disable_pdev:
4013 pci_disable_device(pdev);
4014 err_out:
4015 return err;
4016 }
4017
skge_remove(struct pci_dev * pdev)4018 static void skge_remove(struct pci_dev *pdev)
4019 {
4020 struct skge_hw *hw = pci_get_drvdata(pdev);
4021 struct net_device *dev0, *dev1;
4022
4023 if (!hw)
4024 return;
4025
4026 dev1 = hw->dev[1];
4027 if (dev1)
4028 unregister_netdev(dev1);
4029 dev0 = hw->dev[0];
4030 unregister_netdev(dev0);
4031
4032 tasklet_kill(&hw->phy_task);
4033
4034 spin_lock_irq(&hw->hw_lock);
4035 hw->intr_mask = 0;
4036
4037 if (hw->ports > 1) {
4038 skge_write32(hw, B0_IMSK, 0);
4039 skge_read32(hw, B0_IMSK);
4040 }
4041 spin_unlock_irq(&hw->hw_lock);
4042
4043 skge_write16(hw, B0_LED, LED_STAT_OFF);
4044 skge_write8(hw, B0_CTST, CS_RST_SET);
4045
4046 if (hw->ports > 1)
4047 free_irq(pdev->irq, hw);
4048 pci_release_regions(pdev);
4049 pci_disable_device(pdev);
4050 if (dev1)
4051 free_netdev(dev1);
4052 free_netdev(dev0);
4053
4054 iounmap(hw->regs);
4055 kfree(hw);
4056 }
4057
4058 #ifdef CONFIG_PM_SLEEP
skge_suspend(struct device * dev)4059 static int skge_suspend(struct device *dev)
4060 {
4061 struct skge_hw *hw = dev_get_drvdata(dev);
4062 int i;
4063
4064 if (!hw)
4065 return 0;
4066
4067 for (i = 0; i < hw->ports; i++) {
4068 struct net_device *dev = hw->dev[i];
4069 struct skge_port *skge = netdev_priv(dev);
4070
4071 if (netif_running(dev))
4072 skge_down(dev);
4073
4074 if (skge->wol)
4075 skge_wol_init(skge);
4076 }
4077
4078 skge_write32(hw, B0_IMSK, 0);
4079
4080 return 0;
4081 }
4082
skge_resume(struct device * dev)4083 static int skge_resume(struct device *dev)
4084 {
4085 struct skge_hw *hw = dev_get_drvdata(dev);
4086 int i, err;
4087
4088 if (!hw)
4089 return 0;
4090
4091 err = skge_reset(hw);
4092 if (err)
4093 goto out;
4094
4095 for (i = 0; i < hw->ports; i++) {
4096 struct net_device *dev = hw->dev[i];
4097
4098 if (netif_running(dev)) {
4099 err = skge_up(dev);
4100
4101 if (err) {
4102 netdev_err(dev, "could not up: %d\n", err);
4103 dev_close(dev);
4104 goto out;
4105 }
4106 }
4107 }
4108 out:
4109 return err;
4110 }
4111
4112 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4113 #define SKGE_PM_OPS (&skge_pm_ops)
4114
4115 #else
4116
4117 #define SKGE_PM_OPS NULL
4118 #endif /* CONFIG_PM_SLEEP */
4119
skge_shutdown(struct pci_dev * pdev)4120 static void skge_shutdown(struct pci_dev *pdev)
4121 {
4122 struct skge_hw *hw = pci_get_drvdata(pdev);
4123 int i;
4124
4125 if (!hw)
4126 return;
4127
4128 for (i = 0; i < hw->ports; i++) {
4129 struct net_device *dev = hw->dev[i];
4130 struct skge_port *skge = netdev_priv(dev);
4131
4132 if (skge->wol)
4133 skge_wol_init(skge);
4134 }
4135
4136 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4137 pci_set_power_state(pdev, PCI_D3hot);
4138 }
4139
4140 static struct pci_driver skge_driver = {
4141 .name = DRV_NAME,
4142 .id_table = skge_id_table,
4143 .probe = skge_probe,
4144 .remove = skge_remove,
4145 .shutdown = skge_shutdown,
4146 .driver.pm = SKGE_PM_OPS,
4147 };
4148
4149 static const struct dmi_system_id skge_32bit_dma_boards[] = {
4150 {
4151 .ident = "Gigabyte nForce boards",
4152 .matches = {
4153 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4154 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4155 },
4156 },
4157 {
4158 .ident = "ASUS P5NSLI",
4159 .matches = {
4160 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4161 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4162 },
4163 },
4164 {
4165 .ident = "FUJITSU SIEMENS A8NE-FM",
4166 .matches = {
4167 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4168 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4169 },
4170 },
4171 {}
4172 };
4173
skge_init_module(void)4174 static int __init skge_init_module(void)
4175 {
4176 if (dmi_check_system(skge_32bit_dma_boards))
4177 only_32bit_dma = 1;
4178 skge_debug_init();
4179 return pci_register_driver(&skge_driver);
4180 }
4181
skge_cleanup_module(void)4182 static void __exit skge_cleanup_module(void)
4183 {
4184 pci_unregister_driver(&skge_driver);
4185 skge_debug_cleanup();
4186 }
4187
4188 module_init(skge_init_module);
4189 module_exit(skge_cleanup_module);
4190