• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
3  *
4  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5  */
6 
7 #include "sparx5_main_regs.h"
8 #include "sparx5_main.h"
9 #include "sparx5_port.h"
10 
11 /* The IFH bit position of the first VSTAX bit. This is because the
12  * VSTAX bit positions in Data sheet is starting from zero.
13  */
14 #define VSTAX 73
15 
16 #define ifh_encode_bitfield(ifh, value, pos, _width)			\
17 	({								\
18 		u32 width = (_width);					\
19 									\
20 		/* Max width is 5 bytes - 40 bits. In worst case this will
21 		 * spread over 6 bytes - 48 bits
22 		 */							\
23 		compiletime_assert(width <= 40,				\
24 				   "Unsupported width, must be <= 40");	\
25 		__ifh_encode_bitfield((ifh), (value), (pos), width);	\
26 	})
27 
__ifh_encode_bitfield(void * ifh,u64 value,u32 pos,u32 width)28 static void __ifh_encode_bitfield(void *ifh, u64 value, u32 pos, u32 width)
29 {
30 	u8 *ifh_hdr = ifh;
31 	/* Calculate the Start IFH byte position of this IFH bit position */
32 	u32 byte = (35 - (pos / 8));
33 	/* Calculate the Start bit position in the Start IFH byte */
34 	u32 bit  = (pos % 8);
35 	u64 encode = GENMASK_ULL(bit + width - 1, bit) & (value << bit);
36 
37 	/* The b0-b7 goes into the start IFH byte */
38 	if (encode & 0xFF)
39 		ifh_hdr[byte] |= (u8)((encode & 0xFF));
40 	/* The b8-b15 goes into the next IFH byte */
41 	if (encode & 0xFF00)
42 		ifh_hdr[byte - 1] |= (u8)((encode & 0xFF00) >> 8);
43 	/* The b16-b23 goes into the next IFH byte */
44 	if (encode & 0xFF0000)
45 		ifh_hdr[byte - 2] |= (u8)((encode & 0xFF0000) >> 16);
46 	/* The b24-b31 goes into the next IFH byte */
47 	if (encode & 0xFF000000)
48 		ifh_hdr[byte - 3] |= (u8)((encode & 0xFF000000) >> 24);
49 	/* The b32-b39 goes into the next IFH byte */
50 	if (encode & 0xFF00000000)
51 		ifh_hdr[byte - 4] |= (u8)((encode & 0xFF00000000) >> 32);
52 	/* The b40-b47 goes into the next IFH byte */
53 	if (encode & 0xFF0000000000)
54 		ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40);
55 }
56 
sparx5_set_port_ifh(void * ifh_hdr,u16 portno)57 static void sparx5_set_port_ifh(void *ifh_hdr, u16 portno)
58 {
59 	/* VSTAX.RSV = 1. MSBit must be 1 */
60 	ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79,  1);
61 	/* VSTAX.INGR_DROP_MODE = Enable. Don't make head-of-line blocking */
62 	ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 55,  1);
63 	/* MISC.CPU_MASK/DPORT = Destination port */
64 	ifh_encode_bitfield(ifh_hdr, portno,   29, 8);
65 	/* MISC.PIPELINE_PT */
66 	ifh_encode_bitfield(ifh_hdr, 16,       37, 5);
67 	/* MISC.PIPELINE_ACT */
68 	ifh_encode_bitfield(ifh_hdr, 1,        42, 3);
69 	/* FWD.SRC_PORT = CPU */
70 	ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7);
71 	/* FWD.SFLOW_ID (disable SFlow sampling) */
72 	ifh_encode_bitfield(ifh_hdr, 124,      57, 7);
73 	/* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */
74 	ifh_encode_bitfield(ifh_hdr, 1,        67, 1);
75 }
76 
sparx5_port_open(struct net_device * ndev)77 static int sparx5_port_open(struct net_device *ndev)
78 {
79 	struct sparx5_port *port = netdev_priv(ndev);
80 	int err = 0;
81 
82 	sparx5_port_enable(port, true);
83 	err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
84 	if (err) {
85 		netdev_err(ndev, "Could not attach to PHY\n");
86 		goto err_connect;
87 	}
88 
89 	phylink_start(port->phylink);
90 
91 	if (!ndev->phydev) {
92 		/* power up serdes */
93 		port->conf.power_down = false;
94 		if (port->conf.serdes_reset)
95 			err = sparx5_serdes_set(port->sparx5, port, &port->conf);
96 		else
97 			err = phy_power_on(port->serdes);
98 		if (err) {
99 			netdev_err(ndev, "%s failed\n", __func__);
100 			goto out_power;
101 		}
102 	}
103 
104 	return 0;
105 
106 out_power:
107 	phylink_stop(port->phylink);
108 	phylink_disconnect_phy(port->phylink);
109 err_connect:
110 	sparx5_port_enable(port, false);
111 
112 	return err;
113 }
114 
sparx5_port_stop(struct net_device * ndev)115 static int sparx5_port_stop(struct net_device *ndev)
116 {
117 	struct sparx5_port *port = netdev_priv(ndev);
118 	int err = 0;
119 
120 	sparx5_port_enable(port, false);
121 	phylink_stop(port->phylink);
122 	phylink_disconnect_phy(port->phylink);
123 
124 	if (!ndev->phydev) {
125 		/* power down serdes */
126 		port->conf.power_down = true;
127 		if (port->conf.serdes_reset)
128 			err = sparx5_serdes_set(port->sparx5, port, &port->conf);
129 		else
130 			err = phy_power_off(port->serdes);
131 		if (err)
132 			netdev_err(ndev, "%s failed\n", __func__);
133 	}
134 	return 0;
135 }
136 
sparx5_set_rx_mode(struct net_device * dev)137 static void sparx5_set_rx_mode(struct net_device *dev)
138 {
139 	struct sparx5_port *port = netdev_priv(dev);
140 	struct sparx5 *sparx5 = port->sparx5;
141 
142 	if (!test_bit(port->portno, sparx5->bridge_mask))
143 		__dev_mc_sync(dev, sparx5_mc_sync, sparx5_mc_unsync);
144 }
145 
sparx5_port_get_phys_port_name(struct net_device * dev,char * buf,size_t len)146 static int sparx5_port_get_phys_port_name(struct net_device *dev,
147 					  char *buf, size_t len)
148 {
149 	struct sparx5_port *port = netdev_priv(dev);
150 	int ret;
151 
152 	ret = snprintf(buf, len, "p%d", port->portno);
153 	if (ret >= len)
154 		return -EINVAL;
155 
156 	return 0;
157 }
158 
sparx5_set_mac_address(struct net_device * dev,void * p)159 static int sparx5_set_mac_address(struct net_device *dev, void *p)
160 {
161 	struct sparx5_port *port = netdev_priv(dev);
162 	struct sparx5 *sparx5 = port->sparx5;
163 	const struct sockaddr *addr = p;
164 
165 	if (!is_valid_ether_addr(addr->sa_data))
166 		return -EADDRNOTAVAIL;
167 
168 	/* Remove current */
169 	sparx5_mact_forget(sparx5, dev->dev_addr,  port->pvid);
170 
171 	/* Add new */
172 	sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid);
173 
174 	/* Record the address */
175 	eth_hw_addr_set(dev, addr->sa_data);
176 
177 	return 0;
178 }
179 
sparx5_get_port_parent_id(struct net_device * dev,struct netdev_phys_item_id * ppid)180 static int sparx5_get_port_parent_id(struct net_device *dev,
181 				     struct netdev_phys_item_id *ppid)
182 {
183 	struct sparx5_port *sparx5_port = netdev_priv(dev);
184 	struct sparx5 *sparx5 = sparx5_port->sparx5;
185 
186 	ppid->id_len = sizeof(sparx5->base_mac);
187 	memcpy(&ppid->id, &sparx5->base_mac, ppid->id_len);
188 
189 	return 0;
190 }
191 
192 static const struct net_device_ops sparx5_port_netdev_ops = {
193 	.ndo_open               = sparx5_port_open,
194 	.ndo_stop               = sparx5_port_stop,
195 	.ndo_start_xmit         = sparx5_port_xmit_impl,
196 	.ndo_set_rx_mode        = sparx5_set_rx_mode,
197 	.ndo_get_phys_port_name = sparx5_port_get_phys_port_name,
198 	.ndo_set_mac_address    = sparx5_set_mac_address,
199 	.ndo_validate_addr      = eth_validate_addr,
200 	.ndo_get_stats64        = sparx5_get_stats64,
201 	.ndo_get_port_parent_id = sparx5_get_port_parent_id,
202 };
203 
sparx5_netdevice_check(const struct net_device * dev)204 bool sparx5_netdevice_check(const struct net_device *dev)
205 {
206 	return dev && (dev->netdev_ops == &sparx5_port_netdev_ops);
207 }
208 
sparx5_create_netdev(struct sparx5 * sparx5,u32 portno)209 struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno)
210 {
211 	struct sparx5_port *spx5_port;
212 	struct net_device *ndev;
213 	u64 val;
214 
215 	ndev = devm_alloc_etherdev(sparx5->dev, sizeof(struct sparx5_port));
216 	if (!ndev)
217 		return ERR_PTR(-ENOMEM);
218 
219 	SET_NETDEV_DEV(ndev, sparx5->dev);
220 	spx5_port = netdev_priv(ndev);
221 	spx5_port->ndev = ndev;
222 	spx5_port->sparx5 = sparx5;
223 	spx5_port->portno = portno;
224 	sparx5_set_port_ifh(spx5_port->ifh, portno);
225 
226 	ndev->netdev_ops = &sparx5_port_netdev_ops;
227 	ndev->ethtool_ops = &sparx5_ethtool_ops;
228 
229 	val = ether_addr_to_u64(sparx5->base_mac) + portno + 1;
230 	u64_to_ether_addr(val, ndev->dev_addr);
231 
232 	return ndev;
233 }
234 
sparx5_register_netdevs(struct sparx5 * sparx5)235 int sparx5_register_netdevs(struct sparx5 *sparx5)
236 {
237 	int portno;
238 	int err;
239 
240 	for (portno = 0; portno < SPX5_PORTS; portno++)
241 		if (sparx5->ports[portno]) {
242 			err = register_netdev(sparx5->ports[portno]->ndev);
243 			if (err) {
244 				dev_err(sparx5->dev,
245 					"port: %02u: netdev registration failed\n",
246 					portno);
247 				return err;
248 			}
249 			sparx5_port_inj_timer_setup(sparx5->ports[portno]);
250 		}
251 	return 0;
252 }
253 
sparx5_destroy_netdevs(struct sparx5 * sparx5)254 void sparx5_destroy_netdevs(struct sparx5 *sparx5)
255 {
256 	struct sparx5_port *port;
257 	int portno;
258 
259 	for (portno = 0; portno < SPX5_PORTS; portno++) {
260 		port = sparx5->ports[portno];
261 		if (port && port->phylink) {
262 			/* Disconnect the phy */
263 			rtnl_lock();
264 			sparx5_port_stop(port->ndev);
265 			phylink_disconnect_phy(port->phylink);
266 			rtnl_unlock();
267 			phylink_destroy(port->phylink);
268 			port->phylink = NULL;
269 		}
270 	}
271 }
272 
sparx5_unregister_netdevs(struct sparx5 * sparx5)273 void sparx5_unregister_netdevs(struct sparx5 *sparx5)
274 {
275 	int portno;
276 
277 	for (portno = 0; portno < SPX5_PORTS; portno++)
278 		if (sparx5->ports[portno])
279 			unregister_netdev(sparx5->ports[portno]->ndev);
280 }
281 
282