1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /**
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
4 *
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
6 *
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
8 */
9
10 #include <linux/stmmac.h>
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/phy.h>
14 #include <linux/of_net.h>
15 #include <linux/gpio.h>
16 #include <linux/module.h>
17 #include <linux/of_gpio.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/delay.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
24 #include <linux/pm_runtime.h>
25
26 #include "stmmac_platform.h"
27
28 struct rk_priv_data;
29 struct rk_gmac_ops {
30 void (*set_to_rgmii)(struct rk_priv_data *bsp_priv,
31 int tx_delay, int rx_delay);
32 void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
33 void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
34 void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
35 void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
36 bool regs_valid;
37 u32 regs[];
38 };
39
40 struct rk_priv_data {
41 struct platform_device *pdev;
42 phy_interface_t phy_iface;
43 int id;
44 struct regulator *regulator;
45 bool suspended;
46 const struct rk_gmac_ops *ops;
47
48 bool clk_enabled;
49 bool clock_input;
50 bool integrated_phy;
51
52 struct clk *clk_mac;
53 struct clk *gmac_clkin;
54 struct clk *mac_clk_rx;
55 struct clk *mac_clk_tx;
56 struct clk *clk_mac_ref;
57 struct clk *clk_mac_refout;
58 struct clk *clk_mac_speed;
59 struct clk *aclk_mac;
60 struct clk *pclk_mac;
61 struct clk *clk_phy;
62
63 struct reset_control *phy_reset;
64
65 int tx_delay;
66 int rx_delay;
67
68 struct regmap *grf;
69 };
70
71 #define HIWORD_UPDATE(val, mask, shift) \
72 ((val) << (shift) | (mask) << ((shift) + 16))
73
74 #define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
75 #define GRF_CLR_BIT(nr) (BIT(nr+16))
76
77 #define DELAY_ENABLE(soc, tx, rx) \
78 (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
79 ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
80
81 #define PX30_GRF_GMAC_CON1 0x0904
82
83 /* PX30_GRF_GMAC_CON1 */
84 #define PX30_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
85 GRF_BIT(6))
86 #define PX30_GMAC_SPEED_10M GRF_CLR_BIT(2)
87 #define PX30_GMAC_SPEED_100M GRF_BIT(2)
88
px30_set_to_rmii(struct rk_priv_data * bsp_priv)89 static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
90 {
91 struct device *dev = &bsp_priv->pdev->dev;
92
93 if (IS_ERR(bsp_priv->grf)) {
94 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
95 return;
96 }
97
98 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
99 PX30_GMAC_PHY_INTF_SEL_RMII);
100 }
101
px30_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)102 static void px30_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
103 {
104 struct device *dev = &bsp_priv->pdev->dev;
105 int ret;
106
107 if (IS_ERR(bsp_priv->clk_mac_speed)) {
108 dev_err(dev, "%s: Missing clk_mac_speed clock\n", __func__);
109 return;
110 }
111
112 if (speed == 10) {
113 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
114 PX30_GMAC_SPEED_10M);
115
116 ret = clk_set_rate(bsp_priv->clk_mac_speed, 2500000);
117 if (ret)
118 dev_err(dev, "%s: set clk_mac_speed rate 2500000 failed: %d\n",
119 __func__, ret);
120 } else if (speed == 100) {
121 regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
122 PX30_GMAC_SPEED_100M);
123
124 ret = clk_set_rate(bsp_priv->clk_mac_speed, 25000000);
125 if (ret)
126 dev_err(dev, "%s: set clk_mac_speed rate 25000000 failed: %d\n",
127 __func__, ret);
128
129 } else {
130 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
131 }
132 }
133
134 static const struct rk_gmac_ops px30_ops = {
135 .set_to_rmii = px30_set_to_rmii,
136 .set_rmii_speed = px30_set_rmii_speed,
137 };
138
139 #define RK3128_GRF_MAC_CON0 0x0168
140 #define RK3128_GRF_MAC_CON1 0x016c
141
142 /* RK3128_GRF_MAC_CON0 */
143 #define RK3128_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
144 #define RK3128_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
145 #define RK3128_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
146 #define RK3128_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
147 #define RK3128_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
148 #define RK3128_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
149
150 /* RK3128_GRF_MAC_CON1 */
151 #define RK3128_GMAC_PHY_INTF_SEL_RGMII \
152 (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
153 #define RK3128_GMAC_PHY_INTF_SEL_RMII \
154 (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
155 #define RK3128_GMAC_FLOW_CTRL GRF_BIT(9)
156 #define RK3128_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
157 #define RK3128_GMAC_SPEED_10M GRF_CLR_BIT(10)
158 #define RK3128_GMAC_SPEED_100M GRF_BIT(10)
159 #define RK3128_GMAC_RMII_CLK_25M GRF_BIT(11)
160 #define RK3128_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
161 #define RK3128_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
162 #define RK3128_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
163 #define RK3128_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
164 #define RK3128_GMAC_RMII_MODE GRF_BIT(14)
165 #define RK3128_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
166
rk3128_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)167 static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
168 int tx_delay, int rx_delay)
169 {
170 struct device *dev = &bsp_priv->pdev->dev;
171
172 if (IS_ERR(bsp_priv->grf)) {
173 dev_err(dev, "Missing rockchip,grf property\n");
174 return;
175 }
176
177 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
178 RK3128_GMAC_PHY_INTF_SEL_RGMII |
179 RK3128_GMAC_RMII_MODE_CLR);
180 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
181 DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
182 RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
183 RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
184 }
185
rk3128_set_to_rmii(struct rk_priv_data * bsp_priv)186 static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
187 {
188 struct device *dev = &bsp_priv->pdev->dev;
189
190 if (IS_ERR(bsp_priv->grf)) {
191 dev_err(dev, "Missing rockchip,grf property\n");
192 return;
193 }
194
195 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
196 RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
197 }
198
rk3128_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)199 static void rk3128_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
200 {
201 struct device *dev = &bsp_priv->pdev->dev;
202
203 if (IS_ERR(bsp_priv->grf)) {
204 dev_err(dev, "Missing rockchip,grf property\n");
205 return;
206 }
207
208 if (speed == 10)
209 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
210 RK3128_GMAC_CLK_2_5M);
211 else if (speed == 100)
212 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
213 RK3128_GMAC_CLK_25M);
214 else if (speed == 1000)
215 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
216 RK3128_GMAC_CLK_125M);
217 else
218 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
219 }
220
rk3128_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)221 static void rk3128_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
222 {
223 struct device *dev = &bsp_priv->pdev->dev;
224
225 if (IS_ERR(bsp_priv->grf)) {
226 dev_err(dev, "Missing rockchip,grf property\n");
227 return;
228 }
229
230 if (speed == 10) {
231 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
232 RK3128_GMAC_RMII_CLK_2_5M |
233 RK3128_GMAC_SPEED_10M);
234 } else if (speed == 100) {
235 regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
236 RK3128_GMAC_RMII_CLK_25M |
237 RK3128_GMAC_SPEED_100M);
238 } else {
239 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
240 }
241 }
242
243 static const struct rk_gmac_ops rk3128_ops = {
244 .set_to_rgmii = rk3128_set_to_rgmii,
245 .set_to_rmii = rk3128_set_to_rmii,
246 .set_rgmii_speed = rk3128_set_rgmii_speed,
247 .set_rmii_speed = rk3128_set_rmii_speed,
248 };
249
250 #define RK3228_GRF_MAC_CON0 0x0900
251 #define RK3228_GRF_MAC_CON1 0x0904
252
253 #define RK3228_GRF_CON_MUX 0x50
254
255 /* RK3228_GRF_MAC_CON0 */
256 #define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
257 #define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
258
259 /* RK3228_GRF_MAC_CON1 */
260 #define RK3228_GMAC_PHY_INTF_SEL_RGMII \
261 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
262 #define RK3228_GMAC_PHY_INTF_SEL_RMII \
263 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
264 #define RK3228_GMAC_FLOW_CTRL GRF_BIT(3)
265 #define RK3228_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
266 #define RK3228_GMAC_SPEED_10M GRF_CLR_BIT(2)
267 #define RK3228_GMAC_SPEED_100M GRF_BIT(2)
268 #define RK3228_GMAC_RMII_CLK_25M GRF_BIT(7)
269 #define RK3228_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
270 #define RK3228_GMAC_CLK_125M (GRF_CLR_BIT(8) | GRF_CLR_BIT(9))
271 #define RK3228_GMAC_CLK_25M (GRF_BIT(8) | GRF_BIT(9))
272 #define RK3228_GMAC_CLK_2_5M (GRF_CLR_BIT(8) | GRF_BIT(9))
273 #define RK3228_GMAC_RMII_MODE GRF_BIT(10)
274 #define RK3228_GMAC_RMII_MODE_CLR GRF_CLR_BIT(10)
275 #define RK3228_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
276 #define RK3228_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
277 #define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
278 #define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
279
280 /* RK3228_GRF_COM_MUX */
281 #define RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY GRF_BIT(15)
282
rk3228_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)283 static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
284 int tx_delay, int rx_delay)
285 {
286 struct device *dev = &bsp_priv->pdev->dev;
287
288 if (IS_ERR(bsp_priv->grf)) {
289 dev_err(dev, "Missing rockchip,grf property\n");
290 return;
291 }
292
293 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
294 RK3228_GMAC_PHY_INTF_SEL_RGMII |
295 RK3228_GMAC_RMII_MODE_CLR |
296 DELAY_ENABLE(RK3228, tx_delay, rx_delay));
297
298 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
299 RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
300 RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
301 }
302
rk3228_set_to_rmii(struct rk_priv_data * bsp_priv)303 static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
304 {
305 struct device *dev = &bsp_priv->pdev->dev;
306
307 if (IS_ERR(bsp_priv->grf)) {
308 dev_err(dev, "Missing rockchip,grf property\n");
309 return;
310 }
311
312 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
313 RK3228_GMAC_PHY_INTF_SEL_RMII |
314 RK3228_GMAC_RMII_MODE);
315
316 /* set MAC to RMII mode */
317 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1, GRF_BIT(11));
318 }
319
rk3228_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)320 static void rk3228_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
321 {
322 struct device *dev = &bsp_priv->pdev->dev;
323
324 if (IS_ERR(bsp_priv->grf)) {
325 dev_err(dev, "Missing rockchip,grf property\n");
326 return;
327 }
328
329 if (speed == 10)
330 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
331 RK3228_GMAC_CLK_2_5M);
332 else if (speed == 100)
333 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
334 RK3228_GMAC_CLK_25M);
335 else if (speed == 1000)
336 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
337 RK3228_GMAC_CLK_125M);
338 else
339 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
340 }
341
rk3228_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)342 static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
343 {
344 struct device *dev = &bsp_priv->pdev->dev;
345
346 if (IS_ERR(bsp_priv->grf)) {
347 dev_err(dev, "Missing rockchip,grf property\n");
348 return;
349 }
350
351 if (speed == 10)
352 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
353 RK3228_GMAC_RMII_CLK_2_5M |
354 RK3228_GMAC_SPEED_10M);
355 else if (speed == 100)
356 regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
357 RK3228_GMAC_RMII_CLK_25M |
358 RK3228_GMAC_SPEED_100M);
359 else
360 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
361 }
362
rk3228_integrated_phy_powerup(struct rk_priv_data * priv)363 static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
364 {
365 regmap_write(priv->grf, RK3228_GRF_CON_MUX,
366 RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
367 }
368
369 static const struct rk_gmac_ops rk3228_ops = {
370 .set_to_rgmii = rk3228_set_to_rgmii,
371 .set_to_rmii = rk3228_set_to_rmii,
372 .set_rgmii_speed = rk3228_set_rgmii_speed,
373 .set_rmii_speed = rk3228_set_rmii_speed,
374 .integrated_phy_powerup = rk3228_integrated_phy_powerup,
375 };
376
377 #define RK3288_GRF_SOC_CON1 0x0248
378 #define RK3288_GRF_SOC_CON3 0x0250
379
380 /*RK3288_GRF_SOC_CON1*/
381 #define RK3288_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | \
382 GRF_CLR_BIT(8))
383 #define RK3288_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | \
384 GRF_BIT(8))
385 #define RK3288_GMAC_FLOW_CTRL GRF_BIT(9)
386 #define RK3288_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
387 #define RK3288_GMAC_SPEED_10M GRF_CLR_BIT(10)
388 #define RK3288_GMAC_SPEED_100M GRF_BIT(10)
389 #define RK3288_GMAC_RMII_CLK_25M GRF_BIT(11)
390 #define RK3288_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
391 #define RK3288_GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
392 #define RK3288_GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
393 #define RK3288_GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
394 #define RK3288_GMAC_RMII_MODE GRF_BIT(14)
395 #define RK3288_GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
396
397 /*RK3288_GRF_SOC_CON3*/
398 #define RK3288_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
399 #define RK3288_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
400 #define RK3288_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
401 #define RK3288_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
402 #define RK3288_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
403 #define RK3288_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
404
rk3288_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)405 static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
406 int tx_delay, int rx_delay)
407 {
408 struct device *dev = &bsp_priv->pdev->dev;
409
410 if (IS_ERR(bsp_priv->grf)) {
411 dev_err(dev, "Missing rockchip,grf property\n");
412 return;
413 }
414
415 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
416 RK3288_GMAC_PHY_INTF_SEL_RGMII |
417 RK3288_GMAC_RMII_MODE_CLR);
418 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
419 DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
420 RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
421 RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
422 }
423
rk3288_set_to_rmii(struct rk_priv_data * bsp_priv)424 static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
425 {
426 struct device *dev = &bsp_priv->pdev->dev;
427
428 if (IS_ERR(bsp_priv->grf)) {
429 dev_err(dev, "Missing rockchip,grf property\n");
430 return;
431 }
432
433 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
434 RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
435 }
436
rk3288_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)437 static void rk3288_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
438 {
439 struct device *dev = &bsp_priv->pdev->dev;
440
441 if (IS_ERR(bsp_priv->grf)) {
442 dev_err(dev, "Missing rockchip,grf property\n");
443 return;
444 }
445
446 if (speed == 10)
447 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
448 RK3288_GMAC_CLK_2_5M);
449 else if (speed == 100)
450 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
451 RK3288_GMAC_CLK_25M);
452 else if (speed == 1000)
453 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
454 RK3288_GMAC_CLK_125M);
455 else
456 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
457 }
458
rk3288_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)459 static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
460 {
461 struct device *dev = &bsp_priv->pdev->dev;
462
463 if (IS_ERR(bsp_priv->grf)) {
464 dev_err(dev, "Missing rockchip,grf property\n");
465 return;
466 }
467
468 if (speed == 10) {
469 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
470 RK3288_GMAC_RMII_CLK_2_5M |
471 RK3288_GMAC_SPEED_10M);
472 } else if (speed == 100) {
473 regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
474 RK3288_GMAC_RMII_CLK_25M |
475 RK3288_GMAC_SPEED_100M);
476 } else {
477 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
478 }
479 }
480
481 static const struct rk_gmac_ops rk3288_ops = {
482 .set_to_rgmii = rk3288_set_to_rgmii,
483 .set_to_rmii = rk3288_set_to_rmii,
484 .set_rgmii_speed = rk3288_set_rgmii_speed,
485 .set_rmii_speed = rk3288_set_rmii_speed,
486 };
487
488 #define RK3308_GRF_MAC_CON0 0x04a0
489
490 /* RK3308_GRF_MAC_CON0 */
491 #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \
492 GRF_BIT(4))
493 #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3)
494 #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
495 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0)
496 #define RK3308_GMAC_SPEED_100M GRF_BIT(0)
497
rk3308_set_to_rmii(struct rk_priv_data * bsp_priv)498 static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
499 {
500 struct device *dev = &bsp_priv->pdev->dev;
501
502 if (IS_ERR(bsp_priv->grf)) {
503 dev_err(dev, "Missing rockchip,grf property\n");
504 return;
505 }
506
507 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
508 RK3308_GMAC_PHY_INTF_SEL_RMII);
509 }
510
rk3308_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)511 static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
512 {
513 struct device *dev = &bsp_priv->pdev->dev;
514
515 if (IS_ERR(bsp_priv->grf)) {
516 dev_err(dev, "Missing rockchip,grf property\n");
517 return;
518 }
519
520 if (speed == 10) {
521 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
522 RK3308_GMAC_SPEED_10M);
523 } else if (speed == 100) {
524 regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
525 RK3308_GMAC_SPEED_100M);
526 } else {
527 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
528 }
529 }
530
531 static const struct rk_gmac_ops rk3308_ops = {
532 .set_to_rmii = rk3308_set_to_rmii,
533 .set_rmii_speed = rk3308_set_rmii_speed,
534 };
535
536 #define RK3328_GRF_MAC_CON0 0x0900
537 #define RK3328_GRF_MAC_CON1 0x0904
538 #define RK3328_GRF_MAC_CON2 0x0908
539 #define RK3328_GRF_MACPHY_CON1 0xb04
540
541 /* RK3328_GRF_MAC_CON0 */
542 #define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
543 #define RK3328_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
544
545 /* RK3328_GRF_MAC_CON1 */
546 #define RK3328_GMAC_PHY_INTF_SEL_RGMII \
547 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
548 #define RK3328_GMAC_PHY_INTF_SEL_RMII \
549 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
550 #define RK3328_GMAC_FLOW_CTRL GRF_BIT(3)
551 #define RK3328_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
552 #define RK3328_GMAC_SPEED_10M GRF_CLR_BIT(2)
553 #define RK3328_GMAC_SPEED_100M GRF_BIT(2)
554 #define RK3328_GMAC_RMII_CLK_25M GRF_BIT(7)
555 #define RK3328_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
556 #define RK3328_GMAC_CLK_125M (GRF_CLR_BIT(11) | GRF_CLR_BIT(12))
557 #define RK3328_GMAC_CLK_25M (GRF_BIT(11) | GRF_BIT(12))
558 #define RK3328_GMAC_CLK_2_5M (GRF_CLR_BIT(11) | GRF_BIT(12))
559 #define RK3328_GMAC_RMII_MODE GRF_BIT(9)
560 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9)
561 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
562 #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
563 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
564 #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
565
566 /* RK3328_GRF_MACPHY_CON1 */
567 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
568
rk3328_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)569 static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
570 int tx_delay, int rx_delay)
571 {
572 struct device *dev = &bsp_priv->pdev->dev;
573
574 if (IS_ERR(bsp_priv->grf)) {
575 dev_err(dev, "Missing rockchip,grf property\n");
576 return;
577 }
578
579 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
580 RK3328_GMAC_PHY_INTF_SEL_RGMII |
581 RK3328_GMAC_RMII_MODE_CLR |
582 RK3328_GMAC_RXCLK_DLY_ENABLE |
583 RK3328_GMAC_TXCLK_DLY_ENABLE);
584
585 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
586 RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
587 RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
588 }
589
rk3328_set_to_rmii(struct rk_priv_data * bsp_priv)590 static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
591 {
592 struct device *dev = &bsp_priv->pdev->dev;
593 unsigned int reg;
594
595 if (IS_ERR(bsp_priv->grf)) {
596 dev_err(dev, "Missing rockchip,grf property\n");
597 return;
598 }
599
600 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
601 RK3328_GRF_MAC_CON1;
602
603 regmap_write(bsp_priv->grf, reg,
604 RK3328_GMAC_PHY_INTF_SEL_RMII |
605 RK3328_GMAC_RMII_MODE);
606 }
607
rk3328_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)608 static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
609 {
610 struct device *dev = &bsp_priv->pdev->dev;
611
612 if (IS_ERR(bsp_priv->grf)) {
613 dev_err(dev, "Missing rockchip,grf property\n");
614 return;
615 }
616
617 if (speed == 10)
618 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
619 RK3328_GMAC_CLK_2_5M);
620 else if (speed == 100)
621 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
622 RK3328_GMAC_CLK_25M);
623 else if (speed == 1000)
624 regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
625 RK3328_GMAC_CLK_125M);
626 else
627 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
628 }
629
rk3328_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)630 static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
631 {
632 struct device *dev = &bsp_priv->pdev->dev;
633 unsigned int reg;
634
635 if (IS_ERR(bsp_priv->grf)) {
636 dev_err(dev, "Missing rockchip,grf property\n");
637 return;
638 }
639
640 reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
641 RK3328_GRF_MAC_CON1;
642
643 if (speed == 10)
644 regmap_write(bsp_priv->grf, reg,
645 RK3328_GMAC_RMII_CLK_2_5M |
646 RK3328_GMAC_SPEED_10M);
647 else if (speed == 100)
648 regmap_write(bsp_priv->grf, reg,
649 RK3328_GMAC_RMII_CLK_25M |
650 RK3328_GMAC_SPEED_100M);
651 else
652 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
653 }
654
rk3328_integrated_phy_powerup(struct rk_priv_data * priv)655 static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
656 {
657 regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
658 RK3328_MACPHY_RMII_MODE);
659 }
660
661 static const struct rk_gmac_ops rk3328_ops = {
662 .set_to_rgmii = rk3328_set_to_rgmii,
663 .set_to_rmii = rk3328_set_to_rmii,
664 .set_rgmii_speed = rk3328_set_rgmii_speed,
665 .set_rmii_speed = rk3328_set_rmii_speed,
666 .integrated_phy_powerup = rk3328_integrated_phy_powerup,
667 };
668
669 #define RK3366_GRF_SOC_CON6 0x0418
670 #define RK3366_GRF_SOC_CON7 0x041c
671
672 /* RK3366_GRF_SOC_CON6 */
673 #define RK3366_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
674 GRF_CLR_BIT(11))
675 #define RK3366_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
676 GRF_BIT(11))
677 #define RK3366_GMAC_FLOW_CTRL GRF_BIT(8)
678 #define RK3366_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
679 #define RK3366_GMAC_SPEED_10M GRF_CLR_BIT(7)
680 #define RK3366_GMAC_SPEED_100M GRF_BIT(7)
681 #define RK3366_GMAC_RMII_CLK_25M GRF_BIT(3)
682 #define RK3366_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
683 #define RK3366_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
684 #define RK3366_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
685 #define RK3366_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
686 #define RK3366_GMAC_RMII_MODE GRF_BIT(6)
687 #define RK3366_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
688
689 /* RK3366_GRF_SOC_CON7 */
690 #define RK3366_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
691 #define RK3366_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
692 #define RK3366_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
693 #define RK3366_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
694 #define RK3366_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
695 #define RK3366_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
696
rk3366_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)697 static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
698 int tx_delay, int rx_delay)
699 {
700 struct device *dev = &bsp_priv->pdev->dev;
701
702 if (IS_ERR(bsp_priv->grf)) {
703 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
704 return;
705 }
706
707 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
708 RK3366_GMAC_PHY_INTF_SEL_RGMII |
709 RK3366_GMAC_RMII_MODE_CLR);
710 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
711 DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
712 RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
713 RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
714 }
715
rk3366_set_to_rmii(struct rk_priv_data * bsp_priv)716 static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
717 {
718 struct device *dev = &bsp_priv->pdev->dev;
719
720 if (IS_ERR(bsp_priv->grf)) {
721 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
722 return;
723 }
724
725 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
726 RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
727 }
728
rk3366_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)729 static void rk3366_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
730 {
731 struct device *dev = &bsp_priv->pdev->dev;
732
733 if (IS_ERR(bsp_priv->grf)) {
734 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
735 return;
736 }
737
738 if (speed == 10)
739 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
740 RK3366_GMAC_CLK_2_5M);
741 else if (speed == 100)
742 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
743 RK3366_GMAC_CLK_25M);
744 else if (speed == 1000)
745 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
746 RK3366_GMAC_CLK_125M);
747 else
748 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
749 }
750
rk3366_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)751 static void rk3366_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
752 {
753 struct device *dev = &bsp_priv->pdev->dev;
754
755 if (IS_ERR(bsp_priv->grf)) {
756 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
757 return;
758 }
759
760 if (speed == 10) {
761 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
762 RK3366_GMAC_RMII_CLK_2_5M |
763 RK3366_GMAC_SPEED_10M);
764 } else if (speed == 100) {
765 regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
766 RK3366_GMAC_RMII_CLK_25M |
767 RK3366_GMAC_SPEED_100M);
768 } else {
769 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
770 }
771 }
772
773 static const struct rk_gmac_ops rk3366_ops = {
774 .set_to_rgmii = rk3366_set_to_rgmii,
775 .set_to_rmii = rk3366_set_to_rmii,
776 .set_rgmii_speed = rk3366_set_rgmii_speed,
777 .set_rmii_speed = rk3366_set_rmii_speed,
778 };
779
780 #define RK3368_GRF_SOC_CON15 0x043c
781 #define RK3368_GRF_SOC_CON16 0x0440
782
783 /* RK3368_GRF_SOC_CON15 */
784 #define RK3368_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
785 GRF_CLR_BIT(11))
786 #define RK3368_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
787 GRF_BIT(11))
788 #define RK3368_GMAC_FLOW_CTRL GRF_BIT(8)
789 #define RK3368_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
790 #define RK3368_GMAC_SPEED_10M GRF_CLR_BIT(7)
791 #define RK3368_GMAC_SPEED_100M GRF_BIT(7)
792 #define RK3368_GMAC_RMII_CLK_25M GRF_BIT(3)
793 #define RK3368_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
794 #define RK3368_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
795 #define RK3368_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
796 #define RK3368_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
797 #define RK3368_GMAC_RMII_MODE GRF_BIT(6)
798 #define RK3368_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
799
800 /* RK3368_GRF_SOC_CON16 */
801 #define RK3368_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
802 #define RK3368_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
803 #define RK3368_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
804 #define RK3368_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
805 #define RK3368_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
806 #define RK3368_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
807
rk3368_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)808 static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
809 int tx_delay, int rx_delay)
810 {
811 struct device *dev = &bsp_priv->pdev->dev;
812
813 if (IS_ERR(bsp_priv->grf)) {
814 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
815 return;
816 }
817
818 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
819 RK3368_GMAC_PHY_INTF_SEL_RGMII |
820 RK3368_GMAC_RMII_MODE_CLR);
821 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
822 DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
823 RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
824 RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
825 }
826
rk3368_set_to_rmii(struct rk_priv_data * bsp_priv)827 static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
828 {
829 struct device *dev = &bsp_priv->pdev->dev;
830
831 if (IS_ERR(bsp_priv->grf)) {
832 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
833 return;
834 }
835
836 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
837 RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
838 }
839
rk3368_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)840 static void rk3368_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
841 {
842 struct device *dev = &bsp_priv->pdev->dev;
843
844 if (IS_ERR(bsp_priv->grf)) {
845 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
846 return;
847 }
848
849 if (speed == 10)
850 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
851 RK3368_GMAC_CLK_2_5M);
852 else if (speed == 100)
853 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
854 RK3368_GMAC_CLK_25M);
855 else if (speed == 1000)
856 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
857 RK3368_GMAC_CLK_125M);
858 else
859 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
860 }
861
rk3368_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)862 static void rk3368_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
863 {
864 struct device *dev = &bsp_priv->pdev->dev;
865
866 if (IS_ERR(bsp_priv->grf)) {
867 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
868 return;
869 }
870
871 if (speed == 10) {
872 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
873 RK3368_GMAC_RMII_CLK_2_5M |
874 RK3368_GMAC_SPEED_10M);
875 } else if (speed == 100) {
876 regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
877 RK3368_GMAC_RMII_CLK_25M |
878 RK3368_GMAC_SPEED_100M);
879 } else {
880 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
881 }
882 }
883
884 static const struct rk_gmac_ops rk3368_ops = {
885 .set_to_rgmii = rk3368_set_to_rgmii,
886 .set_to_rmii = rk3368_set_to_rmii,
887 .set_rgmii_speed = rk3368_set_rgmii_speed,
888 .set_rmii_speed = rk3368_set_rmii_speed,
889 };
890
891 #define RK3399_GRF_SOC_CON5 0xc214
892 #define RK3399_GRF_SOC_CON6 0xc218
893
894 /* RK3399_GRF_SOC_CON5 */
895 #define RK3399_GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(9) | GRF_CLR_BIT(10) | \
896 GRF_CLR_BIT(11))
897 #define RK3399_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(9) | GRF_CLR_BIT(10) | \
898 GRF_BIT(11))
899 #define RK3399_GMAC_FLOW_CTRL GRF_BIT(8)
900 #define RK3399_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(8)
901 #define RK3399_GMAC_SPEED_10M GRF_CLR_BIT(7)
902 #define RK3399_GMAC_SPEED_100M GRF_BIT(7)
903 #define RK3399_GMAC_RMII_CLK_25M GRF_BIT(3)
904 #define RK3399_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(3)
905 #define RK3399_GMAC_CLK_125M (GRF_CLR_BIT(4) | GRF_CLR_BIT(5))
906 #define RK3399_GMAC_CLK_25M (GRF_BIT(4) | GRF_BIT(5))
907 #define RK3399_GMAC_CLK_2_5M (GRF_CLR_BIT(4) | GRF_BIT(5))
908 #define RK3399_GMAC_RMII_MODE GRF_BIT(6)
909 #define RK3399_GMAC_RMII_MODE_CLR GRF_CLR_BIT(6)
910
911 /* RK3399_GRF_SOC_CON6 */
912 #define RK3399_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
913 #define RK3399_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
914 #define RK3399_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
915 #define RK3399_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
916 #define RK3399_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
917 #define RK3399_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
918
rk3399_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)919 static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
920 int tx_delay, int rx_delay)
921 {
922 struct device *dev = &bsp_priv->pdev->dev;
923
924 if (IS_ERR(bsp_priv->grf)) {
925 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
926 return;
927 }
928
929 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
930 RK3399_GMAC_PHY_INTF_SEL_RGMII |
931 RK3399_GMAC_RMII_MODE_CLR);
932 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
933 DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
934 RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
935 RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
936 }
937
rk3399_set_to_rmii(struct rk_priv_data * bsp_priv)938 static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
939 {
940 struct device *dev = &bsp_priv->pdev->dev;
941
942 if (IS_ERR(bsp_priv->grf)) {
943 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
944 return;
945 }
946
947 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
948 RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
949 }
950
rk3399_set_rgmii_speed(struct rk_priv_data * bsp_priv,int speed)951 static void rk3399_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
952 {
953 struct device *dev = &bsp_priv->pdev->dev;
954
955 if (IS_ERR(bsp_priv->grf)) {
956 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
957 return;
958 }
959
960 if (speed == 10)
961 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
962 RK3399_GMAC_CLK_2_5M);
963 else if (speed == 100)
964 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
965 RK3399_GMAC_CLK_25M);
966 else if (speed == 1000)
967 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
968 RK3399_GMAC_CLK_125M);
969 else
970 dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
971 }
972
rk3399_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)973 static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
974 {
975 struct device *dev = &bsp_priv->pdev->dev;
976
977 if (IS_ERR(bsp_priv->grf)) {
978 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
979 return;
980 }
981
982 if (speed == 10) {
983 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
984 RK3399_GMAC_RMII_CLK_2_5M |
985 RK3399_GMAC_SPEED_10M);
986 } else if (speed == 100) {
987 regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
988 RK3399_GMAC_RMII_CLK_25M |
989 RK3399_GMAC_SPEED_100M);
990 } else {
991 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
992 }
993 }
994
995 static const struct rk_gmac_ops rk3399_ops = {
996 .set_to_rgmii = rk3399_set_to_rgmii,
997 .set_to_rmii = rk3399_set_to_rmii,
998 .set_rgmii_speed = rk3399_set_rgmii_speed,
999 .set_rmii_speed = rk3399_set_rmii_speed,
1000 };
1001
1002 #define RK3568_GRF_GMAC0_CON0 0x0380
1003 #define RK3568_GRF_GMAC0_CON1 0x0384
1004 #define RK3568_GRF_GMAC1_CON0 0x0388
1005 #define RK3568_GRF_GMAC1_CON1 0x038c
1006
1007 /* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
1008 #define RK3568_GMAC_PHY_INTF_SEL_RGMII \
1009 (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
1010 #define RK3568_GMAC_PHY_INTF_SEL_RMII \
1011 (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
1012 #define RK3568_GMAC_FLOW_CTRL GRF_BIT(3)
1013 #define RK3568_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1014 #define RK3568_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
1015 #define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1016 #define RK3568_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
1017 #define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1018
1019 /* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
1020 #define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1021 #define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1022
rk3568_set_to_rgmii(struct rk_priv_data * bsp_priv,int tx_delay,int rx_delay)1023 static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
1024 int tx_delay, int rx_delay)
1025 {
1026 struct device *dev = &bsp_priv->pdev->dev;
1027 u32 con0, con1;
1028
1029 if (IS_ERR(bsp_priv->grf)) {
1030 dev_err(dev, "Missing rockchip,grf property\n");
1031 return;
1032 }
1033
1034 con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
1035 RK3568_GRF_GMAC0_CON0;
1036 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1037 RK3568_GRF_GMAC0_CON1;
1038
1039 regmap_write(bsp_priv->grf, con0,
1040 RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
1041 RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
1042
1043 regmap_write(bsp_priv->grf, con1,
1044 RK3568_GMAC_PHY_INTF_SEL_RGMII |
1045 RK3568_GMAC_RXCLK_DLY_ENABLE |
1046 RK3568_GMAC_TXCLK_DLY_ENABLE);
1047 }
1048
rk3568_set_to_rmii(struct rk_priv_data * bsp_priv)1049 static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
1050 {
1051 struct device *dev = &bsp_priv->pdev->dev;
1052 u32 con1;
1053
1054 if (IS_ERR(bsp_priv->grf)) {
1055 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1056 return;
1057 }
1058
1059 con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
1060 RK3568_GRF_GMAC0_CON1;
1061 regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
1062 }
1063
rk3568_set_gmac_speed(struct rk_priv_data * bsp_priv,int speed)1064 static void rk3568_set_gmac_speed(struct rk_priv_data *bsp_priv, int speed)
1065 {
1066 struct device *dev = &bsp_priv->pdev->dev;
1067 unsigned long rate;
1068 int ret;
1069
1070 switch (speed) {
1071 case 10:
1072 rate = 2500000;
1073 break;
1074 case 100:
1075 rate = 25000000;
1076 break;
1077 case 1000:
1078 rate = 125000000;
1079 break;
1080 default:
1081 dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
1082 return;
1083 }
1084
1085 ret = clk_set_rate(bsp_priv->clk_mac_speed, rate);
1086 if (ret)
1087 dev_err(dev, "%s: set clk_mac_speed rate %ld failed %d\n",
1088 __func__, rate, ret);
1089 }
1090
1091 static const struct rk_gmac_ops rk3568_ops = {
1092 .set_to_rgmii = rk3568_set_to_rgmii,
1093 .set_to_rmii = rk3568_set_to_rmii,
1094 .set_rgmii_speed = rk3568_set_gmac_speed,
1095 .set_rmii_speed = rk3568_set_gmac_speed,
1096 .regs_valid = true,
1097 .regs = {
1098 0xfe2a0000, /* gmac0 */
1099 0xfe010000, /* gmac1 */
1100 0x0, /* sentinel */
1101 },
1102 };
1103
1104 #define RV1108_GRF_GMAC_CON0 0X0900
1105
1106 /* RV1108_GRF_GMAC_CON0 */
1107 #define RV1108_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | \
1108 GRF_BIT(6))
1109 #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3)
1110 #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3)
1111 #define RV1108_GMAC_SPEED_10M GRF_CLR_BIT(2)
1112 #define RV1108_GMAC_SPEED_100M GRF_BIT(2)
1113 #define RV1108_GMAC_RMII_CLK_25M GRF_BIT(7)
1114 #define RV1108_GMAC_RMII_CLK_2_5M GRF_CLR_BIT(7)
1115
rv1108_set_to_rmii(struct rk_priv_data * bsp_priv)1116 static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
1117 {
1118 struct device *dev = &bsp_priv->pdev->dev;
1119
1120 if (IS_ERR(bsp_priv->grf)) {
1121 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1122 return;
1123 }
1124
1125 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1126 RV1108_GMAC_PHY_INTF_SEL_RMII);
1127 }
1128
rv1108_set_rmii_speed(struct rk_priv_data * bsp_priv,int speed)1129 static void rv1108_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1130 {
1131 struct device *dev = &bsp_priv->pdev->dev;
1132
1133 if (IS_ERR(bsp_priv->grf)) {
1134 dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1135 return;
1136 }
1137
1138 if (speed == 10) {
1139 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1140 RV1108_GMAC_RMII_CLK_2_5M |
1141 RV1108_GMAC_SPEED_10M);
1142 } else if (speed == 100) {
1143 regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
1144 RV1108_GMAC_RMII_CLK_25M |
1145 RV1108_GMAC_SPEED_100M);
1146 } else {
1147 dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
1148 }
1149 }
1150
1151 static const struct rk_gmac_ops rv1108_ops = {
1152 .set_to_rmii = rv1108_set_to_rmii,
1153 .set_rmii_speed = rv1108_set_rmii_speed,
1154 };
1155
1156 #define RK_GRF_MACPHY_CON0 0xb00
1157 #define RK_GRF_MACPHY_CON1 0xb04
1158 #define RK_GRF_MACPHY_CON2 0xb08
1159 #define RK_GRF_MACPHY_CON3 0xb0c
1160
1161 #define RK_MACPHY_ENABLE GRF_BIT(0)
1162 #define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
1163 #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
1164 #define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
1165 #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
1166 #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
1167
rk_gmac_integrated_phy_powerup(struct rk_priv_data * priv)1168 static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1169 {
1170 if (priv->ops->integrated_phy_powerup)
1171 priv->ops->integrated_phy_powerup(priv);
1172
1173 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1174 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1175
1176 regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1177 regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1178
1179 if (priv->phy_reset) {
1180 /* PHY needs to be disabled before trying to reset it */
1181 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1182 if (priv->phy_reset)
1183 reset_control_assert(priv->phy_reset);
1184 usleep_range(10, 20);
1185 if (priv->phy_reset)
1186 reset_control_deassert(priv->phy_reset);
1187 usleep_range(10, 20);
1188 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1189 msleep(30);
1190 }
1191 }
1192
rk_gmac_integrated_phy_powerdown(struct rk_priv_data * priv)1193 static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1194 {
1195 regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1196 if (priv->phy_reset)
1197 reset_control_assert(priv->phy_reset);
1198 }
1199
rk_gmac_clk_init(struct plat_stmmacenet_data * plat)1200 static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1201 {
1202 struct rk_priv_data *bsp_priv = plat->bsp_priv;
1203 struct device *dev = &bsp_priv->pdev->dev;
1204 int ret;
1205
1206 bsp_priv->clk_enabled = false;
1207
1208 bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
1209 if (IS_ERR(bsp_priv->mac_clk_rx))
1210 dev_err(dev, "cannot get clock %s\n",
1211 "mac_clk_rx");
1212
1213 bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
1214 if (IS_ERR(bsp_priv->mac_clk_tx))
1215 dev_err(dev, "cannot get clock %s\n",
1216 "mac_clk_tx");
1217
1218 bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
1219 if (IS_ERR(bsp_priv->aclk_mac))
1220 dev_err(dev, "cannot get clock %s\n",
1221 "aclk_mac");
1222
1223 bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
1224 if (IS_ERR(bsp_priv->pclk_mac))
1225 dev_err(dev, "cannot get clock %s\n",
1226 "pclk_mac");
1227
1228 bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
1229 if (IS_ERR(bsp_priv->clk_mac))
1230 dev_err(dev, "cannot get clock %s\n",
1231 "stmmaceth");
1232
1233 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
1234 bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
1235 if (IS_ERR(bsp_priv->clk_mac_ref))
1236 dev_err(dev, "cannot get clock %s\n",
1237 "clk_mac_ref");
1238
1239 if (!bsp_priv->clock_input) {
1240 bsp_priv->clk_mac_refout =
1241 devm_clk_get(dev, "clk_mac_refout");
1242 if (IS_ERR(bsp_priv->clk_mac_refout))
1243 dev_err(dev, "cannot get clock %s\n",
1244 "clk_mac_refout");
1245 }
1246 }
1247
1248 bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
1249 if (IS_ERR(bsp_priv->clk_mac_speed))
1250 dev_err(dev, "cannot get clock %s\n", "clk_mac_speed");
1251
1252 if (bsp_priv->clock_input) {
1253 dev_info(dev, "clock input from PHY\n");
1254 } else {
1255 if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
1256 clk_set_rate(bsp_priv->clk_mac, 50000000);
1257 }
1258
1259 if (plat->phy_node && bsp_priv->integrated_phy) {
1260 bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
1261 if (IS_ERR(bsp_priv->clk_phy)) {
1262 ret = PTR_ERR(bsp_priv->clk_phy);
1263 dev_err(dev, "Cannot get PHY clock: %d\n", ret);
1264 return -EINVAL;
1265 }
1266 clk_set_rate(bsp_priv->clk_phy, 50000000);
1267 }
1268
1269 return 0;
1270 }
1271
gmac_clk_enable(struct rk_priv_data * bsp_priv,bool enable)1272 static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
1273 {
1274 int phy_iface = bsp_priv->phy_iface;
1275
1276 if (enable) {
1277 if (!bsp_priv->clk_enabled) {
1278 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1279 if (!IS_ERR(bsp_priv->mac_clk_rx))
1280 clk_prepare_enable(
1281 bsp_priv->mac_clk_rx);
1282
1283 if (!IS_ERR(bsp_priv->clk_mac_ref))
1284 clk_prepare_enable(
1285 bsp_priv->clk_mac_ref);
1286
1287 if (!IS_ERR(bsp_priv->clk_mac_refout))
1288 clk_prepare_enable(
1289 bsp_priv->clk_mac_refout);
1290 }
1291
1292 if (!IS_ERR(bsp_priv->clk_phy))
1293 clk_prepare_enable(bsp_priv->clk_phy);
1294
1295 if (!IS_ERR(bsp_priv->aclk_mac))
1296 clk_prepare_enable(bsp_priv->aclk_mac);
1297
1298 if (!IS_ERR(bsp_priv->pclk_mac))
1299 clk_prepare_enable(bsp_priv->pclk_mac);
1300
1301 if (!IS_ERR(bsp_priv->mac_clk_tx))
1302 clk_prepare_enable(bsp_priv->mac_clk_tx);
1303
1304 if (!IS_ERR(bsp_priv->clk_mac_speed))
1305 clk_prepare_enable(bsp_priv->clk_mac_speed);
1306
1307 /**
1308 * if (!IS_ERR(bsp_priv->clk_mac))
1309 * clk_prepare_enable(bsp_priv->clk_mac);
1310 */
1311 mdelay(5);
1312 bsp_priv->clk_enabled = true;
1313 }
1314 } else {
1315 if (bsp_priv->clk_enabled) {
1316 if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1317 clk_disable_unprepare(bsp_priv->mac_clk_rx);
1318
1319 clk_disable_unprepare(bsp_priv->clk_mac_ref);
1320
1321 clk_disable_unprepare(bsp_priv->clk_mac_refout);
1322 }
1323
1324 clk_disable_unprepare(bsp_priv->clk_phy);
1325
1326 clk_disable_unprepare(bsp_priv->aclk_mac);
1327
1328 clk_disable_unprepare(bsp_priv->pclk_mac);
1329
1330 clk_disable_unprepare(bsp_priv->mac_clk_tx);
1331
1332 clk_disable_unprepare(bsp_priv->clk_mac_speed);
1333 /**
1334 * if (!IS_ERR(bsp_priv->clk_mac))
1335 * clk_disable_unprepare(bsp_priv->clk_mac);
1336 */
1337 bsp_priv->clk_enabled = false;
1338 }
1339 }
1340
1341 return 0;
1342 }
1343
phy_power_on(struct rk_priv_data * bsp_priv,bool enable)1344 static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
1345 {
1346 struct regulator *ldo = bsp_priv->regulator;
1347 int ret;
1348 struct device *dev = &bsp_priv->pdev->dev;
1349
1350 if (enable) {
1351 ret = regulator_enable(ldo);
1352 if (ret)
1353 dev_err(dev, "fail to enable phy-supply\n");
1354 } else {
1355 ret = regulator_disable(ldo);
1356 if (ret)
1357 dev_err(dev, "fail to disable phy-supply\n");
1358 }
1359
1360 return 0;
1361 }
1362
rk_gmac_setup(struct platform_device * pdev,struct plat_stmmacenet_data * plat,const struct rk_gmac_ops * ops)1363 static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
1364 struct plat_stmmacenet_data *plat,
1365 const struct rk_gmac_ops *ops)
1366 {
1367 struct rk_priv_data *bsp_priv;
1368 struct device *dev = &pdev->dev;
1369 struct resource *res;
1370 int ret;
1371 const char *strings = NULL;
1372 int value;
1373
1374 bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
1375 if (!bsp_priv)
1376 return ERR_PTR(-ENOMEM);
1377
1378 of_get_phy_mode(dev->of_node, &bsp_priv->phy_iface);
1379 bsp_priv->ops = ops;
1380
1381 /* Some SoCs have multiple MAC controllers, which need
1382 * to be distinguished.
1383 */
1384 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1385 if (res && ops->regs_valid) {
1386 int i = 0;
1387
1388 while (ops->regs[i]) {
1389 if (ops->regs[i] == res->start) {
1390 bsp_priv->id = i;
1391 break;
1392 }
1393 i++;
1394 }
1395 }
1396
1397 bsp_priv->regulator = devm_regulator_get(dev, "phy");
1398 if (IS_ERR(bsp_priv->regulator)) {
1399 ret = PTR_ERR(bsp_priv->regulator);
1400 dev_err_probe(dev, ret, "failed to get phy regulator\n");
1401 return ERR_PTR(ret);
1402 }
1403
1404 ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
1405 if (ret) {
1406 dev_err(dev, "Can not read property: clock_in_out.\n");
1407 bsp_priv->clock_input = true;
1408 } else {
1409 dev_info(dev, "clock input or output? (%s).\n",
1410 strings);
1411 if (!strcmp(strings, "input"))
1412 bsp_priv->clock_input = true;
1413 else
1414 bsp_priv->clock_input = false;
1415 }
1416
1417 ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1418 if (ret) {
1419 bsp_priv->tx_delay = 0x30;
1420 dev_err(dev, "Can not read property: tx_delay.");
1421 dev_err(dev, "set tx_delay to 0x%x\n",
1422 bsp_priv->tx_delay);
1423 } else {
1424 dev_info(dev, "TX delay(0x%x).\n", value);
1425 bsp_priv->tx_delay = value;
1426 }
1427
1428 ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1429 if (ret) {
1430 bsp_priv->rx_delay = 0x10;
1431 dev_err(dev, "Can not read property: rx_delay.");
1432 dev_err(dev, "set rx_delay to 0x%x\n",
1433 bsp_priv->rx_delay);
1434 } else {
1435 dev_info(dev, "RX delay(0x%x).\n", value);
1436 bsp_priv->rx_delay = value;
1437 }
1438
1439 bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1440 "rockchip,grf");
1441
1442 if (plat->phy_node) {
1443 bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1444 "phy-is-integrated");
1445 if (bsp_priv->integrated_phy) {
1446 bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1447 if (IS_ERR(bsp_priv->phy_reset)) {
1448 dev_err(&pdev->dev, "No PHY reset control found.\n");
1449 bsp_priv->phy_reset = NULL;
1450 }
1451 }
1452 }
1453 dev_info(dev, "integrated PHY? (%s).\n",
1454 bsp_priv->integrated_phy ? "yes" : "no");
1455
1456 bsp_priv->pdev = pdev;
1457
1458 return bsp_priv;
1459 }
1460
rk_gmac_check_ops(struct rk_priv_data * bsp_priv)1461 static int rk_gmac_check_ops(struct rk_priv_data *bsp_priv)
1462 {
1463 switch (bsp_priv->phy_iface) {
1464 case PHY_INTERFACE_MODE_RGMII:
1465 case PHY_INTERFACE_MODE_RGMII_ID:
1466 case PHY_INTERFACE_MODE_RGMII_RXID:
1467 case PHY_INTERFACE_MODE_RGMII_TXID:
1468 if (!bsp_priv->ops->set_to_rgmii)
1469 return -EINVAL;
1470 break;
1471 case PHY_INTERFACE_MODE_RMII:
1472 if (!bsp_priv->ops->set_to_rmii)
1473 return -EINVAL;
1474 break;
1475 default:
1476 dev_err(&bsp_priv->pdev->dev,
1477 "unsupported interface %d", bsp_priv->phy_iface);
1478 }
1479 return 0;
1480 }
1481
rk_gmac_powerup(struct rk_priv_data * bsp_priv)1482 static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
1483 {
1484 int ret;
1485 struct device *dev = &bsp_priv->pdev->dev;
1486
1487 ret = rk_gmac_check_ops(bsp_priv);
1488 if (ret)
1489 return ret;
1490
1491 ret = gmac_clk_enable(bsp_priv, true);
1492 if (ret)
1493 return ret;
1494
1495 /*rmii or rgmii*/
1496 switch (bsp_priv->phy_iface) {
1497 case PHY_INTERFACE_MODE_RGMII:
1498 dev_info(dev, "init for RGMII\n");
1499 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay,
1500 bsp_priv->rx_delay);
1501 break;
1502 case PHY_INTERFACE_MODE_RGMII_ID:
1503 dev_info(dev, "init for RGMII_ID\n");
1504 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
1505 break;
1506 case PHY_INTERFACE_MODE_RGMII_RXID:
1507 dev_info(dev, "init for RGMII_RXID\n");
1508 bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
1509 break;
1510 case PHY_INTERFACE_MODE_RGMII_TXID:
1511 dev_info(dev, "init for RGMII_TXID\n");
1512 bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
1513 break;
1514 case PHY_INTERFACE_MODE_RMII:
1515 dev_info(dev, "init for RMII\n");
1516 bsp_priv->ops->set_to_rmii(bsp_priv);
1517 break;
1518 default:
1519 dev_err(dev, "NO interface defined!\n");
1520 }
1521
1522 ret = phy_power_on(bsp_priv, true);
1523 if (ret) {
1524 gmac_clk_enable(bsp_priv, false);
1525 return ret;
1526 }
1527
1528 pm_runtime_get_sync(dev);
1529
1530 if (bsp_priv->integrated_phy)
1531 rk_gmac_integrated_phy_powerup(bsp_priv);
1532
1533 return 0;
1534 }
1535
rk_gmac_powerdown(struct rk_priv_data * gmac)1536 static void rk_gmac_powerdown(struct rk_priv_data *gmac)
1537 {
1538 if (gmac->integrated_phy)
1539 rk_gmac_integrated_phy_powerdown(gmac);
1540
1541 pm_runtime_put_sync(&gmac->pdev->dev);
1542
1543 phy_power_on(gmac, false);
1544 gmac_clk_enable(gmac, false);
1545 }
1546
rk_fix_speed(void * priv,unsigned int speed)1547 static void rk_fix_speed(void *priv, unsigned int speed)
1548 {
1549 struct rk_priv_data *bsp_priv = priv;
1550 struct device *dev = &bsp_priv->pdev->dev;
1551
1552 switch (bsp_priv->phy_iface) {
1553 case PHY_INTERFACE_MODE_RGMII:
1554 case PHY_INTERFACE_MODE_RGMII_ID:
1555 case PHY_INTERFACE_MODE_RGMII_RXID:
1556 case PHY_INTERFACE_MODE_RGMII_TXID:
1557 if (bsp_priv->ops->set_rgmii_speed)
1558 bsp_priv->ops->set_rgmii_speed(bsp_priv, speed);
1559 break;
1560 case PHY_INTERFACE_MODE_RMII:
1561 if (bsp_priv->ops->set_rmii_speed)
1562 bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
1563 break;
1564 default:
1565 dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
1566 }
1567 }
1568
rk_gmac_probe(struct platform_device * pdev)1569 static int rk_gmac_probe(struct platform_device *pdev)
1570 {
1571 struct plat_stmmacenet_data *plat_dat;
1572 struct stmmac_resources stmmac_res;
1573 const struct rk_gmac_ops *data;
1574 int ret;
1575
1576 data = of_device_get_match_data(&pdev->dev);
1577 if (!data) {
1578 dev_err(&pdev->dev, "no of match data provided\n");
1579 return -EINVAL;
1580 }
1581
1582 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
1583 if (ret)
1584 return ret;
1585
1586 plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac);
1587 if (IS_ERR(plat_dat))
1588 return PTR_ERR(plat_dat);
1589
1590 /* If the stmmac is not already selected as gmac4,
1591 * then make sure we fallback to gmac.
1592 */
1593 if (!plat_dat->has_gmac4)
1594 plat_dat->has_gmac = true;
1595 plat_dat->fix_mac_speed = rk_fix_speed;
1596
1597 plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
1598 if (IS_ERR(plat_dat->bsp_priv)) {
1599 ret = PTR_ERR(plat_dat->bsp_priv);
1600 goto err_remove_config_dt;
1601 }
1602
1603 ret = rk_gmac_clk_init(plat_dat);
1604 if (ret)
1605 goto err_remove_config_dt;
1606
1607 ret = rk_gmac_powerup(plat_dat->bsp_priv);
1608 if (ret)
1609 goto err_remove_config_dt;
1610
1611 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
1612 if (ret)
1613 goto err_gmac_powerdown;
1614
1615 return 0;
1616
1617 err_gmac_powerdown:
1618 rk_gmac_powerdown(plat_dat->bsp_priv);
1619 err_remove_config_dt:
1620 stmmac_remove_config_dt(pdev, plat_dat);
1621
1622 return ret;
1623 }
1624
rk_gmac_remove(struct platform_device * pdev)1625 static int rk_gmac_remove(struct platform_device *pdev)
1626 {
1627 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(&pdev->dev);
1628 int ret = stmmac_dvr_remove(&pdev->dev);
1629
1630 rk_gmac_powerdown(bsp_priv);
1631
1632 return ret;
1633 }
1634
1635 #ifdef CONFIG_PM_SLEEP
rk_gmac_suspend(struct device * dev)1636 static int rk_gmac_suspend(struct device *dev)
1637 {
1638 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1639 int ret = stmmac_suspend(dev);
1640
1641 /* Keep the PHY up if we use Wake-on-Lan. */
1642 if (!device_may_wakeup(dev)) {
1643 rk_gmac_powerdown(bsp_priv);
1644 bsp_priv->suspended = true;
1645 }
1646
1647 return ret;
1648 }
1649
rk_gmac_resume(struct device * dev)1650 static int rk_gmac_resume(struct device *dev)
1651 {
1652 struct rk_priv_data *bsp_priv = get_stmmac_bsp_priv(dev);
1653
1654 /* The PHY was up for Wake-on-Lan. */
1655 if (bsp_priv->suspended) {
1656 rk_gmac_powerup(bsp_priv);
1657 bsp_priv->suspended = false;
1658 }
1659
1660 return stmmac_resume(dev);
1661 }
1662 #endif /* CONFIG_PM_SLEEP */
1663
1664 static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
1665
1666 static const struct of_device_id rk_gmac_dwmac_match[] = {
1667 { .compatible = "rockchip,px30-gmac", .data = &px30_ops },
1668 { .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
1669 { .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
1670 { .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
1671 { .compatible = "rockchip,rk3308-gmac", .data = &rk3308_ops },
1672 { .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
1673 { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
1674 { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
1675 { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
1676 { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
1677 { .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
1678 { }
1679 };
1680 MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
1681
1682 static struct platform_driver rk_gmac_dwmac_driver = {
1683 .probe = rk_gmac_probe,
1684 .remove = rk_gmac_remove,
1685 .driver = {
1686 .name = "rk_gmac-dwmac",
1687 .pm = &rk_gmac_pm_ops,
1688 .of_match_table = rk_gmac_dwmac_match,
1689 },
1690 };
1691 module_platform_driver(rk_gmac_dwmac_driver);
1692
1693 MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
1694 MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
1695 MODULE_LICENSE("GPL");
1696