1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include <linux/etherdevice.h>
5 #include <linux/timekeeping.h>
6 #include "mt7915.h"
7 #include "../dma.h"
8 #include "mac.h"
9
10 #define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
11
12 #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f)
13 #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\
14 IEEE80211_RADIOTAP_HE_##f)
15
16 static const struct mt7915_dfs_radar_spec etsi_radar_specs = {
17 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
18 .radar_pattern = {
19 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 },
20 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 },
21 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 },
22 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 },
23 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 },
24 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 },
25 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 },
26 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 },
27 },
28 };
29
30 static const struct mt7915_dfs_radar_spec fcc_radar_specs = {
31 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
32 .radar_pattern = {
33 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
34 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
35 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
36 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
37 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
38 },
39 };
40
41 static const struct mt7915_dfs_radar_spec jp_radar_specs = {
42 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 },
43 .radar_pattern = {
44 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 },
45 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 },
46 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 },
47 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 },
48 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 },
49 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 },
50 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 },
51 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 },
52 },
53 };
54
mt7915_rx_get_wcid(struct mt7915_dev * dev,u16 idx,bool unicast)55 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev,
56 u16 idx, bool unicast)
57 {
58 struct mt7915_sta *sta;
59 struct mt76_wcid *wcid;
60
61 if (idx >= ARRAY_SIZE(dev->mt76.wcid))
62 return NULL;
63
64 wcid = rcu_dereference(dev->mt76.wcid[idx]);
65 if (unicast || !wcid)
66 return wcid;
67
68 if (!wcid->sta)
69 return NULL;
70
71 sta = container_of(wcid, struct mt7915_sta, wcid);
72 if (!sta->vif)
73 return NULL;
74
75 return &sta->vif->sta.wcid;
76 }
77
mt7915_sta_ps(struct mt76_dev * mdev,struct ieee80211_sta * sta,bool ps)78 void mt7915_sta_ps(struct mt76_dev *mdev, struct ieee80211_sta *sta, bool ps)
79 {
80 }
81
mt7915_mac_wtbl_update(struct mt7915_dev * dev,int idx,u32 mask)82 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask)
83 {
84 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
85 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
86
87 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
88 0, 5000);
89 }
90
mt7915_mac_wtbl_lmac_addr(struct mt7915_dev * dev,u16 wcid)91 static u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid)
92 {
93 mt76_wr(dev, MT_WTBLON_TOP_WDUCR,
94 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7)));
95
96 return MT_WTBL_LMAC_OFFS(wcid, 0);
97 }
98
99 /* TODO: use txfree airtime info to avoid runtime accessing in the long run */
mt7915_mac_sta_poll(struct mt7915_dev * dev)100 static void mt7915_mac_sta_poll(struct mt7915_dev *dev)
101 {
102 static const u8 ac_to_tid[] = {
103 [IEEE80211_AC_BE] = 0,
104 [IEEE80211_AC_BK] = 1,
105 [IEEE80211_AC_VI] = 4,
106 [IEEE80211_AC_VO] = 6
107 };
108 struct ieee80211_sta *sta;
109 struct mt7915_sta *msta;
110 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS];
111 LIST_HEAD(sta_poll_list);
112 int i;
113
114 spin_lock_bh(&dev->sta_poll_lock);
115 list_splice_init(&dev->sta_poll_list, &sta_poll_list);
116 spin_unlock_bh(&dev->sta_poll_lock);
117
118 rcu_read_lock();
119
120 while (true) {
121 bool clear = false;
122 u32 addr;
123 u16 idx;
124
125 spin_lock_bh(&dev->sta_poll_lock);
126 if (list_empty(&sta_poll_list)) {
127 spin_unlock_bh(&dev->sta_poll_lock);
128 break;
129 }
130 msta = list_first_entry(&sta_poll_list,
131 struct mt7915_sta, poll_list);
132 list_del_init(&msta->poll_list);
133 spin_unlock_bh(&dev->sta_poll_lock);
134
135 idx = msta->wcid.idx;
136 addr = mt7915_mac_wtbl_lmac_addr(dev, idx) + 20 * 4;
137
138 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
139 u32 tx_last = msta->airtime_ac[i];
140 u32 rx_last = msta->airtime_ac[i + 4];
141
142 msta->airtime_ac[i] = mt76_rr(dev, addr);
143 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4);
144
145 tx_time[i] = msta->airtime_ac[i] - tx_last;
146 rx_time[i] = msta->airtime_ac[i + 4] - rx_last;
147
148 if ((tx_last | rx_last) & BIT(30))
149 clear = true;
150
151 addr += 8;
152 }
153
154 if (clear) {
155 mt7915_mac_wtbl_update(dev, idx,
156 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
157 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac));
158 }
159
160 if (!msta->wcid.sta)
161 continue;
162
163 sta = container_of((void *)msta, struct ieee80211_sta,
164 drv_priv);
165 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
166 u8 q = mt7915_lmac_mapping(dev, i);
167 u32 tx_cur = tx_time[q];
168 u32 rx_cur = rx_time[q];
169 u8 tid = ac_to_tid[i];
170
171 if (!tx_cur && !rx_cur)
172 continue;
173
174 ieee80211_sta_register_airtime(sta, tid, tx_cur,
175 rx_cur);
176 }
177 }
178
179 rcu_read_unlock();
180 }
181
182 static void
mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status * status,struct ieee80211_radiotap_he * he,__le32 * rxv)183 mt7915_mac_decode_he_radiotap_ru(struct mt76_rx_status *status,
184 struct ieee80211_radiotap_he *he,
185 __le32 *rxv)
186 {
187 u32 ru_h, ru_l;
188 u8 ru, offs = 0;
189
190 ru_l = FIELD_GET(MT_PRXV_HE_RU_ALLOC_L, le32_to_cpu(rxv[0]));
191 ru_h = FIELD_GET(MT_PRXV_HE_RU_ALLOC_H, le32_to_cpu(rxv[1]));
192 ru = (u8)(ru_l | ru_h << 4);
193
194 status->bw = RATE_INFO_BW_HE_RU;
195
196 switch (ru) {
197 case 0 ... 36:
198 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_26;
199 offs = ru;
200 break;
201 case 37 ... 52:
202 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_52;
203 offs = ru - 37;
204 break;
205 case 53 ... 60:
206 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106;
207 offs = ru - 53;
208 break;
209 case 61 ... 64:
210 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_242;
211 offs = ru - 61;
212 break;
213 case 65 ... 66:
214 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_484;
215 offs = ru - 65;
216 break;
217 case 67:
218 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_996;
219 break;
220 case 68:
221 status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
222 break;
223 }
224
225 he->data1 |= HE_BITS(DATA1_BW_RU_ALLOC_KNOWN);
226 he->data2 |= HE_BITS(DATA2_RU_OFFSET_KNOWN) |
227 le16_encode_bits(offs,
228 IEEE80211_RADIOTAP_HE_DATA2_RU_OFFSET);
229 }
230
231 static void
mt7915_mac_decode_he_radiotap(struct sk_buff * skb,struct mt76_rx_status * status,__le32 * rxv,u32 phy)232 mt7915_mac_decode_he_radiotap(struct sk_buff *skb,
233 struct mt76_rx_status *status,
234 __le32 *rxv, u32 phy)
235 {
236 /* TODO: struct ieee80211_radiotap_he_mu */
237 static const struct ieee80211_radiotap_he known = {
238 .data1 = HE_BITS(DATA1_DATA_MCS_KNOWN) |
239 HE_BITS(DATA1_DATA_DCM_KNOWN) |
240 HE_BITS(DATA1_STBC_KNOWN) |
241 HE_BITS(DATA1_CODING_KNOWN) |
242 HE_BITS(DATA1_LDPC_XSYMSEG_KNOWN) |
243 HE_BITS(DATA1_DOPPLER_KNOWN) |
244 HE_BITS(DATA1_BSS_COLOR_KNOWN),
245 .data2 = HE_BITS(DATA2_GI_KNOWN) |
246 HE_BITS(DATA2_TXBF_KNOWN) |
247 HE_BITS(DATA2_PE_DISAMBIG_KNOWN) |
248 HE_BITS(DATA2_TXOP_KNOWN),
249 };
250 struct ieee80211_radiotap_he *he = NULL;
251 u32 ltf_size = le32_get_bits(rxv[2], MT_CRXV_HE_LTF_SIZE) + 1;
252
253 he = skb_push(skb, sizeof(known));
254 memcpy(he, &known, sizeof(known));
255
256 he->data3 = HE_PREP(DATA3_BSS_COLOR, BSS_COLOR, rxv[14]) |
257 HE_PREP(DATA3_LDPC_XSYMSEG, LDPC_EXT_SYM, rxv[2]);
258 he->data5 = HE_PREP(DATA5_PE_DISAMBIG, PE_DISAMBIG, rxv[2]) |
259 le16_encode_bits(ltf_size,
260 IEEE80211_RADIOTAP_HE_DATA5_LTF_SIZE);
261 he->data6 = HE_PREP(DATA6_TXOP, TXOP_DUR, rxv[14]) |
262 HE_PREP(DATA6_DOPPLER, DOPPLER, rxv[14]);
263
264 switch (phy) {
265 case MT_PHY_TYPE_HE_SU:
266 he->data1 |= HE_BITS(DATA1_FORMAT_SU) |
267 HE_BITS(DATA1_UL_DL_KNOWN) |
268 HE_BITS(DATA1_BEAM_CHANGE_KNOWN) |
269 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
270
271 he->data3 |= HE_PREP(DATA3_BEAM_CHANGE, BEAM_CHNG, rxv[14]) |
272 HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
273 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
274 break;
275 case MT_PHY_TYPE_HE_EXT_SU:
276 he->data1 |= HE_BITS(DATA1_FORMAT_EXT_SU) |
277 HE_BITS(DATA1_UL_DL_KNOWN);
278
279 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
280 break;
281 case MT_PHY_TYPE_HE_MU:
282 he->data1 |= HE_BITS(DATA1_FORMAT_MU) |
283 HE_BITS(DATA1_UL_DL_KNOWN) |
284 HE_BITS(DATA1_SPTL_REUSE_KNOWN);
285
286 he->data3 |= HE_PREP(DATA3_UL_DL, UPLINK, rxv[2]);
287 he->data4 |= HE_PREP(DATA4_SU_MU_SPTL_REUSE, SR_MASK, rxv[11]);
288
289 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
290 break;
291 case MT_PHY_TYPE_HE_TB:
292 he->data1 |= HE_BITS(DATA1_FORMAT_TRIG) |
293 HE_BITS(DATA1_SPTL_REUSE_KNOWN) |
294 HE_BITS(DATA1_SPTL_REUSE2_KNOWN) |
295 HE_BITS(DATA1_SPTL_REUSE3_KNOWN) |
296 HE_BITS(DATA1_SPTL_REUSE4_KNOWN);
297
298 he->data4 |= HE_PREP(DATA4_TB_SPTL_REUSE1, SR_MASK, rxv[11]) |
299 HE_PREP(DATA4_TB_SPTL_REUSE2, SR1_MASK, rxv[11]) |
300 HE_PREP(DATA4_TB_SPTL_REUSE3, SR2_MASK, rxv[11]) |
301 HE_PREP(DATA4_TB_SPTL_REUSE4, SR3_MASK, rxv[11]);
302
303 mt7915_mac_decode_he_radiotap_ru(status, he, rxv);
304 break;
305 default:
306 break;
307 }
308 }
309
310 static int
mt7915_mac_fill_rx(struct mt7915_dev * dev,struct sk_buff * skb)311 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
312 {
313 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
314 struct mt76_phy *mphy = &dev->mt76.phy;
315 struct mt7915_phy *phy = &dev->phy;
316 struct ieee80211_supported_band *sband;
317 struct ieee80211_hdr *hdr;
318 __le32 *rxd = (__le32 *)skb->data;
319 __le32 *rxv = NULL;
320 u32 mode = 0;
321 u32 rxd0 = le32_to_cpu(rxd[0]);
322 u32 rxd1 = le32_to_cpu(rxd[1]);
323 u32 rxd2 = le32_to_cpu(rxd[2]);
324 u32 rxd3 = le32_to_cpu(rxd[3]);
325 u32 rxd4 = le32_to_cpu(rxd[4]);
326 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
327 bool unicast, insert_ccmp_hdr = false;
328 u8 remove_pad, amsdu_info;
329 bool hdr_trans;
330 u16 seq_ctrl = 0;
331 u8 qos_ctl = 0;
332 __le16 fc = 0;
333 int i, idx;
334
335 memset(status, 0, sizeof(*status));
336
337 if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) {
338 mphy = dev->mt76.phy2;
339 if (!mphy)
340 return -EINVAL;
341
342 phy = mphy->priv;
343 status->ext_phy = true;
344 }
345
346 if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
347 return -EINVAL;
348
349 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
350 return -EINVAL;
351
352 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS;
353 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM))
354 return -EINVAL;
355
356 /* ICV error or CCMP/BIP/WPI MIC error */
357 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR)
358 status->flag |= RX_FLAG_ONLY_MONITOR;
359
360 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
361 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
362 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast);
363
364 if (status->wcid) {
365 struct mt7915_sta *msta;
366
367 msta = container_of(status->wcid, struct mt7915_sta, wcid);
368 spin_lock_bh(&dev->sta_poll_lock);
369 if (list_empty(&msta->poll_list))
370 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
371 spin_unlock_bh(&dev->sta_poll_lock);
372 }
373
374 status->freq = mphy->chandef.chan->center_freq;
375 status->band = mphy->chandef.chan->band;
376 if (status->band == NL80211_BAND_5GHZ)
377 sband = &mphy->sband_5g.sband;
378 else
379 sband = &mphy->sband_2g.sband;
380
381 if (!sband->channels)
382 return -EINVAL;
383
384 if ((rxd0 & csum_mask) == csum_mask)
385 skb->ip_summed = CHECKSUM_UNNECESSARY;
386
387 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR)
388 status->flag |= RX_FLAG_FAILED_FCS_CRC;
389
390 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR)
391 status->flag |= RX_FLAG_MMIC_ERROR;
392
393 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 &&
394 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) {
395 status->flag |= RX_FLAG_DECRYPTED;
396 status->flag |= RX_FLAG_IV_STRIPPED;
397 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
398 }
399
400 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
401
402 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
403 return -EINVAL;
404
405 rxd += 6;
406 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
407 u32 v0 = le32_to_cpu(rxd[0]);
408 u32 v2 = le32_to_cpu(rxd[2]);
409
410 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));
411 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2);
412 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2);
413
414 rxd += 4;
415 if ((u8 *)rxd - skb->data >= skb->len)
416 return -EINVAL;
417 }
418
419 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
420 u8 *data = (u8 *)rxd;
421
422 if (status->flag & RX_FLAG_DECRYPTED) {
423 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) {
424 case MT_CIPHER_AES_CCMP:
425 case MT_CIPHER_CCMP_CCX:
426 case MT_CIPHER_CCMP_256:
427 insert_ccmp_hdr =
428 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
429 fallthrough;
430 case MT_CIPHER_TKIP:
431 case MT_CIPHER_TKIP_NO_MIC:
432 case MT_CIPHER_GCMP:
433 case MT_CIPHER_GCMP_256:
434 status->iv[0] = data[5];
435 status->iv[1] = data[4];
436 status->iv[2] = data[3];
437 status->iv[3] = data[2];
438 status->iv[4] = data[1];
439 status->iv[5] = data[0];
440 break;
441 default:
442 break;
443 }
444 }
445 rxd += 4;
446 if ((u8 *)rxd - skb->data >= skb->len)
447 return -EINVAL;
448 }
449
450 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
451 status->timestamp = le32_to_cpu(rxd[0]);
452 status->flag |= RX_FLAG_MACTIME_START;
453
454 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) {
455 status->flag |= RX_FLAG_AMPDU_DETAILS;
456
457 /* all subframes of an A-MPDU have the same timestamp */
458 if (phy->rx_ampdu_ts != status->timestamp) {
459 if (!++phy->ampdu_ref)
460 phy->ampdu_ref++;
461 }
462 phy->rx_ampdu_ts = status->timestamp;
463
464 status->ampdu_ref = phy->ampdu_ref;
465 }
466
467 rxd += 2;
468 if ((u8 *)rxd - skb->data >= skb->len)
469 return -EINVAL;
470 }
471
472 /* RXD Group 3 - P-RXV */
473 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
474 u32 v0, v1, v2;
475
476 rxv = rxd;
477 rxd += 2;
478 if ((u8 *)rxd - skb->data >= skb->len)
479 return -EINVAL;
480
481 v0 = le32_to_cpu(rxv[0]);
482 v1 = le32_to_cpu(rxv[1]);
483 v2 = le32_to_cpu(rxv[2]);
484
485 if (v0 & MT_PRXV_HT_AD_CODE)
486 status->enc_flags |= RX_ENC_FLAG_LDPC;
487
488 status->chains = mphy->antenna_mask;
489 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
490 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
491 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
492 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
493 status->signal = status->chain_signal[0];
494
495 for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
496 if (!(status->chains & BIT(i)))
497 continue;
498
499 status->signal = max(status->signal,
500 status->chain_signal[i]);
501 }
502
503 /* RXD Group 5 - C-RXV */
504 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
505 u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
506 u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
507 bool cck = false;
508
509 rxd += 18;
510 if ((u8 *)rxd - skb->data >= skb->len)
511 return -EINVAL;
512
513 idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
514 mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
515
516 switch (mode) {
517 case MT_PHY_TYPE_CCK:
518 cck = true;
519 fallthrough;
520 case MT_PHY_TYPE_OFDM:
521 i = mt76_get_rate(&dev->mt76, sband, i, cck);
522 break;
523 case MT_PHY_TYPE_HT_GF:
524 case MT_PHY_TYPE_HT:
525 status->encoding = RX_ENC_HT;
526 if (i > 31)
527 return -EINVAL;
528 break;
529 case MT_PHY_TYPE_VHT:
530 status->nss =
531 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
532 status->encoding = RX_ENC_VHT;
533 if (i > 9)
534 return -EINVAL;
535 break;
536 case MT_PHY_TYPE_HE_MU:
537 status->flag |= RX_FLAG_RADIOTAP_HE_MU;
538 fallthrough;
539 case MT_PHY_TYPE_HE_SU:
540 case MT_PHY_TYPE_HE_EXT_SU:
541 case MT_PHY_TYPE_HE_TB:
542 status->nss =
543 FIELD_GET(MT_PRXV_NSTS, v0) + 1;
544 status->encoding = RX_ENC_HE;
545 status->flag |= RX_FLAG_RADIOTAP_HE;
546 i &= GENMASK(3, 0);
547
548 if (gi <= NL80211_RATE_INFO_HE_GI_3_2)
549 status->he_gi = gi;
550
551 status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
552 break;
553 default:
554 return -EINVAL;
555 }
556 status->rate_idx = i;
557
558 switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
559 case IEEE80211_STA_RX_BW_20:
560 break;
561 case IEEE80211_STA_RX_BW_40:
562 if (mode & MT_PHY_TYPE_HE_EXT_SU &&
563 (idx & MT_PRXV_TX_ER_SU_106T)) {
564 status->bw = RATE_INFO_BW_HE_RU;
565 status->he_ru =
566 NL80211_RATE_INFO_HE_RU_ALLOC_106;
567 } else {
568 status->bw = RATE_INFO_BW_40;
569 }
570 break;
571 case IEEE80211_STA_RX_BW_80:
572 status->bw = RATE_INFO_BW_80;
573 break;
574 case IEEE80211_STA_RX_BW_160:
575 status->bw = RATE_INFO_BW_160;
576 break;
577 default:
578 return -EINVAL;
579 }
580
581 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * stbc;
582 if (mode < MT_PHY_TYPE_HE_SU && gi)
583 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
584 }
585 }
586
587 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
588
589 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4);
590 status->amsdu = !!amsdu_info;
591 if (status->amsdu) {
592 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME;
593 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME;
594 if (!hdr_trans) {
595 memmove(skb->data + 2, skb->data,
596 ieee80211_get_hdrlen_from_skb(skb));
597 skb_pull(skb, 2);
598 }
599 }
600
601 if (insert_ccmp_hdr && !hdr_trans) {
602 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
603
604 mt76_insert_ccmp_hdr(skb, key_id);
605 }
606
607 if (!hdr_trans) {
608 hdr = mt76_skb_get_hdr(skb);
609 fc = hdr->frame_control;
610 if (ieee80211_is_data_qos(fc)) {
611 seq_ctrl = le16_to_cpu(hdr->seq_ctrl);
612 qos_ctl = *ieee80211_get_qos_ctl(hdr);
613 }
614 } else {
615 status->flag &= ~(RX_FLAG_RADIOTAP_HE |
616 RX_FLAG_RADIOTAP_HE_MU);
617 status->flag |= RX_FLAG_8023;
618 }
619
620 if (rxv && status->flag & RX_FLAG_RADIOTAP_HE)
621 mt7915_mac_decode_he_radiotap(skb, status, rxv, mode);
622
623 if (!status->wcid || !ieee80211_is_data_qos(fc))
624 return 0;
625
626 status->aggr = unicast &&
627 !ieee80211_is_qos_nullfunc(fc);
628 status->qos_ctl = qos_ctl;
629 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl);
630
631 return 0;
632 }
633
634 static void
mt7915_mac_fill_rx_vector(struct mt7915_dev * dev,struct sk_buff * skb)635 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb)
636 {
637 #ifdef CONFIG_NL80211_TESTMODE
638 struct mt7915_phy *phy = &dev->phy;
639 __le32 *rxd = (__le32 *)skb->data;
640 __le32 *rxv_hdr = rxd + 2;
641 __le32 *rxv = rxd + 4;
642 u32 rcpi, ib_rssi, wb_rssi, v20, v21;
643 bool ext_phy;
644 s32 foe;
645 u8 snr;
646 int i;
647
648 ext_phy = FIELD_GET(MT_RXV_HDR_BAND_IDX, le32_to_cpu(rxv_hdr[1]));
649 if (ext_phy)
650 phy = mt7915_ext_phy(dev);
651
652 rcpi = le32_to_cpu(rxv[6]);
653 ib_rssi = le32_to_cpu(rxv[7]);
654 wb_rssi = le32_to_cpu(rxv[8]) >> 5;
655
656 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) {
657 if (i == 3)
658 wb_rssi = le32_to_cpu(rxv[9]);
659
660 phy->test.last_rcpi[i] = rcpi & 0xff;
661 phy->test.last_ib_rssi[i] = ib_rssi & 0xff;
662 phy->test.last_wb_rssi[i] = wb_rssi & 0xff;
663 }
664
665 v20 = le32_to_cpu(rxv[20]);
666 v21 = le32_to_cpu(rxv[21]);
667
668 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) |
669 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT);
670
671 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16;
672
673 phy->test.last_freq_offset = foe;
674 phy->test.last_snr = snr;
675 #endif
676
677 dev_kfree_skb(skb);
678 }
679
680 static void
mt7915_mac_write_txwi_tm(struct mt7915_phy * phy,__le32 * txwi,struct sk_buff * skb)681 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi,
682 struct sk_buff *skb)
683 {
684 #ifdef CONFIG_NL80211_TESTMODE
685 struct mt76_testmode_data *td = &phy->mt76->test;
686 const struct ieee80211_rate *r;
687 u8 bw, mode, nss = td->tx_rate_nss;
688 u8 rate_idx = td->tx_rate_idx;
689 u16 rateval = 0;
690 u32 val;
691 bool cck = false;
692 int band;
693
694 if (skb != phy->mt76->test.tx_skb)
695 return;
696
697 switch (td->tx_rate_mode) {
698 case MT76_TM_TX_MODE_HT:
699 nss = 1 + (rate_idx >> 3);
700 mode = MT_PHY_TYPE_HT;
701 break;
702 case MT76_TM_TX_MODE_VHT:
703 mode = MT_PHY_TYPE_VHT;
704 break;
705 case MT76_TM_TX_MODE_HE_SU:
706 mode = MT_PHY_TYPE_HE_SU;
707 break;
708 case MT76_TM_TX_MODE_HE_EXT_SU:
709 mode = MT_PHY_TYPE_HE_EXT_SU;
710 break;
711 case MT76_TM_TX_MODE_HE_TB:
712 mode = MT_PHY_TYPE_HE_TB;
713 break;
714 case MT76_TM_TX_MODE_HE_MU:
715 mode = MT_PHY_TYPE_HE_MU;
716 break;
717 case MT76_TM_TX_MODE_CCK:
718 cck = true;
719 fallthrough;
720 case MT76_TM_TX_MODE_OFDM:
721 band = phy->mt76->chandef.chan->band;
722 if (band == NL80211_BAND_2GHZ && !cck)
723 rate_idx += 4;
724
725 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx];
726 val = cck ? r->hw_value_short : r->hw_value;
727
728 mode = val >> 8;
729 rate_idx = val & 0xff;
730 break;
731 default:
732 mode = MT_PHY_TYPE_OFDM;
733 break;
734 }
735
736 switch (phy->mt76->chandef.width) {
737 case NL80211_CHAN_WIDTH_40:
738 bw = 1;
739 break;
740 case NL80211_CHAN_WIDTH_80:
741 bw = 2;
742 break;
743 case NL80211_CHAN_WIDTH_80P80:
744 case NL80211_CHAN_WIDTH_160:
745 bw = 3;
746 break;
747 default:
748 bw = 0;
749 break;
750 }
751
752 if (td->tx_rate_stbc && nss == 1) {
753 nss++;
754 rateval |= MT_TX_RATE_STBC;
755 }
756
757 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
758 FIELD_PREP(MT_TX_RATE_MODE, mode) |
759 FIELD_PREP(MT_TX_RATE_NSS, nss - 1);
760
761 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
762
763 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT);
764 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT)
765 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
766
767 val = MT_TXD6_FIXED_BW |
768 FIELD_PREP(MT_TXD6_BW, bw) |
769 FIELD_PREP(MT_TXD6_TX_RATE, rateval) |
770 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi);
771
772 /* for HE_SU/HE_EXT_SU PPDU
773 * - 1x, 2x, 4x LTF + 0.8us GI
774 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
775 * for HE_MU PPDU
776 * - 2x, 4x LTF + 0.8us GI
777 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI
778 * for HE_TB PPDU
779 * - 1x, 2x LTF + 1.6us GI
780 * - 4x LTF + 3.2us GI
781 */
782 if (mode >= MT_PHY_TYPE_HE_SU)
783 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf);
784
785 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU))
786 val |= MT_TXD6_LDPC;
787
788 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID);
789 txwi[6] |= cpu_to_le32(val);
790 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX,
791 phy->test.spe_idx));
792 #endif
793 }
794
795 static void
mt7915_mac_write_txwi_8023(struct mt7915_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid)796 mt7915_mac_write_txwi_8023(struct mt7915_dev *dev, __le32 *txwi,
797 struct sk_buff *skb, struct mt76_wcid *wcid)
798 {
799
800 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
801 u8 fc_type, fc_stype;
802 u16 ethertype;
803 bool wmm = false;
804 u32 val;
805
806 if (wcid->sta) {
807 struct ieee80211_sta *sta;
808
809 sta = container_of((void *)wcid, struct ieee80211_sta, drv_priv);
810 wmm = sta->wme;
811 }
812
813 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3) |
814 FIELD_PREP(MT_TXD1_TID, tid);
815
816 ethertype = get_unaligned_be16(&skb->data[12]);
817 if (ethertype >= ETH_P_802_3_MIN)
818 val |= MT_TXD1_ETH_802_3;
819
820 txwi[1] |= cpu_to_le32(val);
821
822 fc_type = IEEE80211_FTYPE_DATA >> 2;
823 fc_stype = wmm ? IEEE80211_STYPE_QOS_DATA >> 4 : 0;
824
825 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
826 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype);
827
828 txwi[2] |= cpu_to_le32(val);
829
830 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
831 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
832 txwi[7] |= cpu_to_le32(val);
833 }
834
835 static void
mt7915_mac_write_txwi_80211(struct mt7915_dev * dev,__le32 * txwi,struct sk_buff * skb,struct ieee80211_key_conf * key)836 mt7915_mac_write_txwi_80211(struct mt7915_dev *dev, __le32 *txwi,
837 struct sk_buff *skb, struct ieee80211_key_conf *key)
838 {
839 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
840 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
841 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
842 bool multicast = is_multicast_ether_addr(hdr->addr1);
843 u8 tid = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
844 __le16 fc = hdr->frame_control;
845 u8 fc_type, fc_stype;
846 u32 val;
847
848 if (ieee80211_is_action(fc) &&
849 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
850 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ) {
851 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
852
853 txwi[5] |= cpu_to_le32(MT_TXD5_ADD_BA);
854 tid = (capab >> 2) & IEEE80211_QOS_CTL_TID_MASK;
855 } else if (ieee80211_is_back_req(hdr->frame_control)) {
856 struct ieee80211_bar *bar = (struct ieee80211_bar *)hdr;
857 u16 control = le16_to_cpu(bar->control);
858
859 tid = FIELD_GET(IEEE80211_BAR_CTRL_TID_INFO_MASK, control);
860 }
861
862 val = FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
863 FIELD_PREP(MT_TXD1_HDR_INFO,
864 ieee80211_get_hdrlen_from_skb(skb) / 2) |
865 FIELD_PREP(MT_TXD1_TID, tid);
866 txwi[1] |= cpu_to_le32(val);
867
868 fc_type = (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE) >> 2;
869 fc_stype = (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE) >> 4;
870
871 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, fc_type) |
872 FIELD_PREP(MT_TXD2_SUB_TYPE, fc_stype) |
873 FIELD_PREP(MT_TXD2_MULTICAST, multicast);
874
875 if (key && multicast && ieee80211_is_robust_mgmt_frame(skb) &&
876 key->cipher == WLAN_CIPHER_SUITE_AES_CMAC) {
877 val |= MT_TXD2_BIP;
878 txwi[3] &= ~cpu_to_le32(MT_TXD3_PROTECT_FRAME);
879 }
880
881 if (!ieee80211_is_data(fc) || multicast)
882 val |= MT_TXD2_FIX_RATE;
883
884 txwi[2] |= cpu_to_le32(val);
885
886 if (ieee80211_is_beacon(fc)) {
887 txwi[3] &= ~cpu_to_le32(MT_TXD3_SW_POWER_MGMT);
888 txwi[3] |= cpu_to_le32(MT_TXD3_REM_TX_COUNT);
889 }
890
891 if (info->flags & IEEE80211_TX_CTL_INJECTED) {
892 u16 seqno = le16_to_cpu(hdr->seq_ctrl);
893
894 if (ieee80211_is_back_req(hdr->frame_control)) {
895 struct ieee80211_bar *bar;
896
897 bar = (struct ieee80211_bar *)skb->data;
898 seqno = le16_to_cpu(bar->start_seq_num);
899 }
900
901 val = MT_TXD3_SN_VALID |
902 FIELD_PREP(MT_TXD3_SEQ, IEEE80211_SEQ_TO_SN(seqno));
903 txwi[3] |= cpu_to_le32(val);
904 txwi[7] &= ~cpu_to_le32(MT_TXD7_HW_AMSDU);
905 }
906
907 val = FIELD_PREP(MT_TXD7_TYPE, fc_type) |
908 FIELD_PREP(MT_TXD7_SUB_TYPE, fc_stype);
909 txwi[7] |= cpu_to_le32(val);
910 }
911
mt7915_mac_write_txwi(struct mt7915_dev * dev,__le32 * txwi,struct sk_buff * skb,struct mt76_wcid * wcid,int pid,struct ieee80211_key_conf * key,bool beacon)912 void mt7915_mac_write_txwi(struct mt7915_dev *dev, __le32 *txwi,
913 struct sk_buff *skb, struct mt76_wcid *wcid, int pid,
914 struct ieee80211_key_conf *key, bool beacon)
915 {
916 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
917 struct ieee80211_vif *vif = info->control.vif;
918 struct mt76_phy *mphy = &dev->mphy;
919 bool ext_phy = info->hw_queue & MT_TX_HW_QUEUE_EXT_PHY;
920 u8 p_fmt, q_idx, omac_idx = 0, wmm_idx = 0;
921 bool is_8023 = info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP;
922 u16 tx_count = 15;
923 u32 val;
924
925 if (vif) {
926 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
927
928 omac_idx = mvif->omac_idx;
929 wmm_idx = mvif->wmm_idx;
930 }
931
932 if (ext_phy && dev->mt76.phy2)
933 mphy = dev->mt76.phy2;
934
935 if (beacon) {
936 p_fmt = MT_TX_TYPE_FW;
937 q_idx = MT_LMAC_BCN0;
938 } else if (skb_get_queue_mapping(skb) >= MT_TXQ_PSD) {
939 p_fmt = MT_TX_TYPE_CT;
940 q_idx = MT_LMAC_ALTX0;
941 } else {
942 p_fmt = MT_TX_TYPE_CT;
943 q_idx = wmm_idx * MT7915_MAX_WMM_SETS +
944 mt7915_lmac_mapping(dev, skb_get_queue_mapping(skb));
945 }
946
947 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
948 FIELD_PREP(MT_TXD0_PKT_FMT, p_fmt) |
949 FIELD_PREP(MT_TXD0_Q_IDX, q_idx);
950 txwi[0] = cpu_to_le32(val);
951
952 val = MT_TXD1_LONG_FORMAT |
953 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) |
954 FIELD_PREP(MT_TXD1_OWN_MAC, omac_idx);
955
956 if (ext_phy && q_idx >= MT_LMAC_ALTX0 && q_idx <= MT_LMAC_BCN0)
957 val |= MT_TXD1_TGID;
958
959 txwi[1] = cpu_to_le32(val);
960
961 txwi[2] = 0;
962
963 val = MT_TXD3_SW_POWER_MGMT |
964 FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count);
965 if (key)
966 val |= MT_TXD3_PROTECT_FRAME;
967 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
968 val |= MT_TXD3_NO_ACK;
969
970 txwi[3] = cpu_to_le32(val);
971 txwi[4] = 0;
972
973 val = FIELD_PREP(MT_TXD5_PID, pid);
974 if (pid >= MT_PACKET_ID_FIRST)
975 val |= MT_TXD5_TX_STATUS_HOST;
976 txwi[5] = cpu_to_le32(val);
977
978 txwi[6] = 0;
979 txwi[7] = wcid->amsdu ? cpu_to_le32(MT_TXD7_HW_AMSDU) : 0;
980
981 if (is_8023)
982 mt7915_mac_write_txwi_8023(dev, txwi, skb, wcid);
983 else
984 mt7915_mac_write_txwi_80211(dev, txwi, skb, key);
985
986 if (txwi[2] & cpu_to_le32(MT_TXD2_FIX_RATE)) {
987 u16 rate;
988
989 /* hardware won't add HTC for mgmt/ctrl frame */
990 txwi[2] |= cpu_to_le32(MT_TXD2_HTC_VLD);
991
992 if (mphy->chandef.chan->band == NL80211_BAND_5GHZ)
993 rate = MT7915_5G_RATE_DEFAULT;
994 else
995 rate = MT7915_2G_RATE_DEFAULT;
996
997 val = MT_TXD6_FIXED_BW |
998 FIELD_PREP(MT_TXD6_TX_RATE, rate);
999 txwi[6] |= cpu_to_le32(val);
1000 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE);
1001 }
1002
1003 if (mt76_testmode_enabled(mphy))
1004 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb);
1005 }
1006
mt7915_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)1007 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1008 enum mt76_txq_id qid, struct mt76_wcid *wcid,
1009 struct ieee80211_sta *sta,
1010 struct mt76_tx_info *tx_info)
1011 {
1012 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data;
1013 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1014 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1015 struct ieee80211_key_conf *key = info->control.hw_key;
1016 struct ieee80211_vif *vif = info->control.vif;
1017 struct mt76_txwi_cache *t;
1018 struct mt7915_txp *txp;
1019 int id, i, nbuf = tx_info->nbuf - 1;
1020 u8 *txwi = (u8 *)txwi_ptr;
1021 int pid;
1022
1023 if (unlikely(tx_info->skb->len <= ETH_HLEN))
1024 return -EINVAL;
1025
1026 if (!wcid)
1027 wcid = &dev->mt76.global_wcid;
1028
1029 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1030
1031 mt7915_mac_write_txwi(dev, txwi_ptr, tx_info->skb, wcid, pid, key,
1032 false);
1033
1034 txp = (struct mt7915_txp *)(txwi + MT_TXD_SIZE);
1035 for (i = 0; i < nbuf; i++) {
1036 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr);
1037 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len);
1038 }
1039 txp->nbuf = nbuf;
1040
1041 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST);
1042
1043 if (!key)
1044 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME);
1045
1046 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
1047 ieee80211_is_mgmt(hdr->frame_control))
1048 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME);
1049
1050 if (vif) {
1051 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv;
1052
1053 txp->bss_idx = mvif->idx;
1054 }
1055
1056 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size);
1057 t->skb = tx_info->skb;
1058
1059 id = mt76_token_consume(mdev, &t);
1060 if (id < 0)
1061 return id;
1062
1063 txp->token = cpu_to_le16(id);
1064 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags))
1065 txp->rept_wds_wcid = cpu_to_le16(wcid->idx);
1066 else
1067 txp->rept_wds_wcid = cpu_to_le16(0x3ff);
1068 tx_info->skb = DMA_DUMMY_DATA;
1069
1070 /* pass partial skb header to fw */
1071 tx_info->buf[1].len = MT_CT_PARSE_LEN;
1072 tx_info->buf[1].skip_unmap = true;
1073 tx_info->nbuf = MT_CT_DMA_BUF_NUM;
1074
1075 return 0;
1076 }
1077
1078 static void
mt7915_tx_check_aggr(struct ieee80211_sta * sta,__le32 * txwi)1079 mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi)
1080 {
1081 struct mt7915_sta *msta;
1082 u16 fc, tid;
1083 u32 val;
1084
1085 if (!sta || !sta->deflink.ht_cap.ht_supported)
1086 return;
1087
1088 tid = FIELD_GET(MT_TXD1_TID, le32_to_cpu(txwi[1]));
1089 if (tid >= 6) /* skip VO queue */
1090 return;
1091
1092 val = le32_to_cpu(txwi[2]);
1093 fc = FIELD_GET(MT_TXD2_FRAME_TYPE, val) << 2 |
1094 FIELD_GET(MT_TXD2_SUB_TYPE, val) << 4;
1095 if (unlikely(fc != (IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_DATA)))
1096 return;
1097
1098 msta = (struct mt7915_sta *)sta->drv_priv;
1099 if (!test_and_set_bit(tid, &msta->ampdu_state))
1100 ieee80211_start_tx_ba_session(sta, tid, 0);
1101 }
1102
1103 static void
mt7915_txp_skb_unmap(struct mt76_dev * dev,struct mt76_txwi_cache * t)1104 mt7915_txp_skb_unmap(struct mt76_dev *dev, struct mt76_txwi_cache *t)
1105 {
1106 struct mt7915_txp *txp;
1107 int i;
1108
1109 txp = mt7915_txwi_to_txp(dev, t);
1110 for (i = 0; i < txp->nbuf; i++)
1111 dma_unmap_single(dev->dev, le32_to_cpu(txp->buf[i]),
1112 le16_to_cpu(txp->len[i]), DMA_TO_DEVICE);
1113 }
1114
1115 static void
mt7915_txwi_free(struct mt7915_dev * dev,struct mt76_txwi_cache * t,struct ieee80211_sta * sta,struct list_head * free_list)1116 mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
1117 struct ieee80211_sta *sta, struct list_head *free_list)
1118 {
1119 struct mt76_dev *mdev = &dev->mt76;
1120 struct mt76_wcid *wcid;
1121 __le32 *txwi;
1122 u16 wcid_idx;
1123
1124 mt7915_txp_skb_unmap(mdev, t);
1125 if (!t->skb)
1126 goto out;
1127
1128 txwi = (__le32 *)mt76_get_txwi_ptr(mdev, t);
1129 if (sta) {
1130 wcid = (struct mt76_wcid *)sta->drv_priv;
1131 wcid_idx = wcid->idx;
1132
1133 if (likely(t->skb->protocol != cpu_to_be16(ETH_P_PAE)))
1134 mt7915_tx_check_aggr(sta, txwi);
1135 } else {
1136 wcid_idx = FIELD_GET(MT_TXD1_WLAN_IDX, le32_to_cpu(txwi[1]));
1137 }
1138
1139 __mt76_tx_complete_skb(mdev, wcid_idx, t->skb, free_list);
1140
1141 out:
1142 t->skb = NULL;
1143 mt76_put_txwi(mdev, t);
1144 }
1145
1146 static void
mt7915_mac_tx_free(struct mt7915_dev * dev,struct sk_buff * skb)1147 mt7915_mac_tx_free(struct mt7915_dev *dev, struct sk_buff *skb)
1148 {
1149 struct mt7915_tx_free *free = (struct mt7915_tx_free *)skb->data;
1150 struct mt76_dev *mdev = &dev->mt76;
1151 struct mt76_phy *mphy_ext = mdev->phy2;
1152 struct mt76_txwi_cache *txwi;
1153 struct ieee80211_sta *sta = NULL;
1154 LIST_HEAD(free_list);
1155 struct sk_buff *tmp;
1156 u8 i, count;
1157 bool wake = false;
1158
1159 /* clean DMA queues and unmap buffers first */
1160 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false);
1161 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false);
1162 if (mphy_ext) {
1163 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false);
1164 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false);
1165 }
1166
1167 /*
1168 * TODO: MT_TX_FREE_LATENCY is msdu time from the TXD is queued into PLE,
1169 * to the time ack is received or dropped by hw (air + hw queue time).
1170 * Should avoid accessing WTBL to get Tx airtime, and use it instead.
1171 */
1172 count = FIELD_GET(MT_TX_FREE_MSDU_CNT, le16_to_cpu(free->ctrl));
1173 for (i = 0; i < count; i++) {
1174 u32 msdu, info = le32_to_cpu(free->info[i]);
1175 u8 stat;
1176
1177 /*
1178 * 1'b1: new wcid pair.
1179 * 1'b0: msdu_id with the same 'wcid pair' as above.
1180 */
1181 if (info & MT_TX_FREE_PAIR) {
1182 struct mt7915_sta *msta;
1183 struct mt7915_phy *phy;
1184 struct mt76_wcid *wcid;
1185 u16 idx;
1186
1187 count++;
1188 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info);
1189 wcid = rcu_dereference(dev->mt76.wcid[idx]);
1190 sta = wcid_to_sta(wcid);
1191 if (!sta)
1192 continue;
1193
1194 msta = container_of(wcid, struct mt7915_sta, wcid);
1195 phy = msta->vif->phy;
1196 spin_lock_bh(&dev->sta_poll_lock);
1197 if (list_empty(&msta->stats_list))
1198 list_add_tail(&msta->stats_list, &phy->stats_list);
1199 if (list_empty(&msta->poll_list))
1200 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1201 spin_unlock_bh(&dev->sta_poll_lock);
1202 continue;
1203 }
1204
1205 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info);
1206 stat = FIELD_GET(MT_TX_FREE_STATUS, info);
1207
1208 txwi = mt76_token_release(mdev, msdu, &wake);
1209 if (!txwi)
1210 continue;
1211
1212 mt7915_txwi_free(dev, txwi, sta, &free_list);
1213 }
1214
1215 mt7915_mac_sta_poll(dev);
1216
1217 if (wake)
1218 mt76_set_tx_blocked(&dev->mt76, false);
1219
1220 mt76_worker_schedule(&dev->mt76.tx_worker);
1221
1222 napi_consume_skb(skb, 1);
1223
1224 list_for_each_entry_safe(skb, tmp, &free_list, list) {
1225 skb_list_del_init(skb);
1226 napi_consume_skb(skb, 1);
1227 }
1228 }
1229
1230 static bool
mt7915_mac_add_txs_skb(struct mt7915_dev * dev,struct mt76_wcid * wcid,int pid,__le32 * txs_data)1231 mt7915_mac_add_txs_skb(struct mt7915_dev *dev, struct mt76_wcid *wcid, int pid,
1232 __le32 *txs_data)
1233 {
1234 struct mt76_dev *mdev = &dev->mt76;
1235 struct ieee80211_tx_info *info;
1236 struct sk_buff_head list;
1237 struct sk_buff *skb;
1238
1239 mt76_tx_status_lock(mdev, &list);
1240 skb = mt76_tx_status_skb_get(mdev, wcid, pid, &list);
1241 if (!skb)
1242 goto out;
1243
1244 info = IEEE80211_SKB_CB(skb);
1245 if (!(txs_data[0] & cpu_to_le32(MT_TXS0_ACK_ERROR_MASK)))
1246 info->flags |= IEEE80211_TX_STAT_ACK;
1247
1248 info->status.ampdu_len = 1;
1249 info->status.ampdu_ack_len = !!(info->flags &
1250 IEEE80211_TX_STAT_ACK);
1251
1252 info->status.rates[0].idx = -1;
1253 mt76_tx_status_skb_done(mdev, skb, &list);
1254
1255 out:
1256 mt76_tx_status_unlock(mdev, &list);
1257
1258 return !!skb;
1259 }
1260
mt7915_mac_add_txs(struct mt7915_dev * dev,void * data)1261 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data)
1262 {
1263 struct mt7915_sta *msta = NULL;
1264 struct mt76_wcid *wcid;
1265 __le32 *txs_data = data;
1266 u16 wcidx;
1267 u32 txs;
1268 u8 pid;
1269
1270 txs = le32_to_cpu(txs_data[0]);
1271 if (FIELD_GET(MT_TXS0_TXS_FORMAT, txs) > 1)
1272 return;
1273
1274 txs = le32_to_cpu(txs_data[2]);
1275 wcidx = FIELD_GET(MT_TXS2_WCID, txs);
1276
1277 txs = le32_to_cpu(txs_data[3]);
1278 pid = FIELD_GET(MT_TXS3_PID, txs);
1279
1280 if (pid < MT_PACKET_ID_FIRST)
1281 return;
1282
1283 if (wcidx >= MT7915_WTBL_SIZE)
1284 return;
1285
1286 rcu_read_lock();
1287
1288 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
1289 if (!wcid)
1290 goto out;
1291
1292 mt7915_mac_add_txs_skb(dev, wcid, pid, txs_data);
1293
1294 if (!wcid->sta)
1295 goto out;
1296
1297 msta = container_of(wcid, struct mt7915_sta, wcid);
1298 spin_lock_bh(&dev->sta_poll_lock);
1299 if (list_empty(&msta->poll_list))
1300 list_add_tail(&msta->poll_list, &dev->sta_poll_list);
1301 spin_unlock_bh(&dev->sta_poll_lock);
1302
1303 out:
1304 rcu_read_unlock();
1305 }
1306
mt7915_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)1307 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
1308 struct sk_buff *skb)
1309 {
1310 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
1311 __le32 *rxd = (__le32 *)skb->data;
1312 __le32 *end = (__le32 *)&skb->data[skb->len];
1313 enum rx_pkt_type type;
1314
1315 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
1316
1317 switch (type) {
1318 case PKT_TYPE_TXRX_NOTIFY:
1319 mt7915_mac_tx_free(dev, skb);
1320 break;
1321 case PKT_TYPE_RX_EVENT:
1322 mt7915_mcu_rx_event(dev, skb);
1323 break;
1324 case PKT_TYPE_TXRXV:
1325 mt7915_mac_fill_rx_vector(dev, skb);
1326 break;
1327 case PKT_TYPE_TXS:
1328 for (rxd += 2; rxd + 8 <= end; rxd += 8)
1329 mt7915_mac_add_txs(dev, rxd);
1330 dev_kfree_skb(skb);
1331 break;
1332 case PKT_TYPE_NORMAL:
1333 if (!mt7915_mac_fill_rx(dev, skb)) {
1334 mt76_rx(&dev->mt76, q, skb);
1335 return;
1336 }
1337 fallthrough;
1338 default:
1339 dev_kfree_skb(skb);
1340 break;
1341 }
1342 }
1343
mt7915_tx_complete_skb(struct mt76_dev * mdev,struct mt76_queue_entry * e)1344 void mt7915_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1345 {
1346 struct mt7915_dev *dev;
1347
1348 if (!e->txwi) {
1349 dev_kfree_skb_any(e->skb);
1350 return;
1351 }
1352
1353 dev = container_of(mdev, struct mt7915_dev, mt76);
1354
1355 /* error path */
1356 if (e->skb == DMA_DUMMY_DATA) {
1357 struct mt76_txwi_cache *t;
1358 struct mt7915_txp *txp;
1359
1360 txp = mt7915_txwi_to_txp(mdev, e->txwi);
1361 t = mt76_token_put(mdev, le16_to_cpu(txp->token));
1362 e->skb = t ? t->skb : NULL;
1363 }
1364
1365 if (e->skb)
1366 mt76_tx_complete_skb(mdev, e->wcid, e->skb);
1367 }
1368
mt7915_mac_cca_stats_reset(struct mt7915_phy * phy)1369 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy)
1370 {
1371 struct mt7915_dev *dev = phy->dev;
1372 bool ext_phy = phy != &dev->phy;
1373 u32 reg = MT_WF_PHY_RX_CTRL1(ext_phy);
1374
1375 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN);
1376 mt76_set(dev, reg, BIT(11) | BIT(9));
1377 }
1378
mt7915_mac_reset_counters(struct mt7915_phy * phy)1379 void mt7915_mac_reset_counters(struct mt7915_phy *phy)
1380 {
1381 struct mt7915_dev *dev = phy->dev;
1382 bool ext_phy = phy != &dev->phy;
1383 int i;
1384
1385 for (i = 0; i < 4; i++) {
1386 mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1387 mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
1388 }
1389
1390 if (ext_phy) {
1391 dev->mt76.phy2->survey_time = ktime_get_boottime();
1392 i = ARRAY_SIZE(dev->mt76.aggr_stats) / 2;
1393 } else {
1394 dev->mt76.phy.survey_time = ktime_get_boottime();
1395 i = 0;
1396 }
1397 memset(&dev->mt76.aggr_stats[i], 0, sizeof(dev->mt76.aggr_stats) / 2);
1398
1399 /* reset airtime counters */
1400 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(ext_phy),
1401 MT_WF_RMAC_MIB_RXTIME_CLR);
1402
1403 mt7915_mcu_get_chan_mib_info(phy, true);
1404 }
1405
mt7915_mac_set_timing(struct mt7915_phy * phy)1406 void mt7915_mac_set_timing(struct mt7915_phy *phy)
1407 {
1408 s16 coverage_class = phy->coverage_class;
1409 struct mt7915_dev *dev = phy->dev;
1410 bool ext_phy = phy != &dev->phy;
1411 u32 val, reg_offset;
1412 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
1413 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
1414 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
1415 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
1416 int sifs, offset;
1417 bool is_5ghz = phy->mt76->chandef.chan->band == NL80211_BAND_5GHZ;
1418
1419 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
1420 return;
1421
1422 if (is_5ghz)
1423 sifs = 16;
1424 else
1425 sifs = 10;
1426
1427 if (ext_phy) {
1428 coverage_class = max_t(s16, dev->phy.coverage_class,
1429 coverage_class);
1430 } else {
1431 struct mt7915_phy *phy_ext = mt7915_ext_phy(dev);
1432
1433 if (phy_ext)
1434 coverage_class = max_t(s16, phy_ext->coverage_class,
1435 coverage_class);
1436 }
1437 mt76_set(dev, MT_ARB_SCR(ext_phy),
1438 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1439 udelay(1);
1440
1441 offset = 3 * coverage_class;
1442 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
1443 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
1444
1445 mt76_wr(dev, MT_TMAC_CDTR(ext_phy), cck + reg_offset);
1446 mt76_wr(dev, MT_TMAC_ODTR(ext_phy), ofdm + reg_offset);
1447 mt76_wr(dev, MT_TMAC_ICR0(ext_phy),
1448 FIELD_PREP(MT_IFS_EIFS, 360) |
1449 FIELD_PREP(MT_IFS_RIFS, 2) |
1450 FIELD_PREP(MT_IFS_SIFS, sifs) |
1451 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
1452
1453 if (phy->slottime < 20 || is_5ghz)
1454 val = MT7915_CFEND_RATE_DEFAULT;
1455 else
1456 val = MT7915_CFEND_RATE_11B;
1457
1458 mt76_rmw_field(dev, MT_AGG_ACR0(ext_phy), MT_AGG_ACR_CFEND_RATE, val);
1459 mt76_clear(dev, MT_ARB_SCR(ext_phy),
1460 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1461 }
1462
mt7915_mac_enable_nf(struct mt7915_dev * dev,bool ext_phy)1463 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy)
1464 {
1465 mt76_set(dev, MT_WF_PHY_RXTD12(ext_phy),
1466 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY |
1467 MT_WF_PHY_RXTD12_IRPI_SW_CLR);
1468
1469 mt76_set(dev, MT_WF_PHY_RX_CTRL1(ext_phy),
1470 FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));
1471 }
1472
1473 static u8
mt7915_phy_get_nf(struct mt7915_phy * phy,int idx)1474 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx)
1475 {
1476 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 };
1477 struct mt7915_dev *dev = phy->dev;
1478 u32 val, sum = 0, n = 0;
1479 int nss, i;
1480
1481 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) {
1482 u32 reg = MT_WF_IRPI(nss + (idx << dev->dbdc_support));
1483
1484 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {
1485 val = mt76_rr(dev, reg);
1486 sum += val * nf_power[i];
1487 n += val;
1488 }
1489 }
1490
1491 if (!n)
1492 return 0;
1493
1494 return sum / n;
1495 }
1496
mt7915_update_channel(struct mt76_phy * mphy)1497 void mt7915_update_channel(struct mt76_phy *mphy)
1498 {
1499 struct mt7915_phy *phy = (struct mt7915_phy *)mphy->priv;
1500 struct mt76_channel_state *state = mphy->chan_state;
1501 bool ext_phy = phy != &phy->dev->phy;
1502 int nf;
1503
1504 mt7915_mcu_get_chan_mib_info(phy, false);
1505
1506 nf = mt7915_phy_get_nf(phy, ext_phy);
1507 if (!phy->noise)
1508 phy->noise = nf << 4;
1509 else if (nf)
1510 phy->noise += nf - (phy->noise >> 4);
1511
1512 state->noise = -(phy->noise >> 4);
1513 }
1514
1515 static bool
mt7915_wait_reset_state(struct mt7915_dev * dev,u32 state)1516 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state)
1517 {
1518 bool ret;
1519
1520 ret = wait_event_timeout(dev->reset_wait,
1521 (READ_ONCE(dev->reset_state) & state),
1522 MT7915_RESET_TIMEOUT);
1523
1524 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state);
1525 return ret;
1526 }
1527
1528 static void
mt7915_update_vif_beacon(void * priv,u8 * mac,struct ieee80211_vif * vif)1529 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif)
1530 {
1531 struct ieee80211_hw *hw = priv;
1532
1533 switch (vif->type) {
1534 case NL80211_IFTYPE_MESH_POINT:
1535 case NL80211_IFTYPE_ADHOC:
1536 case NL80211_IFTYPE_AP:
1537 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon);
1538 break;
1539 default:
1540 break;
1541 }
1542 }
1543
1544 static void
mt7915_update_beacons(struct mt7915_dev * dev)1545 mt7915_update_beacons(struct mt7915_dev *dev)
1546 {
1547 ieee80211_iterate_active_interfaces(dev->mt76.hw,
1548 IEEE80211_IFACE_ITER_RESUME_ALL,
1549 mt7915_update_vif_beacon, dev->mt76.hw);
1550
1551 if (!dev->mt76.phy2)
1552 return;
1553
1554 ieee80211_iterate_active_interfaces(dev->mt76.phy2->hw,
1555 IEEE80211_IFACE_ITER_RESUME_ALL,
1556 mt7915_update_vif_beacon, dev->mt76.phy2->hw);
1557 }
1558
1559 static void
mt7915_dma_reset(struct mt7915_dev * dev)1560 mt7915_dma_reset(struct mt7915_dev *dev)
1561 {
1562 struct mt76_phy *mphy_ext = dev->mt76.phy2;
1563 u32 hif1_ofs = MT_WFDMA1_PCIE1_BASE - MT_WFDMA1_BASE;
1564 int i;
1565
1566 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
1567 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1568 mt76_clear(dev, MT_WFDMA1_GLO_CFG,
1569 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN);
1570 if (dev->hif2) {
1571 mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
1572 (MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1573 MT_WFDMA0_GLO_CFG_RX_DMA_EN));
1574 mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
1575 (MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1576 MT_WFDMA1_GLO_CFG_RX_DMA_EN));
1577 }
1578
1579 usleep_range(1000, 2000);
1580
1581 for (i = 0; i < __MT_TXQ_MAX; i++) {
1582 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1583 if (mphy_ext)
1584 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[i], true);
1585 }
1586
1587 for (i = 0; i < __MT_MCUQ_MAX; i++)
1588 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
1589
1590 mt76_for_each_q_rx(&dev->mt76, i)
1591 mt76_queue_rx_reset(dev, i);
1592
1593 mt76_tx_status_check(&dev->mt76, NULL, true);
1594
1595 /* re-init prefetch settings after reset */
1596 mt7915_dma_prefetch(dev);
1597
1598 mt76_set(dev, MT_WFDMA0_GLO_CFG,
1599 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
1600 mt76_set(dev, MT_WFDMA1_GLO_CFG,
1601 MT_WFDMA1_GLO_CFG_TX_DMA_EN | MT_WFDMA1_GLO_CFG_RX_DMA_EN |
1602 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
1603 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO);
1604 if (dev->hif2) {
1605 mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,
1606 (MT_WFDMA0_GLO_CFG_TX_DMA_EN |
1607 MT_WFDMA0_GLO_CFG_RX_DMA_EN));
1608 mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,
1609 (MT_WFDMA1_GLO_CFG_TX_DMA_EN |
1610 MT_WFDMA1_GLO_CFG_RX_DMA_EN |
1611 MT_WFDMA1_GLO_CFG_OMIT_TX_INFO |
1612 MT_WFDMA1_GLO_CFG_OMIT_RX_INFO));
1613 }
1614 }
1615
mt7915_tx_token_put(struct mt7915_dev * dev)1616 void mt7915_tx_token_put(struct mt7915_dev *dev)
1617 {
1618 struct mt76_txwi_cache *txwi;
1619 int id;
1620
1621 spin_lock_bh(&dev->mt76.token_lock);
1622 idr_for_each_entry(&dev->mt76.token, txwi, id) {
1623 mt7915_txwi_free(dev, txwi, NULL, NULL);
1624 dev->mt76.token_count--;
1625 }
1626 spin_unlock_bh(&dev->mt76.token_lock);
1627 idr_destroy(&dev->mt76.token);
1628 }
1629
1630 /* system error recovery */
mt7915_mac_reset_work(struct work_struct * work)1631 void mt7915_mac_reset_work(struct work_struct *work)
1632 {
1633 struct mt7915_phy *phy2;
1634 struct mt76_phy *ext_phy;
1635 struct mt7915_dev *dev;
1636
1637 dev = container_of(work, struct mt7915_dev, reset_work);
1638 ext_phy = dev->mt76.phy2;
1639 phy2 = ext_phy ? ext_phy->priv : NULL;
1640
1641 if (!(READ_ONCE(dev->reset_state) & MT_MCU_CMD_STOP_DMA))
1642 return;
1643
1644 ieee80211_stop_queues(mt76_hw(dev));
1645 if (ext_phy)
1646 ieee80211_stop_queues(ext_phy->hw);
1647
1648 set_bit(MT76_RESET, &dev->mphy.state);
1649 set_bit(MT76_MCU_RESET, &dev->mphy.state);
1650 wake_up(&dev->mt76.mcu.wait);
1651 cancel_delayed_work_sync(&dev->mphy.mac_work);
1652 if (phy2) {
1653 set_bit(MT76_RESET, &phy2->mt76->state);
1654 cancel_delayed_work_sync(&phy2->mt76->mac_work);
1655 }
1656 mt76_worker_disable(&dev->mt76.tx_worker);
1657 napi_disable(&dev->mt76.napi[0]);
1658 napi_disable(&dev->mt76.napi[1]);
1659 napi_disable(&dev->mt76.napi[2]);
1660 napi_disable(&dev->mt76.tx_napi);
1661
1662 mutex_lock(&dev->mt76.mutex);
1663
1664 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED);
1665
1666 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) {
1667 mt7915_dma_reset(dev);
1668
1669 mt7915_tx_token_put(dev);
1670 idr_init(&dev->mt76.token);
1671
1672 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT);
1673 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE);
1674 }
1675
1676 clear_bit(MT76_MCU_RESET, &dev->mphy.state);
1677 clear_bit(MT76_RESET, &dev->mphy.state);
1678 if (phy2)
1679 clear_bit(MT76_RESET, &phy2->mt76->state);
1680
1681 napi_enable(&dev->mt76.napi[0]);
1682 napi_schedule(&dev->mt76.napi[0]);
1683
1684 napi_enable(&dev->mt76.napi[1]);
1685 napi_schedule(&dev->mt76.napi[1]);
1686
1687 napi_enable(&dev->mt76.napi[2]);
1688 napi_schedule(&dev->mt76.napi[2]);
1689 tasklet_schedule(&dev->irq_tasklet);
1690
1691 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE);
1692 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE);
1693
1694 mt76_worker_enable(&dev->mt76.tx_worker);
1695
1696 napi_enable(&dev->mt76.tx_napi);
1697 napi_schedule(&dev->mt76.tx_napi);
1698
1699 ieee80211_wake_queues(mt76_hw(dev));
1700 if (ext_phy)
1701 ieee80211_wake_queues(ext_phy->hw);
1702
1703 mutex_unlock(&dev->mt76.mutex);
1704
1705 mt7915_update_beacons(dev);
1706
1707 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1708 MT7915_WATCHDOG_TIME);
1709 if (phy2)
1710 ieee80211_queue_delayed_work(ext_phy->hw,
1711 &phy2->mt76->mac_work,
1712 MT7915_WATCHDOG_TIME);
1713 }
1714
1715 static void
mt7915_mac_update_stats(struct mt7915_phy * phy)1716 mt7915_mac_update_stats(struct mt7915_phy *phy)
1717 {
1718 struct mt7915_dev *dev = phy->dev;
1719 struct mib_stats *mib = &phy->mib;
1720 bool ext_phy = phy != &dev->phy;
1721 int i, aggr0, aggr1;
1722
1723 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
1724 MT_MIB_SDR3_FCS_ERR_MASK);
1725
1726 aggr0 = ext_phy ? ARRAY_SIZE(dev->mt76.aggr_stats) / 2 : 0;
1727 for (i = 0, aggr1 = aggr0 + 4; i < 4; i++) {
1728 u32 val;
1729
1730 val = mt76_rr(dev, MT_MIB_MB_SDR1(ext_phy, i));
1731 mib->ba_miss_cnt += FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val);
1732 mib->ack_fail_cnt +=
1733 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val);
1734
1735 val = mt76_rr(dev, MT_MIB_MB_SDR0(ext_phy, i));
1736 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val);
1737 mib->rts_retries_cnt +=
1738 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val);
1739
1740 val = mt76_rr(dev, MT_TX_AGG_CNT(ext_phy, i));
1741 dev->mt76.aggr_stats[aggr0++] += val & 0xffff;
1742 dev->mt76.aggr_stats[aggr0++] += val >> 16;
1743
1744 val = mt76_rr(dev, MT_TX_AGG_CNT2(ext_phy, i));
1745 dev->mt76.aggr_stats[aggr1++] += val & 0xffff;
1746 dev->mt76.aggr_stats[aggr1++] += val >> 16;
1747 }
1748 }
1749
1750 static void
mt7915_mac_sta_stats_work(struct mt7915_phy * phy)1751 mt7915_mac_sta_stats_work(struct mt7915_phy *phy)
1752 {
1753 struct mt7915_dev *dev = phy->dev;
1754 struct mt7915_sta *msta;
1755 LIST_HEAD(list);
1756
1757 spin_lock_bh(&dev->sta_poll_lock);
1758 list_splice_init(&phy->stats_list, &list);
1759
1760 while (!list_empty(&list)) {
1761 msta = list_first_entry(&list, struct mt7915_sta, stats_list);
1762 list_del_init(&msta->stats_list);
1763 spin_unlock_bh(&dev->sta_poll_lock);
1764
1765 /* use MT_TX_FREE_RATE to report Tx rate for further devices */
1766 mt7915_mcu_get_tx_rate(dev, RATE_CTRL_RU_INFO, msta->wcid.idx);
1767
1768 spin_lock_bh(&dev->sta_poll_lock);
1769 }
1770
1771 spin_unlock_bh(&dev->sta_poll_lock);
1772 }
1773
mt7915_mac_sta_rc_work(struct work_struct * work)1774 void mt7915_mac_sta_rc_work(struct work_struct *work)
1775 {
1776 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work);
1777 struct ieee80211_sta *sta;
1778 struct ieee80211_vif *vif;
1779 struct mt7915_sta *msta;
1780 u32 changed;
1781 LIST_HEAD(list);
1782
1783 spin_lock_bh(&dev->sta_poll_lock);
1784 list_splice_init(&dev->sta_rc_list, &list);
1785
1786 while (!list_empty(&list)) {
1787 msta = list_first_entry(&list, struct mt7915_sta, rc_list);
1788 list_del_init(&msta->rc_list);
1789 changed = msta->stats.changed;
1790 msta->stats.changed = 0;
1791 spin_unlock_bh(&dev->sta_poll_lock);
1792
1793 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
1794 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv);
1795
1796 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED |
1797 IEEE80211_RC_NSS_CHANGED |
1798 IEEE80211_RC_BW_CHANGED)) {
1799 mt7915_mcu_add_he(dev, vif, sta);
1800 mt7915_mcu_add_rate_ctrl(dev, vif, sta);
1801 }
1802
1803 if (changed & IEEE80211_RC_SMPS_CHANGED)
1804 mt7915_mcu_add_smps(dev, vif, sta);
1805
1806 spin_lock_bh(&dev->sta_poll_lock);
1807 }
1808
1809 spin_unlock_bh(&dev->sta_poll_lock);
1810 }
1811
mt7915_mac_work(struct work_struct * work)1812 void mt7915_mac_work(struct work_struct *work)
1813 {
1814 struct mt7915_phy *phy;
1815 struct mt76_phy *mphy;
1816
1817 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
1818 mac_work.work);
1819 phy = mphy->priv;
1820
1821 mutex_lock(&mphy->dev->mutex);
1822
1823 mt76_update_survey(mphy);
1824 if (++mphy->mac_work_count == 5) {
1825 mphy->mac_work_count = 0;
1826
1827 mt7915_mac_update_stats(phy);
1828 }
1829
1830 if (++phy->sta_work_count == 10) {
1831 phy->sta_work_count = 0;
1832 mt7915_mac_sta_stats_work(phy);
1833 }
1834
1835 mutex_unlock(&mphy->dev->mutex);
1836
1837 mt76_tx_status_check(mphy->dev, NULL, false);
1838
1839 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
1840 MT7915_WATCHDOG_TIME);
1841 }
1842
mt7915_dfs_stop_radar_detector(struct mt7915_phy * phy)1843 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy)
1844 {
1845 struct mt7915_dev *dev = phy->dev;
1846
1847 if (phy->rdd_state & BIT(0))
1848 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 0, MT_RX_SEL0, 0);
1849 if (phy->rdd_state & BIT(1))
1850 mt7915_mcu_rdd_cmd(dev, RDD_STOP, 1, MT_RX_SEL0, 0);
1851 }
1852
mt7915_dfs_start_rdd(struct mt7915_dev * dev,int chain)1853 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain)
1854 {
1855 int err;
1856
1857 err = mt7915_mcu_rdd_cmd(dev, RDD_START, chain, MT_RX_SEL0, 0);
1858 if (err < 0)
1859 return err;
1860
1861 return mt7915_mcu_rdd_cmd(dev, RDD_DET_MODE, chain, MT_RX_SEL0, 1);
1862 }
1863
mt7915_dfs_start_radar_detector(struct mt7915_phy * phy)1864 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy)
1865 {
1866 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1867 struct mt7915_dev *dev = phy->dev;
1868 bool ext_phy = phy != &dev->phy;
1869 int err;
1870
1871 /* start CAC */
1872 err = mt7915_mcu_rdd_cmd(dev, RDD_CAC_START, ext_phy, MT_RX_SEL0, 0);
1873 if (err < 0)
1874 return err;
1875
1876 err = mt7915_dfs_start_rdd(dev, ext_phy);
1877 if (err < 0)
1878 return err;
1879
1880 phy->rdd_state |= BIT(ext_phy);
1881
1882 if (chandef->width == NL80211_CHAN_WIDTH_160 ||
1883 chandef->width == NL80211_CHAN_WIDTH_80P80) {
1884 err = mt7915_dfs_start_rdd(dev, 1);
1885 if (err < 0)
1886 return err;
1887
1888 phy->rdd_state |= BIT(1);
1889 }
1890
1891 return 0;
1892 }
1893
1894 static int
mt7915_dfs_init_radar_specs(struct mt7915_phy * phy)1895 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy)
1896 {
1897 const struct mt7915_dfs_radar_spec *radar_specs;
1898 struct mt7915_dev *dev = phy->dev;
1899 int err, i;
1900
1901 switch (dev->mt76.region) {
1902 case NL80211_DFS_FCC:
1903 radar_specs = &fcc_radar_specs;
1904 err = mt7915_mcu_set_fcc5_lpn(dev, 8);
1905 if (err < 0)
1906 return err;
1907 break;
1908 case NL80211_DFS_ETSI:
1909 radar_specs = &etsi_radar_specs;
1910 break;
1911 case NL80211_DFS_JP:
1912 radar_specs = &jp_radar_specs;
1913 break;
1914 default:
1915 return -EINVAL;
1916 }
1917
1918 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
1919 err = mt7915_mcu_set_radar_th(dev, i,
1920 &radar_specs->radar_pattern[i]);
1921 if (err < 0)
1922 return err;
1923 }
1924
1925 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
1926 }
1927
mt7915_dfs_init_radar_detector(struct mt7915_phy * phy)1928 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy)
1929 {
1930 struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
1931 struct mt7915_dev *dev = phy->dev;
1932 bool ext_phy = phy != &dev->phy;
1933 int err;
1934
1935 if (dev->mt76.region == NL80211_DFS_UNSET) {
1936 phy->dfs_state = -1;
1937 if (phy->rdd_state)
1938 goto stop;
1939
1940 return 0;
1941 }
1942
1943 if (test_bit(MT76_SCANNING, &phy->mt76->state))
1944 return 0;
1945
1946 if (phy->dfs_state == chandef->chan->dfs_state)
1947 return 0;
1948
1949 err = mt7915_dfs_init_radar_specs(phy);
1950 if (err < 0) {
1951 phy->dfs_state = -1;
1952 goto stop;
1953 }
1954
1955 phy->dfs_state = chandef->chan->dfs_state;
1956
1957 if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
1958 if (chandef->chan->dfs_state != NL80211_DFS_AVAILABLE)
1959 return mt7915_dfs_start_radar_detector(phy);
1960
1961 return mt7915_mcu_rdd_cmd(dev, RDD_CAC_END, ext_phy,
1962 MT_RX_SEL0, 0);
1963 }
1964
1965 stop:
1966 err = mt7915_mcu_rdd_cmd(dev, RDD_NORMAL_START, ext_phy,
1967 MT_RX_SEL0, 0);
1968 if (err < 0)
1969 return err;
1970
1971 mt7915_dfs_stop_radar_detector(phy);
1972 return 0;
1973 }
1974