1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #include "mt7921.h"
5 #include "../dma.h"
6 #include "mac.h"
7
mt7921_init_tx_queues(struct mt7921_phy * phy,int idx,int n_desc)8 int mt7921_init_tx_queues(struct mt7921_phy *phy, int idx, int n_desc)
9 {
10 int i, err;
11
12 err = mt76_init_tx_queue(phy->mt76, 0, idx, n_desc, MT_TX_RING_BASE);
13 if (err < 0)
14 return err;
15
16 for (i = 0; i <= MT_TXQ_PSD; i++)
17 phy->mt76->q_tx[i] = phy->mt76->q_tx[0];
18
19 return 0;
20 }
21
mt7921_queue_rx_skb(struct mt76_dev * mdev,enum mt76_rxq_id q,struct sk_buff * skb)22 void mt7921_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
23 struct sk_buff *skb)
24 {
25 struct mt7921_dev *dev = container_of(mdev, struct mt7921_dev, mt76);
26 __le32 *rxd = (__le32 *)skb->data;
27 enum rx_pkt_type type;
28 u16 flag;
29
30 type = FIELD_GET(MT_RXD0_PKT_TYPE, le32_to_cpu(rxd[0]));
31 flag = FIELD_GET(MT_RXD0_PKT_FLAG, le32_to_cpu(rxd[0]));
32
33 if (type == PKT_TYPE_RX_EVENT && flag == 0x1)
34 type = PKT_TYPE_NORMAL_MCU;
35
36 switch (type) {
37 case PKT_TYPE_TXRX_NOTIFY:
38 mt7921_mac_tx_free(dev, skb);
39 break;
40 case PKT_TYPE_RX_EVENT:
41 mt7921_mcu_rx_event(dev, skb);
42 break;
43 case PKT_TYPE_NORMAL_MCU:
44 case PKT_TYPE_NORMAL:
45 if (!mt7921_mac_fill_rx(dev, skb)) {
46 mt76_rx(&dev->mt76, q, skb);
47 return;
48 }
49 fallthrough;
50 default:
51 dev_kfree_skb(skb);
52 break;
53 }
54 }
55
mt7921_tx_cleanup(struct mt7921_dev * dev)56 void mt7921_tx_cleanup(struct mt7921_dev *dev)
57 {
58 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], false);
59 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WA], false);
60 }
61
mt7921_poll_tx(struct napi_struct * napi,int budget)62 static int mt7921_poll_tx(struct napi_struct *napi, int budget)
63 {
64 struct mt7921_dev *dev;
65
66 dev = container_of(napi, struct mt7921_dev, mt76.tx_napi);
67
68 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
69 napi_complete(napi);
70 queue_work(dev->mt76.wq, &dev->pm.wake_work);
71 return 0;
72 }
73
74 mt7921_tx_cleanup(dev);
75 if (napi_complete(napi))
76 mt7921_irq_enable(dev, MT_INT_TX_DONE_ALL);
77 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
78
79 return 0;
80 }
81
mt7921_poll_rx(struct napi_struct * napi,int budget)82 static int mt7921_poll_rx(struct napi_struct *napi, int budget)
83 {
84 struct mt7921_dev *dev;
85 int done;
86
87 dev = container_of(napi->dev, struct mt7921_dev, mt76.napi_dev);
88
89 if (!mt76_connac_pm_ref(&dev->mphy, &dev->pm)) {
90 napi_complete(napi);
91 queue_work(dev->mt76.wq, &dev->pm.wake_work);
92 return 0;
93 }
94 done = mt76_dma_rx_poll(napi, budget);
95 mt76_connac_pm_unref(&dev->mphy, &dev->pm);
96
97 return done;
98 }
99
mt7921_dma_prefetch(struct mt7921_dev * dev)100 static void mt7921_dma_prefetch(struct mt7921_dev *dev)
101 {
102 #define PREFETCH(base, depth) ((base) << 16 | (depth))
103
104 mt76_wr(dev, MT_WFDMA0_RX_RING0_EXT_CTRL, PREFETCH(0x0, 0x4));
105 mt76_wr(dev, MT_WFDMA0_RX_RING2_EXT_CTRL, PREFETCH(0x40, 0x4));
106 mt76_wr(dev, MT_WFDMA0_RX_RING3_EXT_CTRL, PREFETCH(0x80, 0x4));
107 mt76_wr(dev, MT_WFDMA0_RX_RING4_EXT_CTRL, PREFETCH(0xc0, 0x4));
108 mt76_wr(dev, MT_WFDMA0_RX_RING5_EXT_CTRL, PREFETCH(0x100, 0x4));
109
110 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, PREFETCH(0x140, 0x4));
111 mt76_wr(dev, MT_WFDMA0_TX_RING1_EXT_CTRL, PREFETCH(0x180, 0x4));
112 mt76_wr(dev, MT_WFDMA0_TX_RING2_EXT_CTRL, PREFETCH(0x1c0, 0x4));
113 mt76_wr(dev, MT_WFDMA0_TX_RING3_EXT_CTRL, PREFETCH(0x200, 0x4));
114 mt76_wr(dev, MT_WFDMA0_TX_RING4_EXT_CTRL, PREFETCH(0x240, 0x4));
115 mt76_wr(dev, MT_WFDMA0_TX_RING5_EXT_CTRL, PREFETCH(0x280, 0x4));
116 mt76_wr(dev, MT_WFDMA0_TX_RING6_EXT_CTRL, PREFETCH(0x2c0, 0x4));
117 mt76_wr(dev, MT_WFDMA0_TX_RING16_EXT_CTRL, PREFETCH(0x340, 0x4));
118 mt76_wr(dev, MT_WFDMA0_TX_RING17_EXT_CTRL, PREFETCH(0x380, 0x4));
119 }
120
mt7921_dma_disable(struct mt7921_dev * dev,bool force)121 static int mt7921_dma_disable(struct mt7921_dev *dev, bool force)
122 {
123 /* disable WFDMA0 */
124 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
125 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN |
126 MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
127 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
128 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
129 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
130
131 if (!mt76_poll_msec_tick(dev, MT_WFDMA0_GLO_CFG,
132 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
133 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 100, 1))
134 return -ETIMEDOUT;
135
136 /* disable dmashdl */
137 mt76_clear(dev, MT_WFDMA0_GLO_CFG_EXT0,
138 MT_WFDMA0_CSR_TX_DMASHDL_ENABLE);
139 mt76_set(dev, MT_DMASHDL_SW_CONTROL, MT_DMASHDL_DMASHDL_BYPASS);
140
141 if (force) {
142 /* reset */
143 mt76_clear(dev, MT_WFDMA0_RST,
144 MT_WFDMA0_RST_DMASHDL_ALL_RST |
145 MT_WFDMA0_RST_LOGIC_RST);
146
147 mt76_set(dev, MT_WFDMA0_RST,
148 MT_WFDMA0_RST_DMASHDL_ALL_RST |
149 MT_WFDMA0_RST_LOGIC_RST);
150 }
151
152 return 0;
153 }
154
mt7921_dma_enable(struct mt7921_dev * dev)155 static int mt7921_dma_enable(struct mt7921_dev *dev)
156 {
157 /* configure perfetch settings */
158 mt7921_dma_prefetch(dev);
159
160 /* reset dma idx */
161 mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR, ~0);
162
163 /* configure delay interrupt */
164 mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0, 0);
165
166 mt76_set(dev, MT_WFDMA0_GLO_CFG,
167 MT_WFDMA0_GLO_CFG_TX_WB_DDONE |
168 MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN |
169 MT_WFDMA0_GLO_CFG_CLK_GAT_DIS |
170 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
171 MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
172 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
173
174 mt76_set(dev, MT_WFDMA0_GLO_CFG,
175 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
176
177 mt76_set(dev, MT_WFDMA_DUMMY_CR, MT_WFDMA_NEED_REINIT);
178
179 /* enable interrupts for TX/RX rings */
180 mt7921_irq_enable(dev,
181 MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
182 MT_INT_MCU_CMD);
183 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
184
185 return 0;
186 }
187
mt7921_dma_reset(struct mt7921_dev * dev,bool force)188 static int mt7921_dma_reset(struct mt7921_dev *dev, bool force)
189 {
190 int i, err;
191
192 err = mt7921_dma_disable(dev, force);
193 if (err)
194 return err;
195
196 /* reset hw queues */
197 for (i = 0; i < __MT_TXQ_MAX; i++)
198 mt76_queue_reset(dev, dev->mphy.q_tx[i]);
199
200 for (i = 0; i < __MT_MCUQ_MAX; i++)
201 mt76_queue_reset(dev, dev->mt76.q_mcu[i]);
202
203 mt76_for_each_q_rx(&dev->mt76, i)
204 mt76_queue_reset(dev, &dev->mt76.q_rx[i]);
205
206 mt76_tx_status_check(&dev->mt76, NULL, true);
207
208 return mt7921_dma_enable(dev);
209 }
210
mt7921_wfsys_reset(struct mt7921_dev * dev)211 int mt7921_wfsys_reset(struct mt7921_dev *dev)
212 {
213 mt76_clear(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
214 msleep(50);
215 mt76_set(dev, MT_WFSYS_SW_RST_B, WFSYS_SW_RST_B);
216
217 if (!__mt76_poll_msec(&dev->mt76, MT_WFSYS_SW_RST_B,
218 WFSYS_SW_INIT_DONE, WFSYS_SW_INIT_DONE, 500))
219 return -ETIMEDOUT;
220
221 return 0;
222 }
223
mt7921_wpdma_reset(struct mt7921_dev * dev,bool force)224 int mt7921_wpdma_reset(struct mt7921_dev *dev, bool force)
225 {
226 int i, err;
227
228 /* clean up hw queues */
229 for (i = 0; i < ARRAY_SIZE(dev->mt76.phy.q_tx); i++)
230 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
231
232 for (i = 0; i < ARRAY_SIZE(dev->mt76.q_mcu); i++)
233 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[i], true);
234
235 mt76_for_each_q_rx(&dev->mt76, i)
236 mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]);
237
238 if (force) {
239 err = mt7921_wfsys_reset(dev);
240 if (err)
241 return err;
242 }
243 err = mt7921_dma_reset(dev, force);
244 if (err)
245 return err;
246
247 mt76_for_each_q_rx(&dev->mt76, i)
248 mt76_queue_rx_reset(dev, i);
249
250 return 0;
251 }
252
mt7921_wpdma_reinit_cond(struct mt7921_dev * dev)253 int mt7921_wpdma_reinit_cond(struct mt7921_dev *dev)
254 {
255 struct mt76_connac_pm *pm = &dev->pm;
256 int err;
257
258 /* check if the wpdma must be reinitialized */
259 if (mt7921_dma_need_reinit(dev)) {
260 /* disable interrutpts */
261 mt76_wr(dev, MT_WFDMA0_HOST_INT_ENA, 0);
262 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
263
264 err = mt7921_wpdma_reset(dev, false);
265 if (err) {
266 dev_err(dev->mt76.dev, "wpdma reset failed\n");
267 return err;
268 }
269
270 /* enable interrutpts */
271 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
272 pm->stats.lp_wake++;
273 }
274
275 return 0;
276 }
277
mt7921_dma_init(struct mt7921_dev * dev)278 int mt7921_dma_init(struct mt7921_dev *dev)
279 {
280 int ret;
281
282 mt76_dma_attach(&dev->mt76);
283
284 ret = mt7921_dma_disable(dev, true);
285 if (ret)
286 return ret;
287
288 ret = mt7921_wfsys_reset(dev);
289 if (ret)
290 return ret;
291
292 /* init tx queue */
293 ret = mt7921_init_tx_queues(&dev->phy, MT7921_TXQ_BAND0,
294 MT7921_TX_RING_SIZE);
295 if (ret)
296 return ret;
297
298 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
299
300 /* command to WM */
301 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
302 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
303 if (ret)
304 return ret;
305
306 /* firmware download */
307 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
308 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
309 if (ret)
310 return ret;
311
312 /* event from WM before firmware download */
313 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
314 MT7921_RXQ_MCU_WM,
315 MT7921_RX_MCU_RING_SIZE,
316 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
317 if (ret)
318 return ret;
319
320 /* Change mcu queue after firmware download */
321 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
322 MT7921_RXQ_MCU_WM,
323 MT7921_RX_MCU_RING_SIZE,
324 MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
325 if (ret)
326 return ret;
327
328 /* rx data */
329 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
330 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
331 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
332 if (ret)
333 return ret;
334
335 ret = mt76_init_queues(dev, mt7921_poll_rx);
336 if (ret < 0)
337 return ret;
338
339 netif_tx_napi_add(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
340 mt7921_poll_tx, NAPI_POLL_WEIGHT);
341 napi_enable(&dev->mt76.tx_napi);
342
343 return mt7921_dma_enable(dev);
344 }
345
mt7921_dma_cleanup(struct mt7921_dev * dev)346 void mt7921_dma_cleanup(struct mt7921_dev *dev)
347 {
348 /* disable */
349 mt76_clear(dev, MT_WFDMA0_GLO_CFG,
350 MT_WFDMA0_GLO_CFG_TX_DMA_EN |
351 MT_WFDMA0_GLO_CFG_RX_DMA_EN |
352 MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN |
353 MT_WFDMA0_GLO_CFG_OMIT_TX_INFO |
354 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO |
355 MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2);
356
357 mt76_poll_msec_tick(dev, MT_WFDMA0_GLO_CFG,
358 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
359 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 100, 1);
360
361 /* reset */
362 mt76_clear(dev, MT_WFDMA0_RST,
363 MT_WFDMA0_RST_DMASHDL_ALL_RST |
364 MT_WFDMA0_RST_LOGIC_RST);
365
366 mt76_set(dev, MT_WFDMA0_RST,
367 MT_WFDMA0_RST_DMASHDL_ALL_RST |
368 MT_WFDMA0_RST_LOGIC_RST);
369
370 mt76_dma_cleanup(&dev->mt76);
371 }
372