1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT7921_MAC_H
5 #define __MT7921_MAC_H
6
7 #define MT_CT_PARSE_LEN 72
8 #define MT_CT_DMA_BUF_NUM 2
9
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
13
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17
18 enum rx_pkt_type {
19 PKT_TYPE_TXS,
20 PKT_TYPE_TXRXV,
21 PKT_TYPE_NORMAL,
22 PKT_TYPE_RX_DUP_RFB,
23 PKT_TYPE_RX_TMR,
24 PKT_TYPE_RETRIEVE,
25 PKT_TYPE_TXRX_NOTIFY,
26 PKT_TYPE_RX_EVENT,
27 PKT_TYPE_NORMAL_MCU,
28 };
29
30 /* RXD DW1 */
31 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
32 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
33 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
34 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
35 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
36 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
38 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
39 #define MT_RXD1_NORMAL_CM BIT(23)
40 #define MT_RXD1_NORMAL_CLM BIT(24)
41 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
42 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
43 #define MT_RXD1_NORMAL_FCS_ERR BIT(27)
44 #define MT_RXD1_NORMAL_BAND_IDX BIT(28)
45 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
46 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
47 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
48
49 /* RXD DW2 */
50 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
51 #define MT_RXD2_NORMAL_CO_ANT BIT(6)
52 #define MT_RXD2_NORMAL_BF_CQI BIT(7)
53 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
54 #define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
55 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
56 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
57 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
58 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
59 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
60 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
61 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
62 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
63 #define MT_RXD2_NORMAL_FRAG BIT(27)
64 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
65 #define MT_RXD2_NORMAL_NDATA BIT(29)
66 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
67 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
68
69 /* RXD DW3 */
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
71 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
72 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
73 #define MT_RXD3_NORMAL_U2M BIT(0)
74 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
75 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
76 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
77 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
78 #define MT_RXD3_NORMAL_AMSDU BIT(22)
79 #define MT_RXD3_NORMAL_MESH BIT(23)
80 #define MT_RXD3_NORMAL_MHCP BIT(24)
81 #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
82 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
83 #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
84 #define MT_RXD3_NORMAL_MORE BIT(28)
85 #define MT_RXD3_NORMAL_UNWANT BIT(29)
86 #define MT_RXD3_NORMAL_RX_DROP BIT(30)
87 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
88
89 /* RXD DW4 */
90 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
91 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
92 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
93 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
94 #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
95 #define MT_RXD4_NORMAL_CLS BIT(10)
96 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
97 #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
98 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
99 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
100 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
101 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
102
103 /* RXD GROUP4 */
104 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
105 #define MT_RXD6_TA_LO GENMASK(31, 16)
106
107 #define MT_RXD7_TA_HI GENMASK(31, 0)
108
109 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
110 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
111
112 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
113
114 /* P-RXV DW0 */
115 #define MT_PRXV_TX_RATE GENMASK(6, 0)
116 #define MT_PRXV_TX_DCM BIT(4)
117 #define MT_PRXV_TX_ER_SU_106T BIT(5)
118 #define MT_PRXV_NSTS GENMASK(9, 7)
119 #define MT_PRXV_TXBF BIT(10)
120 #define MT_PRXV_HT_AD_CODE BIT(11)
121 #define MT_PRXV_FRAME_MODE GENMASK(14, 12)
122 #define MT_PRXV_SGI GENMASK(16, 15)
123 #define MT_PRXV_STBC GENMASK(23, 22)
124 #define MT_PRXV_TX_MODE GENMASK(27, 24)
125 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
126
127 /* P-RXV DW1 */
128 #define MT_PRXV_RCPI3 GENMASK(31, 24)
129 #define MT_PRXV_RCPI2 GENMASK(23, 16)
130 #define MT_PRXV_RCPI1 GENMASK(15, 8)
131 #define MT_PRXV_RCPI0 GENMASK(7, 0)
132 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
133
134 /* C-RXV */
135 #define MT_CRXV_HT_STBC GENMASK(1, 0)
136 #define MT_CRXV_TX_MODE GENMASK(7, 4)
137 #define MT_CRXV_FRAME_MODE GENMASK(10, 8)
138 #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
139 #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
140 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
141 #define MT_CRXV_HE_PE_DISAMBIG BIT(23)
142 #define MT_CRXV_HE_NUM_USER GENMASK(30, 24)
143 #define MT_CRXV_HE_UPLINK BIT(31)
144
145 #define MT_CRXV_HE_RU0 GENMASK(7, 0)
146 #define MT_CRXV_HE_RU1 GENMASK(15, 8)
147 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
148 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
149 #define MT_CRXV_HE_MU_AID GENMASK(30, 20)
150
151 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
152 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
153 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
154 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
155
156 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
157 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
158 #define MT_CRXV_HE_BEAM_CHNG BIT(13)
159 #define MT_CRXV_HE_DOPPLER BIT(16)
160
161 #define MT_CRXV_SNR GENMASK(18, 13)
162 #define MT_CRXV_FOE_LO GENMASK(31, 19)
163 #define MT_CRXV_FOE_HI GENMASK(6, 0)
164 #define MT_CRXV_FOE_SHIFT 13
165
166 enum tx_header_format {
167 MT_HDR_FORMAT_802_3,
168 MT_HDR_FORMAT_CMD,
169 MT_HDR_FORMAT_802_11,
170 MT_HDR_FORMAT_802_11_EXT,
171 };
172
173 enum tx_pkt_type {
174 MT_TX_TYPE_CT,
175 MT_TX_TYPE_SF,
176 MT_TX_TYPE_CMD,
177 MT_TX_TYPE_FW,
178 };
179
180 enum tx_port_idx {
181 MT_TX_PORT_IDX_LMAC,
182 MT_TX_PORT_IDX_MCU
183 };
184
185 enum tx_mcu_port_q_idx {
186 MT_TX_MCU_PORT_RX_Q0 = 0x20,
187 MT_TX_MCU_PORT_RX_Q1,
188 MT_TX_MCU_PORT_RX_Q2,
189 MT_TX_MCU_PORT_RX_Q3,
190 MT_TX_MCU_PORT_RX_FWDL = 0x3e
191 };
192
193 #define MT_CT_INFO_APPLY_TXD BIT(0)
194 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
195 #define MT_CT_INFO_MGMT_FRAME BIT(2)
196 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
197 #define MT_CT_INFO_HSR2_TX BIT(4)
198 #define MT_CT_INFO_FROM_HOST BIT(7)
199
200 #define MT_TXD_SIZE (8 * 4)
201
202 #define MT_TXD0_Q_IDX GENMASK(31, 25)
203 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
204 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
205 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
206
207 #define MT_TXD1_LONG_FORMAT BIT(31)
208 #define MT_TXD1_TGID BIT(30)
209 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
210 #define MT_TXD1_AMSDU BIT(23)
211 #define MT_TXD1_TID GENMASK(22, 20)
212 #define MT_TXD1_HDR_PAD GENMASK(19, 18)
213 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
214 #define MT_TXD1_HDR_INFO GENMASK(15, 11)
215 #define MT_TXD1_ETH_802_3 BIT(15)
216 #define MT_TXD1_VTA BIT(10)
217 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
218
219 #define MT_TXD2_FIX_RATE BIT(31)
220 #define MT_TXD2_FIXED_RATE BIT(30)
221 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
222 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
223 #define MT_TXD2_FRAG GENMASK(15, 14)
224 #define MT_TXD2_HTC_VLD BIT(13)
225 #define MT_TXD2_DURATION BIT(12)
226 #define MT_TXD2_BIP BIT(11)
227 #define MT_TXD2_MULTICAST BIT(10)
228 #define MT_TXD2_RTS BIT(9)
229 #define MT_TXD2_SOUNDING BIT(8)
230 #define MT_TXD2_NDPA BIT(7)
231 #define MT_TXD2_NDP BIT(6)
232 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
233 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
234
235 #define MT_TXD3_SN_VALID BIT(31)
236 #define MT_TXD3_PN_VALID BIT(30)
237 #define MT_TXD3_SW_POWER_MGMT BIT(29)
238 #define MT_TXD3_BA_DISABLE BIT(28)
239 #define MT_TXD3_SEQ GENMASK(27, 16)
240 #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
241 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
242 #define MT_TXD3_TIMING_MEASURE BIT(5)
243 #define MT_TXD3_DAS BIT(4)
244 #define MT_TXD3_EEOSP BIT(3)
245 #define MT_TXD3_EMRD BIT(2)
246 #define MT_TXD3_PROTECT_FRAME BIT(1)
247 #define MT_TXD3_NO_ACK BIT(0)
248
249 #define MT_TXD4_PN_LOW GENMASK(31, 0)
250
251 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
252 #define MT_TXD5_MD BIT(15)
253 #define MT_TXD5_ADD_BA BIT(14)
254 #define MT_TXD5_TX_STATUS_HOST BIT(10)
255 #define MT_TXD5_TX_STATUS_MCU BIT(9)
256 #define MT_TXD5_TX_STATUS_FMT BIT(8)
257 #define MT_TXD5_PID GENMASK(7, 0)
258
259 #define MT_TXD6_TX_IBF BIT(31)
260 #define MT_TXD6_TX_EBF BIT(30)
261 #define MT_TXD6_TX_RATE GENMASK(29, 16)
262 #define MT_TXD6_SGI GENMASK(15, 14)
263 #define MT_TXD6_HELTF GENMASK(13, 12)
264 #define MT_TXD6_LDPC BIT(11)
265 #define MT_TXD6_SPE_ID_IDX BIT(10)
266 #define MT_TXD6_ANT_ID GENMASK(7, 4)
267 #define MT_TXD6_DYN_BW BIT(3)
268 #define MT_TXD6_FIXED_BW BIT(2)
269 #define MT_TXD6_BW GENMASK(1, 0)
270
271 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
272 #define MT_TXD7_UDP_TCP_SUM BIT(29)
273 #define MT_TXD7_IP_SUM BIT(28)
274
275 #define MT_TXD7_TYPE GENMASK(21, 20)
276 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
277
278 #define MT_TXD7_PSE_FID GENMASK(27, 16)
279 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
280 #define MT_TXD7_HW_AMSDU BIT(10)
281 #define MT_TXD7_TX_TIME GENMASK(9, 0)
282
283 #define MT_TX_RATE_STBC BIT(13)
284 #define MT_TX_RATE_NSS GENMASK(12, 10)
285 #define MT_TX_RATE_MODE GENMASK(9, 6)
286 #define MT_TX_RATE_SU_EXT_TONE BIT(5)
287 #define MT_TX_RATE_DCM BIT(4)
288 #define MT_TX_RATE_IDX GENMASK(3, 0)
289
290 #define MT_TXP_MAX_BUF_NUM 6
291
292 struct mt7921_txp {
293 __le16 flags;
294 __le16 token;
295 u8 bss_idx;
296 __le16 rept_wds_wcid;
297 u8 nbuf;
298 __le32 buf[MT_TXP_MAX_BUF_NUM];
299 __le16 len[MT_TXP_MAX_BUF_NUM];
300 } __packed __aligned(4);
301
302 struct mt7921_tx_free {
303 __le16 rx_byte_cnt;
304 __le16 ctrl;
305 u8 txd_cnt;
306 u8 rsv[3];
307 __le32 info[];
308 } __packed __aligned(4);
309
310 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
311 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
312 #define MT_TX_FREE_LATENCY GENMASK(12, 0)
313 /* 0: success, others: dropped */
314 #define MT_TX_FREE_STATUS GENMASK(14, 13)
315 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
316 #define MT_TX_FREE_PAIR BIT(31)
317 /* will support this field in further revision */
318 #define MT_TX_FREE_RATE GENMASK(13, 0)
319
320 static inline struct mt7921_txp_common *
mt7921_txwi_to_txp(struct mt76_dev * dev,struct mt76_txwi_cache * t)321 mt7921_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
322 {
323 u8 *txwi;
324
325 if (!t)
326 return NULL;
327
328 txwi = mt76_get_txwi_ptr(dev, t);
329
330 return (struct mt7921_txp_common *)(txwi + MT_TXD_SIZE);
331 }
332
333 #define MT_HW_TXP_MAX_MSDU_NUM 4
334 #define MT_HW_TXP_MAX_BUF_NUM 4
335
336 #define MT_MSDU_ID_VALID BIT(15)
337
338 #define MT_TXD_LEN_MASK GENMASK(11, 0)
339 #define MT_TXD_LEN_MSDU_LAST BIT(14)
340 #define MT_TXD_LEN_AMSDU_LAST BIT(15)
341 #define MT_TXD_LEN_LAST BIT(15)
342
343 struct mt7921_txp_ptr {
344 __le32 buf0;
345 __le16 len0;
346 __le16 len1;
347 __le32 buf1;
348 } __packed __aligned(4);
349
350 struct mt7921_hw_txp {
351 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
352 struct mt7921_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
353 } __packed __aligned(4);
354
355 struct mt7921_txp_common {
356 union {
357 struct mt7921_hw_txp hw;
358 };
359 };
360
361 #endif
362