1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver - 8723a specific subdriver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/list.h>
24 #include <linux/usb.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/wireless.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31 #include <net/mac80211.h>
32 #include "rtl8xxxu.h"
33 #include "rtl8xxxu_regs.h"
34
35 static struct rtl8xxxu_power_base rtl8723a_power_base = {
36 .reg_0e00 = 0x0a0c0c0c,
37 .reg_0e04 = 0x02040608,
38 .reg_0e08 = 0x00000000,
39 .reg_086c = 0x00000000,
40
41 .reg_0e10 = 0x0a0c0d0e,
42 .reg_0e14 = 0x02040608,
43 .reg_0e18 = 0x0a0c0d0e,
44 .reg_0e1c = 0x02040608,
45
46 .reg_0830 = 0x0a0c0c0c,
47 .reg_0834 = 0x02040608,
48 .reg_0838 = 0x00000000,
49 .reg_086c_2 = 0x00000000,
50
51 .reg_083c = 0x0a0c0d0e,
52 .reg_0848 = 0x02040608,
53 .reg_084c = 0x0a0c0d0e,
54 .reg_0868 = 0x02040608,
55 };
56
57 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
58 {0x00, 0x00030159}, {0x01, 0x00031284},
59 {0x02, 0x00098000}, {0x03, 0x00039c63},
60 {0x04, 0x000210e7}, {0x09, 0x0002044f},
61 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
62 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
63 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
64 {0x19, 0x00000000}, {0x1a, 0x00030355},
65 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
66 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
67 {0x1f, 0x00000000}, {0x20, 0x0000b614},
68 {0x21, 0x0006c000}, {0x22, 0x00000000},
69 {0x23, 0x00001558}, {0x24, 0x00000060},
70 {0x25, 0x00000483}, {0x26, 0x0004f000},
71 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
72 {0x29, 0x00004783}, {0x2a, 0x00000001},
73 {0x2b, 0x00021334}, {0x2a, 0x00000000},
74 {0x2b, 0x00000054}, {0x2a, 0x00000001},
75 {0x2b, 0x00000808}, {0x2b, 0x00053333},
76 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
77 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
78 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
79 {0x2b, 0x00000808}, {0x2b, 0x00063333},
80 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
81 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
82 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
83 {0x2b, 0x00000808}, {0x2b, 0x00073333},
84 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
85 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
86 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
87 {0x2b, 0x00000709}, {0x2b, 0x00063333},
88 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
89 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
90 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
91 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
92 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
93 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
94 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
95 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
96 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
97 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
98 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
99 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
100 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
101 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
102 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
103 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
104 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
105 {0x10, 0x0002000f}, {0x11, 0x000203f9},
106 {0x10, 0x0003000f}, {0x11, 0x000ff500},
107 {0x10, 0x00000000}, {0x11, 0x00000000},
108 {0x10, 0x0008000f}, {0x11, 0x0003f100},
109 {0x10, 0x0009000f}, {0x11, 0x00023100},
110 {0x12, 0x00032000}, {0x12, 0x00071000},
111 {0x12, 0x000b0000}, {0x12, 0x000fc000},
112 {0x13, 0x000287b3}, {0x13, 0x000244b7},
113 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
114 {0x13, 0x00018493}, {0x13, 0x0001429b},
115 {0x13, 0x00010299}, {0x13, 0x0000c29c},
116 {0x13, 0x000081a0}, {0x13, 0x000040ac},
117 {0x13, 0x00000020}, {0x14, 0x0001944c},
118 {0x14, 0x00059444}, {0x14, 0x0009944c},
119 {0x14, 0x000d9444}, {0x15, 0x0000f474},
120 {0x15, 0x0004f477}, {0x15, 0x0008f455},
121 {0x15, 0x000cf455}, {0x16, 0x00000339},
122 {0x16, 0x00040339}, {0x16, 0x00080339},
123 {0x16, 0x000c0366}, {0x00, 0x00010159},
124 {0x18, 0x0000f401}, {0xfe, 0x00000000},
125 {0xfe, 0x00000000}, {0x1f, 0x00000003},
126 {0xfe, 0x00000000}, {0xfe, 0x00000000},
127 {0x1e, 0x00000247}, {0x1f, 0x00000000},
128 {0x00, 0x00030159},
129 {0xff, 0xffffffff}
130 };
131
rtl8723au_parse_efuse(struct rtl8xxxu_priv * priv)132 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
133 {
134 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
135
136 if (efuse->rtl_id != cpu_to_le16(0x8129))
137 return -EINVAL;
138
139 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
140
141 memcpy(priv->cck_tx_power_index_A,
142 efuse->cck_tx_power_index_A,
143 sizeof(efuse->cck_tx_power_index_A));
144 memcpy(priv->cck_tx_power_index_B,
145 efuse->cck_tx_power_index_B,
146 sizeof(efuse->cck_tx_power_index_B));
147
148 memcpy(priv->ht40_1s_tx_power_index_A,
149 efuse->ht40_1s_tx_power_index_A,
150 sizeof(efuse->ht40_1s_tx_power_index_A));
151 memcpy(priv->ht40_1s_tx_power_index_B,
152 efuse->ht40_1s_tx_power_index_B,
153 sizeof(efuse->ht40_1s_tx_power_index_B));
154
155 memcpy(priv->ht20_tx_power_index_diff,
156 efuse->ht20_tx_power_index_diff,
157 sizeof(efuse->ht20_tx_power_index_diff));
158 memcpy(priv->ofdm_tx_power_index_diff,
159 efuse->ofdm_tx_power_index_diff,
160 sizeof(efuse->ofdm_tx_power_index_diff));
161
162 memcpy(priv->ht40_max_power_offset,
163 efuse->ht40_max_power_offset,
164 sizeof(efuse->ht40_max_power_offset));
165 memcpy(priv->ht20_max_power_offset,
166 efuse->ht20_max_power_offset,
167 sizeof(efuse->ht20_max_power_offset));
168
169 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
170 priv->has_xtalk = 1;
171 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
172 }
173
174 priv->power_base = &rtl8723a_power_base;
175
176 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
177 efuse->vendor_name);
178 dev_info(&priv->udev->dev, "Product: %.41s\n",
179 efuse->device_name);
180 return 0;
181 }
182
rtl8723au_load_firmware(struct rtl8xxxu_priv * priv)183 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
184 {
185 char *fw_name;
186 int ret;
187
188 switch (priv->chip_cut) {
189 case 0:
190 fw_name = "rtlwifi/rtl8723aufw_A.bin";
191 break;
192 case 1:
193 if (priv->enable_bluetooth)
194 fw_name = "rtlwifi/rtl8723aufw_B.bin";
195 else
196 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
197
198 break;
199 default:
200 return -EINVAL;
201 }
202
203 ret = rtl8xxxu_load_firmware(priv, fw_name);
204 return ret;
205 }
206
rtl8723au_init_phy_rf(struct rtl8xxxu_priv * priv)207 static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
208 {
209 int ret;
210
211 ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
212
213 /* Reduce 80M spur */
214 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
215 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
216 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
217 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
218
219 return ret;
220 }
221
rtl8723a_emu_to_active(struct rtl8xxxu_priv * priv)222 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
223 {
224 u8 val8;
225 u32 val32;
226 int count, ret = 0;
227
228 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
229 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
230 val8 |= LDOA15_ENABLE;
231 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
232
233 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
234 val8 = rtl8xxxu_read8(priv, 0x0067);
235 val8 &= ~BIT(4);
236 rtl8xxxu_write8(priv, 0x0067, val8);
237
238 mdelay(1);
239
240 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
241 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
242 val8 &= ~SYS_ISO_ANALOG_IPS;
243 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
244
245 /* disable SW LPS 0x04[10]= 0 */
246 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
247 val8 &= ~BIT(2);
248 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
249
250 /* wait till 0x04[17] = 1 power ready*/
251 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
252 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
253 if (val32 & BIT(17))
254 break;
255
256 udelay(10);
257 }
258
259 if (!count) {
260 ret = -EBUSY;
261 goto exit;
262 }
263
264 /* We should be able to optimize the following three entries into one */
265
266 /* release WLON reset 0x04[16]= 1*/
267 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
268 val8 |= BIT(0);
269 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
270
271 /* disable HWPDN 0x04[15]= 0*/
272 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
273 val8 &= ~BIT(7);
274 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
275
276 /* disable WL suspend*/
277 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
278 val8 &= ~(BIT(3) | BIT(4));
279 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
280
281 /* set, then poll until 0 */
282 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
283 val32 |= APS_FSMCO_MAC_ENABLE;
284 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
285
286 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
287 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
288 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
289 ret = 0;
290 break;
291 }
292 udelay(10);
293 }
294
295 if (!count) {
296 ret = -EBUSY;
297 goto exit;
298 }
299
300 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
301 /*
302 * Note: Vendor driver actually clears this bit, despite the
303 * documentation claims it's being set!
304 */
305 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
306 val8 |= LEDCFG2_DPDT_SELECT;
307 val8 &= ~LEDCFG2_DPDT_SELECT;
308 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
309
310 exit:
311 return ret;
312 }
313
rtl8723au_power_on(struct rtl8xxxu_priv * priv)314 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
315 {
316 u8 val8;
317 u16 val16;
318 u32 val32;
319 int ret;
320
321 /*
322 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
323 */
324 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
325
326 rtl8xxxu_disabled_to_emu(priv);
327
328 ret = rtl8723a_emu_to_active(priv);
329 if (ret)
330 goto exit;
331
332 /*
333 * 0x0004[19] = 1, reset 8051
334 */
335 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
336 val8 |= BIT(3);
337 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
338
339 /*
340 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
341 * Set CR bit10 to enable 32k calibration.
342 */
343 val16 = rtl8xxxu_read16(priv, REG_CR);
344 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
345 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
346 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
347 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
348 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
349 rtl8xxxu_write16(priv, REG_CR, val16);
350
351 /* For EFuse PG */
352 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
353 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
354 val32 |= (0x06 << 28);
355 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
356 exit:
357 return ret;
358 }
359
360 struct rtl8xxxu_fileops rtl8723au_fops = {
361 .parse_efuse = rtl8723au_parse_efuse,
362 .load_firmware = rtl8723au_load_firmware,
363 .power_on = rtl8723au_power_on,
364 .power_off = rtl8xxxu_power_off,
365 .reset_8051 = rtl8xxxu_reset_8051,
366 .llt_init = rtl8xxxu_init_llt_table,
367 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
368 .init_phy_rf = rtl8723au_init_phy_rf,
369 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
370 .config_channel = rtl8xxxu_gen1_config_channel,
371 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
372 .init_aggregation = rtl8xxxu_gen1_init_aggregation,
373 .enable_rf = rtl8xxxu_gen1_enable_rf,
374 .disable_rf = rtl8xxxu_gen1_disable_rf,
375 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
376 .set_tx_power = rtl8xxxu_gen1_set_tx_power,
377 .update_rate_mask = rtl8xxxu_update_rate_mask,
378 .report_connect = rtl8xxxu_gen1_report_connect,
379 .fill_txdesc = rtl8xxxu_fill_txdesc_v1,
380 .writeN_block_size = 1024,
381 .rx_agg_buf_size = 16000,
382 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
383 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
384 .adda_1t_init = 0x0b1b25a0,
385 .adda_1t_path_on = 0x0bdb25a0,
386 .adda_2t_path_on_a = 0x04db25a4,
387 .adda_2t_path_on_b = 0x0b1b25a4,
388 .trxff_boundary = 0x27ff,
389 .pbp_rx = PBP_PAGE_SIZE_128,
390 .pbp_tx = PBP_PAGE_SIZE_128,
391 .mactable = rtl8xxxu_gen1_mac_init_table,
392 .total_page_num = TX_TOTAL_PAGE_NUM,
393 .page_num_hi = TX_PAGE_NUM_HI_PQ,
394 .page_num_lo = TX_PAGE_NUM_LO_PQ,
395 .page_num_norm = TX_PAGE_NUM_NORM_PQ,
396 };
397