1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 *
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/pci.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/init.h>
14 #include <linux/mbus.h>
15 #include <linux/slab.h>
16 #include <linux/platform_device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22
23 #include "../pci.h"
24 #include "../pci-bridge-emul.h"
25
26 /*
27 * PCIe unit register offsets.
28 */
29 #define PCIE_DEV_ID_OFF 0x0000
30 #define PCIE_CMD_OFF 0x0004
31 #define PCIE_DEV_REV_OFF 0x0008
32 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
33 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
34 #define PCIE_CAP_PCIEXP 0x0060
35 #define PCIE_HEADER_LOG_4_OFF 0x0128
36 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
37 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
38 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
39 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
40 #define PCIE_WIN5_CTRL_OFF 0x1880
41 #define PCIE_WIN5_BASE_OFF 0x1884
42 #define PCIE_WIN5_REMAP_OFF 0x188c
43 #define PCIE_CONF_ADDR_OFF 0x18f8
44 #define PCIE_CONF_ADDR_EN 0x80000000
45 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
46 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
47 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
48 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
49 #define PCIE_CONF_ADDR(bus, devfn, where) \
50 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
51 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
52 PCIE_CONF_ADDR_EN)
53 #define PCIE_CONF_DATA_OFF 0x18fc
54 #define PCIE_INT_CAUSE_OFF 0x1900
55 #define PCIE_INT_PM_PME BIT(28)
56 #define PCIE_MASK_OFF 0x1910
57 #define PCIE_MASK_ENABLE_INTS 0x0f000000
58 #define PCIE_CTRL_OFF 0x1a00
59 #define PCIE_CTRL_X1_MODE 0x0001
60 #define PCIE_CTRL_RC_MODE BIT(1)
61 #define PCIE_CTRL_MASTER_HOT_RESET BIT(24)
62 #define PCIE_STAT_OFF 0x1a04
63 #define PCIE_STAT_BUS 0xff00
64 #define PCIE_STAT_DEV 0x1f0000
65 #define PCIE_STAT_LINK_DOWN BIT(0)
66 #define PCIE_RC_RTSTA 0x1a14
67 #define PCIE_DEBUG_CTRL 0x1a60
68 #define PCIE_DEBUG_SOFT_RESET BIT(20)
69
70 struct mvebu_pcie_port;
71
72 /* Structure representing all PCIe interfaces */
73 struct mvebu_pcie {
74 struct platform_device *pdev;
75 struct mvebu_pcie_port *ports;
76 struct resource io;
77 struct resource realio;
78 struct resource mem;
79 struct resource busn;
80 int nports;
81 };
82
83 struct mvebu_pcie_window {
84 phys_addr_t base;
85 phys_addr_t remap;
86 size_t size;
87 };
88
89 /* Structure representing one PCIe interface */
90 struct mvebu_pcie_port {
91 char *name;
92 void __iomem *base;
93 u32 port;
94 u32 lane;
95 int devfn;
96 unsigned int mem_target;
97 unsigned int mem_attr;
98 unsigned int io_target;
99 unsigned int io_attr;
100 struct clk *clk;
101 struct gpio_desc *reset_gpio;
102 char *reset_name;
103 struct pci_bridge_emul bridge;
104 struct device_node *dn;
105 struct mvebu_pcie *pcie;
106 struct mvebu_pcie_window memwin;
107 struct mvebu_pcie_window iowin;
108 u32 saved_pcie_stat;
109 struct resource regs;
110 };
111
mvebu_writel(struct mvebu_pcie_port * port,u32 val,u32 reg)112 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
113 {
114 writel(val, port->base + reg);
115 }
116
mvebu_readl(struct mvebu_pcie_port * port,u32 reg)117 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
118 {
119 return readl(port->base + reg);
120 }
121
mvebu_has_ioport(struct mvebu_pcie_port * port)122 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
123 {
124 return port->io_target != -1 && port->io_attr != -1;
125 }
126
mvebu_pcie_link_up(struct mvebu_pcie_port * port)127 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
128 {
129 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
130 }
131
mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port * port)132 static u8 mvebu_pcie_get_local_bus_nr(struct mvebu_pcie_port *port)
133 {
134 return (mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_BUS) >> 8;
135 }
136
mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port * port,int nr)137 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
138 {
139 u32 stat;
140
141 stat = mvebu_readl(port, PCIE_STAT_OFF);
142 stat &= ~PCIE_STAT_BUS;
143 stat |= nr << 8;
144 mvebu_writel(port, stat, PCIE_STAT_OFF);
145 }
146
mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port * port,int nr)147 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
148 {
149 u32 stat;
150
151 stat = mvebu_readl(port, PCIE_STAT_OFF);
152 stat &= ~PCIE_STAT_DEV;
153 stat |= nr << 16;
154 mvebu_writel(port, stat, PCIE_STAT_OFF);
155 }
156
157 /*
158 * Setup PCIE BARs and Address Decode Wins:
159 * BAR[0] -> internal registers (needed for MSI)
160 * BAR[1] -> covers all DRAM banks
161 * BAR[2] -> Disabled
162 * WIN[0-3] -> DRAM bank[0-3]
163 */
mvebu_pcie_setup_wins(struct mvebu_pcie_port * port)164 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
165 {
166 const struct mbus_dram_target_info *dram;
167 u32 size;
168 int i;
169
170 dram = mv_mbus_dram_info();
171
172 /* First, disable and clear BARs and windows. */
173 for (i = 1; i < 3; i++) {
174 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
175 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
176 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
177 }
178
179 for (i = 0; i < 5; i++) {
180 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
181 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
182 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
183 }
184
185 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
186 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
187 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
188
189 /* Setup windows for DDR banks. Count total DDR size on the fly. */
190 size = 0;
191 for (i = 0; i < dram->num_cs; i++) {
192 const struct mbus_dram_window *cs = dram->cs + i;
193
194 mvebu_writel(port, cs->base & 0xffff0000,
195 PCIE_WIN04_BASE_OFF(i));
196 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
197 mvebu_writel(port,
198 ((cs->size - 1) & 0xffff0000) |
199 (cs->mbus_attr << 8) |
200 (dram->mbus_dram_target_id << 4) | 1,
201 PCIE_WIN04_CTRL_OFF(i));
202
203 size += cs->size;
204 }
205
206 /* Round up 'size' to the nearest power of two. */
207 if ((size & (size - 1)) != 0)
208 size = 1 << fls(size);
209
210 /* Setup BAR[1] to all DRAM banks. */
211 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
212 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
213 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
214 PCIE_BAR_CTRL_OFF(1));
215
216 /*
217 * Point BAR[0] to the device's internal registers.
218 */
219 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0));
220 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(0));
221 }
222
mvebu_pcie_setup_hw(struct mvebu_pcie_port * port)223 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
224 {
225 u32 ctrl, cmd, mask;
226
227 /* Setup PCIe controller to Root Complex mode. */
228 ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
229 ctrl |= PCIE_CTRL_RC_MODE;
230 mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
231
232 /* Disable Root Bridge I/O space, memory space and bus mastering. */
233 cmd = mvebu_readl(port, PCIE_CMD_OFF);
234 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
235 mvebu_writel(port, cmd, PCIE_CMD_OFF);
236
237 /* Point PCIe unit MBUS decode windows to DRAM space. */
238 mvebu_pcie_setup_wins(port);
239
240 /* Enable interrupt lines A-D. */
241 mask = mvebu_readl(port, PCIE_MASK_OFF);
242 mask |= PCIE_MASK_ENABLE_INTS;
243 mvebu_writel(port, mask, PCIE_MASK_OFF);
244 }
245
mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port * port,struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)246 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
247 struct pci_bus *bus,
248 u32 devfn, int where, int size, u32 *val)
249 {
250 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
251
252 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
253 PCIE_CONF_ADDR_OFF);
254
255 switch (size) {
256 case 1:
257 *val = readb_relaxed(conf_data + (where & 3));
258 break;
259 case 2:
260 *val = readw_relaxed(conf_data + (where & 2));
261 break;
262 case 4:
263 *val = readl_relaxed(conf_data);
264 break;
265 }
266
267 return PCIBIOS_SUCCESSFUL;
268 }
269
mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port * port,struct pci_bus * bus,u32 devfn,int where,int size,u32 val)270 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
271 struct pci_bus *bus,
272 u32 devfn, int where, int size, u32 val)
273 {
274 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
275
276 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
277 PCIE_CONF_ADDR_OFF);
278
279 switch (size) {
280 case 1:
281 writeb(val, conf_data + (where & 3));
282 break;
283 case 2:
284 writew(val, conf_data + (where & 2));
285 break;
286 case 4:
287 writel(val, conf_data);
288 break;
289 default:
290 return PCIBIOS_BAD_REGISTER_NUMBER;
291 }
292
293 return PCIBIOS_SUCCESSFUL;
294 }
295
296 /*
297 * Remove windows, starting from the largest ones to the smallest
298 * ones.
299 */
mvebu_pcie_del_windows(struct mvebu_pcie_port * port,phys_addr_t base,size_t size)300 static void mvebu_pcie_del_windows(struct mvebu_pcie_port *port,
301 phys_addr_t base, size_t size)
302 {
303 while (size) {
304 size_t sz = 1 << (fls(size) - 1);
305
306 mvebu_mbus_del_window(base, sz);
307 base += sz;
308 size -= sz;
309 }
310 }
311
312 /*
313 * MBus windows can only have a power of two size, but PCI BARs do not
314 * have this constraint. Therefore, we have to split the PCI BAR into
315 * areas each having a power of two size. We start from the largest
316 * one (i.e highest order bit set in the size).
317 */
mvebu_pcie_add_windows(struct mvebu_pcie_port * port,unsigned int target,unsigned int attribute,phys_addr_t base,size_t size,phys_addr_t remap)318 static void mvebu_pcie_add_windows(struct mvebu_pcie_port *port,
319 unsigned int target, unsigned int attribute,
320 phys_addr_t base, size_t size,
321 phys_addr_t remap)
322 {
323 size_t size_mapped = 0;
324
325 while (size) {
326 size_t sz = 1 << (fls(size) - 1);
327 int ret;
328
329 ret = mvebu_mbus_add_window_remap_by_id(target, attribute, base,
330 sz, remap);
331 if (ret) {
332 phys_addr_t end = base + sz - 1;
333
334 dev_err(&port->pcie->pdev->dev,
335 "Could not create MBus window at [mem %pa-%pa]: %d\n",
336 &base, &end, ret);
337 mvebu_pcie_del_windows(port, base - size_mapped,
338 size_mapped);
339 return;
340 }
341
342 size -= sz;
343 size_mapped += sz;
344 base += sz;
345 if (remap != MVEBU_MBUS_NO_REMAP)
346 remap += sz;
347 }
348 }
349
mvebu_pcie_set_window(struct mvebu_pcie_port * port,unsigned int target,unsigned int attribute,const struct mvebu_pcie_window * desired,struct mvebu_pcie_window * cur)350 static void mvebu_pcie_set_window(struct mvebu_pcie_port *port,
351 unsigned int target, unsigned int attribute,
352 const struct mvebu_pcie_window *desired,
353 struct mvebu_pcie_window *cur)
354 {
355 if (desired->base == cur->base && desired->remap == cur->remap &&
356 desired->size == cur->size)
357 return;
358
359 if (cur->size != 0) {
360 mvebu_pcie_del_windows(port, cur->base, cur->size);
361 cur->size = 0;
362 cur->base = 0;
363
364 /*
365 * If something tries to change the window while it is enabled
366 * the change will not be done atomically. That would be
367 * difficult to do in the general case.
368 */
369 }
370
371 if (desired->size == 0)
372 return;
373
374 mvebu_pcie_add_windows(port, target, attribute, desired->base,
375 desired->size, desired->remap);
376 *cur = *desired;
377 }
378
mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port * port)379 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
380 {
381 struct mvebu_pcie_window desired = {};
382 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
383
384 /* Are the new iobase/iolimit values invalid? */
385 if (conf->iolimit < conf->iobase ||
386 conf->iolimitupper < conf->iobaseupper) {
387 mvebu_pcie_set_window(port, port->io_target, port->io_attr,
388 &desired, &port->iowin);
389 return;
390 }
391
392 if (!mvebu_has_ioport(port)) {
393 dev_WARN(&port->pcie->pdev->dev,
394 "Attempt to set IO when IO is disabled\n");
395 return;
396 }
397
398 /*
399 * We read the PCI-to-PCI bridge emulated registers, and
400 * calculate the base address and size of the address decoding
401 * window to setup, according to the PCI-to-PCI bridge
402 * specifications. iobase is the bus address, port->iowin_base
403 * is the CPU address.
404 */
405 desired.remap = ((conf->iobase & 0xF0) << 8) |
406 (conf->iobaseupper << 16);
407 desired.base = port->pcie->io.start + desired.remap;
408 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) |
409 (conf->iolimitupper << 16)) -
410 desired.remap) +
411 1;
412
413 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired,
414 &port->iowin);
415 }
416
mvebu_pcie_handle_membase_change(struct mvebu_pcie_port * port)417 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
418 {
419 struct mvebu_pcie_window desired = {.remap = MVEBU_MBUS_NO_REMAP};
420 struct pci_bridge_emul_conf *conf = &port->bridge.conf;
421
422 /* Are the new membase/memlimit values invalid? */
423 if (conf->memlimit < conf->membase) {
424 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr,
425 &desired, &port->memwin);
426 return;
427 }
428
429 /*
430 * We read the PCI-to-PCI bridge emulated registers, and
431 * calculate the base address and size of the address decoding
432 * window to setup, according to the PCI-to-PCI bridge
433 * specifications.
434 */
435 desired.base = ((conf->membase & 0xFFF0) << 16);
436 desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) -
437 desired.base + 1;
438
439 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired,
440 &port->memwin);
441 }
442
443 static pci_bridge_emul_read_status_t
mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul * bridge,int reg,u32 * value)444 mvebu_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
445 int reg, u32 *value)
446 {
447 struct mvebu_pcie_port *port = bridge->data;
448
449 switch (reg) {
450 case PCI_COMMAND:
451 *value = mvebu_readl(port, PCIE_CMD_OFF);
452 break;
453
454 case PCI_PRIMARY_BUS: {
455 /*
456 * From the whole 32bit register we support reading from HW only
457 * secondary bus number which is mvebu local bus number.
458 * Other bits are retrieved only from emulated config buffer.
459 */
460 __le32 *cfgspace = (__le32 *)&bridge->conf;
461 u32 val = le32_to_cpu(cfgspace[PCI_PRIMARY_BUS / 4]);
462 val &= ~0xff00;
463 val |= mvebu_pcie_get_local_bus_nr(port) << 8;
464 *value = val;
465 break;
466 }
467
468 case PCI_INTERRUPT_LINE: {
469 /*
470 * From the whole 32bit register we support reading from HW only
471 * one bit: PCI_BRIDGE_CTL_BUS_RESET.
472 * Other bits are retrieved only from emulated config buffer.
473 */
474 __le32 *cfgspace = (__le32 *)&bridge->conf;
475 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
476 if (mvebu_readl(port, PCIE_CTRL_OFF) & PCIE_CTRL_MASTER_HOT_RESET)
477 val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
478 else
479 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
480 *value = val;
481 break;
482 }
483
484 default:
485 return PCI_BRIDGE_EMUL_NOT_HANDLED;
486 }
487
488 return PCI_BRIDGE_EMUL_HANDLED;
489 }
490
491 static pci_bridge_emul_read_status_t
mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul * bridge,int reg,u32 * value)492 mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
493 int reg, u32 *value)
494 {
495 struct mvebu_pcie_port *port = bridge->data;
496
497 switch (reg) {
498 case PCI_EXP_DEVCAP:
499 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP);
500 break;
501
502 case PCI_EXP_DEVCTL:
503 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
504 break;
505
506 case PCI_EXP_LNKCAP:
507 /*
508 * PCIe requires the clock power management capability to be
509 * hard-wired to zero for downstream ports
510 */
511 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
512 ~PCI_EXP_LNKCAP_CLKPM;
513 break;
514
515 case PCI_EXP_LNKCTL:
516 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
517 break;
518
519 case PCI_EXP_SLTCTL:
520 *value = PCI_EXP_SLTSTA_PDS << 16;
521 break;
522
523 case PCI_EXP_RTSTA:
524 *value = mvebu_readl(port, PCIE_RC_RTSTA);
525 break;
526
527 case PCI_EXP_DEVCAP2:
528 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCAP2);
529 break;
530
531 case PCI_EXP_DEVCTL2:
532 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
533 break;
534
535 case PCI_EXP_LNKCTL2:
536 *value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
537 break;
538
539 default:
540 return PCI_BRIDGE_EMUL_NOT_HANDLED;
541 }
542
543 return PCI_BRIDGE_EMUL_HANDLED;
544 }
545
546 static void
mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul * bridge,int reg,u32 old,u32 new,u32 mask)547 mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
548 int reg, u32 old, u32 new, u32 mask)
549 {
550 struct mvebu_pcie_port *port = bridge->data;
551 struct pci_bridge_emul_conf *conf = &bridge->conf;
552
553 switch (reg) {
554 case PCI_COMMAND:
555 if (!mvebu_has_ioport(port)) {
556 conf->command = cpu_to_le16(
557 le16_to_cpu(conf->command) & ~PCI_COMMAND_IO);
558 new &= ~PCI_COMMAND_IO;
559 }
560
561 mvebu_writel(port, new, PCIE_CMD_OFF);
562 break;
563
564 case PCI_IO_BASE:
565 mvebu_pcie_handle_iobase_change(port);
566 break;
567
568 case PCI_MEMORY_BASE:
569 mvebu_pcie_handle_membase_change(port);
570 break;
571
572 case PCI_IO_BASE_UPPER16:
573 mvebu_pcie_handle_iobase_change(port);
574 break;
575
576 case PCI_PRIMARY_BUS:
577 if (mask & 0xff00)
578 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus);
579 break;
580
581 case PCI_INTERRUPT_LINE:
582 if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
583 u32 ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
584 if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
585 ctrl |= PCIE_CTRL_MASTER_HOT_RESET;
586 else
587 ctrl &= ~PCIE_CTRL_MASTER_HOT_RESET;
588 mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
589 }
590 break;
591
592 default:
593 break;
594 }
595 }
596
597 static void
mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul * bridge,int reg,u32 old,u32 new,u32 mask)598 mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
599 int reg, u32 old, u32 new, u32 mask)
600 {
601 struct mvebu_pcie_port *port = bridge->data;
602
603 switch (reg) {
604 case PCI_EXP_DEVCTL:
605 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL);
606 break;
607
608 case PCI_EXP_LNKCTL:
609 /*
610 * If we don't support CLKREQ, we must ensure that the
611 * CLKREQ enable bit always reads zero. Since we haven't
612 * had this capability, and it's dependent on board wiring,
613 * disable it for the time being.
614 */
615 new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
616
617 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
618 break;
619
620 case PCI_EXP_RTSTA:
621 /*
622 * PME Status bit in Root Status Register (PCIE_RC_RTSTA)
623 * is read-only and can be cleared only by writing 0b to the
624 * Interrupt Cause RW0C register (PCIE_INT_CAUSE_OFF). So
625 * clear PME via Interrupt Cause.
626 */
627 if (new & PCI_EXP_RTSTA_PME)
628 mvebu_writel(port, ~PCIE_INT_PM_PME, PCIE_INT_CAUSE_OFF);
629 break;
630
631 case PCI_EXP_DEVCTL2:
632 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_DEVCTL2);
633 break;
634
635 case PCI_EXP_LNKCTL2:
636 mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL2);
637 break;
638
639 default:
640 break;
641 }
642 }
643
644 static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
645 .read_base = mvebu_pci_bridge_emul_base_conf_read,
646 .write_base = mvebu_pci_bridge_emul_base_conf_write,
647 .read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
648 .write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
649 };
650
651 /*
652 * Initialize the configuration space of the PCI-to-PCI bridge
653 * associated with the given PCIe interface.
654 */
mvebu_pci_bridge_emul_init(struct mvebu_pcie_port * port)655 static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
656 {
657 struct pci_bridge_emul *bridge = &port->bridge;
658 u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
659 u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);
660
661 bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
662 bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
663 bridge->conf.class_revision =
664 mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
665
666 if (mvebu_has_ioport(port)) {
667 /* We support 32 bits I/O addressing */
668 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
669 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
670 }
671
672 /*
673 * Older mvebu hardware provides PCIe Capability structure only in
674 * version 1. New hardware provides it in version 2.
675 */
676 bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
677
678 bridge->has_pcie = true;
679 bridge->data = port;
680 bridge->ops = &mvebu_pci_bridge_emul_ops;
681
682 return pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
683 }
684
sys_to_pcie(struct pci_sys_data * sys)685 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
686 {
687 return sys->private_data;
688 }
689
mvebu_pcie_find_port(struct mvebu_pcie * pcie,struct pci_bus * bus,int devfn)690 static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
691 struct pci_bus *bus,
692 int devfn)
693 {
694 int i;
695
696 for (i = 0; i < pcie->nports; i++) {
697 struct mvebu_pcie_port *port = &pcie->ports[i];
698
699 if (bus->number == 0 && port->devfn == devfn)
700 return port;
701 if (bus->number != 0 &&
702 bus->number >= port->bridge.conf.secondary_bus &&
703 bus->number <= port->bridge.conf.subordinate_bus)
704 return port;
705 }
706
707 return NULL;
708 }
709
710 /* PCI configuration space write function */
mvebu_pcie_wr_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 val)711 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
712 int where, int size, u32 val)
713 {
714 struct mvebu_pcie *pcie = bus->sysdata;
715 struct mvebu_pcie_port *port;
716 int ret;
717
718 port = mvebu_pcie_find_port(pcie, bus, devfn);
719 if (!port)
720 return PCIBIOS_DEVICE_NOT_FOUND;
721
722 /* Access the emulated PCI-to-PCI bridge */
723 if (bus->number == 0)
724 return pci_bridge_emul_conf_write(&port->bridge, where,
725 size, val);
726
727 if (!mvebu_pcie_link_up(port))
728 return PCIBIOS_DEVICE_NOT_FOUND;
729
730 /* Access the real PCIe interface */
731 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
732 where, size, val);
733
734 return ret;
735 }
736
737 /* PCI configuration space read function */
mvebu_pcie_rd_conf(struct pci_bus * bus,u32 devfn,int where,int size,u32 * val)738 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
739 int size, u32 *val)
740 {
741 struct mvebu_pcie *pcie = bus->sysdata;
742 struct mvebu_pcie_port *port;
743 int ret;
744
745 port = mvebu_pcie_find_port(pcie, bus, devfn);
746 if (!port) {
747 *val = 0xffffffff;
748 return PCIBIOS_DEVICE_NOT_FOUND;
749 }
750
751 /* Access the emulated PCI-to-PCI bridge */
752 if (bus->number == 0)
753 return pci_bridge_emul_conf_read(&port->bridge, where,
754 size, val);
755
756 if (!mvebu_pcie_link_up(port)) {
757 *val = 0xffffffff;
758 return PCIBIOS_DEVICE_NOT_FOUND;
759 }
760
761 /* Access the real PCIe interface */
762 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
763 where, size, val);
764
765 return ret;
766 }
767
768 static struct pci_ops mvebu_pcie_ops = {
769 .read = mvebu_pcie_rd_conf,
770 .write = mvebu_pcie_wr_conf,
771 };
772
mvebu_pcie_align_resource(struct pci_dev * dev,const struct resource * res,resource_size_t start,resource_size_t size,resource_size_t align)773 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
774 const struct resource *res,
775 resource_size_t start,
776 resource_size_t size,
777 resource_size_t align)
778 {
779 if (dev->bus->number != 0)
780 return start;
781
782 /*
783 * On the PCI-to-PCI bridge side, the I/O windows must have at
784 * least a 64 KB size and the memory windows must have at
785 * least a 1 MB size. Moreover, MBus windows need to have a
786 * base address aligned on their size, and their size must be
787 * a power of two. This means that if the BAR doesn't have a
788 * power of two size, several MBus windows will actually be
789 * created. We need to ensure that the biggest MBus window
790 * (which will be the first one) is aligned on its size, which
791 * explains the rounddown_pow_of_two() being done here.
792 */
793 if (res->flags & IORESOURCE_IO)
794 return round_up(start, max_t(resource_size_t, SZ_64K,
795 rounddown_pow_of_two(size)));
796 else if (res->flags & IORESOURCE_MEM)
797 return round_up(start, max_t(resource_size_t, SZ_1M,
798 rounddown_pow_of_two(size)));
799 else
800 return start;
801 }
802
mvebu_pcie_map_registers(struct platform_device * pdev,struct device_node * np,struct mvebu_pcie_port * port)803 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
804 struct device_node *np,
805 struct mvebu_pcie_port *port)
806 {
807 int ret = 0;
808
809 ret = of_address_to_resource(np, 0, &port->regs);
810 if (ret)
811 return (void __iomem *)ERR_PTR(ret);
812
813 return devm_ioremap_resource(&pdev->dev, &port->regs);
814 }
815
816 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
817 #define DT_TYPE_IO 0x1
818 #define DT_TYPE_MEM32 0x2
819 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
820 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
821
mvebu_get_tgt_attr(struct device_node * np,int devfn,unsigned long type,unsigned int * tgt,unsigned int * attr)822 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
823 unsigned long type,
824 unsigned int *tgt,
825 unsigned int *attr)
826 {
827 const int na = 3, ns = 2;
828 const __be32 *range;
829 int rlen, nranges, rangesz, pna, i;
830
831 *tgt = -1;
832 *attr = -1;
833
834 range = of_get_property(np, "ranges", &rlen);
835 if (!range)
836 return -EINVAL;
837
838 pna = of_n_addr_cells(np);
839 rangesz = pna + na + ns;
840 nranges = rlen / sizeof(__be32) / rangesz;
841
842 for (i = 0; i < nranges; i++, range += rangesz) {
843 u32 flags = of_read_number(range, 1);
844 u32 slot = of_read_number(range + 1, 1);
845 u64 cpuaddr = of_read_number(range + na, pna);
846 unsigned long rtype;
847
848 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
849 rtype = IORESOURCE_IO;
850 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
851 rtype = IORESOURCE_MEM;
852 else
853 continue;
854
855 if (slot == PCI_SLOT(devfn) && type == rtype) {
856 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
857 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
858 return 0;
859 }
860 }
861
862 return -ENOENT;
863 }
864
865 #ifdef CONFIG_PM_SLEEP
mvebu_pcie_suspend(struct device * dev)866 static int mvebu_pcie_suspend(struct device *dev)
867 {
868 struct mvebu_pcie *pcie;
869 int i;
870
871 pcie = dev_get_drvdata(dev);
872 for (i = 0; i < pcie->nports; i++) {
873 struct mvebu_pcie_port *port = pcie->ports + i;
874 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF);
875 }
876
877 return 0;
878 }
879
mvebu_pcie_resume(struct device * dev)880 static int mvebu_pcie_resume(struct device *dev)
881 {
882 struct mvebu_pcie *pcie;
883 int i;
884
885 pcie = dev_get_drvdata(dev);
886 for (i = 0; i < pcie->nports; i++) {
887 struct mvebu_pcie_port *port = pcie->ports + i;
888 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF);
889 mvebu_pcie_setup_hw(port);
890 }
891
892 return 0;
893 }
894 #endif
895
mvebu_pcie_port_clk_put(void * data)896 static void mvebu_pcie_port_clk_put(void *data)
897 {
898 struct mvebu_pcie_port *port = data;
899
900 clk_put(port->clk);
901 }
902
mvebu_pcie_parse_port(struct mvebu_pcie * pcie,struct mvebu_pcie_port * port,struct device_node * child)903 static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
904 struct mvebu_pcie_port *port, struct device_node *child)
905 {
906 struct device *dev = &pcie->pdev->dev;
907 enum of_gpio_flags flags;
908 int reset_gpio, ret;
909
910 port->pcie = pcie;
911
912 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) {
913 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n",
914 child);
915 goto skip;
916 }
917
918 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
919 port->lane = 0;
920
921 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
922 port->lane);
923 if (!port->name) {
924 ret = -ENOMEM;
925 goto err;
926 }
927
928 port->devfn = of_pci_get_devfn(child);
929 if (port->devfn < 0)
930 goto skip;
931
932 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM,
933 &port->mem_target, &port->mem_attr);
934 if (ret < 0) {
935 dev_err(dev, "%s: cannot get tgt/attr for mem window\n",
936 port->name);
937 goto skip;
938 }
939
940 if (resource_size(&pcie->io) != 0) {
941 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO,
942 &port->io_target, &port->io_attr);
943 } else {
944 port->io_target = -1;
945 port->io_attr = -1;
946 }
947
948 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
949 if (reset_gpio == -EPROBE_DEFER) {
950 ret = reset_gpio;
951 goto err;
952 }
953
954 if (gpio_is_valid(reset_gpio)) {
955 unsigned long gpio_flags;
956
957 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset",
958 port->name);
959 if (!port->reset_name) {
960 ret = -ENOMEM;
961 goto err;
962 }
963
964 if (flags & OF_GPIO_ACTIVE_LOW) {
965 dev_info(dev, "%pOF: reset gpio is active low\n",
966 child);
967 gpio_flags = GPIOF_ACTIVE_LOW |
968 GPIOF_OUT_INIT_LOW;
969 } else {
970 gpio_flags = GPIOF_OUT_INIT_HIGH;
971 }
972
973 ret = devm_gpio_request_one(dev, reset_gpio, gpio_flags,
974 port->reset_name);
975 if (ret) {
976 if (ret == -EPROBE_DEFER)
977 goto err;
978 goto skip;
979 }
980
981 port->reset_gpio = gpio_to_desc(reset_gpio);
982 }
983
984 port->clk = of_clk_get_by_name(child, NULL);
985 if (IS_ERR(port->clk)) {
986 dev_err(dev, "%s: cannot get clock\n", port->name);
987 goto skip;
988 }
989
990 ret = devm_add_action(dev, mvebu_pcie_port_clk_put, port);
991 if (ret < 0) {
992 clk_put(port->clk);
993 goto err;
994 }
995
996 return 1;
997
998 skip:
999 ret = 0;
1000
1001 /* In the case of skipping, we need to free these */
1002 devm_kfree(dev, port->reset_name);
1003 port->reset_name = NULL;
1004 devm_kfree(dev, port->name);
1005 port->name = NULL;
1006
1007 err:
1008 return ret;
1009 }
1010
1011 /*
1012 * Power up a PCIe port. PCIe requires the refclk to be stable for 100µs
1013 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
1014 * of the PCI Express Card Electromechanical Specification, 1.1.
1015 */
mvebu_pcie_powerup(struct mvebu_pcie_port * port)1016 static int mvebu_pcie_powerup(struct mvebu_pcie_port *port)
1017 {
1018 int ret;
1019
1020 ret = clk_prepare_enable(port->clk);
1021 if (ret < 0)
1022 return ret;
1023
1024 if (port->reset_gpio) {
1025 u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
1026
1027 of_property_read_u32(port->dn, "reset-delay-us",
1028 &reset_udelay);
1029
1030 udelay(100);
1031
1032 gpiod_set_value_cansleep(port->reset_gpio, 0);
1033 msleep(reset_udelay / 1000);
1034 }
1035
1036 return 0;
1037 }
1038
1039 /*
1040 * Power down a PCIe port. Strictly, PCIe requires us to place the card
1041 * in D3hot state before asserting PERST#.
1042 */
mvebu_pcie_powerdown(struct mvebu_pcie_port * port)1043 static void mvebu_pcie_powerdown(struct mvebu_pcie_port *port)
1044 {
1045 gpiod_set_value_cansleep(port->reset_gpio, 1);
1046
1047 clk_disable_unprepare(port->clk);
1048 }
1049
1050 /*
1051 * devm_of_pci_get_host_bridge_resources() only sets up translateable resources,
1052 * so we need extra resource setup parsing our special DT properties encoding
1053 * the MEM and IO apertures.
1054 */
mvebu_pcie_parse_request_resources(struct mvebu_pcie * pcie)1055 static int mvebu_pcie_parse_request_resources(struct mvebu_pcie *pcie)
1056 {
1057 struct device *dev = &pcie->pdev->dev;
1058 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1059 int ret;
1060
1061 /* Get the PCIe memory aperture */
1062 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
1063 if (resource_size(&pcie->mem) == 0) {
1064 dev_err(dev, "invalid memory aperture size\n");
1065 return -EINVAL;
1066 }
1067
1068 pcie->mem.name = "PCI MEM";
1069 pci_add_resource(&bridge->windows, &pcie->mem);
1070 ret = devm_request_resource(dev, &iomem_resource, &pcie->mem);
1071 if (ret)
1072 return ret;
1073
1074 /* Get the PCIe IO aperture */
1075 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
1076
1077 if (resource_size(&pcie->io) != 0) {
1078 pcie->realio.flags = pcie->io.flags;
1079 pcie->realio.start = PCIBIOS_MIN_IO;
1080 pcie->realio.end = min_t(resource_size_t,
1081 IO_SPACE_LIMIT - SZ_64K,
1082 resource_size(&pcie->io) - 1);
1083 pcie->realio.name = "PCI I/O";
1084
1085 pci_add_resource(&bridge->windows, &pcie->realio);
1086 ret = devm_request_resource(dev, &ioport_resource, &pcie->realio);
1087 if (ret)
1088 return ret;
1089 }
1090
1091 return 0;
1092 }
1093
1094 /*
1095 * This is a copy of pci_host_probe(), except that it does the I/O
1096 * remap as the last step, once we are sure we won't fail.
1097 *
1098 * It should be removed once the I/O remap error handling issue has
1099 * been sorted out.
1100 */
mvebu_pci_host_probe(struct pci_host_bridge * bridge)1101 static int mvebu_pci_host_probe(struct pci_host_bridge *bridge)
1102 {
1103 struct mvebu_pcie *pcie;
1104 struct pci_bus *bus, *child;
1105 int ret;
1106
1107 ret = pci_scan_root_bus_bridge(bridge);
1108 if (ret < 0) {
1109 dev_err(bridge->dev.parent, "Scanning root bridge failed");
1110 return ret;
1111 }
1112
1113 pcie = pci_host_bridge_priv(bridge);
1114 if (resource_size(&pcie->io) != 0) {
1115 unsigned int i;
1116
1117 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K)
1118 pci_ioremap_io(i, pcie->io.start + i);
1119 }
1120
1121 bus = bridge->bus;
1122
1123 /*
1124 * We insert PCI resources into the iomem_resource and
1125 * ioport_resource trees in either pci_bus_claim_resources()
1126 * or pci_bus_assign_resources().
1127 */
1128 if (pci_has_flag(PCI_PROBE_ONLY)) {
1129 pci_bus_claim_resources(bus);
1130 } else {
1131 pci_bus_size_bridges(bus);
1132 pci_bus_assign_resources(bus);
1133
1134 list_for_each_entry(child, &bus->children, node)
1135 pcie_bus_configure_settings(child);
1136 }
1137
1138 pci_bus_add_devices(bus);
1139 return 0;
1140 }
1141
mvebu_pcie_probe(struct platform_device * pdev)1142 static int mvebu_pcie_probe(struct platform_device *pdev)
1143 {
1144 struct device *dev = &pdev->dev;
1145 struct mvebu_pcie *pcie;
1146 struct pci_host_bridge *bridge;
1147 struct device_node *np = dev->of_node;
1148 struct device_node *child;
1149 int num, i, ret;
1150
1151 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct mvebu_pcie));
1152 if (!bridge)
1153 return -ENOMEM;
1154
1155 pcie = pci_host_bridge_priv(bridge);
1156 pcie->pdev = pdev;
1157 platform_set_drvdata(pdev, pcie);
1158
1159 ret = mvebu_pcie_parse_request_resources(pcie);
1160 if (ret)
1161 return ret;
1162
1163 num = of_get_available_child_count(np);
1164
1165 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL);
1166 if (!pcie->ports)
1167 return -ENOMEM;
1168
1169 i = 0;
1170 for_each_available_child_of_node(np, child) {
1171 struct mvebu_pcie_port *port = &pcie->ports[i];
1172
1173 ret = mvebu_pcie_parse_port(pcie, port, child);
1174 if (ret < 0) {
1175 of_node_put(child);
1176 return ret;
1177 } else if (ret == 0) {
1178 continue;
1179 }
1180
1181 port->dn = child;
1182 i++;
1183 }
1184 pcie->nports = i;
1185
1186 for (i = 0; i < pcie->nports; i++) {
1187 struct mvebu_pcie_port *port = &pcie->ports[i];
1188
1189 child = port->dn;
1190 if (!child)
1191 continue;
1192
1193 ret = mvebu_pcie_powerup(port);
1194 if (ret < 0)
1195 continue;
1196
1197 port->base = mvebu_pcie_map_registers(pdev, child, port);
1198 if (IS_ERR(port->base)) {
1199 dev_err(dev, "%s: cannot map registers\n", port->name);
1200 port->base = NULL;
1201 mvebu_pcie_powerdown(port);
1202 continue;
1203 }
1204
1205 ret = mvebu_pci_bridge_emul_init(port);
1206 if (ret < 0) {
1207 dev_err(dev, "%s: cannot init emulated bridge\n",
1208 port->name);
1209 devm_iounmap(dev, port->base);
1210 port->base = NULL;
1211 mvebu_pcie_powerdown(port);
1212 continue;
1213 }
1214
1215 /*
1216 * PCIe topology exported by mvebu hw is quite complicated. In
1217 * reality has something like N fully independent host bridges
1218 * where each host bridge has one PCIe Root Port (which acts as
1219 * PCI Bridge device). Each host bridge has its own independent
1220 * internal registers, independent access to PCI config space,
1221 * independent interrupt lines, independent window and memory
1222 * access configuration. But additionally there is some kind of
1223 * peer-to-peer support between PCIe devices behind different
1224 * host bridges limited just to forwarding of memory and I/O
1225 * transactions (forwarding of error messages and config cycles
1226 * is not supported). So we could say there are N independent
1227 * PCIe Root Complexes.
1228 *
1229 * For this kind of setup DT should have been structured into
1230 * N independent PCIe controllers / host bridges. But instead
1231 * structure in past was defined to put PCIe Root Ports of all
1232 * host bridges into one bus zero, like in classic multi-port
1233 * Root Complex setup with just one host bridge.
1234 *
1235 * This means that pci-mvebu.c driver provides "virtual" bus 0
1236 * on which registers all PCIe Root Ports (PCI Bridge devices)
1237 * specified in DT by their BDF addresses and virtually routes
1238 * PCI config access of each PCI bridge device to specific PCIe
1239 * host bridge.
1240 *
1241 * Normally PCI Bridge should choose between Type 0 and Type 1
1242 * config requests based on primary and secondary bus numbers
1243 * configured on the bridge itself. But because mvebu PCI Bridge
1244 * does not have registers for primary and secondary bus numbers
1245 * in its config space, it determinates type of config requests
1246 * via its own custom way.
1247 *
1248 * There are two options how mvebu determinate type of config
1249 * request.
1250 *
1251 * 1. If Secondary Bus Number Enable bit is not set or is not
1252 * available (applies for pre-XP PCIe controllers) then Type 0
1253 * is used if target bus number equals Local Bus Number (bits
1254 * [15:8] in register 0x1a04) and target device number differs
1255 * from Local Device Number (bits [20:16] in register 0x1a04).
1256 * Type 1 is used if target bus number differs from Local Bus
1257 * Number. And when target bus number equals Local Bus Number
1258 * and target device equals Local Device Number then request is
1259 * routed to Local PCI Bridge (PCIe Root Port).
1260 *
1261 * 2. If Secondary Bus Number Enable bit is set (bit 7 in
1262 * register 0x1a2c) then mvebu hw determinate type of config
1263 * request like compliant PCI Bridge based on primary bus number
1264 * which is configured via Local Bus Number (bits [15:8] in
1265 * register 0x1a04) and secondary bus number which is configured
1266 * via Secondary Bus Number (bits [7:0] in register 0x1a2c).
1267 * Local PCI Bridge (PCIe Root Port) is available on primary bus
1268 * as device with Local Device Number (bits [20:16] in register
1269 * 0x1a04).
1270 *
1271 * Secondary Bus Number Enable bit is disabled by default and
1272 * option 2. is not available on pre-XP PCIe controllers. Hence
1273 * this driver always use option 1.
1274 *
1275 * Basically it means that primary and secondary buses shares
1276 * one virtual number configured via Local Bus Number bits and
1277 * Local Device Number bits determinates if accessing primary
1278 * or secondary bus. Set Local Device Number to 1 and redirect
1279 * all writes of PCI Bridge Secondary Bus Number register to
1280 * Local Bus Number (bits [15:8] in register 0x1a04).
1281 *
1282 * So when accessing devices on buses behind secondary bus
1283 * number it would work correctly. And also when accessing
1284 * device 0 at secondary bus number via config space would be
1285 * correctly routed to secondary bus. Due to issues described
1286 * in mvebu_pcie_setup_hw(), PCI Bridges at primary bus (zero)
1287 * are not accessed directly via PCI config space but rarher
1288 * indirectly via kernel emulated PCI bridge driver.
1289 */
1290 mvebu_pcie_setup_hw(port);
1291 mvebu_pcie_set_local_dev_nr(port, 1);
1292 mvebu_pcie_set_local_bus_nr(port, 0);
1293 }
1294
1295 pcie->nports = i;
1296
1297 bridge->sysdata = pcie;
1298 bridge->ops = &mvebu_pcie_ops;
1299 bridge->align_resource = mvebu_pcie_align_resource;
1300
1301 return mvebu_pci_host_probe(bridge);
1302 }
1303
1304 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1305 { .compatible = "marvell,armada-xp-pcie", },
1306 { .compatible = "marvell,armada-370-pcie", },
1307 { .compatible = "marvell,dove-pcie", },
1308 { .compatible = "marvell,kirkwood-pcie", },
1309 {},
1310 };
1311
1312 static const struct dev_pm_ops mvebu_pcie_pm_ops = {
1313 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mvebu_pcie_suspend, mvebu_pcie_resume)
1314 };
1315
1316 static struct platform_driver mvebu_pcie_driver = {
1317 .driver = {
1318 .name = "mvebu-pcie",
1319 .of_match_table = mvebu_pcie_of_match_table,
1320 /* driver unloading/unbinding currently not supported */
1321 .suppress_bind_attrs = true,
1322 .pm = &mvebu_pcie_pm_ops,
1323 },
1324 .probe = mvebu_pcie_probe,
1325 };
1326 builtin_platform_driver(mvebu_pcie_driver);
1327