1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Standard Hot Plug Controller Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM
8 * Copyright (C) 2003-2004 Intel Corporation
9 *
10 * All rights reserved.
11 *
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
13 *
14 */
15 #ifndef _SHPCHP_H
16 #define _SHPCHP_H
17
18 #include <linux/types.h>
19 #include <linux/pci.h>
20 #include <linux/pci_hotplug.h>
21 #include <linux/delay.h>
22 #include <linux/sched/signal.h> /* signal_pending(), struct timer_list */
23 #include <linux/mutex.h>
24 #include <linux/workqueue.h>
25
26 #if !defined(MODULE)
27 #define MY_NAME "shpchp"
28 #else
29 #define MY_NAME THIS_MODULE->name
30 #endif
31
32 extern bool shpchp_poll_mode;
33 extern int shpchp_poll_time;
34 extern bool shpchp_debug;
35
36 #define dbg(format, arg...) \
37 do { \
38 if (shpchp_debug) \
39 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
40 } while (0)
41 #define err(format, arg...) \
42 printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
43 #define info(format, arg...) \
44 printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
45 #define warn(format, arg...) \
46 printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
47
48 #define ctrl_dbg(ctrl, format, arg...) \
49 do { \
50 if (shpchp_debug) \
51 pci_printk(KERN_DEBUG, ctrl->pci_dev, \
52 format, ## arg); \
53 } while (0)
54 #define ctrl_err(ctrl, format, arg...) \
55 pci_err(ctrl->pci_dev, format, ## arg)
56 #define ctrl_info(ctrl, format, arg...) \
57 pci_info(ctrl->pci_dev, format, ## arg)
58 #define ctrl_warn(ctrl, format, arg...) \
59 pci_warn(ctrl->pci_dev, format, ## arg)
60
61
62 #define SLOT_NAME_SIZE 10
63 struct slot {
64 u8 bus;
65 u8 device;
66 u16 status;
67 u32 number;
68 u8 is_a_board;
69 u8 state;
70 u8 attention_save;
71 u8 presence_save;
72 u8 latch_save;
73 u8 pwr_save;
74 struct controller *ctrl;
75 const struct hpc_ops *hpc_ops;
76 struct hotplug_slot hotplug_slot;
77 struct list_head slot_list;
78 struct delayed_work work; /* work for button event */
79 struct mutex lock;
80 struct workqueue_struct *wq;
81 u8 hp_slot;
82 };
83
84 struct event_info {
85 u32 event_type;
86 struct slot *p_slot;
87 struct work_struct work;
88 };
89
90 struct controller {
91 struct mutex crit_sect; /* critical section mutex */
92 struct mutex cmd_lock; /* command lock */
93 int num_slots; /* Number of slots on ctlr */
94 int slot_num_inc; /* 1 or -1 */
95 struct pci_dev *pci_dev;
96 struct list_head slot_list;
97 const struct hpc_ops *hpc_ops;
98 wait_queue_head_t queue; /* sleep & wake process */
99 u8 slot_device_offset;
100 u32 pcix_misc2_reg; /* for amd pogo errata */
101 u32 first_slot; /* First physical slot number */
102 u32 cap_offset;
103 unsigned long mmio_base;
104 unsigned long mmio_size;
105 void __iomem *creg;
106 struct timer_list poll_timer;
107 };
108
109 /* Define AMD SHPC ID */
110 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
111
112 /* AMD PCI-X bridge registers */
113 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
114 #define PCIX_MISCII_OFFSET 0x48
115 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
116
117 /* AMD PCIX_MISCII masks and offsets */
118 #define PERRNONFATALENABLE_MASK 0x00040000
119 #define PERRFATALENABLE_MASK 0x00080000
120 #define PERRFLOODENABLE_MASK 0x00100000
121 #define SERRNONFATALENABLE_MASK 0x00200000
122 #define SERRFATALENABLE_MASK 0x00400000
123
124 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
125 #define PERR_OBSERVED_MASK 0x00000001
126
127 /* AMD PCIX_MEM_BASE_LIMIT masks */
128 #define RSE_MASK 0x40000000
129
130 #define INT_BUTTON_IGNORE 0
131 #define INT_PRESENCE_ON 1
132 #define INT_PRESENCE_OFF 2
133 #define INT_SWITCH_CLOSE 3
134 #define INT_SWITCH_OPEN 4
135 #define INT_POWER_FAULT 5
136 #define INT_POWER_FAULT_CLEAR 6
137 #define INT_BUTTON_PRESS 7
138 #define INT_BUTTON_RELEASE 8
139 #define INT_BUTTON_CANCEL 9
140
141 #define STATIC_STATE 0
142 #define BLINKINGON_STATE 1
143 #define BLINKINGOFF_STATE 2
144 #define POWERON_STATE 3
145 #define POWEROFF_STATE 4
146
147 /* Error messages */
148 #define INTERLOCK_OPEN 0x00000002
149 #define ADD_NOT_SUPPORTED 0x00000003
150 #define CARD_FUNCTIONING 0x00000005
151 #define ADAPTER_NOT_SAME 0x00000006
152 #define NO_ADAPTER_PRESENT 0x00000009
153 #define NOT_ENOUGH_RESOURCES 0x0000000B
154 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
155 #define WRONG_BUS_FREQUENCY 0x0000000D
156 #define POWER_FAILURE 0x0000000E
157
158 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
159 void shpchp_remove_ctrl_files(struct controller *ctrl);
160 int shpchp_sysfs_enable_slot(struct slot *slot);
161 int shpchp_sysfs_disable_slot(struct slot *slot);
162 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
163 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
164 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
165 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
166 int shpchp_configure_device(struct slot *p_slot);
167 void shpchp_unconfigure_device(struct slot *p_slot);
168 void cleanup_slots(struct controller *ctrl);
169 void shpchp_queue_pushbutton_work(struct work_struct *work);
170 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
171
slot_name(struct slot * slot)172 static inline const char *slot_name(struct slot *slot)
173 {
174 return hotplug_slot_name(&slot->hotplug_slot);
175 }
176
177 struct ctrl_reg {
178 volatile u32 base_offset;
179 volatile u32 slot_avail1;
180 volatile u32 slot_avail2;
181 volatile u32 slot_config;
182 volatile u16 sec_bus_config;
183 volatile u8 msi_ctrl;
184 volatile u8 prog_interface;
185 volatile u16 cmd;
186 volatile u16 cmd_status;
187 volatile u32 intr_loc;
188 volatile u32 serr_loc;
189 volatile u32 serr_intr_enable;
190 volatile u32 slot1;
191 } __attribute__ ((packed));
192
193 /* offsets to the controller registers based on the above structure layout */
194 enum ctrl_offsets {
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
199 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
201 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
204 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
205 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
206 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
207 SLOT1 = offsetof(struct ctrl_reg, slot1),
208 };
209
get_slot(struct hotplug_slot * hotplug_slot)210 static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
211 {
212 return container_of(hotplug_slot, struct slot, hotplug_slot);
213 }
214
shpchp_find_slot(struct controller * ctrl,u8 device)215 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
216 {
217 struct slot *slot;
218
219 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
220 if (slot->device == device)
221 return slot;
222 }
223
224 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
225 return NULL;
226 }
227
amd_pogo_errata_save_misc_reg(struct slot * p_slot)228 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
229 {
230 u32 pcix_misc2_temp;
231
232 /* save MiscII register */
233 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
234
235 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
236
237 /* clear SERR/PERR enable bits */
238 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
239 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
240 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
241 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
242 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
243 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
244 }
245
amd_pogo_errata_restore_misc_reg(struct slot * p_slot)246 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
247 {
248 u32 pcix_misc2_temp;
249 u32 pcix_bridge_errors_reg;
250 u32 pcix_mem_base_reg;
251 u8 perr_set;
252 u8 rse_set;
253
254 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
255 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
256 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
257 if (perr_set) {
258 ctrl_dbg(p_slot->ctrl,
259 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
260 perr_set);
261
262 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
263 }
264
265 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
266 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
267 rse_set = pcix_mem_base_reg & RSE_MASK;
268 if (rse_set) {
269 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
270
271 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
272 }
273 /* restore MiscII register */
274 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
275
276 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
277 pcix_misc2_temp |= SERRFATALENABLE_MASK;
278 else
279 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
280
281 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
282 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
283 else
284 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
285
286 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
287 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
288 else
289 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
290
291 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
292 pcix_misc2_temp |= PERRFATALENABLE_MASK;
293 else
294 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
295
296 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
297 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
298 else
299 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
300 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
301 }
302
303 struct hpc_ops {
304 int (*power_on_slot)(struct slot *slot);
305 int (*slot_enable)(struct slot *slot);
306 int (*slot_disable)(struct slot *slot);
307 int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
308 int (*get_power_status)(struct slot *slot, u8 *status);
309 int (*get_attention_status)(struct slot *slot, u8 *status);
310 int (*set_attention_status)(struct slot *slot, u8 status);
311 int (*get_latch_status)(struct slot *slot, u8 *status);
312 int (*get_adapter_status)(struct slot *slot, u8 *status);
313 int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
314 int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
315 int (*get_prog_int)(struct slot *slot, u8 *prog_int);
316 int (*query_power_fault)(struct slot *slot);
317 void (*green_led_on)(struct slot *slot);
318 void (*green_led_off)(struct slot *slot);
319 void (*green_led_blink)(struct slot *slot);
320 void (*release_ctlr)(struct controller *ctrl);
321 int (*check_cmd_status)(struct controller *ctrl);
322 };
323
324 #endif /* _SHPCHP_H */
325