1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Microsemi/Microchip SoCs serial gpio driver
4 *
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
6 *
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/gpio/driver.h>
14 #include <linux/io.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/module.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/spinlock.h>
22
23 #include "core.h"
24 #include "pinconf.h"
25
26 #define SGPIO_BITS_PER_WORD 32
27 #define SGPIO_MAX_BITS 4
28 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
29
30 enum {
31 REG_INPUT_DATA,
32 REG_PORT_CONFIG,
33 REG_PORT_ENABLE,
34 REG_SIO_CONFIG,
35 REG_SIO_CLOCK,
36 REG_INT_POLARITY,
37 REG_INT_TRIGGER,
38 REG_INT_ACK,
39 REG_INT_ENABLE,
40 REG_INT_IDENT,
41 MAXREG
42 };
43
44 enum {
45 SGPIO_ARCH_LUTON,
46 SGPIO_ARCH_OCELOT,
47 SGPIO_ARCH_SPARX5,
48 };
49
50 enum {
51 SGPIO_FLAGS_HAS_IRQ = BIT(0),
52 };
53
54 struct sgpio_properties {
55 int arch;
56 int flags;
57 u8 regoff[MAXREG];
58 };
59
60 #define SGPIO_LUTON_AUTO_REPEAT BIT(5)
61 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
62 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
63 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
64
65 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
66 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
67 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
68 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
69
70 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
71 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
72 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
73 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
74
75 #define SGPIO_MASTER_INTR_ENA BIT(0)
76
77 #define SGPIO_INT_TRG_LEVEL 0
78 #define SGPIO_INT_TRG_EDGE 1
79 #define SGPIO_INT_TRG_EDGE_FALL 2
80 #define SGPIO_INT_TRG_EDGE_RISE 3
81
82 #define SGPIO_TRG_LEVEL_HIGH 0
83 #define SGPIO_TRG_LEVEL_LOW 1
84
85 static const struct sgpio_properties properties_luton = {
86 .arch = SGPIO_ARCH_LUTON,
87 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
88 };
89
90 static const struct sgpio_properties properties_ocelot = {
91 .arch = SGPIO_ARCH_OCELOT,
92 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
93 };
94
95 static const struct sgpio_properties properties_sparx5 = {
96 .arch = SGPIO_ARCH_SPARX5,
97 .flags = SGPIO_FLAGS_HAS_IRQ,
98 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
99 };
100
101 static const char * const functions[] = { "gpio" };
102
103 struct sgpio_bank {
104 struct sgpio_priv *priv;
105 bool is_input;
106 struct gpio_chip gpio;
107 struct pinctrl_desc pctl_desc;
108 };
109
110 struct sgpio_priv {
111 struct device *dev;
112 struct sgpio_bank in;
113 struct sgpio_bank out;
114 u32 bitcount;
115 u32 ports;
116 u32 clock;
117 u32 __iomem *regs;
118 const struct sgpio_properties *properties;
119 spinlock_t lock;
120 };
121
122 struct sgpio_port_addr {
123 u8 port;
124 u8 bit;
125 };
126
sgpio_pin_to_addr(struct sgpio_priv * priv,int pin,struct sgpio_port_addr * addr)127 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
128 struct sgpio_port_addr *addr)
129 {
130 addr->port = pin / priv->bitcount;
131 addr->bit = pin % priv->bitcount;
132 }
133
sgpio_addr_to_pin(struct sgpio_priv * priv,int port,int bit)134 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
135 {
136 return bit + port * priv->bitcount;
137 }
138
sgpio_readl(struct sgpio_priv * priv,u32 rno,u32 off)139 static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
140 {
141 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
142
143 return readl(reg);
144 }
145
sgpio_writel(struct sgpio_priv * priv,u32 val,u32 rno,u32 off)146 static inline void sgpio_writel(struct sgpio_priv *priv,
147 u32 val, u32 rno, u32 off)
148 {
149 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
150
151 writel(val, reg);
152 }
153
sgpio_clrsetbits(struct sgpio_priv * priv,u32 rno,u32 off,u32 clear,u32 set)154 static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
155 u32 rno, u32 off, u32 clear, u32 set)
156 {
157 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
158 u32 val = readl(reg);
159
160 val &= ~clear;
161 val |= set;
162
163 writel(val, reg);
164 }
165
sgpio_configure_bitstream(struct sgpio_priv * priv)166 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
167 {
168 int width = priv->bitcount - 1;
169 u32 clr, set;
170
171 switch (priv->properties->arch) {
172 case SGPIO_ARCH_LUTON:
173 clr = SGPIO_LUTON_PORT_WIDTH;
174 set = SGPIO_LUTON_AUTO_REPEAT |
175 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
176 break;
177 case SGPIO_ARCH_OCELOT:
178 clr = SGPIO_OCELOT_PORT_WIDTH;
179 set = SGPIO_OCELOT_AUTO_REPEAT |
180 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
181 break;
182 case SGPIO_ARCH_SPARX5:
183 clr = SGPIO_SPARX5_PORT_WIDTH;
184 set = SGPIO_SPARX5_AUTO_REPEAT |
185 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
186 break;
187 default:
188 return;
189 }
190 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
191 }
192
sgpio_configure_clock(struct sgpio_priv * priv,u32 clkfrq)193 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
194 {
195 u32 clr, set;
196
197 switch (priv->properties->arch) {
198 case SGPIO_ARCH_LUTON:
199 clr = SGPIO_LUTON_CLK_FREQ;
200 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
201 break;
202 case SGPIO_ARCH_OCELOT:
203 clr = SGPIO_OCELOT_CLK_FREQ;
204 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
205 break;
206 case SGPIO_ARCH_SPARX5:
207 clr = SGPIO_SPARX5_CLK_FREQ;
208 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
209 break;
210 default:
211 return;
212 }
213 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
214 }
215
sgpio_output_set(struct sgpio_priv * priv,struct sgpio_port_addr * addr,int value)216 static void sgpio_output_set(struct sgpio_priv *priv,
217 struct sgpio_port_addr *addr,
218 int value)
219 {
220 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
221 unsigned long flags;
222 u32 clr, set;
223
224 switch (priv->properties->arch) {
225 case SGPIO_ARCH_LUTON:
226 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
227 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
228 break;
229 case SGPIO_ARCH_OCELOT:
230 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
231 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
232 break;
233 case SGPIO_ARCH_SPARX5:
234 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
235 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
236 break;
237 default:
238 return;
239 }
240
241 spin_lock_irqsave(&priv->lock, flags);
242 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set);
243 spin_unlock_irqrestore(&priv->lock, flags);
244 }
245
sgpio_output_get(struct sgpio_priv * priv,struct sgpio_port_addr * addr)246 static int sgpio_output_get(struct sgpio_priv *priv,
247 struct sgpio_port_addr *addr)
248 {
249 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
250 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
251
252 switch (priv->properties->arch) {
253 case SGPIO_ARCH_LUTON:
254 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
255 break;
256 case SGPIO_ARCH_OCELOT:
257 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
258 break;
259 case SGPIO_ARCH_SPARX5:
260 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
261 break;
262 default:
263 val = 0;
264 break;
265 }
266 return !!(val & BIT(bit));
267 }
268
sgpio_input_get(struct sgpio_priv * priv,struct sgpio_port_addr * addr)269 static int sgpio_input_get(struct sgpio_priv *priv,
270 struct sgpio_port_addr *addr)
271 {
272 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
273 }
274
sgpio_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)275 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
276 unsigned int pin, unsigned long *config)
277 {
278 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
279 u32 param = pinconf_to_config_param(*config);
280 struct sgpio_priv *priv = bank->priv;
281 struct sgpio_port_addr addr;
282 int val;
283
284 sgpio_pin_to_addr(priv, pin, &addr);
285
286 switch (param) {
287 case PIN_CONFIG_INPUT_ENABLE:
288 val = bank->is_input;
289 break;
290
291 case PIN_CONFIG_OUTPUT_ENABLE:
292 val = !bank->is_input;
293 break;
294
295 case PIN_CONFIG_OUTPUT:
296 if (bank->is_input)
297 return -EINVAL;
298 val = sgpio_output_get(priv, &addr);
299 break;
300
301 default:
302 return -ENOTSUPP;
303 }
304
305 *config = pinconf_to_config_packed(param, val);
306
307 return 0;
308 }
309
sgpio_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)310 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
311 unsigned long *configs, unsigned int num_configs)
312 {
313 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
314 struct sgpio_priv *priv = bank->priv;
315 struct sgpio_port_addr addr;
316 int cfg, err = 0;
317 u32 param, arg;
318
319 sgpio_pin_to_addr(priv, pin, &addr);
320
321 for (cfg = 0; cfg < num_configs; cfg++) {
322 param = pinconf_to_config_param(configs[cfg]);
323 arg = pinconf_to_config_argument(configs[cfg]);
324
325 switch (param) {
326 case PIN_CONFIG_OUTPUT:
327 if (bank->is_input)
328 return -EINVAL;
329 sgpio_output_set(priv, &addr, arg);
330 break;
331
332 default:
333 err = -ENOTSUPP;
334 }
335 }
336
337 return err;
338 }
339
340 static const struct pinconf_ops sgpio_confops = {
341 .is_generic = true,
342 .pin_config_get = sgpio_pinconf_get,
343 .pin_config_set = sgpio_pinconf_set,
344 .pin_config_config_dbg_show = pinconf_generic_dump_config,
345 };
346
sgpio_get_functions_count(struct pinctrl_dev * pctldev)347 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
348 {
349 return 1;
350 }
351
sgpio_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)352 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
353 unsigned int function)
354 {
355 return functions[0];
356 }
357
sgpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned * const num_groups)358 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
359 unsigned int function,
360 const char *const **groups,
361 unsigned *const num_groups)
362 {
363 *groups = functions;
364 *num_groups = ARRAY_SIZE(functions);
365
366 return 0;
367 }
368
sgpio_pinmux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)369 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
370 unsigned int selector, unsigned int group)
371 {
372 return 0;
373 }
374
sgpio_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int pin,bool input)375 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
376 struct pinctrl_gpio_range *range,
377 unsigned int pin, bool input)
378 {
379 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
380
381 return (input == bank->is_input) ? 0 : -EINVAL;
382 }
383
sgpio_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)384 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
385 struct pinctrl_gpio_range *range,
386 unsigned int offset)
387 {
388 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
389 struct sgpio_priv *priv = bank->priv;
390 struct sgpio_port_addr addr;
391
392 sgpio_pin_to_addr(priv, offset, &addr);
393
394 if ((priv->ports & BIT(addr.port)) == 0) {
395 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
396 addr.port, addr.bit);
397 return -EINVAL;
398 }
399
400 return 0;
401 }
402
403 static const struct pinmux_ops sgpio_pmx_ops = {
404 .get_functions_count = sgpio_get_functions_count,
405 .get_function_name = sgpio_get_function_name,
406 .get_function_groups = sgpio_get_function_groups,
407 .set_mux = sgpio_pinmux_set_mux,
408 .gpio_set_direction = sgpio_gpio_set_direction,
409 .gpio_request_enable = sgpio_gpio_request_enable,
410 };
411
sgpio_pctl_get_groups_count(struct pinctrl_dev * pctldev)412 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
413 {
414 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
415
416 return bank->pctl_desc.npins;
417 }
418
sgpio_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)419 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
420 unsigned int group)
421 {
422 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
423
424 return bank->pctl_desc.pins[group].name;
425 }
426
sgpio_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)427 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
428 unsigned int group,
429 const unsigned int **pins,
430 unsigned int *num_pins)
431 {
432 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
433
434 *pins = &bank->pctl_desc.pins[group].number;
435 *num_pins = 1;
436
437 return 0;
438 }
439
440 static const struct pinctrl_ops sgpio_pctl_ops = {
441 .get_groups_count = sgpio_pctl_get_groups_count,
442 .get_group_name = sgpio_pctl_get_group_name,
443 .get_group_pins = sgpio_pctl_get_group_pins,
444 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
445 .dt_free_map = pinconf_generic_dt_free_map,
446 };
447
microchip_sgpio_direction_input(struct gpio_chip * gc,unsigned int gpio)448 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
449 {
450 struct sgpio_bank *bank = gpiochip_get_data(gc);
451
452 /* Fixed-position function */
453 return bank->is_input ? 0 : -EINVAL;
454 }
455
microchip_sgpio_direction_output(struct gpio_chip * gc,unsigned int gpio,int value)456 static int microchip_sgpio_direction_output(struct gpio_chip *gc,
457 unsigned int gpio, int value)
458 {
459 struct sgpio_bank *bank = gpiochip_get_data(gc);
460 struct sgpio_priv *priv = bank->priv;
461 struct sgpio_port_addr addr;
462
463 /* Fixed-position function */
464 if (bank->is_input)
465 return -EINVAL;
466
467 sgpio_pin_to_addr(priv, gpio, &addr);
468
469 sgpio_output_set(priv, &addr, value);
470
471 return 0;
472 }
473
microchip_sgpio_get_direction(struct gpio_chip * gc,unsigned int gpio)474 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
475 {
476 struct sgpio_bank *bank = gpiochip_get_data(gc);
477
478 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
479 }
480
microchip_sgpio_set_value(struct gpio_chip * gc,unsigned int gpio,int value)481 static void microchip_sgpio_set_value(struct gpio_chip *gc,
482 unsigned int gpio, int value)
483 {
484 microchip_sgpio_direction_output(gc, gpio, value);
485 }
486
microchip_sgpio_get_value(struct gpio_chip * gc,unsigned int gpio)487 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
488 {
489 struct sgpio_bank *bank = gpiochip_get_data(gc);
490 struct sgpio_priv *priv = bank->priv;
491 struct sgpio_port_addr addr;
492
493 sgpio_pin_to_addr(priv, gpio, &addr);
494
495 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
496 }
497
microchip_sgpio_of_xlate(struct gpio_chip * gc,const struct of_phandle_args * gpiospec,u32 * flags)498 static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
499 const struct of_phandle_args *gpiospec,
500 u32 *flags)
501 {
502 struct sgpio_bank *bank = gpiochip_get_data(gc);
503 struct sgpio_priv *priv = bank->priv;
504 int pin;
505
506 /*
507 * Note that the SGIO pin is defined by *2* numbers, a port
508 * number between 0 and 31, and a bit index, 0 to 3.
509 */
510 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
511 gpiospec->args[1] > priv->bitcount)
512 return -EINVAL;
513
514 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
515
516 if (pin > gc->ngpio)
517 return -EINVAL;
518
519 if (flags)
520 *flags = gpiospec->args[2];
521
522 return pin;
523 }
524
microchip_sgpio_get_ports(struct sgpio_priv * priv)525 static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
526 {
527 const char *range_property_name = "microchip,sgpio-port-ranges";
528 struct device *dev = priv->dev;
529 u32 range_params[64];
530 int i, nranges, ret;
531
532 /* Calculate port mask */
533 nranges = device_property_count_u32(dev, range_property_name);
534 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
535 dev_err(dev, "%s port range: '%s' property\n",
536 nranges == -EINVAL ? "Missing" : "Invalid",
537 range_property_name);
538 return -EINVAL;
539 }
540
541 ret = device_property_read_u32_array(dev, range_property_name,
542 range_params, nranges);
543 if (ret) {
544 dev_err(dev, "failed to parse '%s' property: %d\n",
545 range_property_name, ret);
546 return ret;
547 }
548 for (i = 0; i < nranges; i += 2) {
549 int start, end;
550
551 start = range_params[i];
552 end = range_params[i + 1];
553 if (start > end || end >= SGPIO_BITS_PER_WORD) {
554 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
555 start, end);
556 }
557 priv->ports |= GENMASK(end, start);
558 }
559
560 return 0;
561 }
562
microchip_sgpio_irq_settype(struct irq_data * data,int type,int polarity)563 static void microchip_sgpio_irq_settype(struct irq_data *data,
564 int type,
565 int polarity)
566 {
567 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
568 struct sgpio_bank *bank = gpiochip_get_data(chip);
569 unsigned int gpio = irqd_to_hwirq(data);
570 struct sgpio_port_addr addr;
571 unsigned long flags;
572 u32 ena;
573
574 sgpio_pin_to_addr(bank->priv, gpio, &addr);
575
576 spin_lock_irqsave(&bank->priv->lock, flags);
577
578 /* Disable interrupt while changing type */
579 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
580 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
581
582 /* Type value spread over 2 registers sets: low, high bit */
583 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
584 BIT(addr.port), (!!(type & 0x1)) << addr.port);
585 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
586 BIT(addr.port), (!!(type & 0x2)) << addr.port);
587
588 if (type == SGPIO_INT_TRG_LEVEL)
589 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
590 BIT(addr.port), polarity << addr.port);
591
592 /* Possibly re-enable interrupts */
593 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
594
595 spin_unlock_irqrestore(&bank->priv->lock, flags);
596 }
597
microchip_sgpio_irq_setreg(struct irq_data * data,int reg,bool clear)598 static void microchip_sgpio_irq_setreg(struct irq_data *data,
599 int reg,
600 bool clear)
601 {
602 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
603 struct sgpio_bank *bank = gpiochip_get_data(chip);
604 unsigned int gpio = irqd_to_hwirq(data);
605 struct sgpio_port_addr addr;
606 unsigned long flags;
607
608 sgpio_pin_to_addr(bank->priv, gpio, &addr);
609
610 spin_lock_irqsave(&bank->priv->lock, flags);
611 if (clear)
612 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
613 else
614 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
615 spin_unlock_irqrestore(&bank->priv->lock, flags);
616 }
617
microchip_sgpio_irq_mask(struct irq_data * data)618 static void microchip_sgpio_irq_mask(struct irq_data *data)
619 {
620 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
621 }
622
microchip_sgpio_irq_unmask(struct irq_data * data)623 static void microchip_sgpio_irq_unmask(struct irq_data *data)
624 {
625 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
626 }
627
microchip_sgpio_irq_ack(struct irq_data * data)628 static void microchip_sgpio_irq_ack(struct irq_data *data)
629 {
630 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);
631 }
632
microchip_sgpio_irq_set_type(struct irq_data * data,unsigned int type)633 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
634 {
635 type &= IRQ_TYPE_SENSE_MASK;
636
637 switch (type) {
638 case IRQ_TYPE_EDGE_BOTH:
639 irq_set_handler_locked(data, handle_edge_irq);
640 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
641 break;
642 case IRQ_TYPE_EDGE_RISING:
643 irq_set_handler_locked(data, handle_edge_irq);
644 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
645 break;
646 case IRQ_TYPE_EDGE_FALLING:
647 irq_set_handler_locked(data, handle_edge_irq);
648 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
649 break;
650 case IRQ_TYPE_LEVEL_HIGH:
651 irq_set_handler_locked(data, handle_level_irq);
652 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
653 break;
654 case IRQ_TYPE_LEVEL_LOW:
655 irq_set_handler_locked(data, handle_level_irq);
656 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
657 break;
658 default:
659 return -EINVAL;
660 }
661
662 return 0;
663 }
664
665 static const struct irq_chip microchip_sgpio_irqchip = {
666 .name = "gpio",
667 .irq_mask = microchip_sgpio_irq_mask,
668 .irq_ack = microchip_sgpio_irq_ack,
669 .irq_unmask = microchip_sgpio_irq_unmask,
670 .irq_set_type = microchip_sgpio_irq_set_type,
671 };
672
sgpio_irq_handler(struct irq_desc * desc)673 static void sgpio_irq_handler(struct irq_desc *desc)
674 {
675 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
676 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
677 struct sgpio_bank *bank = gpiochip_get_data(chip);
678 struct sgpio_priv *priv = bank->priv;
679 int bit, port, gpio;
680 long val;
681
682 for (bit = 0; bit < priv->bitcount; bit++) {
683 val = sgpio_readl(priv, REG_INT_IDENT, bit);
684 if (!val)
685 continue;
686
687 chained_irq_enter(parent_chip, desc);
688
689 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
690 gpio = sgpio_addr_to_pin(priv, port, bit);
691 generic_handle_domain_irq(chip->irq.domain, gpio);
692 }
693
694 chained_irq_exit(parent_chip, desc);
695 }
696 }
697
microchip_sgpio_register_bank(struct device * dev,struct sgpio_priv * priv,struct fwnode_handle * fwnode,int bankno)698 static int microchip_sgpio_register_bank(struct device *dev,
699 struct sgpio_priv *priv,
700 struct fwnode_handle *fwnode,
701 int bankno)
702 {
703 struct pinctrl_pin_desc *pins;
704 struct pinctrl_desc *pctl_desc;
705 struct pinctrl_dev *pctldev;
706 struct sgpio_bank *bank;
707 struct gpio_chip *gc;
708 u32 ngpios;
709 int i, ret;
710
711 /* Get overall bank struct */
712 bank = (bankno == 0) ? &priv->in : &priv->out;
713 bank->priv = priv;
714
715 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
716 dev_info(dev, "failed to get number of gpios for bank%d\n",
717 bankno);
718 ngpios = 64;
719 }
720
721 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
722 if (priv->bitcount > SGPIO_MAX_BITS) {
723 dev_err(dev, "Bit width exceeds maximum (%d)\n",
724 SGPIO_MAX_BITS);
725 return -EINVAL;
726 }
727
728 pctl_desc = &bank->pctl_desc;
729 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
730 dev_name(dev),
731 bank->is_input ? "in" : "out");
732 if (!pctl_desc->name)
733 return -ENOMEM;
734
735 pctl_desc->pctlops = &sgpio_pctl_ops;
736 pctl_desc->pmxops = &sgpio_pmx_ops;
737 pctl_desc->confops = &sgpio_confops;
738 pctl_desc->owner = THIS_MODULE;
739
740 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
741 if (!pins)
742 return -ENOMEM;
743
744 pctl_desc->npins = ngpios;
745 pctl_desc->pins = pins;
746
747 for (i = 0; i < ngpios; i++) {
748 struct sgpio_port_addr addr;
749
750 sgpio_pin_to_addr(priv, i, &addr);
751
752 pins[i].number = i;
753 pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
754 "SGPIO_%c_p%db%d",
755 bank->is_input ? 'I' : 'O',
756 addr.port, addr.bit);
757 if (!pins[i].name)
758 return -ENOMEM;
759 }
760
761 pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
762 if (IS_ERR(pctldev))
763 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
764
765 gc = &bank->gpio;
766 gc->label = pctl_desc->name;
767 gc->parent = dev;
768 gc->of_node = to_of_node(fwnode);
769 gc->owner = THIS_MODULE;
770 gc->get_direction = microchip_sgpio_get_direction;
771 gc->direction_input = microchip_sgpio_direction_input;
772 gc->direction_output = microchip_sgpio_direction_output;
773 gc->get = microchip_sgpio_get_value;
774 gc->set = microchip_sgpio_set_value;
775 gc->request = gpiochip_generic_request;
776 gc->free = gpiochip_generic_free;
777 gc->of_xlate = microchip_sgpio_of_xlate;
778 gc->of_gpio_n_cells = 3;
779 gc->base = -1;
780 gc->ngpio = ngpios;
781
782 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
783 int irq = fwnode_irq_get(fwnode, 0);
784
785 if (irq) {
786 struct gpio_irq_chip *girq = &gc->irq;
787
788 girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip,
789 sizeof(microchip_sgpio_irqchip),
790 GFP_KERNEL);
791 if (!girq->chip)
792 return -ENOMEM;
793 girq->parent_handler = sgpio_irq_handler;
794 girq->num_parents = 1;
795 girq->parents = devm_kcalloc(dev, 1,
796 sizeof(*girq->parents),
797 GFP_KERNEL);
798 if (!girq->parents)
799 return -ENOMEM;
800 girq->parents[0] = irq;
801 girq->default_type = IRQ_TYPE_NONE;
802 girq->handler = handle_bad_irq;
803
804 /* Disable all individual pins */
805 for (i = 0; i < SGPIO_MAX_BITS; i++)
806 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
807 /* Master enable */
808 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
809 }
810 }
811
812 ret = devm_gpiochip_add_data(dev, gc, bank);
813 if (ret)
814 dev_err(dev, "Failed to register: ret %d\n", ret);
815
816 return ret;
817 }
818
microchip_sgpio_probe(struct platform_device * pdev)819 static int microchip_sgpio_probe(struct platform_device *pdev)
820 {
821 int div_clock = 0, ret, port, i, nbanks;
822 struct device *dev = &pdev->dev;
823 struct fwnode_handle *fwnode;
824 struct reset_control *reset;
825 struct sgpio_priv *priv;
826 struct clk *clk;
827 u32 val;
828
829 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
830 if (!priv)
831 return -ENOMEM;
832
833 priv->dev = dev;
834 spin_lock_init(&priv->lock);
835
836 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
837 if (IS_ERR(reset))
838 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
839 reset_control_reset(reset);
840
841 clk = devm_clk_get(dev, NULL);
842 if (IS_ERR(clk))
843 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
844
845 div_clock = clk_get_rate(clk);
846 if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
847 priv->clock = 12500000;
848 if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
849 dev_err(dev, "Invalid frequency %d\n", priv->clock);
850 return -EINVAL;
851 }
852
853 priv->regs = devm_platform_ioremap_resource(pdev, 0);
854 if (IS_ERR(priv->regs))
855 return PTR_ERR(priv->regs);
856 priv->properties = device_get_match_data(dev);
857 priv->in.is_input = true;
858
859 /* Get rest of device properties */
860 ret = microchip_sgpio_get_ports(priv);
861 if (ret)
862 return ret;
863
864 nbanks = device_get_child_node_count(dev);
865 if (nbanks != 2) {
866 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
867 return -EINVAL;
868 }
869
870 i = 0;
871 device_for_each_child_node(dev, fwnode) {
872 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
873 if (ret) {
874 fwnode_handle_put(fwnode);
875 return ret;
876 }
877 }
878
879 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
880 dev_err(dev, "Banks must have same GPIO count\n");
881 return -ERANGE;
882 }
883
884 sgpio_configure_bitstream(priv);
885
886 val = max(2U, div_clock / priv->clock);
887 sgpio_configure_clock(priv, val);
888
889 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
890 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
891 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
892
893 return 0;
894 }
895
896 static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
897 {
898 .compatible = "microchip,sparx5-sgpio",
899 .data = &properties_sparx5,
900 }, {
901 .compatible = "mscc,luton-sgpio",
902 .data = &properties_luton,
903 }, {
904 .compatible = "mscc,ocelot-sgpio",
905 .data = &properties_ocelot,
906 }, {
907 /* sentinel */
908 }
909 };
910
911 static struct platform_driver microchip_sgpio_pinctrl_driver = {
912 .driver = {
913 .name = "pinctrl-microchip-sgpio",
914 .of_match_table = microchip_sgpio_gpio_of_match,
915 .suppress_bind_attrs = true,
916 },
917 .probe = microchip_sgpio_probe,
918 };
919 builtin_platform_driver(microchip_sgpio_pinctrl_driver);
920