1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020 Linaro Ltd.
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/pinctrl/pinconf.h>
17 #include <linux/pinctrl/pinmux.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/types.h>
21 #include "../core.h"
22 #include "../pinctrl-utils.h"
23
24 #define LPI_SLEW_RATE_CTL_REG 0xa000
25 #define LPI_TLMM_REG_OFFSET 0x1000
26 #define LPI_SLEW_RATE_MAX 0x03
27 #define LPI_SLEW_BITS_SIZE 0x02
28 #define LPI_SLEW_RATE_MASK GENMASK(1, 0)
29 #define LPI_GPIO_CFG_REG 0x00
30 #define LPI_GPIO_PULL_MASK GENMASK(1, 0)
31 #define LPI_GPIO_FUNCTION_MASK GENMASK(5, 2)
32 #define LPI_GPIO_OUT_STRENGTH_MASK GENMASK(8, 6)
33 #define LPI_GPIO_OE_MASK BIT(9)
34 #define LPI_GPIO_VALUE_REG 0x04
35 #define LPI_GPIO_VALUE_IN_MASK BIT(0)
36 #define LPI_GPIO_VALUE_OUT_MASK BIT(1)
37
38 #define LPI_GPIO_BIAS_DISABLE 0x0
39 #define LPI_GPIO_PULL_DOWN 0x1
40 #define LPI_GPIO_KEEPER 0x2
41 #define LPI_GPIO_PULL_UP 0x3
42 #define LPI_GPIO_DS_TO_VAL(v) (v / 2 - 1)
43 #define NO_SLEW -1
44
45 #define LPI_FUNCTION(fname) \
46 [LPI_MUX_##fname] = { \
47 .name = #fname, \
48 .groups = fname##_groups, \
49 .ngroups = ARRAY_SIZE(fname##_groups), \
50 }
51
52 #define LPI_PINGROUP(id, soff, f1, f2, f3, f4) \
53 { \
54 .name = "gpio" #id, \
55 .pins = gpio##id##_pins, \
56 .pin = id, \
57 .slew_offset = soff, \
58 .npins = ARRAY_SIZE(gpio##id##_pins), \
59 .funcs = (int[]){ \
60 LPI_MUX_gpio, \
61 LPI_MUX_##f1, \
62 LPI_MUX_##f2, \
63 LPI_MUX_##f3, \
64 LPI_MUX_##f4, \
65 }, \
66 .nfuncs = 5, \
67 }
68
69 struct lpi_pingroup {
70 const char *name;
71 const unsigned int *pins;
72 unsigned int npins;
73 unsigned int pin;
74 /* Bit offset in slew register for SoundWire pins only */
75 int slew_offset;
76 unsigned int *funcs;
77 unsigned int nfuncs;
78 };
79
80 struct lpi_function {
81 const char *name;
82 const char * const *groups;
83 unsigned int ngroups;
84 };
85
86 struct lpi_pinctrl_variant_data {
87 const struct pinctrl_pin_desc *pins;
88 int npins;
89 const struct lpi_pingroup *groups;
90 int ngroups;
91 const struct lpi_function *functions;
92 int nfunctions;
93 };
94
95 #define MAX_LPI_NUM_CLKS 2
96
97 struct lpi_pinctrl {
98 struct device *dev;
99 struct pinctrl_dev *ctrl;
100 struct gpio_chip chip;
101 struct pinctrl_desc desc;
102 char __iomem *tlmm_base;
103 char __iomem *slew_base;
104 struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
105 /* Protects from concurrent register updates */
106 struct mutex lock;
107 const struct lpi_pinctrl_variant_data *data;
108 };
109
110 /* sm8250 variant specific data */
111 static const struct pinctrl_pin_desc sm8250_lpi_pins[] = {
112 PINCTRL_PIN(0, "gpio0"),
113 PINCTRL_PIN(1, "gpio1"),
114 PINCTRL_PIN(2, "gpio2"),
115 PINCTRL_PIN(3, "gpio3"),
116 PINCTRL_PIN(4, "gpio4"),
117 PINCTRL_PIN(5, "gpio5"),
118 PINCTRL_PIN(6, "gpio6"),
119 PINCTRL_PIN(7, "gpio7"),
120 PINCTRL_PIN(8, "gpio8"),
121 PINCTRL_PIN(9, "gpio9"),
122 PINCTRL_PIN(10, "gpio10"),
123 PINCTRL_PIN(11, "gpio11"),
124 PINCTRL_PIN(12, "gpio12"),
125 PINCTRL_PIN(13, "gpio13"),
126 };
127
128 enum sm8250_lpi_functions {
129 LPI_MUX_dmic1_clk,
130 LPI_MUX_dmic1_data,
131 LPI_MUX_dmic2_clk,
132 LPI_MUX_dmic2_data,
133 LPI_MUX_dmic3_clk,
134 LPI_MUX_dmic3_data,
135 LPI_MUX_i2s1_clk,
136 LPI_MUX_i2s1_data,
137 LPI_MUX_i2s1_ws,
138 LPI_MUX_i2s2_clk,
139 LPI_MUX_i2s2_data,
140 LPI_MUX_i2s2_ws,
141 LPI_MUX_qua_mi2s_data,
142 LPI_MUX_qua_mi2s_sclk,
143 LPI_MUX_qua_mi2s_ws,
144 LPI_MUX_swr_rx_clk,
145 LPI_MUX_swr_rx_data,
146 LPI_MUX_swr_tx_clk,
147 LPI_MUX_swr_tx_data,
148 LPI_MUX_wsa_swr_clk,
149 LPI_MUX_wsa_swr_data,
150 LPI_MUX_gpio,
151 LPI_MUX__,
152 };
153
154 static const unsigned int gpio0_pins[] = { 0 };
155 static const unsigned int gpio1_pins[] = { 1 };
156 static const unsigned int gpio2_pins[] = { 2 };
157 static const unsigned int gpio3_pins[] = { 3 };
158 static const unsigned int gpio4_pins[] = { 4 };
159 static const unsigned int gpio5_pins[] = { 5 };
160 static const unsigned int gpio6_pins[] = { 6 };
161 static const unsigned int gpio7_pins[] = { 7 };
162 static const unsigned int gpio8_pins[] = { 8 };
163 static const unsigned int gpio9_pins[] = { 9 };
164 static const unsigned int gpio10_pins[] = { 10 };
165 static const unsigned int gpio11_pins[] = { 11 };
166 static const unsigned int gpio12_pins[] = { 12 };
167 static const unsigned int gpio13_pins[] = { 13 };
168 static const char * const swr_tx_clk_groups[] = { "gpio0" };
169 static const char * const swr_tx_data_groups[] = { "gpio1", "gpio2", "gpio5" };
170 static const char * const swr_rx_clk_groups[] = { "gpio3" };
171 static const char * const swr_rx_data_groups[] = { "gpio4", "gpio5" };
172 static const char * const dmic1_clk_groups[] = { "gpio6" };
173 static const char * const dmic1_data_groups[] = { "gpio7" };
174 static const char * const dmic2_clk_groups[] = { "gpio8" };
175 static const char * const dmic2_data_groups[] = { "gpio9" };
176 static const char * const i2s2_clk_groups[] = { "gpio10" };
177 static const char * const i2s2_ws_groups[] = { "gpio11" };
178 static const char * const dmic3_clk_groups[] = { "gpio12" };
179 static const char * const dmic3_data_groups[] = { "gpio13" };
180 static const char * const qua_mi2s_sclk_groups[] = { "gpio0" };
181 static const char * const qua_mi2s_ws_groups[] = { "gpio1" };
182 static const char * const qua_mi2s_data_groups[] = { "gpio2", "gpio3", "gpio4" };
183 static const char * const i2s1_clk_groups[] = { "gpio6" };
184 static const char * const i2s1_ws_groups[] = { "gpio7" };
185 static const char * const i2s1_data_groups[] = { "gpio8", "gpio9" };
186 static const char * const wsa_swr_clk_groups[] = { "gpio10" };
187 static const char * const wsa_swr_data_groups[] = { "gpio11" };
188 static const char * const i2s2_data_groups[] = { "gpio12", "gpio12" };
189
190 static const struct lpi_pingroup sm8250_groups[] = {
191 LPI_PINGROUP(0, 0, swr_tx_clk, qua_mi2s_sclk, _, _),
192 LPI_PINGROUP(1, 2, swr_tx_data, qua_mi2s_ws, _, _),
193 LPI_PINGROUP(2, 4, swr_tx_data, qua_mi2s_data, _, _),
194 LPI_PINGROUP(3, 8, swr_rx_clk, qua_mi2s_data, _, _),
195 LPI_PINGROUP(4, 10, swr_rx_data, qua_mi2s_data, _, _),
196 LPI_PINGROUP(5, 12, swr_tx_data, swr_rx_data, _, _),
197 LPI_PINGROUP(6, NO_SLEW, dmic1_clk, i2s1_clk, _, _),
198 LPI_PINGROUP(7, NO_SLEW, dmic1_data, i2s1_ws, _, _),
199 LPI_PINGROUP(8, NO_SLEW, dmic2_clk, i2s1_data, _, _),
200 LPI_PINGROUP(9, NO_SLEW, dmic2_data, i2s1_data, _, _),
201 LPI_PINGROUP(10, 16, i2s2_clk, wsa_swr_clk, _, _),
202 LPI_PINGROUP(11, 18, i2s2_ws, wsa_swr_data, _, _),
203 LPI_PINGROUP(12, NO_SLEW, dmic3_clk, i2s2_data, _, _),
204 LPI_PINGROUP(13, NO_SLEW, dmic3_data, i2s2_data, _, _),
205 };
206
207 static const struct lpi_function sm8250_functions[] = {
208 LPI_FUNCTION(dmic1_clk),
209 LPI_FUNCTION(dmic1_data),
210 LPI_FUNCTION(dmic2_clk),
211 LPI_FUNCTION(dmic2_data),
212 LPI_FUNCTION(dmic3_clk),
213 LPI_FUNCTION(dmic3_data),
214 LPI_FUNCTION(i2s1_clk),
215 LPI_FUNCTION(i2s1_data),
216 LPI_FUNCTION(i2s1_ws),
217 LPI_FUNCTION(i2s2_clk),
218 LPI_FUNCTION(i2s2_data),
219 LPI_FUNCTION(i2s2_ws),
220 LPI_FUNCTION(qua_mi2s_data),
221 LPI_FUNCTION(qua_mi2s_sclk),
222 LPI_FUNCTION(qua_mi2s_ws),
223 LPI_FUNCTION(swr_rx_clk),
224 LPI_FUNCTION(swr_rx_data),
225 LPI_FUNCTION(swr_tx_clk),
226 LPI_FUNCTION(swr_tx_data),
227 LPI_FUNCTION(wsa_swr_clk),
228 LPI_FUNCTION(wsa_swr_data),
229 };
230
231 static struct lpi_pinctrl_variant_data sm8250_lpi_data = {
232 .pins = sm8250_lpi_pins,
233 .npins = ARRAY_SIZE(sm8250_lpi_pins),
234 .groups = sm8250_groups,
235 .ngroups = ARRAY_SIZE(sm8250_groups),
236 .functions = sm8250_functions,
237 .nfunctions = ARRAY_SIZE(sm8250_functions),
238 };
239
lpi_gpio_read(struct lpi_pinctrl * state,unsigned int pin,unsigned int addr)240 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
241 unsigned int addr)
242 {
243 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
244 }
245
lpi_gpio_write(struct lpi_pinctrl * state,unsigned int pin,unsigned int addr,unsigned int val)246 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
247 unsigned int addr, unsigned int val)
248 {
249 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
250
251 return 0;
252 }
253
lpi_gpio_get_groups_count(struct pinctrl_dev * pctldev)254 static int lpi_gpio_get_groups_count(struct pinctrl_dev *pctldev)
255 {
256 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
257
258 return pctrl->data->ngroups;
259 }
260
lpi_gpio_get_group_name(struct pinctrl_dev * pctldev,unsigned int group)261 static const char *lpi_gpio_get_group_name(struct pinctrl_dev *pctldev,
262 unsigned int group)
263 {
264 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
265
266 return pctrl->data->groups[group].name;
267 }
268
lpi_gpio_get_group_pins(struct pinctrl_dev * pctldev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)269 static int lpi_gpio_get_group_pins(struct pinctrl_dev *pctldev,
270 unsigned int group,
271 const unsigned int **pins,
272 unsigned int *num_pins)
273 {
274 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
275
276 *pins = pctrl->data->groups[group].pins;
277 *num_pins = pctrl->data->groups[group].npins;
278
279 return 0;
280 }
281
282 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
283 .get_groups_count = lpi_gpio_get_groups_count,
284 .get_group_name = lpi_gpio_get_group_name,
285 .get_group_pins = lpi_gpio_get_group_pins,
286 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
287 .dt_free_map = pinctrl_utils_free_map,
288 };
289
lpi_gpio_get_functions_count(struct pinctrl_dev * pctldev)290 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
291 {
292 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
293
294 return pctrl->data->nfunctions;
295 }
296
lpi_gpio_get_function_name(struct pinctrl_dev * pctldev,unsigned int function)297 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
298 unsigned int function)
299 {
300 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
301
302 return pctrl->data->functions[function].name;
303 }
304
lpi_gpio_get_function_groups(struct pinctrl_dev * pctldev,unsigned int function,const char * const ** groups,unsigned * const num_qgroups)305 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
306 unsigned int function,
307 const char *const **groups,
308 unsigned *const num_qgroups)
309 {
310 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
311
312 *groups = pctrl->data->functions[function].groups;
313 *num_qgroups = pctrl->data->functions[function].ngroups;
314
315 return 0;
316 }
317
lpi_gpio_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group_num)318 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
319 unsigned int group_num)
320 {
321 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
322 const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
323 u32 val;
324 int i, pin = g->pin;
325
326 for (i = 0; i < g->nfuncs; i++) {
327 if (g->funcs[i] == function)
328 break;
329 }
330
331 if (WARN_ON(i == g->nfuncs))
332 return -EINVAL;
333
334 mutex_lock(&pctrl->lock);
335 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
336 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
337 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
338 mutex_unlock(&pctrl->lock);
339
340 return 0;
341 }
342
343 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
344 .get_functions_count = lpi_gpio_get_functions_count,
345 .get_function_name = lpi_gpio_get_function_name,
346 .get_function_groups = lpi_gpio_get_function_groups,
347 .set_mux = lpi_gpio_set_mux,
348 };
349
lpi_config_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)350 static int lpi_config_get(struct pinctrl_dev *pctldev,
351 unsigned int pin, unsigned long *config)
352 {
353 unsigned int param = pinconf_to_config_param(*config);
354 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
355 unsigned int arg = 0;
356 int is_out;
357 int pull;
358 u32 ctl_reg;
359
360 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
361 is_out = ctl_reg & LPI_GPIO_OE_MASK;
362 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
363
364 switch (param) {
365 case PIN_CONFIG_BIAS_DISABLE:
366 if (pull == LPI_GPIO_BIAS_DISABLE)
367 arg = 1;
368 break;
369 case PIN_CONFIG_BIAS_PULL_DOWN:
370 if (pull == LPI_GPIO_PULL_DOWN)
371 arg = 1;
372 break;
373 case PIN_CONFIG_BIAS_BUS_HOLD:
374 if (pull == LPI_GPIO_KEEPER)
375 arg = 1;
376 break;
377 case PIN_CONFIG_BIAS_PULL_UP:
378 if (pull == LPI_GPIO_PULL_UP)
379 arg = 1;
380 break;
381 case PIN_CONFIG_INPUT_ENABLE:
382 case PIN_CONFIG_OUTPUT:
383 if (is_out)
384 arg = 1;
385 break;
386 default:
387 return -EINVAL;
388 }
389
390 *config = pinconf_to_config_packed(param, arg);
391 return 0;
392 }
393
lpi_config_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int nconfs)394 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
395 unsigned long *configs, unsigned int nconfs)
396 {
397 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
398 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
399 bool value, output_enabled = false;
400 const struct lpi_pingroup *g;
401 unsigned long sval;
402 int i, slew_offset;
403 u32 val;
404
405 g = &pctrl->data->groups[group];
406 for (i = 0; i < nconfs; i++) {
407 param = pinconf_to_config_param(configs[i]);
408 arg = pinconf_to_config_argument(configs[i]);
409
410 switch (param) {
411 case PIN_CONFIG_BIAS_DISABLE:
412 pullup = LPI_GPIO_BIAS_DISABLE;
413 break;
414 case PIN_CONFIG_BIAS_PULL_DOWN:
415 pullup = LPI_GPIO_PULL_DOWN;
416 break;
417 case PIN_CONFIG_BIAS_BUS_HOLD:
418 pullup = LPI_GPIO_KEEPER;
419 break;
420 case PIN_CONFIG_BIAS_PULL_UP:
421 pullup = LPI_GPIO_PULL_UP;
422 break;
423 case PIN_CONFIG_INPUT_ENABLE:
424 output_enabled = false;
425 break;
426 case PIN_CONFIG_OUTPUT:
427 output_enabled = true;
428 value = arg;
429 break;
430 case PIN_CONFIG_DRIVE_STRENGTH:
431 strength = arg;
432 break;
433 case PIN_CONFIG_SLEW_RATE:
434 if (arg > LPI_SLEW_RATE_MAX) {
435 dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
436 arg, group);
437 return -EINVAL;
438 }
439
440 slew_offset = g->slew_offset;
441 if (slew_offset == NO_SLEW)
442 break;
443
444 mutex_lock(&pctrl->lock);
445
446 sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
447 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
448 sval |= arg << slew_offset;
449 iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
450
451 mutex_unlock(&pctrl->lock);
452 break;
453 default:
454 return -EINVAL;
455 }
456 }
457
458 /*
459 * As per Hardware Programming Guide, when configuring pin as output,
460 * set the pin value before setting output-enable (OE).
461 */
462 if (output_enabled) {
463 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
464 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
465 }
466
467 mutex_lock(&pctrl->lock);
468 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
469
470 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
471 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
472 LPI_GPIO_OUT_STRENGTH_MASK);
473 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
474
475 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
476 mutex_unlock(&pctrl->lock);
477
478 return 0;
479 }
480
481 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
482 .is_generic = true,
483 .pin_config_group_get = lpi_config_get,
484 .pin_config_group_set = lpi_config_set,
485 };
486
lpi_gpio_direction_input(struct gpio_chip * chip,unsigned int pin)487 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
488 {
489 struct lpi_pinctrl *state = gpiochip_get_data(chip);
490 unsigned long config;
491
492 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
493
494 return lpi_config_set(state->ctrl, pin, &config, 1);
495 }
496
lpi_gpio_direction_output(struct gpio_chip * chip,unsigned int pin,int val)497 static int lpi_gpio_direction_output(struct gpio_chip *chip,
498 unsigned int pin, int val)
499 {
500 struct lpi_pinctrl *state = gpiochip_get_data(chip);
501 unsigned long config;
502
503 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
504
505 return lpi_config_set(state->ctrl, pin, &config, 1);
506 }
507
lpi_gpio_get(struct gpio_chip * chip,unsigned int pin)508 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
509 {
510 struct lpi_pinctrl *state = gpiochip_get_data(chip);
511
512 return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
513 LPI_GPIO_VALUE_IN_MASK;
514 }
515
lpi_gpio_set(struct gpio_chip * chip,unsigned int pin,int value)516 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
517 {
518 struct lpi_pinctrl *state = gpiochip_get_data(chip);
519 unsigned long config;
520
521 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
522
523 lpi_config_set(state->ctrl, pin, &config, 1);
524 }
525
526 #ifdef CONFIG_DEBUG_FS
527 #include <linux/seq_file.h>
528
lpi_regval_to_drive(u32 val)529 static unsigned int lpi_regval_to_drive(u32 val)
530 {
531 return (val + 1) * 2;
532 }
533
lpi_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned int offset,unsigned int gpio)534 static void lpi_gpio_dbg_show_one(struct seq_file *s,
535 struct pinctrl_dev *pctldev,
536 struct gpio_chip *chip,
537 unsigned int offset,
538 unsigned int gpio)
539 {
540 struct lpi_pinctrl *state = gpiochip_get_data(chip);
541 struct pinctrl_pin_desc pindesc;
542 unsigned int func;
543 int is_out;
544 int drive;
545 int pull;
546 u32 ctl_reg;
547
548 static const char * const pulls[] = {
549 "no pull",
550 "pull down",
551 "keeper",
552 "pull up"
553 };
554
555 pctldev = pctldev ? : state->ctrl;
556 pindesc = pctldev->desc->pins[offset];
557 ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
558 is_out = ctl_reg & LPI_GPIO_OE_MASK;
559
560 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
561 drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
562 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
563
564 seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
565 seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
566 seq_printf(s, " %s", pulls[pull]);
567 }
568
lpi_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)569 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
570 {
571 unsigned int gpio = chip->base;
572 unsigned int i;
573
574 for (i = 0; i < chip->ngpio; i++, gpio++) {
575 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
576 seq_puts(s, "\n");
577 }
578 }
579
580 #else
581 #define lpi_gpio_dbg_show NULL
582 #endif
583
584 static const struct gpio_chip lpi_gpio_template = {
585 .direction_input = lpi_gpio_direction_input,
586 .direction_output = lpi_gpio_direction_output,
587 .get = lpi_gpio_get,
588 .set = lpi_gpio_set,
589 .request = gpiochip_generic_request,
590 .free = gpiochip_generic_free,
591 .dbg_show = lpi_gpio_dbg_show,
592 };
593
lpi_pinctrl_probe(struct platform_device * pdev)594 static int lpi_pinctrl_probe(struct platform_device *pdev)
595 {
596 const struct lpi_pinctrl_variant_data *data;
597 struct device *dev = &pdev->dev;
598 struct lpi_pinctrl *pctrl;
599 int ret;
600
601 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
602 if (!pctrl)
603 return -ENOMEM;
604
605 platform_set_drvdata(pdev, pctrl);
606
607 data = of_device_get_match_data(dev);
608 if (!data)
609 return -EINVAL;
610
611 pctrl->data = data;
612 pctrl->dev = &pdev->dev;
613
614 pctrl->clks[0].id = "core";
615 pctrl->clks[1].id = "audio";
616
617 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
618 if (IS_ERR(pctrl->tlmm_base))
619 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
620 "TLMM resource not provided\n");
621
622 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
623 if (IS_ERR(pctrl->slew_base))
624 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
625 "Slew resource not provided\n");
626
627 ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
628 if (ret)
629 return dev_err_probe(dev, ret, "Can't get clocks\n");
630
631 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
632 if (ret)
633 return dev_err_probe(dev, ret, "Can't enable clocks\n");
634
635 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
636 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
637 pctrl->desc.confops = &lpi_gpio_pinconf_ops;
638 pctrl->desc.owner = THIS_MODULE;
639 pctrl->desc.name = dev_name(dev);
640 pctrl->desc.pins = data->pins;
641 pctrl->desc.npins = data->npins;
642 pctrl->chip = lpi_gpio_template;
643 pctrl->chip.parent = dev;
644 pctrl->chip.base = -1;
645 pctrl->chip.ngpio = data->npins;
646 pctrl->chip.label = dev_name(dev);
647 pctrl->chip.of_gpio_n_cells = 2;
648 pctrl->chip.can_sleep = false;
649
650 mutex_init(&pctrl->lock);
651
652 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
653 if (IS_ERR(pctrl->ctrl)) {
654 ret = PTR_ERR(pctrl->ctrl);
655 dev_err(dev, "failed to add pin controller\n");
656 goto err_pinctrl;
657 }
658
659 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
660 if (ret) {
661 dev_err(pctrl->dev, "can't add gpio chip\n");
662 goto err_pinctrl;
663 }
664
665 return 0;
666
667 err_pinctrl:
668 mutex_destroy(&pctrl->lock);
669 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
670
671 return ret;
672 }
673
lpi_pinctrl_remove(struct platform_device * pdev)674 static int lpi_pinctrl_remove(struct platform_device *pdev)
675 {
676 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
677
678 mutex_destroy(&pctrl->lock);
679 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
680
681 return 0;
682 }
683
684 static const struct of_device_id lpi_pinctrl_of_match[] = {
685 {
686 .compatible = "qcom,sm8250-lpass-lpi-pinctrl",
687 .data = &sm8250_lpi_data,
688 },
689 { }
690 };
691 MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match);
692
693 static struct platform_driver lpi_pinctrl_driver = {
694 .driver = {
695 .name = "qcom-lpass-lpi-pinctrl",
696 .of_match_table = lpi_pinctrl_of_match,
697 },
698 .probe = lpi_pinctrl_probe,
699 .remove = lpi_pinctrl_remove,
700 };
701
702 module_platform_driver(lpi_pinctrl_driver);
703 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
704 MODULE_LICENSE("GPL");
705