1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
5 *
6 * Limitations:
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
9 */
10
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/gpio.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/ingenic-tcu.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22
23 struct soc_info {
24 unsigned int num_pwms;
25 };
26
27 struct jz4740_pwm_chip {
28 struct pwm_chip chip;
29 struct regmap *map;
30 };
31
to_jz4740(struct pwm_chip * chip)32 static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
33 {
34 return container_of(chip, struct jz4740_pwm_chip, chip);
35 }
36
jz4740_pwm_can_use_chn(struct jz4740_pwm_chip * jz,unsigned int channel)37 static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
38 unsigned int channel)
39 {
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
42
43 device_property_read_u32(jz->chip.dev->parent,
44 "ingenic,pwm-channels-mask",
45 &pwm_channels_mask);
46
47 return !!(pwm_channels_mask & BIT(channel));
48 }
49
jz4740_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)50 static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
51 {
52 struct jz4740_pwm_chip *jz = to_jz4740(chip);
53 struct clk *clk;
54 char name[16];
55 int err;
56
57 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
58 return -EBUSY;
59
60 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
61
62 clk = clk_get(chip->dev, name);
63 if (IS_ERR(clk)) {
64 dev_err(chip->dev, "error %pe: Failed to get clock\n", clk);
65 return PTR_ERR(clk);
66 }
67
68 err = clk_prepare_enable(clk);
69 if (err < 0) {
70 clk_put(clk);
71 return err;
72 }
73
74 pwm_set_chip_data(pwm, clk);
75
76 return 0;
77 }
78
jz4740_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)79 static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
80 {
81 struct clk *clk = pwm_get_chip_data(pwm);
82
83 clk_disable_unprepare(clk);
84 clk_put(clk);
85 }
86
jz4740_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)87 static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
88 {
89 struct jz4740_pwm_chip *jz = to_jz4740(chip);
90
91 /* Enable PWM output */
92 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
93 TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN);
94
95 /* Start counter */
96 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
97
98 return 0;
99 }
100
jz4740_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)101 static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
102 {
103 struct jz4740_pwm_chip *jz = to_jz4740(chip);
104
105 /*
106 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
107 * properly return to their init level.
108 */
109 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
110 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
111
112 /*
113 * Disable PWM output.
114 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
115 * counter is stopped, while in TCU1 mode the order does not matter.
116 */
117 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
118 TCU_TCSR_PWM_EN, 0);
119
120 /* Stop counter */
121 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
122 }
123
jz4740_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)124 static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
125 const struct pwm_state *state)
126 {
127 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
128 unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
129 struct clk *clk = pwm_get_chip_data(pwm);
130 unsigned long period, duty;
131 long rate;
132 int err;
133
134 /*
135 * Limit the clock to a maximum rate that still gives us a period value
136 * which fits in 16 bits.
137 */
138 do_div(tmp, state->period);
139
140 /*
141 * /!\ IMPORTANT NOTE:
142 * -------------------
143 * This code relies on the fact that clk_round_rate() will always round
144 * down, which is not a valid assumption given by the clk API, but only
145 * happens to be true with the clk drivers used for Ingenic SoCs.
146 *
147 * Right now, there is no alternative as the clk API does not have a
148 * round-down function (and won't have one for a while), but if it ever
149 * comes to light, a round-down function should be used instead.
150 */
151 rate = clk_round_rate(clk, tmp);
152 if (rate < 0) {
153 dev_err(chip->dev, "Unable to round rate: %ld", rate);
154 return rate;
155 }
156
157 /* Calculate period value */
158 tmp = (unsigned long long)rate * state->period;
159 do_div(tmp, NSEC_PER_SEC);
160 period = tmp;
161
162 /* Calculate duty value */
163 tmp = (unsigned long long)rate * state->duty_cycle;
164 do_div(tmp, NSEC_PER_SEC);
165 duty = tmp;
166
167 if (duty >= period)
168 duty = period - 1;
169
170 jz4740_pwm_disable(chip, pwm);
171
172 err = clk_set_rate(clk, rate);
173 if (err) {
174 dev_err(chip->dev, "Unable to set rate: %d", err);
175 return err;
176 }
177
178 /* Reset counter to 0 */
179 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
180
181 /* Set duty */
182 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
183
184 /* Set period */
185 regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
186
187 /* Set abrupt shutdown */
188 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
189 TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
190
191 /*
192 * Set polarity.
193 *
194 * The PWM starts in inactive state until the internal timer reaches the
195 * duty value, then becomes active until the timer reaches the period
196 * value. In theory, we should then use (period - duty) as the real duty
197 * value, as a high duty value would otherwise result in the PWM pin
198 * being inactive most of the time.
199 *
200 * Here, we don't do that, and instead invert the polarity of the PWM
201 * when it is active. This trick makes the PWM start with its active
202 * state instead of its inactive state.
203 */
204 if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
205 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
206 TCU_TCSR_PWM_INITL_HIGH, 0);
207 else
208 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
209 TCU_TCSR_PWM_INITL_HIGH,
210 TCU_TCSR_PWM_INITL_HIGH);
211
212 if (state->enabled)
213 jz4740_pwm_enable(chip, pwm);
214
215 return 0;
216 }
217
218 static const struct pwm_ops jz4740_pwm_ops = {
219 .request = jz4740_pwm_request,
220 .free = jz4740_pwm_free,
221 .apply = jz4740_pwm_apply,
222 .owner = THIS_MODULE,
223 };
224
jz4740_pwm_probe(struct platform_device * pdev)225 static int jz4740_pwm_probe(struct platform_device *pdev)
226 {
227 struct device *dev = &pdev->dev;
228 struct jz4740_pwm_chip *jz4740;
229 const struct soc_info *info;
230
231 info = device_get_match_data(dev);
232 if (!info)
233 return -EINVAL;
234
235 jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
236 if (!jz4740)
237 return -ENOMEM;
238
239 jz4740->map = device_node_to_regmap(dev->parent->of_node);
240 if (IS_ERR(jz4740->map)) {
241 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map));
242 return PTR_ERR(jz4740->map);
243 }
244
245 jz4740->chip.dev = dev;
246 jz4740->chip.ops = &jz4740_pwm_ops;
247 jz4740->chip.npwm = info->num_pwms;
248
249 return devm_pwmchip_add(dev, &jz4740->chip);
250 }
251
252 static const struct soc_info __maybe_unused jz4740_soc_info = {
253 .num_pwms = 8,
254 };
255
256 static const struct soc_info __maybe_unused jz4725b_soc_info = {
257 .num_pwms = 6,
258 };
259
260 #ifdef CONFIG_OF
261 static const struct of_device_id jz4740_pwm_dt_ids[] = {
262 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
263 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
264 {},
265 };
266 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
267 #endif
268
269 static struct platform_driver jz4740_pwm_driver = {
270 .driver = {
271 .name = "jz4740-pwm",
272 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
273 },
274 .probe = jz4740_pwm_probe,
275 };
276 module_platform_driver(jz4740_pwm_driver);
277
278 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
279 MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
280 MODULE_ALIAS("platform:jz4740-pwm");
281 MODULE_LICENSE("GPL");
282