1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
4 *
5 * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
6 *
7 * Notes
8 * =====
9 * NXP LPC18xx provides a State Configurable Timer (SCT) which can be configured
10 * as a Pulse Width Modulator.
11 *
12 * SCT supports 16 outputs, 16 events and 16 registers. Each event will be
13 * triggered when its related register matches the SCT counter value, and it
14 * will set or clear a selected output.
15 *
16 * One of the events is preselected to generate the period, thus the maximum
17 * number of simultaneous channels is limited to 15. Notice that period is
18 * global to all the channels, thus PWM driver will refuse setting different
19 * values to it, unless there's only one channel requested.
20 */
21
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/pwm.h>
28
29 /* LPC18xx SCT registers */
30 #define LPC18XX_PWM_CONFIG 0x000
31 #define LPC18XX_PWM_CONFIG_UNIFY BIT(0)
32 #define LPC18XX_PWM_CONFIG_NORELOAD BIT(7)
33
34 #define LPC18XX_PWM_CTRL 0x004
35 #define LPC18XX_PWM_CTRL_HALT BIT(2)
36 #define LPC18XX_PWM_BIDIR BIT(4)
37 #define LPC18XX_PWM_PRE_SHIFT 5
38 #define LPC18XX_PWM_PRE_MASK (0xff << LPC18XX_PWM_PRE_SHIFT)
39 #define LPC18XX_PWM_PRE(x) (x << LPC18XX_PWM_PRE_SHIFT)
40
41 #define LPC18XX_PWM_LIMIT 0x008
42
43 #define LPC18XX_PWM_RES_BASE 0x058
44 #define LPC18XX_PWM_RES_SHIFT(_ch) (_ch * 2)
45 #define LPC18XX_PWM_RES(_ch, _action) (_action << LPC18XX_PWM_RES_SHIFT(_ch))
46 #define LPC18XX_PWM_RES_MASK(_ch) (0x3 << LPC18XX_PWM_RES_SHIFT(_ch))
47
48 #define LPC18XX_PWM_MATCH_BASE 0x100
49 #define LPC18XX_PWM_MATCH(_ch) (LPC18XX_PWM_MATCH_BASE + _ch * 4)
50
51 #define LPC18XX_PWM_MATCHREL_BASE 0x200
52 #define LPC18XX_PWM_MATCHREL(_ch) (LPC18XX_PWM_MATCHREL_BASE + _ch * 4)
53
54 #define LPC18XX_PWM_EVSTATEMSK_BASE 0x300
55 #define LPC18XX_PWM_EVSTATEMSK(_ch) (LPC18XX_PWM_EVSTATEMSK_BASE + _ch * 8)
56 #define LPC18XX_PWM_EVSTATEMSK_ALL 0xffffffff
57
58 #define LPC18XX_PWM_EVCTRL_BASE 0x304
59 #define LPC18XX_PWM_EVCTRL(_ev) (LPC18XX_PWM_EVCTRL_BASE + _ev * 8)
60
61 #define LPC18XX_PWM_EVCTRL_MATCH(_ch) _ch
62
63 #define LPC18XX_PWM_EVCTRL_COMB_SHIFT 12
64 #define LPC18XX_PWM_EVCTRL_COMB_MATCH (0x1 << LPC18XX_PWM_EVCTRL_COMB_SHIFT)
65
66 #define LPC18XX_PWM_OUTPUTSET_BASE 0x500
67 #define LPC18XX_PWM_OUTPUTSET(_ch) (LPC18XX_PWM_OUTPUTSET_BASE + _ch * 8)
68
69 #define LPC18XX_PWM_OUTPUTCL_BASE 0x504
70 #define LPC18XX_PWM_OUTPUTCL(_ch) (LPC18XX_PWM_OUTPUTCL_BASE + _ch * 8)
71
72 /* LPC18xx SCT unified counter */
73 #define LPC18XX_PWM_TIMER_MAX 0xffffffff
74
75 /* LPC18xx SCT events */
76 #define LPC18XX_PWM_EVENT_PERIOD 0
77 #define LPC18XX_PWM_EVENT_MAX 16
78
79 #define LPC18XX_NUM_PWMS 16
80
81 /* SCT conflict resolution */
82 enum lpc18xx_pwm_res_action {
83 LPC18XX_PWM_RES_NONE,
84 LPC18XX_PWM_RES_SET,
85 LPC18XX_PWM_RES_CLEAR,
86 LPC18XX_PWM_RES_TOGGLE,
87 };
88
89 struct lpc18xx_pwm_data {
90 unsigned int duty_event;
91 };
92
93 struct lpc18xx_pwm_chip {
94 struct device *dev;
95 struct pwm_chip chip;
96 void __iomem *base;
97 struct clk *pwm_clk;
98 unsigned long clk_rate;
99 unsigned int period_ns;
100 unsigned int min_period_ns;
101 u64 max_period_ns;
102 unsigned int period_event;
103 unsigned long event_map;
104 struct mutex res_lock;
105 struct mutex period_lock;
106 struct lpc18xx_pwm_data channeldata[LPC18XX_NUM_PWMS];
107 };
108
109 static inline struct lpc18xx_pwm_chip *
to_lpc18xx_pwm_chip(struct pwm_chip * chip)110 to_lpc18xx_pwm_chip(struct pwm_chip *chip)
111 {
112 return container_of(chip, struct lpc18xx_pwm_chip, chip);
113 }
114
lpc18xx_pwm_writel(struct lpc18xx_pwm_chip * lpc18xx_pwm,u32 reg,u32 val)115 static inline void lpc18xx_pwm_writel(struct lpc18xx_pwm_chip *lpc18xx_pwm,
116 u32 reg, u32 val)
117 {
118 writel(val, lpc18xx_pwm->base + reg);
119 }
120
lpc18xx_pwm_readl(struct lpc18xx_pwm_chip * lpc18xx_pwm,u32 reg)121 static inline u32 lpc18xx_pwm_readl(struct lpc18xx_pwm_chip *lpc18xx_pwm,
122 u32 reg)
123 {
124 return readl(lpc18xx_pwm->base + reg);
125 }
126
lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip * lpc18xx_pwm,struct pwm_device * pwm,enum lpc18xx_pwm_res_action action)127 static void lpc18xx_pwm_set_conflict_res(struct lpc18xx_pwm_chip *lpc18xx_pwm,
128 struct pwm_device *pwm,
129 enum lpc18xx_pwm_res_action action)
130 {
131 u32 val;
132
133 mutex_lock(&lpc18xx_pwm->res_lock);
134
135 /*
136 * Simultaneous set and clear may happen on an output, that is the case
137 * when duty_ns == period_ns. LPC18xx SCT allows to set a conflict
138 * resolution action to be taken in such a case.
139 */
140 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_RES_BASE);
141 val &= ~LPC18XX_PWM_RES_MASK(pwm->hwpwm);
142 val |= LPC18XX_PWM_RES(pwm->hwpwm, action);
143 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_RES_BASE, val);
144
145 mutex_unlock(&lpc18xx_pwm->res_lock);
146 }
147
lpc18xx_pwm_config_period(struct pwm_chip * chip,u64 period_ns)148 static void lpc18xx_pwm_config_period(struct pwm_chip *chip, u64 period_ns)
149 {
150 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
151 u32 val;
152
153 /*
154 * With clk_rate < NSEC_PER_SEC this cannot overflow.
155 * With period_ns < max_period_ns this also fits into an u32.
156 * As period_ns >= min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, lpc18xx_pwm->clk_rate);
157 * we have val >= 1.
158 */
159 val = mul_u64_u64_div_u64(period_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
160
161 lpc18xx_pwm_writel(lpc18xx_pwm,
162 LPC18XX_PWM_MATCH(lpc18xx_pwm->period_event),
163 val - 1);
164
165 lpc18xx_pwm_writel(lpc18xx_pwm,
166 LPC18XX_PWM_MATCHREL(lpc18xx_pwm->period_event),
167 val - 1);
168 }
169
lpc18xx_pwm_config_duty(struct pwm_chip * chip,struct pwm_device * pwm,u64 duty_ns)170 static void lpc18xx_pwm_config_duty(struct pwm_chip *chip,
171 struct pwm_device *pwm, u64 duty_ns)
172 {
173 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
174 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
175 u32 val;
176
177 /*
178 * With clk_rate < NSEC_PER_SEC this cannot overflow.
179 * With duty_ns <= period_ns < max_period_ns this also fits into an u32.
180 */
181 val = mul_u64_u64_div_u64(duty_ns, lpc18xx_pwm->clk_rate, NSEC_PER_SEC);
182
183 lpc18xx_pwm_writel(lpc18xx_pwm,
184 LPC18XX_PWM_MATCH(lpc18xx_data->duty_event),
185 val);
186
187 lpc18xx_pwm_writel(lpc18xx_pwm,
188 LPC18XX_PWM_MATCHREL(lpc18xx_data->duty_event),
189 val);
190 }
191
lpc18xx_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)192 static int lpc18xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
193 int duty_ns, int period_ns)
194 {
195 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
196 int requested_events, i;
197
198 if (period_ns < lpc18xx_pwm->min_period_ns ||
199 period_ns > lpc18xx_pwm->max_period_ns) {
200 dev_err(chip->dev, "period %d not in range\n", period_ns);
201 return -ERANGE;
202 }
203
204 mutex_lock(&lpc18xx_pwm->period_lock);
205
206 requested_events = bitmap_weight(&lpc18xx_pwm->event_map,
207 LPC18XX_PWM_EVENT_MAX);
208
209 /*
210 * The PWM supports only a single period for all PWM channels.
211 * Once the period is set, it can only be changed if no more than one
212 * channel is requested at that moment.
213 */
214 if (requested_events > 2 && lpc18xx_pwm->period_ns != period_ns &&
215 lpc18xx_pwm->period_ns) {
216 dev_err(chip->dev, "conflicting period requested for PWM %u\n",
217 pwm->hwpwm);
218 mutex_unlock(&lpc18xx_pwm->period_lock);
219 return -EBUSY;
220 }
221
222 if ((requested_events <= 2 && lpc18xx_pwm->period_ns != period_ns) ||
223 !lpc18xx_pwm->period_ns) {
224 lpc18xx_pwm->period_ns = period_ns;
225 for (i = 0; i < chip->npwm; i++)
226 pwm_set_period(&chip->pwms[i], period_ns);
227 lpc18xx_pwm_config_period(chip, period_ns);
228 }
229
230 mutex_unlock(&lpc18xx_pwm->period_lock);
231
232 lpc18xx_pwm_config_duty(chip, pwm, duty_ns);
233
234 return 0;
235 }
236
lpc18xx_pwm_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)237 static int lpc18xx_pwm_set_polarity(struct pwm_chip *chip,
238 struct pwm_device *pwm,
239 enum pwm_polarity polarity)
240 {
241 return 0;
242 }
243
lpc18xx_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)244 static int lpc18xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
245 {
246 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
247 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
248 enum lpc18xx_pwm_res_action res_action;
249 unsigned int set_event, clear_event;
250
251 lpc18xx_pwm_writel(lpc18xx_pwm,
252 LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event),
253 LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_data->duty_event) |
254 LPC18XX_PWM_EVCTRL_COMB_MATCH);
255
256 lpc18xx_pwm_writel(lpc18xx_pwm,
257 LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event),
258 LPC18XX_PWM_EVSTATEMSK_ALL);
259
260 if (pwm_get_polarity(pwm) == PWM_POLARITY_NORMAL) {
261 set_event = lpc18xx_pwm->period_event;
262 clear_event = lpc18xx_data->duty_event;
263 res_action = LPC18XX_PWM_RES_SET;
264 } else {
265 set_event = lpc18xx_data->duty_event;
266 clear_event = lpc18xx_pwm->period_event;
267 res_action = LPC18XX_PWM_RES_CLEAR;
268 }
269
270 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm),
271 BIT(set_event));
272 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm),
273 BIT(clear_event));
274 lpc18xx_pwm_set_conflict_res(lpc18xx_pwm, pwm, res_action);
275
276 return 0;
277 }
278
lpc18xx_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)279 static void lpc18xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
280 {
281 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
282 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
283
284 lpc18xx_pwm_writel(lpc18xx_pwm,
285 LPC18XX_PWM_EVCTRL(lpc18xx_data->duty_event), 0);
286 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTSET(pwm->hwpwm), 0);
287 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_OUTPUTCL(pwm->hwpwm), 0);
288 }
289
lpc18xx_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)290 static int lpc18xx_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
291 {
292 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
293 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
294 unsigned long event;
295
296 event = find_first_zero_bit(&lpc18xx_pwm->event_map,
297 LPC18XX_PWM_EVENT_MAX);
298
299 if (event >= LPC18XX_PWM_EVENT_MAX) {
300 dev_err(lpc18xx_pwm->dev,
301 "maximum number of simultaneous channels reached\n");
302 return -EBUSY;
303 }
304
305 set_bit(event, &lpc18xx_pwm->event_map);
306 lpc18xx_data->duty_event = event;
307
308 return 0;
309 }
310
lpc18xx_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)311 static void lpc18xx_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
312 {
313 struct lpc18xx_pwm_chip *lpc18xx_pwm = to_lpc18xx_pwm_chip(chip);
314 struct lpc18xx_pwm_data *lpc18xx_data = &lpc18xx_pwm->channeldata[pwm->hwpwm];
315
316 clear_bit(lpc18xx_data->duty_event, &lpc18xx_pwm->event_map);
317 }
318
319 static const struct pwm_ops lpc18xx_pwm_ops = {
320 .config = lpc18xx_pwm_config,
321 .set_polarity = lpc18xx_pwm_set_polarity,
322 .enable = lpc18xx_pwm_enable,
323 .disable = lpc18xx_pwm_disable,
324 .request = lpc18xx_pwm_request,
325 .free = lpc18xx_pwm_free,
326 .owner = THIS_MODULE,
327 };
328
329 static const struct of_device_id lpc18xx_pwm_of_match[] = {
330 { .compatible = "nxp,lpc1850-sct-pwm" },
331 {}
332 };
333 MODULE_DEVICE_TABLE(of, lpc18xx_pwm_of_match);
334
lpc18xx_pwm_probe(struct platform_device * pdev)335 static int lpc18xx_pwm_probe(struct platform_device *pdev)
336 {
337 struct lpc18xx_pwm_chip *lpc18xx_pwm;
338 int ret;
339 u64 val;
340
341 lpc18xx_pwm = devm_kzalloc(&pdev->dev, sizeof(*lpc18xx_pwm),
342 GFP_KERNEL);
343 if (!lpc18xx_pwm)
344 return -ENOMEM;
345
346 lpc18xx_pwm->dev = &pdev->dev;
347
348 lpc18xx_pwm->base = devm_platform_ioremap_resource(pdev, 0);
349 if (IS_ERR(lpc18xx_pwm->base))
350 return PTR_ERR(lpc18xx_pwm->base);
351
352 lpc18xx_pwm->pwm_clk = devm_clk_get(&pdev->dev, "pwm");
353 if (IS_ERR(lpc18xx_pwm->pwm_clk)) {
354 dev_err(&pdev->dev, "failed to get pwm clock\n");
355 return PTR_ERR(lpc18xx_pwm->pwm_clk);
356 }
357
358 ret = clk_prepare_enable(lpc18xx_pwm->pwm_clk);
359 if (ret < 0) {
360 dev_err(&pdev->dev, "could not prepare or enable pwm clock\n");
361 return ret;
362 }
363
364 lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
365 if (!lpc18xx_pwm->clk_rate) {
366 dev_err(&pdev->dev, "pwm clock has no frequency\n");
367 ret = -EINVAL;
368 goto disable_pwmclk;
369 }
370
371 /*
372 * If clkrate is too fast, the calculations in .apply() might overflow.
373 */
374 if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC) {
375 ret = dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
376 goto disable_pwmclk;
377 }
378
379 /*
380 * If clkrate is too fast, the calculations in .apply() might overflow.
381 */
382 if (lpc18xx_pwm->clk_rate > NSEC_PER_SEC) {
383 ret = dev_err_probe(&pdev->dev, -EINVAL, "pwm clock to fast\n");
384 goto disable_pwmclk;
385 }
386
387 mutex_init(&lpc18xx_pwm->res_lock);
388 mutex_init(&lpc18xx_pwm->period_lock);
389
390 lpc18xx_pwm->max_period_ns =
391 mul_u64_u64_div_u64(NSEC_PER_SEC, LPC18XX_PWM_TIMER_MAX, lpc18xx_pwm->clk_rate);
392
393 lpc18xx_pwm->min_period_ns = DIV_ROUND_UP(NSEC_PER_SEC,
394 lpc18xx_pwm->clk_rate);
395
396 lpc18xx_pwm->chip.dev = &pdev->dev;
397 lpc18xx_pwm->chip.ops = &lpc18xx_pwm_ops;
398 lpc18xx_pwm->chip.npwm = LPC18XX_NUM_PWMS;
399
400 /* SCT counter must be in unify (32 bit) mode */
401 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CONFIG,
402 LPC18XX_PWM_CONFIG_UNIFY);
403
404 /*
405 * Everytime the timer counter reaches the period value, the related
406 * event will be triggered and the counter reset to 0.
407 */
408 set_bit(LPC18XX_PWM_EVENT_PERIOD, &lpc18xx_pwm->event_map);
409 lpc18xx_pwm->period_event = LPC18XX_PWM_EVENT_PERIOD;
410
411 lpc18xx_pwm_writel(lpc18xx_pwm,
412 LPC18XX_PWM_EVSTATEMSK(lpc18xx_pwm->period_event),
413 LPC18XX_PWM_EVSTATEMSK_ALL);
414
415 val = LPC18XX_PWM_EVCTRL_MATCH(lpc18xx_pwm->period_event) |
416 LPC18XX_PWM_EVCTRL_COMB_MATCH;
417 lpc18xx_pwm_writel(lpc18xx_pwm,
418 LPC18XX_PWM_EVCTRL(lpc18xx_pwm->period_event), val);
419
420 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_LIMIT,
421 BIT(lpc18xx_pwm->period_event));
422
423 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
424 val &= ~LPC18XX_PWM_BIDIR;
425 val &= ~LPC18XX_PWM_CTRL_HALT;
426 val &= ~LPC18XX_PWM_PRE_MASK;
427 val |= LPC18XX_PWM_PRE(0);
428 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL, val);
429
430 ret = pwmchip_add(&lpc18xx_pwm->chip);
431 if (ret < 0) {
432 dev_err(&pdev->dev, "pwmchip_add failed: %d\n", ret);
433 goto disable_pwmclk;
434 }
435
436 platform_set_drvdata(pdev, lpc18xx_pwm);
437
438 return 0;
439
440 disable_pwmclk:
441 clk_disable_unprepare(lpc18xx_pwm->pwm_clk);
442 return ret;
443 }
444
lpc18xx_pwm_remove(struct platform_device * pdev)445 static int lpc18xx_pwm_remove(struct platform_device *pdev)
446 {
447 struct lpc18xx_pwm_chip *lpc18xx_pwm = platform_get_drvdata(pdev);
448 u32 val;
449
450 pwmchip_remove(&lpc18xx_pwm->chip);
451
452 val = lpc18xx_pwm_readl(lpc18xx_pwm, LPC18XX_PWM_CTRL);
453 lpc18xx_pwm_writel(lpc18xx_pwm, LPC18XX_PWM_CTRL,
454 val | LPC18XX_PWM_CTRL_HALT);
455
456 clk_disable_unprepare(lpc18xx_pwm->pwm_clk);
457
458 return 0;
459 }
460
461 static struct platform_driver lpc18xx_pwm_driver = {
462 .driver = {
463 .name = "lpc18xx-sct-pwm",
464 .of_match_table = lpc18xx_pwm_of_match,
465 },
466 .probe = lpc18xx_pwm_probe,
467 .remove = lpc18xx_pwm_remove,
468 };
469 module_platform_driver(lpc18xx_pwm_driver);
470
471 MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
472 MODULE_DESCRIPTION("NXP LPC18xx PWM driver");
473 MODULE_LICENSE("GPL v2");
474