1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * Limitations:
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
13 */
14 #include <linux/clk.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/slab.h>
20 #include <linux/bitfield.h>
21
22 /* Register offsets */
23 #define PWM_SIFIVE_PWMCFG 0x0
24 #define PWM_SIFIVE_PWMCOUNT 0x8
25 #define PWM_SIFIVE_PWMS 0x10
26 #define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i))
27
28 /* PWMCFG fields */
29 #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
30 #define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
31 #define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
32 #define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
33 #define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
34 #define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
35 #define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
36 #define PWM_SIFIVE_PWMCFG_GANG BIT(24)
37 #define PWM_SIFIVE_PWMCFG_IP BIT(28)
38
39 #define PWM_SIFIVE_CMPWIDTH 16
40 #define PWM_SIFIVE_DEFAULT_PERIOD 10000000
41
42 struct pwm_sifive_ddata {
43 struct pwm_chip chip;
44 struct mutex lock; /* lock to protect user_count and approx_period */
45 struct notifier_block notifier;
46 struct clk *clk;
47 void __iomem *regs;
48 unsigned int real_period;
49 unsigned int approx_period;
50 int user_count;
51 };
52
53 static inline
pwm_sifive_chip_to_ddata(struct pwm_chip * c)54 struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
55 {
56 return container_of(c, struct pwm_sifive_ddata, chip);
57 }
58
pwm_sifive_request(struct pwm_chip * chip,struct pwm_device * pwm)59 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
60 {
61 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
62
63 mutex_lock(&ddata->lock);
64 ddata->user_count++;
65 mutex_unlock(&ddata->lock);
66
67 return 0;
68 }
69
pwm_sifive_free(struct pwm_chip * chip,struct pwm_device * pwm)70 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
71 {
72 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
73
74 mutex_lock(&ddata->lock);
75 ddata->user_count--;
76 mutex_unlock(&ddata->lock);
77 }
78
79 /* Called holding ddata->lock */
pwm_sifive_update_clock(struct pwm_sifive_ddata * ddata,unsigned long rate)80 static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
81 unsigned long rate)
82 {
83 unsigned long long num;
84 unsigned long scale_pow;
85 int scale;
86 u32 val;
87 /*
88 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
89 * period length is using pwmscale which provides the number of bits the
90 * counter is shifted before being feed to the comparators. A period
91 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
92 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
93 */
94 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
95 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
96
97 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
98 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
99 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
100
101 /* As scale <= 15 the shift operation cannot overflow. */
102 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
103 ddata->real_period = div64_ul(num, rate);
104 dev_dbg(ddata->chip.dev,
105 "New real_period = %u ns\n", ddata->real_period);
106 }
107
pwm_sifive_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)108 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
109 struct pwm_state *state)
110 {
111 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
112 u32 duty, val;
113
114 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
115
116 state->enabled = duty > 0;
117
118 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
119 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
120 state->enabled = false;
121
122 state->period = ddata->real_period;
123 state->duty_cycle =
124 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
125 state->polarity = PWM_POLARITY_INVERSED;
126 }
127
pwm_sifive_enable(struct pwm_chip * chip,bool enable)128 static int pwm_sifive_enable(struct pwm_chip *chip, bool enable)
129 {
130 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
131 int ret;
132
133 if (enable) {
134 ret = clk_enable(ddata->clk);
135 if (ret) {
136 dev_err(ddata->chip.dev, "Enable clk failed\n");
137 return ret;
138 }
139 }
140
141 if (!enable)
142 clk_disable(ddata->clk);
143
144 return 0;
145 }
146
pwm_sifive_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)147 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
148 const struct pwm_state *state)
149 {
150 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
151 struct pwm_state cur_state;
152 unsigned int duty_cycle;
153 unsigned long long num;
154 bool enabled;
155 int ret = 0;
156 u32 frac;
157
158 if (state->polarity != PWM_POLARITY_INVERSED)
159 return -EINVAL;
160
161 ret = clk_enable(ddata->clk);
162 if (ret) {
163 dev_err(ddata->chip.dev, "Enable clk failed\n");
164 return ret;
165 }
166
167 cur_state = pwm->state;
168 enabled = cur_state.enabled;
169
170 duty_cycle = state->duty_cycle;
171 if (!state->enabled)
172 duty_cycle = 0;
173
174 /*
175 * The problem of output producing mixed setting as mentioned at top,
176 * occurs here. To minimize the window for this problem, we are
177 * calculating the register values first and then writing them
178 * consecutively
179 */
180 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
181 frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
182 /* The hardware cannot generate a 100% duty cycle */
183 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
184
185 mutex_lock(&ddata->lock);
186 if (state->period != ddata->approx_period) {
187 /*
188 * Don't let a 2nd user change the period underneath the 1st user.
189 * However if ddate->approx_period == 0 this is the first time we set
190 * any period, so let whoever gets here first set the period so other
191 * users who agree on the period won't fail.
192 */
193 if (ddata->user_count != 1 && ddata->approx_period) {
194 mutex_unlock(&ddata->lock);
195 ret = -EBUSY;
196 goto exit;
197 }
198 ddata->approx_period = state->period;
199 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
200 }
201 mutex_unlock(&ddata->lock);
202
203 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
204
205 if (state->enabled != enabled)
206 pwm_sifive_enable(chip, state->enabled);
207
208 exit:
209 clk_disable(ddata->clk);
210 return ret;
211 }
212
213 static const struct pwm_ops pwm_sifive_ops = {
214 .request = pwm_sifive_request,
215 .free = pwm_sifive_free,
216 .get_state = pwm_sifive_get_state,
217 .apply = pwm_sifive_apply,
218 .owner = THIS_MODULE,
219 };
220
pwm_sifive_clock_notifier(struct notifier_block * nb,unsigned long event,void * data)221 static int pwm_sifive_clock_notifier(struct notifier_block *nb,
222 unsigned long event, void *data)
223 {
224 struct clk_notifier_data *ndata = data;
225 struct pwm_sifive_ddata *ddata =
226 container_of(nb, struct pwm_sifive_ddata, notifier);
227
228 if (event == POST_RATE_CHANGE) {
229 mutex_lock(&ddata->lock);
230 pwm_sifive_update_clock(ddata, ndata->new_rate);
231 mutex_unlock(&ddata->lock);
232 }
233
234 return NOTIFY_OK;
235 }
236
pwm_sifive_probe(struct platform_device * pdev)237 static int pwm_sifive_probe(struct platform_device *pdev)
238 {
239 struct device *dev = &pdev->dev;
240 struct pwm_sifive_ddata *ddata;
241 struct pwm_chip *chip;
242 int ret;
243 u32 val;
244 unsigned int enabled_pwms = 0, enabled_clks = 1;
245
246 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
247 if (!ddata)
248 return -ENOMEM;
249
250 mutex_init(&ddata->lock);
251 chip = &ddata->chip;
252 chip->dev = dev;
253 chip->ops = &pwm_sifive_ops;
254 chip->npwm = 4;
255
256 ddata->regs = devm_platform_ioremap_resource(pdev, 0);
257 if (IS_ERR(ddata->regs))
258 return PTR_ERR(ddata->regs);
259
260 ddata->clk = devm_clk_get(dev, NULL);
261 if (IS_ERR(ddata->clk))
262 return dev_err_probe(dev, PTR_ERR(ddata->clk),
263 "Unable to find controller clock\n");
264
265 ret = clk_prepare_enable(ddata->clk);
266 if (ret) {
267 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
268 return ret;
269 }
270
271 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
272 if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
273 unsigned int i;
274
275 for (i = 0; i < chip->npwm; ++i) {
276 val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
277 if (val > 0)
278 ++enabled_pwms;
279 }
280 }
281
282 /* The clk should be on once for each running PWM. */
283 if (enabled_pwms) {
284 while (enabled_clks < enabled_pwms) {
285 /* This is not expected to fail as the clk is already on */
286 ret = clk_enable(ddata->clk);
287 if (unlikely(ret)) {
288 dev_err_probe(dev, ret, "Failed to enable clk\n");
289 goto disable_clk;
290 }
291 ++enabled_clks;
292 }
293 } else {
294 clk_disable(ddata->clk);
295 enabled_clks = 0;
296 }
297
298 /* Watch for changes to underlying clock frequency */
299 ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
300 ret = clk_notifier_register(ddata->clk, &ddata->notifier);
301 if (ret) {
302 dev_err(dev, "failed to register clock notifier: %d\n", ret);
303 goto disable_clk;
304 }
305
306 ret = pwmchip_add(chip);
307 if (ret < 0) {
308 dev_err(dev, "cannot register PWM: %d\n", ret);
309 goto unregister_clk;
310 }
311
312 platform_set_drvdata(pdev, ddata);
313 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
314
315 return 0;
316
317 unregister_clk:
318 clk_notifier_unregister(ddata->clk, &ddata->notifier);
319 disable_clk:
320 while (enabled_clks) {
321 clk_disable(ddata->clk);
322 --enabled_clks;
323 }
324 clk_unprepare(ddata->clk);
325
326 return ret;
327 }
328
pwm_sifive_remove(struct platform_device * dev)329 static int pwm_sifive_remove(struct platform_device *dev)
330 {
331 struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
332 struct pwm_device *pwm;
333 int ch;
334
335 pwmchip_remove(&ddata->chip);
336 clk_notifier_unregister(ddata->clk, &ddata->notifier);
337
338 for (ch = 0; ch < ddata->chip.npwm; ch++) {
339 pwm = &ddata->chip.pwms[ch];
340 if (pwm->state.enabled)
341 clk_disable(ddata->clk);
342 }
343
344 clk_unprepare(ddata->clk);
345
346 return 0;
347 }
348
349 static const struct of_device_id pwm_sifive_of_match[] = {
350 { .compatible = "sifive,pwm0" },
351 {},
352 };
353 MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
354
355 static struct platform_driver pwm_sifive_driver = {
356 .probe = pwm_sifive_probe,
357 .remove = pwm_sifive_remove,
358 .driver = {
359 .name = "pwm-sifive",
360 .of_match_table = pwm_sifive_of_match,
361 },
362 };
363 module_platform_driver(pwm_sifive_driver);
364
365 MODULE_DESCRIPTION("SiFive PWM driver");
366 MODULE_LICENSE("GPL v2");
367