1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * An RTC driver for Allwinner A31/A23
4 *
5 * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
6 *
7 * based on rtc-sunxi.c
8 *
9 * An RTC driver for Allwinner A10/A20
10 *
11 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/fs.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/rtc.h>
29 #include <linux/slab.h>
30 #include <linux/types.h>
31
32 /* Control register */
33 #define SUN6I_LOSC_CTRL 0x0000
34 #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
35 #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS BIT(15)
36 #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
37 #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
38 #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
39 #define SUN6I_LOSC_CTRL_EXT_LOSC_EN BIT(4)
40 #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
41 #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
42
43 #define SUN6I_LOSC_CLK_PRESCAL 0x0008
44
45 /* RTC */
46 #define SUN6I_RTC_YMD 0x0010
47 #define SUN6I_RTC_HMS 0x0014
48
49 /* Alarm 0 (counter) */
50 #define SUN6I_ALRM_COUNTER 0x0020
51 #define SUN6I_ALRM_CUR_VAL 0x0024
52 #define SUN6I_ALRM_EN 0x0028
53 #define SUN6I_ALRM_EN_CNT_EN BIT(0)
54 #define SUN6I_ALRM_IRQ_EN 0x002c
55 #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
56 #define SUN6I_ALRM_IRQ_STA 0x0030
57 #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
58
59 /* Alarm 1 (wall clock) */
60 #define SUN6I_ALRM1_EN 0x0044
61 #define SUN6I_ALRM1_IRQ_EN 0x0048
62 #define SUN6I_ALRM1_IRQ_STA 0x004c
63 #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
64
65 /* Alarm config */
66 #define SUN6I_ALARM_CONFIG 0x0050
67 #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
68
69 #define SUN6I_LOSC_OUT_GATING 0x0060
70 #define SUN6I_LOSC_OUT_GATING_EN_OFFSET 0
71
72 /*
73 * Get date values
74 */
75 #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
76 #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
77 #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
78 #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
79
80 /*
81 * Get time values
82 */
83 #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
84 #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
85 #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
86
87 /*
88 * Set date values
89 */
90 #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
91 #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
92 #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
93 #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
94
95 /*
96 * Set time values
97 */
98 #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
99 #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
100 #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
101
102 /*
103 * The year parameter passed to the driver is usually an offset relative to
104 * the year 1900. This macro is used to convert this offset to another one
105 * relative to the minimum year allowed by the hardware.
106 *
107 * The year range is 1970 - 2033. This range is selected to match Allwinner's
108 * driver, even though it is somewhat limited.
109 */
110 #define SUN6I_YEAR_MIN 1970
111 #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
112
113 /*
114 * There are other differences between models, including:
115 *
116 * - number of GPIO pins that can be configured to hold a certain level
117 * - crypto-key related registers (H5, H6)
118 * - boot process related (super standby, secondary processor entry address)
119 * registers (R40, H6)
120 * - SYS power domain controls (R40)
121 * - DCXO controls (H6)
122 * - RC oscillator calibration (H6)
123 *
124 * These functions are not covered by this driver.
125 */
126 struct sun6i_rtc_clk_data {
127 unsigned long rc_osc_rate;
128 unsigned int fixed_prescaler : 16;
129 unsigned int has_prescaler : 1;
130 unsigned int has_out_clk : 1;
131 unsigned int has_losc_en : 1;
132 unsigned int has_auto_swt : 1;
133 };
134
135 struct sun6i_rtc_dev {
136 struct rtc_device *rtc;
137 const struct sun6i_rtc_clk_data *data;
138 void __iomem *base;
139 int irq;
140 time64_t alarm;
141
142 struct clk_hw hw;
143 struct clk_hw *int_osc;
144 struct clk *losc;
145 struct clk *ext_losc;
146
147 spinlock_t lock;
148 };
149
150 static struct sun6i_rtc_dev *sun6i_rtc;
151
sun6i_rtc_osc_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)152 static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw,
153 unsigned long parent_rate)
154 {
155 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
156 u32 val = 0;
157
158 val = readl(rtc->base + SUN6I_LOSC_CTRL);
159 if (val & SUN6I_LOSC_CTRL_EXT_OSC)
160 return parent_rate;
161
162 if (rtc->data->fixed_prescaler)
163 parent_rate /= rtc->data->fixed_prescaler;
164
165 if (rtc->data->has_prescaler) {
166 val = readl(rtc->base + SUN6I_LOSC_CLK_PRESCAL);
167 val &= GENMASK(4, 0);
168 }
169
170 return parent_rate / (val + 1);
171 }
172
sun6i_rtc_osc_get_parent(struct clk_hw * hw)173 static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw)
174 {
175 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
176
177 return readl(rtc->base + SUN6I_LOSC_CTRL) & SUN6I_LOSC_CTRL_EXT_OSC;
178 }
179
sun6i_rtc_osc_set_parent(struct clk_hw * hw,u8 index)180 static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index)
181 {
182 struct sun6i_rtc_dev *rtc = container_of(hw, struct sun6i_rtc_dev, hw);
183 unsigned long flags;
184 u32 val;
185
186 if (index > 1)
187 return -EINVAL;
188
189 spin_lock_irqsave(&rtc->lock, flags);
190 val = readl(rtc->base + SUN6I_LOSC_CTRL);
191 val &= ~SUN6I_LOSC_CTRL_EXT_OSC;
192 val |= SUN6I_LOSC_CTRL_KEY;
193 val |= index ? SUN6I_LOSC_CTRL_EXT_OSC : 0;
194 if (rtc->data->has_losc_en) {
195 val &= ~SUN6I_LOSC_CTRL_EXT_LOSC_EN;
196 val |= index ? SUN6I_LOSC_CTRL_EXT_LOSC_EN : 0;
197 }
198 writel(val, rtc->base + SUN6I_LOSC_CTRL);
199 spin_unlock_irqrestore(&rtc->lock, flags);
200
201 return 0;
202 }
203
204 static const struct clk_ops sun6i_rtc_osc_ops = {
205 .recalc_rate = sun6i_rtc_osc_recalc_rate,
206
207 .get_parent = sun6i_rtc_osc_get_parent,
208 .set_parent = sun6i_rtc_osc_set_parent,
209 };
210
sun6i_rtc_clk_init(struct device_node * node,const struct sun6i_rtc_clk_data * data)211 static void __init sun6i_rtc_clk_init(struct device_node *node,
212 const struct sun6i_rtc_clk_data *data)
213 {
214 struct clk_hw_onecell_data *clk_data;
215 struct sun6i_rtc_dev *rtc;
216 struct clk_init_data init = {
217 .ops = &sun6i_rtc_osc_ops,
218 .name = "losc",
219 };
220 const char *iosc_name = "rtc-int-osc";
221 const char *clkout_name = "osc32k-out";
222 const char *parents[2];
223 u32 reg;
224
225 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
226 if (!rtc)
227 return;
228
229 rtc->data = data;
230 clk_data = kzalloc(struct_size(clk_data, hws, 3), GFP_KERNEL);
231 if (!clk_data) {
232 kfree(rtc);
233 return;
234 }
235
236 spin_lock_init(&rtc->lock);
237
238 rtc->base = of_io_request_and_map(node, 0, of_node_full_name(node));
239 if (IS_ERR(rtc->base)) {
240 pr_crit("Can't map RTC registers");
241 goto err;
242 }
243
244 reg = SUN6I_LOSC_CTRL_KEY;
245 if (rtc->data->has_auto_swt) {
246 /* Bypass auto-switch to int osc, on ext losc failure */
247 reg |= SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS;
248 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
249 }
250
251 /* Switch to the external, more precise, oscillator, if present */
252 if (of_get_property(node, "clocks", NULL)) {
253 reg |= SUN6I_LOSC_CTRL_EXT_OSC;
254 if (rtc->data->has_losc_en)
255 reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
256 }
257 writel(reg, rtc->base + SUN6I_LOSC_CTRL);
258
259 /* Yes, I know, this is ugly. */
260 sun6i_rtc = rtc;
261
262 of_property_read_string_index(node, "clock-output-names", 2,
263 &iosc_name);
264
265 rtc->int_osc = clk_hw_register_fixed_rate_with_accuracy(NULL,
266 iosc_name,
267 NULL, 0,
268 rtc->data->rc_osc_rate,
269 300000000);
270 if (IS_ERR(rtc->int_osc)) {
271 pr_crit("Couldn't register the internal oscillator\n");
272 goto err;
273 }
274
275 parents[0] = clk_hw_get_name(rtc->int_osc);
276 /* If there is no external oscillator, this will be NULL and ... */
277 parents[1] = of_clk_get_parent_name(node, 0);
278
279 rtc->hw.init = &init;
280
281 init.parent_names = parents;
282 /* ... number of clock parents will be 1. */
283 init.num_parents = of_clk_get_parent_count(node) + 1;
284 of_property_read_string_index(node, "clock-output-names", 0,
285 &init.name);
286
287 rtc->losc = clk_register(NULL, &rtc->hw);
288 if (IS_ERR(rtc->losc)) {
289 pr_crit("Couldn't register the LOSC clock\n");
290 goto err_register;
291 }
292
293 of_property_read_string_index(node, "clock-output-names", 1,
294 &clkout_name);
295 rtc->ext_losc = clk_register_gate(NULL, clkout_name, init.name,
296 0, rtc->base + SUN6I_LOSC_OUT_GATING,
297 SUN6I_LOSC_OUT_GATING_EN_OFFSET, 0,
298 &rtc->lock);
299 if (IS_ERR(rtc->ext_losc)) {
300 pr_crit("Couldn't register the LOSC external gate\n");
301 goto err_register;
302 }
303
304 clk_data->num = 3;
305 clk_data->hws[0] = &rtc->hw;
306 clk_data->hws[1] = __clk_get_hw(rtc->ext_losc);
307 clk_data->hws[2] = rtc->int_osc;
308 of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
309 return;
310
311 err_register:
312 clk_hw_unregister_fixed_rate(rtc->int_osc);
313 err:
314 kfree(clk_data);
315 }
316
317 static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = {
318 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
319 .has_prescaler = 1,
320 };
321
sun6i_a31_rtc_clk_init(struct device_node * node)322 static void __init sun6i_a31_rtc_clk_init(struct device_node *node)
323 {
324 sun6i_rtc_clk_init(node, &sun6i_a31_rtc_data);
325 }
326 CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc",
327 sun6i_a31_rtc_clk_init);
328
329 static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = {
330 .rc_osc_rate = 667000, /* datasheet says 600 ~ 700 KHz */
331 .has_prescaler = 1,
332 .has_out_clk = 1,
333 };
334
sun8i_a23_rtc_clk_init(struct device_node * node)335 static void __init sun8i_a23_rtc_clk_init(struct device_node *node)
336 {
337 sun6i_rtc_clk_init(node, &sun8i_a23_rtc_data);
338 }
339 CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc",
340 sun8i_a23_rtc_clk_init);
341
342 static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = {
343 .rc_osc_rate = 16000000,
344 .fixed_prescaler = 32,
345 .has_prescaler = 1,
346 .has_out_clk = 1,
347 };
348
sun8i_h3_rtc_clk_init(struct device_node * node)349 static void __init sun8i_h3_rtc_clk_init(struct device_node *node)
350 {
351 sun6i_rtc_clk_init(node, &sun8i_h3_rtc_data);
352 }
353 CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc",
354 sun8i_h3_rtc_clk_init);
355 /* As far as we are concerned, clocks for H5 are the same as H3 */
356 CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc",
357 sun8i_h3_rtc_clk_init);
358
359 static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = {
360 .rc_osc_rate = 16000000,
361 .fixed_prescaler = 32,
362 .has_prescaler = 1,
363 .has_out_clk = 1,
364 .has_losc_en = 1,
365 .has_auto_swt = 1,
366 };
367
sun50i_h6_rtc_clk_init(struct device_node * node)368 static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
369 {
370 sun6i_rtc_clk_init(node, &sun50i_h6_rtc_data);
371 }
372 CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
373 sun50i_h6_rtc_clk_init);
374
375 /*
376 * The R40 user manual is self-conflicting on whether the prescaler is
377 * fixed or configurable. The clock diagram shows it as fixed, but there
378 * is also a configurable divider in the RTC block.
379 */
380 static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = {
381 .rc_osc_rate = 16000000,
382 .fixed_prescaler = 512,
383 };
sun8i_r40_rtc_clk_init(struct device_node * node)384 static void __init sun8i_r40_rtc_clk_init(struct device_node *node)
385 {
386 sun6i_rtc_clk_init(node, &sun8i_r40_rtc_data);
387 }
388 CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc",
389 sun8i_r40_rtc_clk_init);
390
391 static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = {
392 .rc_osc_rate = 32000,
393 .has_out_clk = 1,
394 };
395
sun8i_v3_rtc_clk_init(struct device_node * node)396 static void __init sun8i_v3_rtc_clk_init(struct device_node *node)
397 {
398 sun6i_rtc_clk_init(node, &sun8i_v3_rtc_data);
399 }
400 CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc",
401 sun8i_v3_rtc_clk_init);
402
sun6i_rtc_alarmirq(int irq,void * id)403 static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
404 {
405 struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
406 irqreturn_t ret = IRQ_NONE;
407 u32 val;
408
409 spin_lock(&chip->lock);
410 val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
411
412 if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
413 val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
414 writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
415
416 rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
417
418 ret = IRQ_HANDLED;
419 }
420 spin_unlock(&chip->lock);
421
422 return ret;
423 }
424
sun6i_rtc_setaie(int to,struct sun6i_rtc_dev * chip)425 static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
426 {
427 u32 alrm_val = 0;
428 u32 alrm_irq_val = 0;
429 u32 alrm_wake_val = 0;
430 unsigned long flags;
431
432 if (to) {
433 alrm_val = SUN6I_ALRM_EN_CNT_EN;
434 alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
435 alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
436 } else {
437 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
438 chip->base + SUN6I_ALRM_IRQ_STA);
439 }
440
441 spin_lock_irqsave(&chip->lock, flags);
442 writel(alrm_val, chip->base + SUN6I_ALRM_EN);
443 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
444 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
445 spin_unlock_irqrestore(&chip->lock, flags);
446 }
447
sun6i_rtc_gettime(struct device * dev,struct rtc_time * rtc_tm)448 static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
449 {
450 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
451 u32 date, time;
452
453 /*
454 * read again in case it changes
455 */
456 do {
457 date = readl(chip->base + SUN6I_RTC_YMD);
458 time = readl(chip->base + SUN6I_RTC_HMS);
459 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
460 (time != readl(chip->base + SUN6I_RTC_HMS)));
461
462 rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
463 rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
464 rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
465
466 rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
467 rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
468 rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
469
470 rtc_tm->tm_mon -= 1;
471
472 /*
473 * switch from (data_year->min)-relative offset to
474 * a (1900)-relative one
475 */
476 rtc_tm->tm_year += SUN6I_YEAR_OFF;
477
478 return 0;
479 }
480
sun6i_rtc_getalarm(struct device * dev,struct rtc_wkalrm * wkalrm)481 static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
482 {
483 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
484 unsigned long flags;
485 u32 alrm_st;
486 u32 alrm_en;
487
488 spin_lock_irqsave(&chip->lock, flags);
489 alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
490 alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
491 spin_unlock_irqrestore(&chip->lock, flags);
492
493 wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
494 wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
495 rtc_time64_to_tm(chip->alarm, &wkalrm->time);
496
497 return 0;
498 }
499
sun6i_rtc_setalarm(struct device * dev,struct rtc_wkalrm * wkalrm)500 static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
501 {
502 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
503 struct rtc_time *alrm_tm = &wkalrm->time;
504 struct rtc_time tm_now;
505 time64_t time_now, time_set;
506 int ret;
507
508 ret = sun6i_rtc_gettime(dev, &tm_now);
509 if (ret < 0) {
510 dev_err(dev, "Error in getting time\n");
511 return -EINVAL;
512 }
513
514 time_set = rtc_tm_to_time64(alrm_tm);
515 time_now = rtc_tm_to_time64(&tm_now);
516 if (time_set <= time_now) {
517 dev_err(dev, "Date to set in the past\n");
518 return -EINVAL;
519 }
520
521 if ((time_set - time_now) > U32_MAX) {
522 dev_err(dev, "Date too far in the future\n");
523 return -EINVAL;
524 }
525
526 sun6i_rtc_setaie(0, chip);
527 writel(0, chip->base + SUN6I_ALRM_COUNTER);
528 usleep_range(100, 300);
529
530 writel(time_set - time_now, chip->base + SUN6I_ALRM_COUNTER);
531 chip->alarm = time_set;
532
533 sun6i_rtc_setaie(wkalrm->enabled, chip);
534
535 return 0;
536 }
537
sun6i_rtc_wait(struct sun6i_rtc_dev * chip,int offset,unsigned int mask,unsigned int ms_timeout)538 static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
539 unsigned int mask, unsigned int ms_timeout)
540 {
541 const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
542 u32 reg;
543
544 do {
545 reg = readl(chip->base + offset);
546 reg &= mask;
547
548 if (!reg)
549 return 0;
550
551 } while (time_before(jiffies, timeout));
552
553 return -ETIMEDOUT;
554 }
555
sun6i_rtc_settime(struct device * dev,struct rtc_time * rtc_tm)556 static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
557 {
558 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
559 u32 date = 0;
560 u32 time = 0;
561
562 rtc_tm->tm_year -= SUN6I_YEAR_OFF;
563 rtc_tm->tm_mon += 1;
564
565 date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
566 SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
567 SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
568
569 if (is_leap_year(rtc_tm->tm_year + SUN6I_YEAR_MIN))
570 date |= SUN6I_LEAP_SET_VALUE(1);
571
572 time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
573 SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
574 SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
575
576 /* Check whether registers are writable */
577 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
578 SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
579 dev_err(dev, "rtc is still busy.\n");
580 return -EBUSY;
581 }
582
583 writel(time, chip->base + SUN6I_RTC_HMS);
584
585 /*
586 * After writing the RTC HH-MM-SS register, the
587 * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
588 * be cleared until the real writing operation is finished
589 */
590
591 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
592 SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
593 dev_err(dev, "Failed to set rtc time.\n");
594 return -ETIMEDOUT;
595 }
596
597 writel(date, chip->base + SUN6I_RTC_YMD);
598
599 /*
600 * After writing the RTC YY-MM-DD register, the
601 * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
602 * be cleared until the real writing operation is finished
603 */
604
605 if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
606 SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
607 dev_err(dev, "Failed to set rtc time.\n");
608 return -ETIMEDOUT;
609 }
610
611 return 0;
612 }
613
sun6i_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)614 static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
615 {
616 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
617
618 if (!enabled)
619 sun6i_rtc_setaie(enabled, chip);
620
621 return 0;
622 }
623
624 static const struct rtc_class_ops sun6i_rtc_ops = {
625 .read_time = sun6i_rtc_gettime,
626 .set_time = sun6i_rtc_settime,
627 .read_alarm = sun6i_rtc_getalarm,
628 .set_alarm = sun6i_rtc_setalarm,
629 .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
630 };
631
632 #ifdef CONFIG_PM_SLEEP
633 /* Enable IRQ wake on suspend, to wake up from RTC. */
sun6i_rtc_suspend(struct device * dev)634 static int sun6i_rtc_suspend(struct device *dev)
635 {
636 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
637
638 if (device_may_wakeup(dev))
639 enable_irq_wake(chip->irq);
640
641 return 0;
642 }
643
644 /* Disable IRQ wake on resume. */
sun6i_rtc_resume(struct device * dev)645 static int sun6i_rtc_resume(struct device *dev)
646 {
647 struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
648
649 if (device_may_wakeup(dev))
650 disable_irq_wake(chip->irq);
651
652 return 0;
653 }
654 #endif
655
656 static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
657 sun6i_rtc_suspend, sun6i_rtc_resume);
658
sun6i_rtc_probe(struct platform_device * pdev)659 static int sun6i_rtc_probe(struct platform_device *pdev)
660 {
661 struct sun6i_rtc_dev *chip = sun6i_rtc;
662 int ret;
663
664 if (!chip)
665 return -ENODEV;
666
667 platform_set_drvdata(pdev, chip);
668
669 chip->irq = platform_get_irq(pdev, 0);
670 if (chip->irq < 0)
671 return chip->irq;
672
673 ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
674 0, dev_name(&pdev->dev), chip);
675 if (ret) {
676 dev_err(&pdev->dev, "Could not request IRQ\n");
677 return ret;
678 }
679
680 /* clear the alarm counter value */
681 writel(0, chip->base + SUN6I_ALRM_COUNTER);
682
683 /* disable counter alarm */
684 writel(0, chip->base + SUN6I_ALRM_EN);
685
686 /* disable counter alarm interrupt */
687 writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
688
689 /* disable week alarm */
690 writel(0, chip->base + SUN6I_ALRM1_EN);
691
692 /* disable week alarm interrupt */
693 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
694
695 /* clear counter alarm pending interrupts */
696 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
697 chip->base + SUN6I_ALRM_IRQ_STA);
698
699 /* clear week alarm pending interrupts */
700 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
701 chip->base + SUN6I_ALRM1_IRQ_STA);
702
703 /* disable alarm wakeup */
704 writel(0, chip->base + SUN6I_ALARM_CONFIG);
705
706 clk_prepare_enable(chip->losc);
707
708 device_init_wakeup(&pdev->dev, 1);
709
710 chip->rtc = devm_rtc_allocate_device(&pdev->dev);
711 if (IS_ERR(chip->rtc))
712 return PTR_ERR(chip->rtc);
713
714 chip->rtc->ops = &sun6i_rtc_ops;
715 chip->rtc->range_max = 2019686399LL; /* 2033-12-31 23:59:59 */
716
717 ret = devm_rtc_register_device(chip->rtc);
718 if (ret)
719 return ret;
720
721 dev_info(&pdev->dev, "RTC enabled\n");
722
723 return 0;
724 }
725
726 /*
727 * As far as RTC functionality goes, all models are the same. The
728 * datasheets claim that different models have different number of
729 * registers available for non-volatile storage, but experiments show
730 * that all SoCs have 16 registers available for this purpose.
731 */
732 static const struct of_device_id sun6i_rtc_dt_ids[] = {
733 { .compatible = "allwinner,sun6i-a31-rtc" },
734 { .compatible = "allwinner,sun8i-a23-rtc" },
735 { .compatible = "allwinner,sun8i-h3-rtc" },
736 { .compatible = "allwinner,sun8i-r40-rtc" },
737 { .compatible = "allwinner,sun8i-v3-rtc" },
738 { .compatible = "allwinner,sun50i-h5-rtc" },
739 { .compatible = "allwinner,sun50i-h6-rtc" },
740 { /* sentinel */ },
741 };
742 MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
743
744 static struct platform_driver sun6i_rtc_driver = {
745 .probe = sun6i_rtc_probe,
746 .driver = {
747 .name = "sun6i-rtc",
748 .of_match_table = sun6i_rtc_dt_ids,
749 .pm = &sun6i_rtc_pm_ops,
750 },
751 };
752 builtin_platform_driver(sun6i_rtc_driver);
753