1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
48
49
pm80xx_bar4_shift(struct pm8001_hba_info * pm8001_ha,u32 shift_value)50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51 {
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
62 reg_val);
63 return -1;
64 }
65 return 0;
66 }
67
pm80xx_pci_mem_copy(struct pm8001_hba_info * pm8001_ha,u32 soffset,__le32 * destination,u32 dw_count,u32 bus_base_number)68 static void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
69 __le32 *destination,
70 u32 dw_count, u32 bus_base_number)
71 {
72 u32 index, value, offset;
73
74 for (index = 0; index < dw_count; index += 4, destination++) {
75 offset = (soffset + index);
76 if (offset < (64 * 1024)) {
77 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
78 *destination = cpu_to_le32(value);
79 }
80 }
81 return;
82 }
83
pm80xx_get_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)84 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
85 struct device_attribute *attr, char *buf)
86 {
87 struct Scsi_Host *shost = class_to_shost(cdev);
88 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
89 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
90 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
91 u32 accum_len, reg_val, index, *temp;
92 u32 status = 1;
93 unsigned long start;
94 u8 *direct_data;
95 char *fatal_error_data = buf;
96 u32 length_to_read;
97 u32 offset;
98
99 pm8001_ha->forensic_info.data_buf.direct_data = buf;
100 if (pm8001_ha->chip_id == chip_8001) {
101 pm8001_ha->forensic_info.data_buf.direct_data +=
102 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
103 "Not supported for SPC controller");
104 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
105 (char *)buf;
106 }
107 /* initialize variables for very first call from host application */
108 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
109 pm8001_dbg(pm8001_ha, IO,
110 "forensic_info TYPE_NON_FATAL..............\n");
111 direct_data = (u8 *)fatal_error_data;
112 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
113 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
114 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
115 pm8001_ha->forensic_info.data_buf.read_len = 0;
116 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
117
118 /* Write signature to fatal dump table */
119 pm8001_mw32(fatal_table_address,
120 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
121
122 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
123 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
124 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
125 pm8001_ha->forensic_info.data_buf.read_len);
126 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
127 pm8001_ha->forensic_info.data_buf.direct_len);
128 pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
129 pm8001_ha->forensic_info.data_buf.direct_offset);
130 }
131 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
132 /* start to get data */
133 /* Program the MEMBASE II Shifting Register with 0x00.*/
134 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
135 pm8001_ha->fatal_forensic_shift_offset);
136 pm8001_ha->forensic_last_offset = 0;
137 pm8001_ha->forensic_fatal_step = 0;
138 pm8001_ha->fatal_bar_loc = 0;
139 }
140
141 /* Read until accum_len is retrieved */
142 accum_len = pm8001_mr32(fatal_table_address,
143 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
144 /* Determine length of data between previously stored transfer length
145 * and current accumulated transfer length
146 */
147 length_to_read =
148 accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
149 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
150 accum_len);
151 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
152 length_to_read);
153 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
154 pm8001_ha->forensic_last_offset);
155 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
156 pm8001_ha->forensic_info.data_buf.read_len);
157 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
158 pm8001_ha->forensic_info.data_buf.direct_len);
159 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
160 pm8001_ha->forensic_info.data_buf.direct_offset);
161
162 /* If accumulated length failed to read correctly fail the attempt.*/
163 if (accum_len == 0xFFFFFFFF) {
164 pm8001_dbg(pm8001_ha, IO,
165 "Possible PCI issue 0x%x not expected\n",
166 accum_len);
167 return status;
168 }
169 /* If accumulated length is zero fail the attempt */
170 if (accum_len == 0) {
171 pm8001_ha->forensic_info.data_buf.direct_data +=
172 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
173 "%08x ", 0xFFFFFFFF);
174 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
175 (char *)buf;
176 }
177 /* Accumulated length is good so start capturing the first data */
178 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
179 if (pm8001_ha->forensic_fatal_step == 0) {
180 moreData:
181 /* If data to read is less than SYSFS_OFFSET then reduce the
182 * length of dataLen
183 */
184 if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
185 > length_to_read) {
186 pm8001_ha->forensic_info.data_buf.direct_len =
187 length_to_read -
188 pm8001_ha->forensic_last_offset;
189 } else {
190 pm8001_ha->forensic_info.data_buf.direct_len =
191 SYSFS_OFFSET;
192 }
193 if (pm8001_ha->forensic_info.data_buf.direct_data) {
194 /* Data is in bar, copy to host memory */
195 pm80xx_pci_mem_copy(pm8001_ha,
196 pm8001_ha->fatal_bar_loc,
197 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
198 pm8001_ha->forensic_info.data_buf.direct_len, 1);
199 }
200 pm8001_ha->fatal_bar_loc +=
201 pm8001_ha->forensic_info.data_buf.direct_len;
202 pm8001_ha->forensic_info.data_buf.direct_offset +=
203 pm8001_ha->forensic_info.data_buf.direct_len;
204 pm8001_ha->forensic_last_offset +=
205 pm8001_ha->forensic_info.data_buf.direct_len;
206 pm8001_ha->forensic_info.data_buf.read_len =
207 pm8001_ha->forensic_info.data_buf.direct_len;
208
209 if (pm8001_ha->forensic_last_offset >= length_to_read) {
210 pm8001_ha->forensic_info.data_buf.direct_data +=
211 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
212 "%08x ", 3);
213 for (index = 0; index <
214 (pm8001_ha->forensic_info.data_buf.direct_len
215 / 4); index++) {
216 pm8001_ha->forensic_info.data_buf.direct_data +=
217 sprintf(
218 pm8001_ha->forensic_info.data_buf.direct_data,
219 "%08x ", *(temp + index));
220 }
221
222 pm8001_ha->fatal_bar_loc = 0;
223 pm8001_ha->forensic_fatal_step = 1;
224 pm8001_ha->fatal_forensic_shift_offset = 0;
225 pm8001_ha->forensic_last_offset = 0;
226 status = 0;
227 offset = (int)
228 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
229 - (char *)buf);
230 pm8001_dbg(pm8001_ha, IO,
231 "get_fatal_spcv:return1 0x%x\n", offset);
232 return (char *)pm8001_ha->
233 forensic_info.data_buf.direct_data -
234 (char *)buf;
235 }
236 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
237 pm8001_ha->forensic_info.data_buf.direct_data +=
238 sprintf(pm8001_ha->
239 forensic_info.data_buf.direct_data,
240 "%08x ", 2);
241 for (index = 0; index <
242 (pm8001_ha->forensic_info.data_buf.direct_len
243 / 4); index++) {
244 pm8001_ha->forensic_info.data_buf.direct_data
245 += sprintf(pm8001_ha->
246 forensic_info.data_buf.direct_data,
247 "%08x ", *(temp + index));
248 }
249 status = 0;
250 offset = (int)
251 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
252 - (char *)buf);
253 pm8001_dbg(pm8001_ha, IO,
254 "get_fatal_spcv:return2 0x%x\n", offset);
255 return (char *)pm8001_ha->
256 forensic_info.data_buf.direct_data -
257 (char *)buf;
258 }
259
260 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
261 pm8001_ha->forensic_info.data_buf.direct_data +=
262 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
263 "%08x ", 2);
264 for (index = 0; index <
265 (pm8001_ha->forensic_info.data_buf.direct_len
266 / 4) ; index++) {
267 pm8001_ha->forensic_info.data_buf.direct_data +=
268 sprintf(pm8001_ha->
269 forensic_info.data_buf.direct_data,
270 "%08x ", *(temp + index));
271 }
272 pm8001_ha->fatal_forensic_shift_offset += 0x100;
273 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
274 pm8001_ha->fatal_forensic_shift_offset);
275 pm8001_ha->fatal_bar_loc = 0;
276 status = 0;
277 offset = (int)
278 ((char *)pm8001_ha->forensic_info.data_buf.direct_data
279 - (char *)buf);
280 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
281 offset);
282 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
283 (char *)buf;
284 }
285 if (pm8001_ha->forensic_fatal_step == 1) {
286 /* store previous accumulated length before triggering next
287 * accumulated length update
288 */
289 pm8001_ha->forensic_preserved_accumulated_transfer =
290 pm8001_mr32(fatal_table_address,
291 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
292
293 /* continue capturing the fatal log until Dump status is 0x3 */
294 if (pm8001_mr32(fatal_table_address,
295 MPI_FATAL_EDUMP_TABLE_STATUS) <
296 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
297
298 /* reset fddstat bit by writing to zero*/
299 pm8001_mw32(fatal_table_address,
300 MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
301
302 /* set dump control value to '1' so that new data will
303 * be transferred to shared memory
304 */
305 pm8001_mw32(fatal_table_address,
306 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
307 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
308
309 /*Poll FDDHSHK until clear */
310 start = jiffies + (2 * HZ); /* 2 sec */
311
312 do {
313 reg_val = pm8001_mr32(fatal_table_address,
314 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
315 } while ((reg_val) && time_before(jiffies, start));
316
317 if (reg_val != 0) {
318 pm8001_dbg(pm8001_ha, FAIL,
319 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
320 reg_val);
321 /* Fail the dump if a timeout occurs */
322 pm8001_ha->forensic_info.data_buf.direct_data +=
323 sprintf(
324 pm8001_ha->forensic_info.data_buf.direct_data,
325 "%08x ", 0xFFFFFFFF);
326 return((char *)
327 pm8001_ha->forensic_info.data_buf.direct_data
328 - (char *)buf);
329 }
330 /* Poll status register until set to 2 or
331 * 3 for up to 2 seconds
332 */
333 start = jiffies + (2 * HZ); /* 2 sec */
334
335 do {
336 reg_val = pm8001_mr32(fatal_table_address,
337 MPI_FATAL_EDUMP_TABLE_STATUS);
338 } while (((reg_val != 2) && (reg_val != 3)) &&
339 time_before(jiffies, start));
340
341 if (reg_val < 2) {
342 pm8001_dbg(pm8001_ha, FAIL,
343 "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
344 reg_val);
345 /* Fail the dump if a timeout occurs */
346 pm8001_ha->forensic_info.data_buf.direct_data +=
347 sprintf(
348 pm8001_ha->forensic_info.data_buf.direct_data,
349 "%08x ", 0xFFFFFFFF);
350 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
351 (char *)buf);
352 }
353 /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
354 pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
355 pm8001_cw32(pm8001_ha, 0,
356 MEMBASE_II_SHIFT_REGISTER,
357 pm8001_ha->fatal_forensic_shift_offset);
358 }
359 /* Read the next block of the debug data.*/
360 length_to_read = pm8001_mr32(fatal_table_address,
361 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
362 pm8001_ha->forensic_preserved_accumulated_transfer;
363 if (length_to_read != 0x0) {
364 pm8001_ha->forensic_fatal_step = 0;
365 goto moreData;
366 } else {
367 pm8001_ha->forensic_info.data_buf.direct_data +=
368 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
369 "%08x ", 4);
370 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
371 pm8001_ha->forensic_info.data_buf.direct_len = 0;
372 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
373 pm8001_ha->forensic_info.data_buf.read_len = 0;
374 }
375 }
376 offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
377 - (char *)buf);
378 pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
379 return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
380 (char *)buf);
381 }
382
383 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
384 * location by the firmware.
385 */
pm80xx_get_non_fatal_dump(struct device * cdev,struct device_attribute * attr,char * buf)386 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
387 struct device_attribute *attr, char *buf)
388 {
389 struct Scsi_Host *shost = class_to_shost(cdev);
390 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
391 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
392 void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
393 u32 accum_len = 0;
394 u32 total_len = 0;
395 u32 reg_val = 0;
396 u32 *temp = NULL;
397 u32 index = 0;
398 u32 output_length;
399 unsigned long start = 0;
400 char *buf_copy = buf;
401
402 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
403 if (++pm8001_ha->non_fatal_count == 1) {
404 if (pm8001_ha->chip_id == chip_8001) {
405 snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
406 PAGE_SIZE, "Not supported for SPC controller");
407 return 0;
408 }
409 pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
410 /*
411 * Step 1: Write the host buffer parameters in the MPI Fatal and
412 * Non-Fatal Error Dump Capture Table.This is the buffer
413 * where debug data will be DMAed to.
414 */
415 pm8001_mw32(nonfatal_table_address,
416 MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
417 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
418
419 pm8001_mw32(nonfatal_table_address,
420 MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
421 pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
422
423 pm8001_mw32(nonfatal_table_address,
424 MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
425
426 /* Optionally, set the DUMPCTRL bit to 1 if the host
427 * keeps sending active I/Os while capturing the non-fatal
428 * debug data. Otherwise, leave this bit set to zero
429 */
430 pm8001_mw32(nonfatal_table_address,
431 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
432
433 /*
434 * Step 2: Clear Accumulative Length of Debug Data Transferred
435 * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
436 * Capture Table to zero.
437 */
438 pm8001_mw32(nonfatal_table_address,
439 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
440
441 /* initiallize previous accumulated length to 0 */
442 pm8001_ha->forensic_preserved_accumulated_transfer = 0;
443 pm8001_ha->non_fatal_read_length = 0;
444 }
445
446 total_len = pm8001_mr32(nonfatal_table_address,
447 MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
448 /*
449 * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
450 * field and then request that the SPCv controller transfer the debug
451 * data by setting bit 7 of the Inbound Doorbell Set Register.
452 */
453 pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
454 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
455 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
456
457 /*
458 * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
459 * 2 seconds) until register bit 7 is cleared.
460 * This step only indicates the request is accepted by the controller.
461 */
462 start = jiffies + (2 * HZ); /* 2 sec */
463 do {
464 reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
465 SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
466 } while ((reg_val != 0) && time_before(jiffies, start));
467
468 /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
469 * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
470 * the MPI Fatal and Non-Fatal Error Dump Capture Table.
471 */
472 start = jiffies + (2 * HZ); /* 2 sec */
473 do {
474 reg_val = pm8001_mr32(nonfatal_table_address,
475 MPI_FATAL_EDUMP_TABLE_STATUS);
476 } while ((!reg_val) && time_before(jiffies, start));
477
478 if ((reg_val == 0x00) ||
479 (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
480 (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
481 pm8001_ha->non_fatal_read_length = 0;
482 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
483 pm8001_ha->non_fatal_count = 0;
484 return (buf_copy - buf);
485 } else if (reg_val ==
486 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
487 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
488 } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
489 (pm8001_ha->non_fatal_read_length >= total_len)) {
490 pm8001_ha->non_fatal_read_length = 0;
491 buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
492 pm8001_ha->non_fatal_count = 0;
493 }
494 accum_len = pm8001_mr32(nonfatal_table_address,
495 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
496 output_length = accum_len -
497 pm8001_ha->forensic_preserved_accumulated_transfer;
498
499 for (index = 0; index < output_length/4; index++)
500 buf_copy += snprintf(buf_copy, PAGE_SIZE,
501 "%08x ", *(temp+index));
502
503 pm8001_ha->non_fatal_read_length += output_length;
504
505 /* store current accumulated length to use in next iteration as
506 * the previous accumulated length
507 */
508 pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
509 return (buf_copy - buf);
510 }
511
512 /**
513 * read_main_config_table - read the configure table and save it.
514 * @pm8001_ha: our hba card information
515 */
read_main_config_table(struct pm8001_hba_info * pm8001_ha)516 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
517 {
518 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
519
520 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
521 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
522 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
523 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
524 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
525 pm8001_mr32(address, MAIN_FW_REVISION);
526 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
527 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
528 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
529 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
530 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
531 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
532 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
533 pm8001_mr32(address, MAIN_GST_OFFSET);
534 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
535 pm8001_mr32(address, MAIN_IBQ_OFFSET);
536 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
537 pm8001_mr32(address, MAIN_OBQ_OFFSET);
538
539 /* read Error Dump Offset and Length */
540 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
541 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
542 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
543 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
544 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
545 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
546 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
547 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
548
549 /* read GPIO LED settings from the configuration table */
550 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
551 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
552
553 /* read analog Setting offset from the configuration table */
554 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
555 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
556
557 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
558 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
559 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
560 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
561 /* read port recover and reset timeout */
562 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
563 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
564 /* read ILA and inactive firmware version */
565 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
566 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
567 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
568 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
569
570 pm8001_dbg(pm8001_ha, DEV,
571 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
572 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
575
576 pm8001_dbg(pm8001_ha, DEV,
577 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
578 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
583
584 pm8001_dbg(pm8001_ha, DEV,
585 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
586 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
588 }
589
590 /**
591 * read_general_status_table - read the general status table and save it.
592 * @pm8001_ha: our hba card information
593 */
read_general_status_table(struct pm8001_hba_info * pm8001_ha)594 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
595 {
596 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
597 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
598 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
599 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
600 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
601 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
602 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
603 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
604 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
605 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
606 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
607 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
608 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
609 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
610 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
611 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
612 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
613 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
614 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
615 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
616 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
617 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
618 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
619 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
620 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
621 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
622 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
623 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
624 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
625 }
626 /**
627 * read_phy_attr_table - read the phy attribute table and save it.
628 * @pm8001_ha: our hba card information
629 */
read_phy_attr_table(struct pm8001_hba_info * pm8001_ha)630 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
631 {
632 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
633 pm8001_ha->phy_attr_table.phystart1_16[0] =
634 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
635 pm8001_ha->phy_attr_table.phystart1_16[1] =
636 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
637 pm8001_ha->phy_attr_table.phystart1_16[2] =
638 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
639 pm8001_ha->phy_attr_table.phystart1_16[3] =
640 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
641 pm8001_ha->phy_attr_table.phystart1_16[4] =
642 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
643 pm8001_ha->phy_attr_table.phystart1_16[5] =
644 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
645 pm8001_ha->phy_attr_table.phystart1_16[6] =
646 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
647 pm8001_ha->phy_attr_table.phystart1_16[7] =
648 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
649 pm8001_ha->phy_attr_table.phystart1_16[8] =
650 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
651 pm8001_ha->phy_attr_table.phystart1_16[9] =
652 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
653 pm8001_ha->phy_attr_table.phystart1_16[10] =
654 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
655 pm8001_ha->phy_attr_table.phystart1_16[11] =
656 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
657 pm8001_ha->phy_attr_table.phystart1_16[12] =
658 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
659 pm8001_ha->phy_attr_table.phystart1_16[13] =
660 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
661 pm8001_ha->phy_attr_table.phystart1_16[14] =
662 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
663 pm8001_ha->phy_attr_table.phystart1_16[15] =
664 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
665
666 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
667 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
668 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
669 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
670 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
671 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
672 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
673 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
674 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
675 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
676 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
677 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
678 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
679 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
680 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
681 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
682 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
683 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
684 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
685 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
686 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
687 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
688 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
689 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
690 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
691 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
692 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
693 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
694 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
695 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
696 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
697 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
698
699 }
700
701 /**
702 * read_inbnd_queue_table - read the inbound queue table and save it.
703 * @pm8001_ha: our hba card information
704 */
read_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha)705 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
706 {
707 int i;
708 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
709 for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
710 u32 offset = i * 0x20;
711 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
712 get_pci_bar_index(pm8001_mr32(address,
713 (offset + IB_PIPCI_BAR)));
714 pm8001_ha->inbnd_q_tbl[i].pi_offset =
715 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
716 }
717 }
718
719 /**
720 * read_outbnd_queue_table - read the outbound queue table and save it.
721 * @pm8001_ha: our hba card information
722 */
read_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha)723 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
724 {
725 int i;
726 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
727 for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
728 u32 offset = i * 0x24;
729 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
730 get_pci_bar_index(pm8001_mr32(address,
731 (offset + OB_CIPCI_BAR)));
732 pm8001_ha->outbnd_q_tbl[i].ci_offset =
733 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
734 }
735 }
736
737 /**
738 * init_default_table_values - init the default table.
739 * @pm8001_ha: our hba card information
740 */
init_default_table_values(struct pm8001_hba_info * pm8001_ha)741 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
742 {
743 int i;
744 u32 offsetib, offsetob;
745 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
746 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
747 u32 ib_offset = pm8001_ha->ib_offset;
748 u32 ob_offset = pm8001_ha->ob_offset;
749 u32 ci_offset = pm8001_ha->ci_offset;
750 u32 pi_offset = pm8001_ha->pi_offset;
751
752 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
753 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
754 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
755 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
756 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
757 PM8001_EVENT_LOG_SIZE;
758 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
760 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
761 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
762 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
763 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
764 PM8001_EVENT_LOG_SIZE;
765 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
767
768 /* Enable higher IQs and OQs, 32 to 63, bit 16 */
769 if (pm8001_ha->max_q_num > 32)
770 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
771 1 << 16;
772 /* Disable end to end CRC checking */
773 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
774
775 for (i = 0; i < pm8001_ha->max_q_num; i++) {
776 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
777 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
778 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
779 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
780 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
781 pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
782 pm8001_ha->inbnd_q_tbl[i].base_virt =
783 (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
784 pm8001_ha->inbnd_q_tbl[i].total_length =
785 pm8001_ha->memoryMap.region[ib_offset + i].total_len;
786 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
787 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
788 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
789 pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
790 pm8001_ha->inbnd_q_tbl[i].ci_virt =
791 pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
792 pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
793 offsetib = i * 0x20;
794 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
795 get_pci_bar_index(pm8001_mr32(addressib,
796 (offsetib + 0x14)));
797 pm8001_ha->inbnd_q_tbl[i].pi_offset =
798 pm8001_mr32(addressib, (offsetib + 0x18));
799 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
800 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
801
802 pm8001_dbg(pm8001_ha, DEV,
803 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
804 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
805 pm8001_ha->inbnd_q_tbl[i].pi_offset);
806 }
807 for (i = 0; i < pm8001_ha->max_q_num; i++) {
808 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
809 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
810 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
811 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
812 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
813 pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
814 pm8001_ha->outbnd_q_tbl[i].base_virt =
815 (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
816 pm8001_ha->outbnd_q_tbl[i].total_length =
817 pm8001_ha->memoryMap.region[ob_offset + i].total_len;
818 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
819 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
820 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
821 pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
822 /* interrupt vector based on oq */
823 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
824 pm8001_ha->outbnd_q_tbl[i].pi_virt =
825 pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
826 pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
827 offsetob = i * 0x24;
828 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
829 get_pci_bar_index(pm8001_mr32(addressob,
830 offsetob + 0x14));
831 pm8001_ha->outbnd_q_tbl[i].ci_offset =
832 pm8001_mr32(addressob, (offsetob + 0x18));
833 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
834 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
835
836 pm8001_dbg(pm8001_ha, DEV,
837 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
838 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
839 pm8001_ha->outbnd_q_tbl[i].ci_offset);
840 }
841 }
842
843 /**
844 * update_main_config_table - update the main default table to the HBA.
845 * @pm8001_ha: our hba card information
846 */
update_main_config_table(struct pm8001_hba_info * pm8001_ha)847 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
848 {
849 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
850 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
851 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
852 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
853 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
854 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
855 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
856 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
857 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
858 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
859 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
860 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
861 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
862 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
863 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
864 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
865 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
866 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
867 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
868 /* Update Fatal error interrupt vector */
869 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
870 ((pm8001_ha->max_q_num - 1) << 8);
871 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
872 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
873 pm8001_dbg(pm8001_ha, DEV,
874 "Updated Fatal error interrupt vector 0x%x\n",
875 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
876
877 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
878 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
879
880 /* SPCv specific */
881 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
882 /* Set GPIOLED to 0x2 for LED indicator */
883 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
884 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
885 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
886 pm8001_dbg(pm8001_ha, DEV,
887 "Programming DW 0x21 in main cfg table with 0x%x\n",
888 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
889
890 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
891 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
892 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
893 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
894
895 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
896 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
897 PORT_RECOVERY_TIMEOUT;
898 if (pm8001_ha->chip_id == chip_8006) {
899 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
900 0x0000ffff;
901 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
902 CHIP_8006_PORT_RECOVERY_TIMEOUT;
903 }
904 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
905 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
906 }
907
908 /**
909 * update_inbnd_queue_table - update the inbound queue table to the HBA.
910 * @pm8001_ha: our hba card information
911 * @number: entry in the queue
912 */
update_inbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)913 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
914 int number)
915 {
916 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
917 u16 offset = number * 0x20;
918 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
919 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
920 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
921 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
922 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
923 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
924 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
925 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
926 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
927 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
928
929 pm8001_dbg(pm8001_ha, DEV,
930 "IQ %d: Element pri size 0x%x\n",
931 number,
932 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
933
934 pm8001_dbg(pm8001_ha, DEV,
935 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
936 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
937 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
938
939 pm8001_dbg(pm8001_ha, DEV,
940 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
941 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
942 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
943 }
944
945 /**
946 * update_outbnd_queue_table - update the outbound queue table to the HBA.
947 * @pm8001_ha: our hba card information
948 * @number: entry in the queue
949 */
update_outbnd_queue_table(struct pm8001_hba_info * pm8001_ha,int number)950 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
951 int number)
952 {
953 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
954 u16 offset = number * 0x24;
955 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
956 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
957 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
958 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
959 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
960 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
961 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
962 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
963 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
964 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
965 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
966 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
967
968 pm8001_dbg(pm8001_ha, DEV,
969 "OQ %d: Element pri size 0x%x\n",
970 number,
971 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
972
973 pm8001_dbg(pm8001_ha, DEV,
974 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
975 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
976 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
977
978 pm8001_dbg(pm8001_ha, DEV,
979 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
980 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
981 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
982 }
983
984 /**
985 * mpi_init_check - check firmware initialization status.
986 * @pm8001_ha: our hba card information
987 */
mpi_init_check(struct pm8001_hba_info * pm8001_ha)988 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
989 {
990 u32 max_wait_count;
991 u32 value;
992 u32 gst_len_mpistate;
993
994 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
995 table is updated */
996 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
997 /* wait until Inbound DoorBell Clear Register toggled */
998 if (IS_SPCV_12G(pm8001_ha->pdev)) {
999 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1000 } else {
1001 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1002 }
1003 do {
1004 msleep(FW_READY_INTERVAL);
1005 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1006 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1007 } while ((value != 0) && (--max_wait_count));
1008
1009 if (!max_wait_count) {
1010 /* additional check */
1011 pm8001_dbg(pm8001_ha, FAIL,
1012 "Inb doorbell clear not toggled[value:%x]\n",
1013 value);
1014 return -EBUSY;
1015 }
1016 /* check the MPI-State for initialization up to 100ms*/
1017 max_wait_count = 5;/* 100 msec */
1018 do {
1019 msleep(FW_READY_INTERVAL);
1020 gst_len_mpistate =
1021 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1022 GST_GSTLEN_MPIS_OFFSET);
1023 } while ((GST_MPI_STATE_INIT !=
1024 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1025 if (!max_wait_count)
1026 return -EBUSY;
1027
1028 /* check MPI Initialization error */
1029 gst_len_mpistate = gst_len_mpistate >> 16;
1030 if (0x0000 != gst_len_mpistate)
1031 return -EBUSY;
1032
1033 /*
1034 * As per controller datasheet, after successful MPI
1035 * initialization minimum 500ms delay is required before
1036 * issuing commands.
1037 */
1038 msleep(500);
1039
1040 return 0;
1041 }
1042
1043 /**
1044 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1045 * This function sleeps hence it must not be used in atomic context.
1046 * @pm8001_ha: our hba card information
1047 */
check_fw_ready(struct pm8001_hba_info * pm8001_ha)1048 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1049 {
1050 u32 value;
1051 u32 max_wait_count;
1052 u32 max_wait_time;
1053 u32 expected_mask;
1054 int ret = 0;
1055
1056 /* reset / PCIe ready */
1057 max_wait_time = max_wait_count = 5; /* 100 milli sec */
1058 do {
1059 msleep(FW_READY_INTERVAL);
1060 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1061 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1062
1063 /* check ila, RAAE and iops status */
1064 if ((pm8001_ha->chip_id != chip_8008) &&
1065 (pm8001_ha->chip_id != chip_8009)) {
1066 max_wait_time = max_wait_count = 180; /* 3600 milli sec */
1067 expected_mask = SCRATCH_PAD_ILA_READY |
1068 SCRATCH_PAD_RAAE_READY |
1069 SCRATCH_PAD_IOP0_READY |
1070 SCRATCH_PAD_IOP1_READY;
1071 } else {
1072 max_wait_time = max_wait_count = 170; /* 3400 milli sec */
1073 expected_mask = SCRATCH_PAD_ILA_READY |
1074 SCRATCH_PAD_RAAE_READY |
1075 SCRATCH_PAD_IOP0_READY;
1076 }
1077 do {
1078 msleep(FW_READY_INTERVAL);
1079 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1080 } while (((value & expected_mask) !=
1081 expected_mask) && (--max_wait_count));
1082 if (!max_wait_count) {
1083 pm8001_dbg(pm8001_ha, INIT,
1084 "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1085 max_wait_time * FW_READY_INTERVAL, value);
1086 ret = -1;
1087 } else {
1088 pm8001_dbg(pm8001_ha, MSG,
1089 "All FW components ready by %d ms\n",
1090 (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1091 }
1092 return ret;
1093 }
1094
init_pci_device_addresses(struct pm8001_hba_info * pm8001_ha)1095 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1096 {
1097 void __iomem *base_addr;
1098 u32 value;
1099 u32 offset;
1100 u32 pcibar;
1101 u32 pcilogic;
1102
1103 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1104
1105 /*
1106 * lower 26 bits of SCRATCHPAD0 register describes offset within the
1107 * PCIe BAR where the MPI configuration table is present
1108 */
1109 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1110
1111 pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1112 offset, value);
1113 /*
1114 * Upper 6 bits describe the offset within PCI config space where BAR
1115 * is located.
1116 */
1117 pcilogic = (value & 0xFC000000) >> 26;
1118 pcibar = get_pci_bar_index(pcilogic);
1119 pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1120
1121 /*
1122 * Make sure the offset falls inside the ioremapped PCI BAR
1123 */
1124 if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1125 pm8001_dbg(pm8001_ha, FAIL,
1126 "Main cfg tbl offset outside %u > %u\n",
1127 offset, pm8001_ha->io_mem[pcibar].memsize);
1128 return -EBUSY;
1129 }
1130 pm8001_ha->main_cfg_tbl_addr = base_addr =
1131 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1132
1133 /*
1134 * Validate main configuration table address: first DWord should read
1135 * "PMCS"
1136 */
1137 value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1138 if (memcmp(&value, "PMCS", 4) != 0) {
1139 pm8001_dbg(pm8001_ha, FAIL,
1140 "BAD main config signature 0x%x\n",
1141 value);
1142 return -EBUSY;
1143 }
1144 pm8001_dbg(pm8001_ha, INIT,
1145 "VALID main config signature 0x%x\n", value);
1146 pm8001_ha->general_stat_tbl_addr =
1147 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1148 0xFFFFFF);
1149 pm8001_ha->inbnd_q_tbl_addr =
1150 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1151 0xFFFFFF);
1152 pm8001_ha->outbnd_q_tbl_addr =
1153 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1154 0xFFFFFF);
1155 pm8001_ha->ivt_tbl_addr =
1156 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1157 0xFFFFFF);
1158 pm8001_ha->pspa_q_tbl_addr =
1159 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1160 0xFFFFFF);
1161 pm8001_ha->fatal_tbl_addr =
1162 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1163 0xFFFFFF);
1164
1165 pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1166 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1167 pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1168 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1169 pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1170 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1171 pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1172 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1173 pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1174 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1175 pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1176 pm8001_ha->main_cfg_tbl_addr,
1177 pm8001_ha->general_stat_tbl_addr);
1178 pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1179 pm8001_ha->inbnd_q_tbl_addr,
1180 pm8001_ha->outbnd_q_tbl_addr);
1181 pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1182 pm8001_ha->pspa_q_tbl_addr,
1183 pm8001_ha->ivt_tbl_addr);
1184 return 0;
1185 }
1186
1187 /**
1188 * pm80xx_set_thermal_config - support the thermal configuration
1189 * @pm8001_ha: our hba card information.
1190 */
1191 int
pm80xx_set_thermal_config(struct pm8001_hba_info * pm8001_ha)1192 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1193 {
1194 struct set_ctrl_cfg_req payload;
1195 struct inbound_queue_table *circularQ;
1196 int rc;
1197 u32 tag;
1198 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1199 u32 page_code;
1200
1201 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1202 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1203 if (rc)
1204 return -1;
1205
1206 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1207 payload.tag = cpu_to_le32(tag);
1208
1209 if (IS_SPCV_12G(pm8001_ha->pdev))
1210 page_code = THERMAL_PAGE_CODE_7H;
1211 else
1212 page_code = THERMAL_PAGE_CODE_8H;
1213
1214 payload.cfg_pg[0] =
1215 cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1216 (THERMAL_ENABLE << 8) | page_code);
1217 payload.cfg_pg[1] =
1218 cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1219
1220 pm8001_dbg(pm8001_ha, DEV,
1221 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1222 payload.cfg_pg[0], payload.cfg_pg[1]);
1223
1224 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1225 sizeof(payload), 0);
1226 if (rc)
1227 pm8001_tag_free(pm8001_ha, tag);
1228 return rc;
1229
1230 }
1231
1232 /**
1233 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1234 * Timer configuration page
1235 * @pm8001_ha: our hba card information.
1236 */
1237 static int
pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info * pm8001_ha)1238 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1239 {
1240 struct set_ctrl_cfg_req payload;
1241 struct inbound_queue_table *circularQ;
1242 SASProtocolTimerConfig_t SASConfigPage;
1243 int rc;
1244 u32 tag;
1245 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1246
1247 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1248 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1249
1250 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1251
1252 if (rc)
1253 return -1;
1254
1255 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1256 payload.tag = cpu_to_le32(tag);
1257
1258 SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1259 SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1260 SASConfigPage.STP_SSP_MCT_TMO =
1261 cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1262 SASConfigPage.STP_FRM_TMO =
1263 cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1264 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1265 SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1266
1267 SASConfigPage.OPNRJT_RTRY_INTVL =
1268 cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1269 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1270 cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1271 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1272 cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1273 SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1274
1275 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1276 le32_to_cpu(SASConfigPage.pageCode));
1277 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI 0x%08x\n",
1278 le32_to_cpu(SASConfigPage.MST_MSI));
1279 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO 0x%08x\n",
1280 le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1281 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO 0x%08x\n",
1282 le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1283 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO 0x%08x\n",
1284 le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1285 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL 0x%08x\n",
1286 le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1287 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO 0x%08x\n",
1288 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1289 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR 0x%08x\n",
1290 le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1291 pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP 0x%08x\n",
1292 le32_to_cpu(SASConfigPage.MAX_AIP));
1293
1294 memcpy(&payload.cfg_pg, &SASConfigPage,
1295 sizeof(SASProtocolTimerConfig_t));
1296
1297 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1298 sizeof(payload), 0);
1299 if (rc)
1300 pm8001_tag_free(pm8001_ha, tag);
1301
1302 return rc;
1303 }
1304
1305 /**
1306 * pm80xx_get_encrypt_info - Check for encryption
1307 * @pm8001_ha: our hba card information.
1308 */
1309 static int
pm80xx_get_encrypt_info(struct pm8001_hba_info * pm8001_ha)1310 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1311 {
1312 u32 scratch3_value;
1313 int ret = -1;
1314
1315 /* Read encryption status from SCRATCH PAD 3 */
1316 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1317
1318 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1319 SCRATCH_PAD3_ENC_READY) {
1320 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1321 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1322 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1323 SCRATCH_PAD3_SMF_ENABLED)
1324 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1325 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1326 SCRATCH_PAD3_SMA_ENABLED)
1327 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1328 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1329 SCRATCH_PAD3_SMB_ENABLED)
1330 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1331 pm8001_ha->encrypt_info.status = 0;
1332 pm8001_dbg(pm8001_ha, INIT,
1333 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1334 scratch3_value,
1335 pm8001_ha->encrypt_info.cipher_mode,
1336 pm8001_ha->encrypt_info.sec_mode,
1337 pm8001_ha->encrypt_info.status);
1338 ret = 0;
1339 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1340 SCRATCH_PAD3_ENC_DISABLED) {
1341 pm8001_dbg(pm8001_ha, INIT,
1342 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1343 scratch3_value);
1344 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1345 pm8001_ha->encrypt_info.cipher_mode = 0;
1346 pm8001_ha->encrypt_info.sec_mode = 0;
1347 ret = 0;
1348 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1349 SCRATCH_PAD3_ENC_DIS_ERR) {
1350 pm8001_ha->encrypt_info.status =
1351 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1352 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1353 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1354 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1355 SCRATCH_PAD3_SMF_ENABLED)
1356 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1357 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1358 SCRATCH_PAD3_SMA_ENABLED)
1359 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1360 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1361 SCRATCH_PAD3_SMB_ENABLED)
1362 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1363 pm8001_dbg(pm8001_ha, INIT,
1364 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1365 scratch3_value,
1366 pm8001_ha->encrypt_info.cipher_mode,
1367 pm8001_ha->encrypt_info.sec_mode,
1368 pm8001_ha->encrypt_info.status);
1369 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1370 SCRATCH_PAD3_ENC_ENA_ERR) {
1371
1372 pm8001_ha->encrypt_info.status =
1373 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1374 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1375 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1376 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1377 SCRATCH_PAD3_SMF_ENABLED)
1378 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1379 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1380 SCRATCH_PAD3_SMA_ENABLED)
1381 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1382 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1383 SCRATCH_PAD3_SMB_ENABLED)
1384 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1385
1386 pm8001_dbg(pm8001_ha, INIT,
1387 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1388 scratch3_value,
1389 pm8001_ha->encrypt_info.cipher_mode,
1390 pm8001_ha->encrypt_info.sec_mode,
1391 pm8001_ha->encrypt_info.status);
1392 }
1393 return ret;
1394 }
1395
1396 /**
1397 * pm80xx_encrypt_update - update flash with encryption information
1398 * @pm8001_ha: our hba card information.
1399 */
pm80xx_encrypt_update(struct pm8001_hba_info * pm8001_ha)1400 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1401 {
1402 struct kek_mgmt_req payload;
1403 struct inbound_queue_table *circularQ;
1404 int rc;
1405 u32 tag;
1406 u32 opc = OPC_INB_KEK_MANAGEMENT;
1407
1408 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1409 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1410 if (rc)
1411 return -1;
1412
1413 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1414 payload.tag = cpu_to_le32(tag);
1415 /* Currently only one key is used. New KEK index is 1.
1416 * Current KEK index is 1. Store KEK to NVRAM is 1.
1417 */
1418 payload.new_curidx_ksop =
1419 cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1420 KEK_MGMT_SUBOP_KEYCARDUPDATE));
1421
1422 pm8001_dbg(pm8001_ha, DEV,
1423 "Saving Encryption info to flash. payload 0x%x\n",
1424 le32_to_cpu(payload.new_curidx_ksop));
1425
1426 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1427 sizeof(payload), 0);
1428 if (rc)
1429 pm8001_tag_free(pm8001_ha, tag);
1430
1431 return rc;
1432 }
1433
1434 /**
1435 * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1436 * @pm8001_ha: our hba card information
1437 */
pm80xx_chip_init(struct pm8001_hba_info * pm8001_ha)1438 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1439 {
1440 int ret;
1441 u8 i = 0;
1442
1443 /* check the firmware status */
1444 if (-1 == check_fw_ready(pm8001_ha)) {
1445 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1446 return -EBUSY;
1447 }
1448
1449 /* Initialize the controller fatal error flag */
1450 pm8001_ha->controller_fatal_error = false;
1451
1452 /* Initialize pci space address eg: mpi offset */
1453 ret = init_pci_device_addresses(pm8001_ha);
1454 if (ret) {
1455 pm8001_dbg(pm8001_ha, FAIL,
1456 "Failed to init pci addresses");
1457 return ret;
1458 }
1459 init_default_table_values(pm8001_ha);
1460 read_main_config_table(pm8001_ha);
1461 read_general_status_table(pm8001_ha);
1462 read_inbnd_queue_table(pm8001_ha);
1463 read_outbnd_queue_table(pm8001_ha);
1464 read_phy_attr_table(pm8001_ha);
1465
1466 /* update main config table ,inbound table and outbound table */
1467 update_main_config_table(pm8001_ha);
1468 for (i = 0; i < pm8001_ha->max_q_num; i++) {
1469 update_inbnd_queue_table(pm8001_ha, i);
1470 update_outbnd_queue_table(pm8001_ha, i);
1471 }
1472 /* notify firmware update finished and check initialization status */
1473 if (0 == mpi_init_check(pm8001_ha)) {
1474 pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1475 } else
1476 return -EBUSY;
1477
1478 /* send SAS protocol timer configuration page to FW */
1479 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1480
1481 /* Check for encryption */
1482 if (pm8001_ha->chip->encrypt) {
1483 pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1484 ret = pm80xx_get_encrypt_info(pm8001_ha);
1485 if (ret == -1) {
1486 pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1487 if (pm8001_ha->encrypt_info.status == 0x81) {
1488 pm8001_dbg(pm8001_ha, INIT,
1489 "Encryption enabled with error.Saving encryption key to flash\n");
1490 pm80xx_encrypt_update(pm8001_ha);
1491 }
1492 }
1493 }
1494 return 0;
1495 }
1496
mpi_uninit_check(struct pm8001_hba_info * pm8001_ha)1497 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1498 {
1499 u32 max_wait_count;
1500 u32 value;
1501 u32 gst_len_mpistate;
1502 int ret;
1503
1504 ret = init_pci_device_addresses(pm8001_ha);
1505 if (ret) {
1506 pm8001_dbg(pm8001_ha, FAIL,
1507 "Failed to init pci addresses");
1508 return ret;
1509 }
1510
1511 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1512 table is stop */
1513 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1514
1515 /* wait until Inbound DoorBell Clear Register toggled */
1516 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1517 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1518 } else {
1519 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1520 }
1521 do {
1522 msleep(FW_READY_INTERVAL);
1523 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1524 value &= SPCv_MSGU_CFG_TABLE_RESET;
1525 } while ((value != 0) && (--max_wait_count));
1526
1527 if (!max_wait_count) {
1528 pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1529 return -1;
1530 }
1531
1532 /* check the MPI-State for termination in progress */
1533 /* wait until Inbound DoorBell Clear Register toggled */
1534 max_wait_count = 100; /* 2 sec for spcv/ve */
1535 do {
1536 msleep(FW_READY_INTERVAL);
1537 gst_len_mpistate =
1538 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1539 GST_GSTLEN_MPIS_OFFSET);
1540 if (GST_MPI_STATE_UNINIT ==
1541 (gst_len_mpistate & GST_MPI_STATE_MASK))
1542 break;
1543 } while (--max_wait_count);
1544 if (!max_wait_count) {
1545 pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1546 gst_len_mpistate & GST_MPI_STATE_MASK);
1547 return -1;
1548 }
1549
1550 return 0;
1551 }
1552
1553 /**
1554 * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1555 * @pm8001_ha: our hba card information
1556 *
1557 * Fatal errors are recoverable only after a host reboot.
1558 */
1559 int
pm80xx_fatal_errors(struct pm8001_hba_info * pm8001_ha)1560 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1561 {
1562 int ret = 0;
1563 u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1564 MSGU_HOST_SCRATCH_PAD_6);
1565 u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1566 MSGU_HOST_SCRATCH_PAD_7);
1567 u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1568 u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1569 u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1570
1571 if (pm8001_ha->chip_id != chip_8006 &&
1572 pm8001_ha->chip_id != chip_8074 &&
1573 pm8001_ha->chip_id != chip_8076) {
1574 return 0;
1575 }
1576
1577 if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1578 pm8001_dbg(pm8001_ha, FAIL,
1579 "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1580 scratch_pad1, scratch_pad2, scratch_pad3,
1581 scratch_pad_rsvd0, scratch_pad_rsvd1);
1582 ret = 1;
1583 }
1584
1585 return ret;
1586 }
1587
1588 /**
1589 * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1590 * FW register status are reset to the originated status.
1591 * @pm8001_ha: our hba card information
1592 */
1593
1594 static int
pm80xx_chip_soft_rst(struct pm8001_hba_info * pm8001_ha)1595 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1596 {
1597 u32 regval;
1598 u32 bootloader_state;
1599 u32 ibutton0, ibutton1;
1600
1601 /* Process MPI table uninitialization only if FW is ready */
1602 if (!pm8001_ha->controller_fatal_error) {
1603 /* Check if MPI is in ready state to reset */
1604 if (mpi_uninit_check(pm8001_ha) != 0) {
1605 u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1606 u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1607 u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1608 u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1609 pm8001_dbg(pm8001_ha, FAIL,
1610 "MPI state is not ready scratch: %x:%x:%x:%x\n",
1611 r0, r1, r2, r3);
1612 /* if things aren't ready but the bootloader is ok then
1613 * try the reset anyway.
1614 */
1615 if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1616 return -1;
1617 }
1618 }
1619 /* checked for reset register normal state; 0x0 */
1620 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1621 pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1622 regval);
1623
1624 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1625 msleep(500);
1626
1627 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1628 pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1629 regval);
1630
1631 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1632 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1633 pm8001_dbg(pm8001_ha, MSG,
1634 " soft reset successful [regval: 0x%x]\n",
1635 regval);
1636 } else {
1637 pm8001_dbg(pm8001_ha, MSG,
1638 " soft reset failed [regval: 0x%x]\n",
1639 regval);
1640
1641 /* check bootloader is successfully executed or in HDA mode */
1642 bootloader_state =
1643 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1644 SCRATCH_PAD1_BOOTSTATE_MASK;
1645
1646 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1647 pm8001_dbg(pm8001_ha, MSG,
1648 "Bootloader state - HDA mode SEEPROM\n");
1649 } else if (bootloader_state ==
1650 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1651 pm8001_dbg(pm8001_ha, MSG,
1652 "Bootloader state - HDA mode Bootstrap Pin\n");
1653 } else if (bootloader_state ==
1654 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1655 pm8001_dbg(pm8001_ha, MSG,
1656 "Bootloader state - HDA mode soft reset\n");
1657 } else if (bootloader_state ==
1658 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1659 pm8001_dbg(pm8001_ha, MSG,
1660 "Bootloader state-HDA mode critical error\n");
1661 }
1662 return -EBUSY;
1663 }
1664
1665 /* check the firmware status after reset */
1666 if (-1 == check_fw_ready(pm8001_ha)) {
1667 pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1668 /* check iButton feature support for motherboard controller */
1669 if (pm8001_ha->pdev->subsystem_vendor !=
1670 PCI_VENDOR_ID_ADAPTEC2 &&
1671 pm8001_ha->pdev->subsystem_vendor !=
1672 PCI_VENDOR_ID_ATTO &&
1673 pm8001_ha->pdev->subsystem_vendor != 0) {
1674 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1675 MSGU_HOST_SCRATCH_PAD_6);
1676 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1677 MSGU_HOST_SCRATCH_PAD_7);
1678 if (!ibutton0 && !ibutton1) {
1679 pm8001_dbg(pm8001_ha, FAIL,
1680 "iButton Feature is not Available!!!\n");
1681 return -EBUSY;
1682 }
1683 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1684 pm8001_dbg(pm8001_ha, FAIL,
1685 "CRC Check for iButton Feature Failed!!!\n");
1686 return -EBUSY;
1687 }
1688 }
1689 }
1690 pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1691 return 0;
1692 }
1693
pm80xx_hw_chip_rst(struct pm8001_hba_info * pm8001_ha)1694 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1695 {
1696 u32 i;
1697
1698 pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1699
1700 /* do SPCv chip reset. */
1701 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1702 pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1703
1704 /* Check this ..whether delay is required or no */
1705 /* delay 10 usec */
1706 udelay(10);
1707
1708 /* wait for 20 msec until the firmware gets reloaded */
1709 i = 20;
1710 do {
1711 mdelay(1);
1712 } while ((--i) != 0);
1713
1714 pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1715 }
1716
1717 /**
1718 * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1719 * @pm8001_ha: our hba card information
1720 */
1721 static void
pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info * pm8001_ha)1722 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1723 {
1724 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1725 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1726 }
1727
1728 /**
1729 * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1730 * @pm8001_ha: our hba card information
1731 */
1732 static void
pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info * pm8001_ha)1733 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1734 {
1735 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1736 }
1737
1738 /**
1739 * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1740 * @pm8001_ha: our hba card information
1741 * @vec: interrupt number to enable
1742 */
1743 static void
pm80xx_chip_interrupt_enable(struct pm8001_hba_info * pm8001_ha,u8 vec)1744 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1745 {
1746 #ifdef PM8001_USE_MSIX
1747 if (vec < 32)
1748 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
1749 else
1750 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
1751 1U << (vec - 32));
1752 return;
1753 #endif
1754 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1755
1756 }
1757
1758 /**
1759 * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1760 * @pm8001_ha: our hba card information
1761 * @vec: interrupt number to disable
1762 */
1763 static void
pm80xx_chip_interrupt_disable(struct pm8001_hba_info * pm8001_ha,u8 vec)1764 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1765 {
1766 #ifdef PM8001_USE_MSIX
1767 if (vec == 0xFF) {
1768 /* disable all vectors 0-31, 32-63 */
1769 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
1770 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
1771 } else if (vec < 32)
1772 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
1773 else
1774 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
1775 1U << (vec - 32));
1776 return;
1777 #endif
1778 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1779 }
1780
pm80xx_send_abort_all(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1781 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1782 struct pm8001_device *pm8001_ha_dev)
1783 {
1784 int res;
1785 u32 ccb_tag;
1786 struct pm8001_ccb_info *ccb;
1787 struct sas_task *task = NULL;
1788 struct task_abort_req task_abort;
1789 struct inbound_queue_table *circularQ;
1790 u32 opc = OPC_INB_SATA_ABORT;
1791 int ret;
1792
1793 if (!pm8001_ha_dev) {
1794 pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1795 return;
1796 }
1797
1798 task = sas_alloc_slow_task(GFP_ATOMIC);
1799
1800 if (!task) {
1801 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1802 return;
1803 }
1804
1805 task->task_done = pm8001_task_done;
1806
1807 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1808 if (res) {
1809 sas_free_task(task);
1810 return;
1811 }
1812
1813 ccb = &pm8001_ha->ccb_info[ccb_tag];
1814 ccb->device = pm8001_ha_dev;
1815 ccb->ccb_tag = ccb_tag;
1816 ccb->task = task;
1817 ccb->n_elem = 0;
1818
1819 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1820
1821 memset(&task_abort, 0, sizeof(task_abort));
1822 task_abort.abort_all = cpu_to_le32(1);
1823 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1824 task_abort.tag = cpu_to_le32(ccb_tag);
1825
1826 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1827 sizeof(task_abort), 0);
1828 pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1829 if (ret) {
1830 sas_free_task(task);
1831 pm8001_tag_free(pm8001_ha, ccb_tag);
1832 }
1833 }
1834
pm80xx_send_read_log(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_ha_dev)1835 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1836 struct pm8001_device *pm8001_ha_dev)
1837 {
1838 struct sata_start_req sata_cmd;
1839 int res;
1840 u32 ccb_tag;
1841 struct pm8001_ccb_info *ccb;
1842 struct sas_task *task = NULL;
1843 struct host_to_dev_fis fis;
1844 struct domain_device *dev;
1845 struct inbound_queue_table *circularQ;
1846 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1847
1848 task = sas_alloc_slow_task(GFP_ATOMIC);
1849
1850 if (!task) {
1851 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1852 return;
1853 }
1854 task->task_done = pm8001_task_done;
1855
1856 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1857 if (res) {
1858 sas_free_task(task);
1859 pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1860 return;
1861 }
1862
1863 /* allocate domain device by ourselves as libsas
1864 * is not going to provide any
1865 */
1866 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1867 if (!dev) {
1868 sas_free_task(task);
1869 pm8001_tag_free(pm8001_ha, ccb_tag);
1870 pm8001_dbg(pm8001_ha, FAIL,
1871 "Domain device cannot be allocated\n");
1872 return;
1873 }
1874
1875 task->dev = dev;
1876 task->dev->lldd_dev = pm8001_ha_dev;
1877
1878 ccb = &pm8001_ha->ccb_info[ccb_tag];
1879 ccb->device = pm8001_ha_dev;
1880 ccb->ccb_tag = ccb_tag;
1881 ccb->task = task;
1882 ccb->n_elem = 0;
1883 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1884 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1885
1886 memset(&sata_cmd, 0, sizeof(sata_cmd));
1887 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1888
1889 /* construct read log FIS */
1890 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1891 fis.fis_type = 0x27;
1892 fis.flags = 0x80;
1893 fis.command = ATA_CMD_READ_LOG_EXT;
1894 fis.lbal = 0x10;
1895 fis.sector_count = 0x1;
1896
1897 sata_cmd.tag = cpu_to_le32(ccb_tag);
1898 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1899 sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1900 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1901
1902 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1903 sizeof(sata_cmd), 0);
1904 pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1905 if (res) {
1906 sas_free_task(task);
1907 pm8001_tag_free(pm8001_ha, ccb_tag);
1908 kfree(dev);
1909 }
1910 }
1911
1912 /**
1913 * mpi_ssp_completion - process the event that FW response to the SSP request.
1914 * @pm8001_ha: our hba card information
1915 * @piomb: the message contents of this outbound message.
1916 *
1917 * When FW has completed a ssp request for example a IO request, after it has
1918 * filled the SG data with the data, it will trigger this event representing
1919 * that he has finished the job; please check the corresponding buffer.
1920 * So we will tell the caller who maybe waiting the result to tell upper layer
1921 * that the task has been finished.
1922 */
1923 static void
mpi_ssp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)1924 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1925 {
1926 struct sas_task *t;
1927 struct pm8001_ccb_info *ccb;
1928 unsigned long flags;
1929 u32 status;
1930 u32 param;
1931 u32 tag;
1932 struct ssp_completion_resp *psspPayload;
1933 struct task_status_struct *ts;
1934 struct ssp_response_iu *iu;
1935 struct pm8001_device *pm8001_dev;
1936 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1937 status = le32_to_cpu(psspPayload->status);
1938 tag = le32_to_cpu(psspPayload->tag);
1939 ccb = &pm8001_ha->ccb_info[tag];
1940 if ((status == IO_ABORTED) && ccb->open_retry) {
1941 /* Being completed by another */
1942 ccb->open_retry = 0;
1943 return;
1944 }
1945 pm8001_dev = ccb->device;
1946 param = le32_to_cpu(psspPayload->param);
1947 t = ccb->task;
1948
1949 if (status && status != IO_UNDERFLOW)
1950 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1951 if (unlikely(!t || !t->lldd_task || !t->dev))
1952 return;
1953 ts = &t->task_status;
1954
1955 pm8001_dbg(pm8001_ha, DEV,
1956 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1957
1958 /* Print sas address of IO failed device */
1959 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1960 (status != IO_UNDERFLOW))
1961 pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1962 SAS_ADDR(t->dev->sas_addr));
1963
1964 switch (status) {
1965 case IO_SUCCESS:
1966 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1967 param);
1968 if (param == 0) {
1969 ts->resp = SAS_TASK_COMPLETE;
1970 ts->stat = SAS_SAM_STAT_GOOD;
1971 } else {
1972 ts->resp = SAS_TASK_COMPLETE;
1973 ts->stat = SAS_PROTO_RESPONSE;
1974 ts->residual = param;
1975 iu = &psspPayload->ssp_resp_iu;
1976 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1977 }
1978 if (pm8001_dev)
1979 atomic_dec(&pm8001_dev->running_req);
1980 break;
1981 case IO_ABORTED:
1982 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1983 ts->resp = SAS_TASK_COMPLETE;
1984 ts->stat = SAS_ABORTED_TASK;
1985 if (pm8001_dev)
1986 atomic_dec(&pm8001_dev->running_req);
1987 break;
1988 case IO_UNDERFLOW:
1989 /* SSP Completion with error */
1990 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1991 param);
1992 ts->resp = SAS_TASK_COMPLETE;
1993 ts->stat = SAS_DATA_UNDERRUN;
1994 ts->residual = param;
1995 if (pm8001_dev)
1996 atomic_dec(&pm8001_dev->running_req);
1997 break;
1998 case IO_NO_DEVICE:
1999 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2000 ts->resp = SAS_TASK_UNDELIVERED;
2001 ts->stat = SAS_PHY_DOWN;
2002 if (pm8001_dev)
2003 atomic_dec(&pm8001_dev->running_req);
2004 break;
2005 case IO_XFER_ERROR_BREAK:
2006 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2007 ts->resp = SAS_TASK_COMPLETE;
2008 ts->stat = SAS_OPEN_REJECT;
2009 /* Force the midlayer to retry */
2010 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2011 if (pm8001_dev)
2012 atomic_dec(&pm8001_dev->running_req);
2013 break;
2014 case IO_XFER_ERROR_PHY_NOT_READY:
2015 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2016 ts->resp = SAS_TASK_COMPLETE;
2017 ts->stat = SAS_OPEN_REJECT;
2018 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2019 if (pm8001_dev)
2020 atomic_dec(&pm8001_dev->running_req);
2021 break;
2022 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
2023 pm8001_dbg(pm8001_ha, IO,
2024 "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
2025 ts->resp = SAS_TASK_COMPLETE;
2026 ts->stat = SAS_OPEN_REJECT;
2027 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2028 if (pm8001_dev)
2029 atomic_dec(&pm8001_dev->running_req);
2030 break;
2031 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2032 pm8001_dbg(pm8001_ha, IO,
2033 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2034 ts->resp = SAS_TASK_COMPLETE;
2035 ts->stat = SAS_OPEN_REJECT;
2036 ts->open_rej_reason = SAS_OREJ_EPROTO;
2037 if (pm8001_dev)
2038 atomic_dec(&pm8001_dev->running_req);
2039 break;
2040 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2041 pm8001_dbg(pm8001_ha, IO,
2042 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2043 ts->resp = SAS_TASK_COMPLETE;
2044 ts->stat = SAS_OPEN_REJECT;
2045 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2046 if (pm8001_dev)
2047 atomic_dec(&pm8001_dev->running_req);
2048 break;
2049 case IO_OPEN_CNX_ERROR_BREAK:
2050 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2051 ts->resp = SAS_TASK_COMPLETE;
2052 ts->stat = SAS_OPEN_REJECT;
2053 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2054 if (pm8001_dev)
2055 atomic_dec(&pm8001_dev->running_req);
2056 break;
2057 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2058 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2059 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2060 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2061 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2062 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2063 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2064 ts->resp = SAS_TASK_COMPLETE;
2065 ts->stat = SAS_OPEN_REJECT;
2066 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2067 if (!t->uldd_task)
2068 pm8001_handle_event(pm8001_ha,
2069 pm8001_dev,
2070 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2071 break;
2072 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2073 pm8001_dbg(pm8001_ha, IO,
2074 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2075 ts->resp = SAS_TASK_COMPLETE;
2076 ts->stat = SAS_OPEN_REJECT;
2077 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2078 if (pm8001_dev)
2079 atomic_dec(&pm8001_dev->running_req);
2080 break;
2081 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2082 pm8001_dbg(pm8001_ha, IO,
2083 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2084 ts->resp = SAS_TASK_COMPLETE;
2085 ts->stat = SAS_OPEN_REJECT;
2086 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2087 if (pm8001_dev)
2088 atomic_dec(&pm8001_dev->running_req);
2089 break;
2090 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2091 pm8001_dbg(pm8001_ha, IO,
2092 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2093 ts->resp = SAS_TASK_UNDELIVERED;
2094 ts->stat = SAS_OPEN_REJECT;
2095 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2096 if (pm8001_dev)
2097 atomic_dec(&pm8001_dev->running_req);
2098 break;
2099 case IO_XFER_ERROR_NAK_RECEIVED:
2100 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2101 ts->resp = SAS_TASK_COMPLETE;
2102 ts->stat = SAS_OPEN_REJECT;
2103 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2104 if (pm8001_dev)
2105 atomic_dec(&pm8001_dev->running_req);
2106 break;
2107 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2108 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2109 ts->resp = SAS_TASK_COMPLETE;
2110 ts->stat = SAS_NAK_R_ERR;
2111 if (pm8001_dev)
2112 atomic_dec(&pm8001_dev->running_req);
2113 break;
2114 case IO_XFER_ERROR_DMA:
2115 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2116 ts->resp = SAS_TASK_COMPLETE;
2117 ts->stat = SAS_OPEN_REJECT;
2118 if (pm8001_dev)
2119 atomic_dec(&pm8001_dev->running_req);
2120 break;
2121 case IO_XFER_OPEN_RETRY_TIMEOUT:
2122 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2123 ts->resp = SAS_TASK_COMPLETE;
2124 ts->stat = SAS_OPEN_REJECT;
2125 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2126 if (pm8001_dev)
2127 atomic_dec(&pm8001_dev->running_req);
2128 break;
2129 case IO_XFER_ERROR_OFFSET_MISMATCH:
2130 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2131 ts->resp = SAS_TASK_COMPLETE;
2132 ts->stat = SAS_OPEN_REJECT;
2133 if (pm8001_dev)
2134 atomic_dec(&pm8001_dev->running_req);
2135 break;
2136 case IO_PORT_IN_RESET:
2137 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2138 ts->resp = SAS_TASK_COMPLETE;
2139 ts->stat = SAS_OPEN_REJECT;
2140 if (pm8001_dev)
2141 atomic_dec(&pm8001_dev->running_req);
2142 break;
2143 case IO_DS_NON_OPERATIONAL:
2144 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2145 ts->resp = SAS_TASK_COMPLETE;
2146 ts->stat = SAS_OPEN_REJECT;
2147 if (!t->uldd_task)
2148 pm8001_handle_event(pm8001_ha,
2149 pm8001_dev,
2150 IO_DS_NON_OPERATIONAL);
2151 break;
2152 case IO_DS_IN_RECOVERY:
2153 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2154 ts->resp = SAS_TASK_COMPLETE;
2155 ts->stat = SAS_OPEN_REJECT;
2156 if (pm8001_dev)
2157 atomic_dec(&pm8001_dev->running_req);
2158 break;
2159 case IO_TM_TAG_NOT_FOUND:
2160 pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2161 ts->resp = SAS_TASK_COMPLETE;
2162 ts->stat = SAS_OPEN_REJECT;
2163 if (pm8001_dev)
2164 atomic_dec(&pm8001_dev->running_req);
2165 break;
2166 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2167 pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2168 ts->resp = SAS_TASK_COMPLETE;
2169 ts->stat = SAS_OPEN_REJECT;
2170 if (pm8001_dev)
2171 atomic_dec(&pm8001_dev->running_req);
2172 break;
2173 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2174 pm8001_dbg(pm8001_ha, IO,
2175 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2176 ts->resp = SAS_TASK_COMPLETE;
2177 ts->stat = SAS_OPEN_REJECT;
2178 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2179 if (pm8001_dev)
2180 atomic_dec(&pm8001_dev->running_req);
2181 break;
2182 default:
2183 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2184 /* not allowed case. Therefore, return failed status */
2185 ts->resp = SAS_TASK_COMPLETE;
2186 ts->stat = SAS_OPEN_REJECT;
2187 if (pm8001_dev)
2188 atomic_dec(&pm8001_dev->running_req);
2189 break;
2190 }
2191 pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2192 psspPayload->ssp_resp_iu.status);
2193 spin_lock_irqsave(&t->task_state_lock, flags);
2194 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2195 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2196 t->task_state_flags |= SAS_TASK_STATE_DONE;
2197 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2198 spin_unlock_irqrestore(&t->task_state_lock, flags);
2199 pm8001_dbg(pm8001_ha, FAIL,
2200 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2201 t, status, ts->resp, ts->stat);
2202 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2203 if (t->slow_task)
2204 complete(&t->slow_task->completion);
2205 } else {
2206 spin_unlock_irqrestore(&t->task_state_lock, flags);
2207 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2208 mb();/* in order to force CPU ordering */
2209 t->task_done(t);
2210 }
2211 }
2212
2213 /*See the comments for mpi_ssp_completion */
mpi_ssp_event(struct pm8001_hba_info * pm8001_ha,void * piomb)2214 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2215 {
2216 struct sas_task *t;
2217 unsigned long flags;
2218 struct task_status_struct *ts;
2219 struct pm8001_ccb_info *ccb;
2220 struct pm8001_device *pm8001_dev;
2221 struct ssp_event_resp *psspPayload =
2222 (struct ssp_event_resp *)(piomb + 4);
2223 u32 event = le32_to_cpu(psspPayload->event);
2224 u32 tag = le32_to_cpu(psspPayload->tag);
2225 u32 port_id = le32_to_cpu(psspPayload->port_id);
2226
2227 ccb = &pm8001_ha->ccb_info[tag];
2228 t = ccb->task;
2229 pm8001_dev = ccb->device;
2230 if (event)
2231 pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2232 if (unlikely(!t || !t->lldd_task || !t->dev))
2233 return;
2234 ts = &t->task_status;
2235 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2236 port_id, tag, event);
2237 switch (event) {
2238 case IO_OVERFLOW:
2239 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2240 ts->resp = SAS_TASK_COMPLETE;
2241 ts->stat = SAS_DATA_OVERRUN;
2242 ts->residual = 0;
2243 if (pm8001_dev)
2244 atomic_dec(&pm8001_dev->running_req);
2245 break;
2246 case IO_XFER_ERROR_BREAK:
2247 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2248 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2249 return;
2250 case IO_XFER_ERROR_PHY_NOT_READY:
2251 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2252 ts->resp = SAS_TASK_COMPLETE;
2253 ts->stat = SAS_OPEN_REJECT;
2254 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2255 break;
2256 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2257 pm8001_dbg(pm8001_ha, IO,
2258 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2259 ts->resp = SAS_TASK_COMPLETE;
2260 ts->stat = SAS_OPEN_REJECT;
2261 ts->open_rej_reason = SAS_OREJ_EPROTO;
2262 break;
2263 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2264 pm8001_dbg(pm8001_ha, IO,
2265 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2266 ts->resp = SAS_TASK_COMPLETE;
2267 ts->stat = SAS_OPEN_REJECT;
2268 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2269 break;
2270 case IO_OPEN_CNX_ERROR_BREAK:
2271 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2272 ts->resp = SAS_TASK_COMPLETE;
2273 ts->stat = SAS_OPEN_REJECT;
2274 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2275 break;
2276 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2277 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2278 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2279 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2280 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2281 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2282 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2283 ts->resp = SAS_TASK_COMPLETE;
2284 ts->stat = SAS_OPEN_REJECT;
2285 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2286 if (!t->uldd_task)
2287 pm8001_handle_event(pm8001_ha,
2288 pm8001_dev,
2289 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2290 break;
2291 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2292 pm8001_dbg(pm8001_ha, IO,
2293 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2294 ts->resp = SAS_TASK_COMPLETE;
2295 ts->stat = SAS_OPEN_REJECT;
2296 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2297 break;
2298 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2299 pm8001_dbg(pm8001_ha, IO,
2300 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2301 ts->resp = SAS_TASK_COMPLETE;
2302 ts->stat = SAS_OPEN_REJECT;
2303 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2304 break;
2305 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2306 pm8001_dbg(pm8001_ha, IO,
2307 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2308 ts->resp = SAS_TASK_COMPLETE;
2309 ts->stat = SAS_OPEN_REJECT;
2310 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2311 break;
2312 case IO_XFER_ERROR_NAK_RECEIVED:
2313 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2314 ts->resp = SAS_TASK_COMPLETE;
2315 ts->stat = SAS_OPEN_REJECT;
2316 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2317 break;
2318 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2319 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2320 ts->resp = SAS_TASK_COMPLETE;
2321 ts->stat = SAS_NAK_R_ERR;
2322 break;
2323 case IO_XFER_OPEN_RETRY_TIMEOUT:
2324 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2325 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2326 return;
2327 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2328 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2329 ts->resp = SAS_TASK_COMPLETE;
2330 ts->stat = SAS_DATA_OVERRUN;
2331 break;
2332 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2333 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2334 ts->resp = SAS_TASK_COMPLETE;
2335 ts->stat = SAS_DATA_OVERRUN;
2336 break;
2337 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2338 pm8001_dbg(pm8001_ha, IO,
2339 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2340 ts->resp = SAS_TASK_COMPLETE;
2341 ts->stat = SAS_DATA_OVERRUN;
2342 break;
2343 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2344 pm8001_dbg(pm8001_ha, IO,
2345 "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2346 ts->resp = SAS_TASK_COMPLETE;
2347 ts->stat = SAS_DATA_OVERRUN;
2348 break;
2349 case IO_XFER_ERROR_OFFSET_MISMATCH:
2350 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2351 ts->resp = SAS_TASK_COMPLETE;
2352 ts->stat = SAS_DATA_OVERRUN;
2353 break;
2354 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2355 pm8001_dbg(pm8001_ha, IO,
2356 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2357 ts->resp = SAS_TASK_COMPLETE;
2358 ts->stat = SAS_DATA_OVERRUN;
2359 break;
2360 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2361 pm8001_dbg(pm8001_ha, IOERR,
2362 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2363 /* TBC: used default set values */
2364 ts->resp = SAS_TASK_COMPLETE;
2365 ts->stat = SAS_DATA_OVERRUN;
2366 break;
2367 case IO_XFER_CMD_FRAME_ISSUED:
2368 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2369 return;
2370 default:
2371 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2372 /* not allowed case. Therefore, return failed status */
2373 ts->resp = SAS_TASK_COMPLETE;
2374 ts->stat = SAS_DATA_OVERRUN;
2375 break;
2376 }
2377 spin_lock_irqsave(&t->task_state_lock, flags);
2378 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2379 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2380 t->task_state_flags |= SAS_TASK_STATE_DONE;
2381 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2382 spin_unlock_irqrestore(&t->task_state_lock, flags);
2383 pm8001_dbg(pm8001_ha, FAIL,
2384 "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2385 t, event, ts->resp, ts->stat);
2386 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2387 } else {
2388 spin_unlock_irqrestore(&t->task_state_lock, flags);
2389 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2390 mb();/* in order to force CPU ordering */
2391 t->task_done(t);
2392 }
2393 }
2394
2395 /*See the comments for mpi_ssp_completion */
2396 static void
mpi_sata_completion(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)2397 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2398 struct outbound_queue_table *circularQ, void *piomb)
2399 {
2400 struct sas_task *t;
2401 struct pm8001_ccb_info *ccb;
2402 u32 param;
2403 u32 status;
2404 u32 tag;
2405 int i, j;
2406 u8 sata_addr_low[4];
2407 u32 temp_sata_addr_low, temp_sata_addr_hi;
2408 u8 sata_addr_hi[4];
2409 struct sata_completion_resp *psataPayload;
2410 struct task_status_struct *ts;
2411 struct ata_task_resp *resp ;
2412 u32 *sata_resp;
2413 struct pm8001_device *pm8001_dev;
2414 unsigned long flags;
2415
2416 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2417 status = le32_to_cpu(psataPayload->status);
2418 tag = le32_to_cpu(psataPayload->tag);
2419
2420 if (!tag) {
2421 pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2422 return;
2423 }
2424 ccb = &pm8001_ha->ccb_info[tag];
2425 param = le32_to_cpu(psataPayload->param);
2426 if (ccb) {
2427 t = ccb->task;
2428 pm8001_dev = ccb->device;
2429 } else {
2430 pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2431 return;
2432 }
2433
2434 if (t) {
2435 if (t->dev && (t->dev->lldd_dev))
2436 pm8001_dev = t->dev->lldd_dev;
2437 } else {
2438 pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2439 return;
2440 }
2441
2442 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2443 && unlikely(!t || !t->lldd_task || !t->dev)) {
2444 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2445 return;
2446 }
2447
2448 ts = &t->task_status;
2449 if (!ts) {
2450 pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2451 return;
2452 }
2453
2454 if (status != IO_SUCCESS) {
2455 pm8001_dbg(pm8001_ha, FAIL,
2456 "IO failed device_id %u status 0x%x tag %d\n",
2457 pm8001_dev->device_id, status, tag);
2458 }
2459
2460 /* Print sas address of IO failed device */
2461 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2462 (status != IO_UNDERFLOW)) {
2463 if (!((t->dev->parent) &&
2464 (dev_is_expander(t->dev->parent->dev_type)))) {
2465 for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2466 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2467 for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2468 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2469 memcpy(&temp_sata_addr_low, sata_addr_low,
2470 sizeof(sata_addr_low));
2471 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2472 sizeof(sata_addr_hi));
2473 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2474 |((temp_sata_addr_hi << 8) &
2475 0xff0000) |
2476 ((temp_sata_addr_hi >> 8)
2477 & 0xff00) |
2478 ((temp_sata_addr_hi << 24) &
2479 0xff000000));
2480 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2481 & 0xff) |
2482 ((temp_sata_addr_low << 8)
2483 & 0xff0000) |
2484 ((temp_sata_addr_low >> 8)
2485 & 0xff00) |
2486 ((temp_sata_addr_low << 24)
2487 & 0xff000000)) +
2488 pm8001_dev->attached_phy +
2489 0x10);
2490 pm8001_dbg(pm8001_ha, FAIL,
2491 "SAS Address of IO Failure Drive:%08x%08x\n",
2492 temp_sata_addr_hi,
2493 temp_sata_addr_low);
2494
2495 } else {
2496 pm8001_dbg(pm8001_ha, FAIL,
2497 "SAS Address of IO Failure Drive:%016llx\n",
2498 SAS_ADDR(t->dev->sas_addr));
2499 }
2500 }
2501 switch (status) {
2502 case IO_SUCCESS:
2503 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2504 if (param == 0) {
2505 ts->resp = SAS_TASK_COMPLETE;
2506 ts->stat = SAS_SAM_STAT_GOOD;
2507 /* check if response is for SEND READ LOG */
2508 if (pm8001_dev &&
2509 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2510 /* set new bit for abort_all */
2511 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2512 /* clear bit for read log */
2513 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2514 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2515 /* Free the tag */
2516 pm8001_tag_free(pm8001_ha, tag);
2517 sas_free_task(t);
2518 return;
2519 }
2520 } else {
2521 u8 len;
2522 ts->resp = SAS_TASK_COMPLETE;
2523 ts->stat = SAS_PROTO_RESPONSE;
2524 ts->residual = param;
2525 pm8001_dbg(pm8001_ha, IO,
2526 "SAS_PROTO_RESPONSE len = %d\n",
2527 param);
2528 sata_resp = &psataPayload->sata_resp[0];
2529 resp = (struct ata_task_resp *)ts->buf;
2530 if (t->ata_task.dma_xfer == 0 &&
2531 t->data_dir == DMA_FROM_DEVICE) {
2532 len = sizeof(struct pio_setup_fis);
2533 pm8001_dbg(pm8001_ha, IO,
2534 "PIO read len = %d\n", len);
2535 } else if (t->ata_task.use_ncq &&
2536 t->data_dir != DMA_NONE) {
2537 len = sizeof(struct set_dev_bits_fis);
2538 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2539 len);
2540 } else {
2541 len = sizeof(struct dev_to_host_fis);
2542 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2543 len);
2544 }
2545 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2546 resp->frame_len = len;
2547 memcpy(&resp->ending_fis[0], sata_resp, len);
2548 ts->buf_valid_size = sizeof(*resp);
2549 } else
2550 pm8001_dbg(pm8001_ha, IO,
2551 "response too large\n");
2552 }
2553 if (pm8001_dev)
2554 atomic_dec(&pm8001_dev->running_req);
2555 break;
2556 case IO_ABORTED:
2557 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2558 ts->resp = SAS_TASK_COMPLETE;
2559 ts->stat = SAS_ABORTED_TASK;
2560 if (pm8001_dev)
2561 atomic_dec(&pm8001_dev->running_req);
2562 break;
2563 /* following cases are to do cases */
2564 case IO_UNDERFLOW:
2565 /* SATA Completion with error */
2566 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2567 ts->resp = SAS_TASK_COMPLETE;
2568 ts->stat = SAS_DATA_UNDERRUN;
2569 ts->residual = param;
2570 if (pm8001_dev)
2571 atomic_dec(&pm8001_dev->running_req);
2572 break;
2573 case IO_NO_DEVICE:
2574 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2575 ts->resp = SAS_TASK_UNDELIVERED;
2576 ts->stat = SAS_PHY_DOWN;
2577 if (pm8001_dev)
2578 atomic_dec(&pm8001_dev->running_req);
2579 break;
2580 case IO_XFER_ERROR_BREAK:
2581 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2582 ts->resp = SAS_TASK_COMPLETE;
2583 ts->stat = SAS_INTERRUPTED;
2584 if (pm8001_dev)
2585 atomic_dec(&pm8001_dev->running_req);
2586 break;
2587 case IO_XFER_ERROR_PHY_NOT_READY:
2588 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2589 ts->resp = SAS_TASK_COMPLETE;
2590 ts->stat = SAS_OPEN_REJECT;
2591 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2592 if (pm8001_dev)
2593 atomic_dec(&pm8001_dev->running_req);
2594 break;
2595 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2596 pm8001_dbg(pm8001_ha, IO,
2597 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2598 ts->resp = SAS_TASK_COMPLETE;
2599 ts->stat = SAS_OPEN_REJECT;
2600 ts->open_rej_reason = SAS_OREJ_EPROTO;
2601 if (pm8001_dev)
2602 atomic_dec(&pm8001_dev->running_req);
2603 break;
2604 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2605 pm8001_dbg(pm8001_ha, IO,
2606 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2607 ts->resp = SAS_TASK_COMPLETE;
2608 ts->stat = SAS_OPEN_REJECT;
2609 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2610 if (pm8001_dev)
2611 atomic_dec(&pm8001_dev->running_req);
2612 break;
2613 case IO_OPEN_CNX_ERROR_BREAK:
2614 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2615 ts->resp = SAS_TASK_COMPLETE;
2616 ts->stat = SAS_OPEN_REJECT;
2617 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2618 if (pm8001_dev)
2619 atomic_dec(&pm8001_dev->running_req);
2620 break;
2621 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2622 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2623 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2624 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2625 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2626 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2627 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2628 ts->resp = SAS_TASK_COMPLETE;
2629 ts->stat = SAS_DEV_NO_RESPONSE;
2630 if (!t->uldd_task) {
2631 pm8001_handle_event(pm8001_ha,
2632 pm8001_dev,
2633 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2634 ts->resp = SAS_TASK_UNDELIVERED;
2635 ts->stat = SAS_QUEUE_FULL;
2636 spin_unlock_irqrestore(&circularQ->oq_lock,
2637 circularQ->lock_flags);
2638 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2639 spin_lock_irqsave(&circularQ->oq_lock,
2640 circularQ->lock_flags);
2641 return;
2642 }
2643 break;
2644 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2645 pm8001_dbg(pm8001_ha, IO,
2646 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2647 ts->resp = SAS_TASK_UNDELIVERED;
2648 ts->stat = SAS_OPEN_REJECT;
2649 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2650 if (!t->uldd_task) {
2651 pm8001_handle_event(pm8001_ha,
2652 pm8001_dev,
2653 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2654 ts->resp = SAS_TASK_UNDELIVERED;
2655 ts->stat = SAS_QUEUE_FULL;
2656 spin_unlock_irqrestore(&circularQ->oq_lock,
2657 circularQ->lock_flags);
2658 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2659 spin_lock_irqsave(&circularQ->oq_lock,
2660 circularQ->lock_flags);
2661 return;
2662 }
2663 break;
2664 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2665 pm8001_dbg(pm8001_ha, IO,
2666 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2667 ts->resp = SAS_TASK_COMPLETE;
2668 ts->stat = SAS_OPEN_REJECT;
2669 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2670 if (pm8001_dev)
2671 atomic_dec(&pm8001_dev->running_req);
2672 break;
2673 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2674 pm8001_dbg(pm8001_ha, IO,
2675 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2676 ts->resp = SAS_TASK_COMPLETE;
2677 ts->stat = SAS_DEV_NO_RESPONSE;
2678 if (!t->uldd_task) {
2679 pm8001_handle_event(pm8001_ha,
2680 pm8001_dev,
2681 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2682 ts->resp = SAS_TASK_UNDELIVERED;
2683 ts->stat = SAS_QUEUE_FULL;
2684 spin_unlock_irqrestore(&circularQ->oq_lock,
2685 circularQ->lock_flags);
2686 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2687 spin_lock_irqsave(&circularQ->oq_lock,
2688 circularQ->lock_flags);
2689 return;
2690 }
2691 break;
2692 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2693 pm8001_dbg(pm8001_ha, IO,
2694 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2695 ts->resp = SAS_TASK_COMPLETE;
2696 ts->stat = SAS_OPEN_REJECT;
2697 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2698 if (pm8001_dev)
2699 atomic_dec(&pm8001_dev->running_req);
2700 break;
2701 case IO_XFER_ERROR_NAK_RECEIVED:
2702 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2703 ts->resp = SAS_TASK_COMPLETE;
2704 ts->stat = SAS_NAK_R_ERR;
2705 if (pm8001_dev)
2706 atomic_dec(&pm8001_dev->running_req);
2707 break;
2708 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2709 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2710 ts->resp = SAS_TASK_COMPLETE;
2711 ts->stat = SAS_NAK_R_ERR;
2712 if (pm8001_dev)
2713 atomic_dec(&pm8001_dev->running_req);
2714 break;
2715 case IO_XFER_ERROR_DMA:
2716 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2717 ts->resp = SAS_TASK_COMPLETE;
2718 ts->stat = SAS_ABORTED_TASK;
2719 if (pm8001_dev)
2720 atomic_dec(&pm8001_dev->running_req);
2721 break;
2722 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2723 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2724 ts->resp = SAS_TASK_UNDELIVERED;
2725 ts->stat = SAS_DEV_NO_RESPONSE;
2726 if (pm8001_dev)
2727 atomic_dec(&pm8001_dev->running_req);
2728 break;
2729 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2730 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2731 ts->resp = SAS_TASK_COMPLETE;
2732 ts->stat = SAS_DATA_UNDERRUN;
2733 if (pm8001_dev)
2734 atomic_dec(&pm8001_dev->running_req);
2735 break;
2736 case IO_XFER_OPEN_RETRY_TIMEOUT:
2737 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2738 ts->resp = SAS_TASK_COMPLETE;
2739 ts->stat = SAS_OPEN_TO;
2740 if (pm8001_dev)
2741 atomic_dec(&pm8001_dev->running_req);
2742 break;
2743 case IO_PORT_IN_RESET:
2744 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2745 ts->resp = SAS_TASK_COMPLETE;
2746 ts->stat = SAS_DEV_NO_RESPONSE;
2747 if (pm8001_dev)
2748 atomic_dec(&pm8001_dev->running_req);
2749 break;
2750 case IO_DS_NON_OPERATIONAL:
2751 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2752 ts->resp = SAS_TASK_COMPLETE;
2753 ts->stat = SAS_DEV_NO_RESPONSE;
2754 if (!t->uldd_task) {
2755 pm8001_handle_event(pm8001_ha, pm8001_dev,
2756 IO_DS_NON_OPERATIONAL);
2757 ts->resp = SAS_TASK_UNDELIVERED;
2758 ts->stat = SAS_QUEUE_FULL;
2759 spin_unlock_irqrestore(&circularQ->oq_lock,
2760 circularQ->lock_flags);
2761 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2762 spin_lock_irqsave(&circularQ->oq_lock,
2763 circularQ->lock_flags);
2764 return;
2765 }
2766 break;
2767 case IO_DS_IN_RECOVERY:
2768 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2769 ts->resp = SAS_TASK_COMPLETE;
2770 ts->stat = SAS_DEV_NO_RESPONSE;
2771 if (pm8001_dev)
2772 atomic_dec(&pm8001_dev->running_req);
2773 break;
2774 case IO_DS_IN_ERROR:
2775 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2776 ts->resp = SAS_TASK_COMPLETE;
2777 ts->stat = SAS_DEV_NO_RESPONSE;
2778 if (!t->uldd_task) {
2779 pm8001_handle_event(pm8001_ha, pm8001_dev,
2780 IO_DS_IN_ERROR);
2781 ts->resp = SAS_TASK_UNDELIVERED;
2782 ts->stat = SAS_QUEUE_FULL;
2783 spin_unlock_irqrestore(&circularQ->oq_lock,
2784 circularQ->lock_flags);
2785 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2786 spin_lock_irqsave(&circularQ->oq_lock,
2787 circularQ->lock_flags);
2788 return;
2789 }
2790 break;
2791 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2792 pm8001_dbg(pm8001_ha, IO,
2793 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2794 ts->resp = SAS_TASK_COMPLETE;
2795 ts->stat = SAS_OPEN_REJECT;
2796 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2797 if (pm8001_dev)
2798 atomic_dec(&pm8001_dev->running_req);
2799 break;
2800 default:
2801 pm8001_dbg(pm8001_ha, DEVIO,
2802 "Unknown status device_id %u status 0x%x tag %d\n",
2803 pm8001_dev->device_id, status, tag);
2804 /* not allowed case. Therefore, return failed status */
2805 ts->resp = SAS_TASK_COMPLETE;
2806 ts->stat = SAS_DEV_NO_RESPONSE;
2807 if (pm8001_dev)
2808 atomic_dec(&pm8001_dev->running_req);
2809 break;
2810 }
2811 spin_lock_irqsave(&t->task_state_lock, flags);
2812 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2813 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2814 t->task_state_flags |= SAS_TASK_STATE_DONE;
2815 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2816 spin_unlock_irqrestore(&t->task_state_lock, flags);
2817 pm8001_dbg(pm8001_ha, FAIL,
2818 "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2819 t, status, ts->resp, ts->stat);
2820 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2821 if (t->slow_task)
2822 complete(&t->slow_task->completion);
2823 } else {
2824 spin_unlock_irqrestore(&t->task_state_lock, flags);
2825 spin_unlock_irqrestore(&circularQ->oq_lock,
2826 circularQ->lock_flags);
2827 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2828 spin_lock_irqsave(&circularQ->oq_lock,
2829 circularQ->lock_flags);
2830 }
2831 }
2832
2833 /*See the comments for mpi_ssp_completion */
mpi_sata_event(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)2834 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2835 struct outbound_queue_table *circularQ, void *piomb)
2836 {
2837 struct sas_task *t;
2838 struct task_status_struct *ts;
2839 struct pm8001_ccb_info *ccb;
2840 struct pm8001_device *pm8001_dev;
2841 struct sata_event_resp *psataPayload =
2842 (struct sata_event_resp *)(piomb + 4);
2843 u32 event = le32_to_cpu(psataPayload->event);
2844 u32 tag = le32_to_cpu(psataPayload->tag);
2845 u32 port_id = le32_to_cpu(psataPayload->port_id);
2846 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2847
2848 ccb = &pm8001_ha->ccb_info[tag];
2849
2850 if (ccb) {
2851 t = ccb->task;
2852 pm8001_dev = ccb->device;
2853 } else {
2854 pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2855 return;
2856 }
2857 if (event)
2858 pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2859
2860 /* Check if this is NCQ error */
2861 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2862 /* find device using device id */
2863 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2864 /* send read log extension */
2865 if (pm8001_dev)
2866 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2867 return;
2868 }
2869
2870 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2871 pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2872 return;
2873 }
2874
2875 ts = &t->task_status;
2876 pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2877 port_id, tag, event);
2878 switch (event) {
2879 case IO_OVERFLOW:
2880 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2881 ts->resp = SAS_TASK_COMPLETE;
2882 ts->stat = SAS_DATA_OVERRUN;
2883 ts->residual = 0;
2884 break;
2885 case IO_XFER_ERROR_BREAK:
2886 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2887 ts->resp = SAS_TASK_COMPLETE;
2888 ts->stat = SAS_INTERRUPTED;
2889 break;
2890 case IO_XFER_ERROR_PHY_NOT_READY:
2891 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2892 ts->resp = SAS_TASK_COMPLETE;
2893 ts->stat = SAS_OPEN_REJECT;
2894 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2895 break;
2896 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2897 pm8001_dbg(pm8001_ha, IO,
2898 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2899 ts->resp = SAS_TASK_COMPLETE;
2900 ts->stat = SAS_OPEN_REJECT;
2901 ts->open_rej_reason = SAS_OREJ_EPROTO;
2902 break;
2903 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2904 pm8001_dbg(pm8001_ha, IO,
2905 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2906 ts->resp = SAS_TASK_COMPLETE;
2907 ts->stat = SAS_OPEN_REJECT;
2908 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2909 break;
2910 case IO_OPEN_CNX_ERROR_BREAK:
2911 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2912 ts->resp = SAS_TASK_COMPLETE;
2913 ts->stat = SAS_OPEN_REJECT;
2914 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2915 break;
2916 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2917 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2918 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2919 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2920 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2921 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2922 pm8001_dbg(pm8001_ha, FAIL,
2923 "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2924 ts->resp = SAS_TASK_UNDELIVERED;
2925 ts->stat = SAS_DEV_NO_RESPONSE;
2926 if (!t->uldd_task) {
2927 pm8001_handle_event(pm8001_ha,
2928 pm8001_dev,
2929 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2930 ts->resp = SAS_TASK_COMPLETE;
2931 ts->stat = SAS_QUEUE_FULL;
2932 return;
2933 }
2934 break;
2935 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2936 pm8001_dbg(pm8001_ha, IO,
2937 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2938 ts->resp = SAS_TASK_UNDELIVERED;
2939 ts->stat = SAS_OPEN_REJECT;
2940 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2941 break;
2942 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2943 pm8001_dbg(pm8001_ha, IO,
2944 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2945 ts->resp = SAS_TASK_COMPLETE;
2946 ts->stat = SAS_OPEN_REJECT;
2947 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2948 break;
2949 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2950 pm8001_dbg(pm8001_ha, IO,
2951 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2952 ts->resp = SAS_TASK_COMPLETE;
2953 ts->stat = SAS_OPEN_REJECT;
2954 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2955 break;
2956 case IO_XFER_ERROR_NAK_RECEIVED:
2957 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2958 ts->resp = SAS_TASK_COMPLETE;
2959 ts->stat = SAS_NAK_R_ERR;
2960 break;
2961 case IO_XFER_ERROR_PEER_ABORTED:
2962 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2963 ts->resp = SAS_TASK_COMPLETE;
2964 ts->stat = SAS_NAK_R_ERR;
2965 break;
2966 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2967 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2968 ts->resp = SAS_TASK_COMPLETE;
2969 ts->stat = SAS_DATA_UNDERRUN;
2970 break;
2971 case IO_XFER_OPEN_RETRY_TIMEOUT:
2972 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2973 ts->resp = SAS_TASK_COMPLETE;
2974 ts->stat = SAS_OPEN_TO;
2975 break;
2976 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2977 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2978 ts->resp = SAS_TASK_COMPLETE;
2979 ts->stat = SAS_OPEN_TO;
2980 break;
2981 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2982 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2983 ts->resp = SAS_TASK_COMPLETE;
2984 ts->stat = SAS_OPEN_TO;
2985 break;
2986 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2987 pm8001_dbg(pm8001_ha, IO,
2988 "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2989 ts->resp = SAS_TASK_COMPLETE;
2990 ts->stat = SAS_OPEN_TO;
2991 break;
2992 case IO_XFER_ERROR_OFFSET_MISMATCH:
2993 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2994 ts->resp = SAS_TASK_COMPLETE;
2995 ts->stat = SAS_OPEN_TO;
2996 break;
2997 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2998 pm8001_dbg(pm8001_ha, IO,
2999 "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
3000 ts->resp = SAS_TASK_COMPLETE;
3001 ts->stat = SAS_OPEN_TO;
3002 break;
3003 case IO_XFER_CMD_FRAME_ISSUED:
3004 pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
3005 break;
3006 case IO_XFER_PIO_SETUP_ERROR:
3007 pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
3008 ts->resp = SAS_TASK_COMPLETE;
3009 ts->stat = SAS_OPEN_TO;
3010 break;
3011 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
3012 pm8001_dbg(pm8001_ha, FAIL,
3013 "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
3014 /* TBC: used default set values */
3015 ts->resp = SAS_TASK_COMPLETE;
3016 ts->stat = SAS_OPEN_TO;
3017 break;
3018 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
3019 pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
3020 /* TBC: used default set values */
3021 ts->resp = SAS_TASK_COMPLETE;
3022 ts->stat = SAS_OPEN_TO;
3023 break;
3024 default:
3025 pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
3026 /* not allowed case. Therefore, return failed status */
3027 ts->resp = SAS_TASK_COMPLETE;
3028 ts->stat = SAS_OPEN_TO;
3029 break;
3030 }
3031 }
3032
3033 /*See the comments for mpi_ssp_completion */
3034 static void
mpi_smp_completion(struct pm8001_hba_info * pm8001_ha,void * piomb)3035 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
3036 {
3037 u32 param, i;
3038 struct sas_task *t;
3039 struct pm8001_ccb_info *ccb;
3040 unsigned long flags;
3041 u32 status;
3042 u32 tag;
3043 struct smp_completion_resp *psmpPayload;
3044 struct task_status_struct *ts;
3045 struct pm8001_device *pm8001_dev;
3046 char *pdma_respaddr = NULL;
3047
3048 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
3049 status = le32_to_cpu(psmpPayload->status);
3050 tag = le32_to_cpu(psmpPayload->tag);
3051
3052 ccb = &pm8001_ha->ccb_info[tag];
3053 param = le32_to_cpu(psmpPayload->param);
3054 t = ccb->task;
3055 ts = &t->task_status;
3056 pm8001_dev = ccb->device;
3057 if (status)
3058 pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
3059 if (unlikely(!t || !t->lldd_task || !t->dev))
3060 return;
3061
3062 pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
3063
3064 switch (status) {
3065
3066 case IO_SUCCESS:
3067 pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
3068 ts->resp = SAS_TASK_COMPLETE;
3069 ts->stat = SAS_SAM_STAT_GOOD;
3070 if (pm8001_dev)
3071 atomic_dec(&pm8001_dev->running_req);
3072 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3073 pm8001_dbg(pm8001_ha, IO,
3074 "DIRECT RESPONSE Length:%d\n",
3075 param);
3076 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
3077 ((u64)sg_dma_address
3078 (&t->smp_task.smp_resp))));
3079 for (i = 0; i < param; i++) {
3080 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
3081 pm8001_dbg(pm8001_ha, IO,
3082 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3083 i, *(pdma_respaddr + i),
3084 psmpPayload->_r_a[i]);
3085 }
3086 }
3087 break;
3088 case IO_ABORTED:
3089 pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3090 ts->resp = SAS_TASK_COMPLETE;
3091 ts->stat = SAS_ABORTED_TASK;
3092 if (pm8001_dev)
3093 atomic_dec(&pm8001_dev->running_req);
3094 break;
3095 case IO_OVERFLOW:
3096 pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3097 ts->resp = SAS_TASK_COMPLETE;
3098 ts->stat = SAS_DATA_OVERRUN;
3099 ts->residual = 0;
3100 if (pm8001_dev)
3101 atomic_dec(&pm8001_dev->running_req);
3102 break;
3103 case IO_NO_DEVICE:
3104 pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3105 ts->resp = SAS_TASK_COMPLETE;
3106 ts->stat = SAS_PHY_DOWN;
3107 break;
3108 case IO_ERROR_HW_TIMEOUT:
3109 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3110 ts->resp = SAS_TASK_COMPLETE;
3111 ts->stat = SAS_SAM_STAT_BUSY;
3112 break;
3113 case IO_XFER_ERROR_BREAK:
3114 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3115 ts->resp = SAS_TASK_COMPLETE;
3116 ts->stat = SAS_SAM_STAT_BUSY;
3117 break;
3118 case IO_XFER_ERROR_PHY_NOT_READY:
3119 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3120 ts->resp = SAS_TASK_COMPLETE;
3121 ts->stat = SAS_SAM_STAT_BUSY;
3122 break;
3123 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3124 pm8001_dbg(pm8001_ha, IO,
3125 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3126 ts->resp = SAS_TASK_COMPLETE;
3127 ts->stat = SAS_OPEN_REJECT;
3128 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3129 break;
3130 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3131 pm8001_dbg(pm8001_ha, IO,
3132 "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3133 ts->resp = SAS_TASK_COMPLETE;
3134 ts->stat = SAS_OPEN_REJECT;
3135 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3136 break;
3137 case IO_OPEN_CNX_ERROR_BREAK:
3138 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3139 ts->resp = SAS_TASK_COMPLETE;
3140 ts->stat = SAS_OPEN_REJECT;
3141 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3142 break;
3143 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3144 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3145 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3146 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3147 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3148 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3149 pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3150 ts->resp = SAS_TASK_COMPLETE;
3151 ts->stat = SAS_OPEN_REJECT;
3152 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3153 pm8001_handle_event(pm8001_ha,
3154 pm8001_dev,
3155 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3156 break;
3157 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3158 pm8001_dbg(pm8001_ha, IO,
3159 "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3160 ts->resp = SAS_TASK_COMPLETE;
3161 ts->stat = SAS_OPEN_REJECT;
3162 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3163 break;
3164 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3165 pm8001_dbg(pm8001_ha, IO,
3166 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3167 ts->resp = SAS_TASK_COMPLETE;
3168 ts->stat = SAS_OPEN_REJECT;
3169 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3170 break;
3171 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3172 pm8001_dbg(pm8001_ha, IO,
3173 "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3174 ts->resp = SAS_TASK_COMPLETE;
3175 ts->stat = SAS_OPEN_REJECT;
3176 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3177 break;
3178 case IO_XFER_ERROR_RX_FRAME:
3179 pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3180 ts->resp = SAS_TASK_COMPLETE;
3181 ts->stat = SAS_DEV_NO_RESPONSE;
3182 break;
3183 case IO_XFER_OPEN_RETRY_TIMEOUT:
3184 pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3185 ts->resp = SAS_TASK_COMPLETE;
3186 ts->stat = SAS_OPEN_REJECT;
3187 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3188 break;
3189 case IO_ERROR_INTERNAL_SMP_RESOURCE:
3190 pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3191 ts->resp = SAS_TASK_COMPLETE;
3192 ts->stat = SAS_QUEUE_FULL;
3193 break;
3194 case IO_PORT_IN_RESET:
3195 pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3196 ts->resp = SAS_TASK_COMPLETE;
3197 ts->stat = SAS_OPEN_REJECT;
3198 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3199 break;
3200 case IO_DS_NON_OPERATIONAL:
3201 pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3202 ts->resp = SAS_TASK_COMPLETE;
3203 ts->stat = SAS_DEV_NO_RESPONSE;
3204 break;
3205 case IO_DS_IN_RECOVERY:
3206 pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3207 ts->resp = SAS_TASK_COMPLETE;
3208 ts->stat = SAS_OPEN_REJECT;
3209 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3210 break;
3211 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3212 pm8001_dbg(pm8001_ha, IO,
3213 "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3214 ts->resp = SAS_TASK_COMPLETE;
3215 ts->stat = SAS_OPEN_REJECT;
3216 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3217 break;
3218 default:
3219 pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3220 ts->resp = SAS_TASK_COMPLETE;
3221 ts->stat = SAS_DEV_NO_RESPONSE;
3222 /* not allowed case. Therefore, return failed status */
3223 break;
3224 }
3225 spin_lock_irqsave(&t->task_state_lock, flags);
3226 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3227 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3228 t->task_state_flags |= SAS_TASK_STATE_DONE;
3229 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3230 spin_unlock_irqrestore(&t->task_state_lock, flags);
3231 pm8001_dbg(pm8001_ha, FAIL,
3232 "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3233 t, status, ts->resp, ts->stat);
3234 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3235 } else {
3236 spin_unlock_irqrestore(&t->task_state_lock, flags);
3237 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3238 mb();/* in order to force CPU ordering */
3239 t->task_done(t);
3240 }
3241 }
3242
3243 /**
3244 * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3245 * @pm8001_ha: our hba card information
3246 * @Qnum: the outbound queue message number.
3247 * @SEA: source of event to ack
3248 * @port_id: port id.
3249 * @phyId: phy id.
3250 * @param0: parameter 0.
3251 * @param1: parameter 1.
3252 */
pm80xx_hw_event_ack_req(struct pm8001_hba_info * pm8001_ha,u32 Qnum,u32 SEA,u32 port_id,u32 phyId,u32 param0,u32 param1)3253 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3254 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3255 {
3256 struct hw_event_ack_req payload;
3257 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3258
3259 struct inbound_queue_table *circularQ;
3260
3261 memset((u8 *)&payload, 0, sizeof(payload));
3262 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3263 payload.tag = cpu_to_le32(1);
3264 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3265 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3266 payload.param0 = cpu_to_le32(param0);
3267 payload.param1 = cpu_to_le32(param1);
3268 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3269 sizeof(payload), 0);
3270 }
3271
3272 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3273 u32 phyId, u32 phy_op);
3274
hw_event_port_recover(struct pm8001_hba_info * pm8001_ha,void * piomb)3275 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3276 void *piomb)
3277 {
3278 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3279 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3280 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3281 u32 lr_status_evt_portid =
3282 le32_to_cpu(pPayload->lr_status_evt_portid);
3283 u8 deviceType = pPayload->sas_identify.dev_type;
3284 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3285 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3286 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3287 struct pm8001_port *port = &pm8001_ha->port[port_id];
3288
3289 if (deviceType == SAS_END_DEVICE) {
3290 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3291 PHY_NOTIFY_ENABLE_SPINUP);
3292 }
3293
3294 port->wide_port_phymap |= (1U << phy_id);
3295 pm8001_get_lrate_mode(phy, link_rate);
3296 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3297 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3298 phy->phy_attached = 1;
3299 }
3300
3301 /**
3302 * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3303 * @pm8001_ha: our hba card information
3304 * @piomb: IO message buffer
3305 */
3306 static void
hw_event_sas_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3307 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3308 {
3309 struct hw_event_resp *pPayload =
3310 (struct hw_event_resp *)(piomb + 4);
3311 u32 lr_status_evt_portid =
3312 le32_to_cpu(pPayload->lr_status_evt_portid);
3313 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3314
3315 u8 link_rate =
3316 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3317 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3318 u8 phy_id =
3319 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3320 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3321
3322 struct pm8001_port *port = &pm8001_ha->port[port_id];
3323 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3324 unsigned long flags;
3325 u8 deviceType = pPayload->sas_identify.dev_type;
3326 port->port_state = portstate;
3327 port->wide_port_phymap |= (1U << phy_id);
3328 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3329 pm8001_dbg(pm8001_ha, MSG,
3330 "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3331 port_id, phy_id, link_rate, portstate, deviceType);
3332
3333 switch (deviceType) {
3334 case SAS_PHY_UNUSED:
3335 pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3336 break;
3337 case SAS_END_DEVICE:
3338 pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3339 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3340 PHY_NOTIFY_ENABLE_SPINUP);
3341 port->port_attached = 1;
3342 pm8001_get_lrate_mode(phy, link_rate);
3343 break;
3344 case SAS_EDGE_EXPANDER_DEVICE:
3345 pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3346 port->port_attached = 1;
3347 pm8001_get_lrate_mode(phy, link_rate);
3348 break;
3349 case SAS_FANOUT_EXPANDER_DEVICE:
3350 pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3351 port->port_attached = 1;
3352 pm8001_get_lrate_mode(phy, link_rate);
3353 break;
3354 default:
3355 pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3356 deviceType);
3357 break;
3358 }
3359 phy->phy_type |= PORT_TYPE_SAS;
3360 phy->identify.device_type = deviceType;
3361 phy->phy_attached = 1;
3362 if (phy->identify.device_type == SAS_END_DEVICE)
3363 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3364 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3365 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3366 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3367 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3368 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3369 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3370 sizeof(struct sas_identify_frame)-4);
3371 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3372 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3373 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3374 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3375 mdelay(200); /* delay a moment to wait for disk to spin up */
3376 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3377 }
3378
3379 /**
3380 * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3381 * @pm8001_ha: our hba card information
3382 * @piomb: IO message buffer
3383 */
3384 static void
hw_event_sata_phy_up(struct pm8001_hba_info * pm8001_ha,void * piomb)3385 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3386 {
3387 struct hw_event_resp *pPayload =
3388 (struct hw_event_resp *)(piomb + 4);
3389 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3390 u32 lr_status_evt_portid =
3391 le32_to_cpu(pPayload->lr_status_evt_portid);
3392 u8 link_rate =
3393 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3394 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3395 u8 phy_id =
3396 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3397
3398 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3399
3400 struct pm8001_port *port = &pm8001_ha->port[port_id];
3401 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3402 unsigned long flags;
3403 pm8001_dbg(pm8001_ha, DEVIO,
3404 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3405 port_id, phy_id, link_rate, portstate);
3406
3407 port->port_state = portstate;
3408 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3409 port->port_attached = 1;
3410 pm8001_get_lrate_mode(phy, link_rate);
3411 phy->phy_type |= PORT_TYPE_SATA;
3412 phy->phy_attached = 1;
3413 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3414 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3415 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3416 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3417 sizeof(struct dev_to_host_fis));
3418 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3419 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3420 phy->identify.device_type = SAS_SATA_DEV;
3421 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3422 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3423 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3424 }
3425
3426 /**
3427 * hw_event_phy_down - we should notify the libsas the phy is down.
3428 * @pm8001_ha: our hba card information
3429 * @piomb: IO message buffer
3430 */
3431 static void
hw_event_phy_down(struct pm8001_hba_info * pm8001_ha,void * piomb)3432 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3433 {
3434 struct hw_event_resp *pPayload =
3435 (struct hw_event_resp *)(piomb + 4);
3436
3437 u32 lr_status_evt_portid =
3438 le32_to_cpu(pPayload->lr_status_evt_portid);
3439 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3440 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3441 u8 phy_id =
3442 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3443 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3444
3445 struct pm8001_port *port = &pm8001_ha->port[port_id];
3446 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3447 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3448 port->port_state = portstate;
3449 phy->identify.device_type = 0;
3450 phy->phy_attached = 0;
3451 switch (portstate) {
3452 case PORT_VALID:
3453 break;
3454 case PORT_INVALID:
3455 pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3456 port_id);
3457 pm8001_dbg(pm8001_ha, MSG,
3458 " Last phy Down and port invalid\n");
3459 if (port_sata) {
3460 phy->phy_type = 0;
3461 port->port_attached = 0;
3462 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3463 port_id, phy_id, 0, 0);
3464 }
3465 sas_phy_disconnected(&phy->sas_phy);
3466 break;
3467 case PORT_IN_RESET:
3468 pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3469 port_id);
3470 break;
3471 case PORT_NOT_ESTABLISHED:
3472 pm8001_dbg(pm8001_ha, MSG,
3473 " Phy Down and PORT_NOT_ESTABLISHED\n");
3474 port->port_attached = 0;
3475 break;
3476 case PORT_LOSTCOMM:
3477 pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3478 pm8001_dbg(pm8001_ha, MSG,
3479 " Last phy Down and port invalid\n");
3480 if (port_sata) {
3481 port->port_attached = 0;
3482 phy->phy_type = 0;
3483 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3484 port_id, phy_id, 0, 0);
3485 }
3486 sas_phy_disconnected(&phy->sas_phy);
3487 break;
3488 default:
3489 port->port_attached = 0;
3490 pm8001_dbg(pm8001_ha, DEVIO,
3491 " Phy Down and(default) = 0x%x\n",
3492 portstate);
3493 break;
3494
3495 }
3496 if (port_sata && (portstate != PORT_IN_RESET))
3497 sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3498 GFP_ATOMIC);
3499 }
3500
mpi_phy_start_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3501 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3502 {
3503 struct phy_start_resp *pPayload =
3504 (struct phy_start_resp *)(piomb + 4);
3505 u32 status =
3506 le32_to_cpu(pPayload->status);
3507 u32 phy_id =
3508 le32_to_cpu(pPayload->phyid);
3509 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3510
3511 pm8001_dbg(pm8001_ha, INIT,
3512 "phy start resp status:0x%x, phyid:0x%x\n",
3513 status, phy_id);
3514 if (status == 0)
3515 phy->phy_state = PHY_LINK_DOWN;
3516
3517 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3518 phy->enable_completion != NULL) {
3519 complete(phy->enable_completion);
3520 phy->enable_completion = NULL;
3521 }
3522 return 0;
3523
3524 }
3525
3526 /**
3527 * mpi_thermal_hw_event - a thermal hw event has come.
3528 * @pm8001_ha: our hba card information
3529 * @piomb: IO message buffer
3530 */
mpi_thermal_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3531 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3532 {
3533 struct thermal_hw_event *pPayload =
3534 (struct thermal_hw_event *)(piomb + 4);
3535
3536 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3537 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3538
3539 if (thermal_event & 0x40) {
3540 pm8001_dbg(pm8001_ha, IO,
3541 "Thermal Event: Local high temperature violated!\n");
3542 pm8001_dbg(pm8001_ha, IO,
3543 "Thermal Event: Measured local high temperature %d\n",
3544 ((rht_lht & 0xFF00) >> 8));
3545 }
3546 if (thermal_event & 0x10) {
3547 pm8001_dbg(pm8001_ha, IO,
3548 "Thermal Event: Remote high temperature violated!\n");
3549 pm8001_dbg(pm8001_ha, IO,
3550 "Thermal Event: Measured remote high temperature %d\n",
3551 ((rht_lht & 0xFF000000) >> 24));
3552 }
3553 return 0;
3554 }
3555
3556 /**
3557 * mpi_hw_event - The hw event has come.
3558 * @pm8001_ha: our hba card information
3559 * @piomb: IO message buffer
3560 */
mpi_hw_event(struct pm8001_hba_info * pm8001_ha,void * piomb)3561 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3562 {
3563 unsigned long flags, i;
3564 struct hw_event_resp *pPayload =
3565 (struct hw_event_resp *)(piomb + 4);
3566 u32 lr_status_evt_portid =
3567 le32_to_cpu(pPayload->lr_status_evt_portid);
3568 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3569 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3570 u8 phy_id =
3571 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3572 u16 eventType =
3573 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3574 u8 status =
3575 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3576 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3577 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3578 struct pm8001_port *port = &pm8001_ha->port[port_id];
3579 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3580 pm8001_dbg(pm8001_ha, DEV,
3581 "portid:%d phyid:%d event:0x%x status:0x%x\n",
3582 port_id, phy_id, eventType, status);
3583
3584 switch (eventType) {
3585
3586 case HW_EVENT_SAS_PHY_UP:
3587 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3588 hw_event_sas_phy_up(pm8001_ha, piomb);
3589 break;
3590 case HW_EVENT_SATA_PHY_UP:
3591 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3592 hw_event_sata_phy_up(pm8001_ha, piomb);
3593 break;
3594 case HW_EVENT_SATA_SPINUP_HOLD:
3595 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3596 sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3597 GFP_ATOMIC);
3598 break;
3599 case HW_EVENT_PHY_DOWN:
3600 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3601 hw_event_phy_down(pm8001_ha, piomb);
3602 if (pm8001_ha->reset_in_progress) {
3603 pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3604 return 0;
3605 }
3606 phy->phy_attached = 0;
3607 phy->phy_state = PHY_LINK_DISABLE;
3608 break;
3609 case HW_EVENT_PORT_INVALID:
3610 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3611 sas_phy_disconnected(sas_phy);
3612 phy->phy_attached = 0;
3613 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3614 GFP_ATOMIC);
3615 break;
3616 /* the broadcast change primitive received, tell the LIBSAS this event
3617 to revalidate the sas domain*/
3618 case HW_EVENT_BROADCAST_CHANGE:
3619 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3620 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3621 port_id, phy_id, 1, 0);
3622 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3623 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3624 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3625 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3626 GFP_ATOMIC);
3627 break;
3628 case HW_EVENT_PHY_ERROR:
3629 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3630 sas_phy_disconnected(&phy->sas_phy);
3631 phy->phy_attached = 0;
3632 sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3633 break;
3634 case HW_EVENT_BROADCAST_EXP:
3635 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3636 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3637 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3638 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3639 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3640 GFP_ATOMIC);
3641 break;
3642 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3643 pm8001_dbg(pm8001_ha, MSG,
3644 "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3645 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3646 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3647 break;
3648 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3649 pm8001_dbg(pm8001_ha, MSG,
3650 "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3651 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3652 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3653 port_id, phy_id, 0, 0);
3654 break;
3655 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3656 pm8001_dbg(pm8001_ha, MSG,
3657 "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3658 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3659 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3660 port_id, phy_id, 0, 0);
3661 break;
3662 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3663 pm8001_dbg(pm8001_ha, MSG,
3664 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3665 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3666 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3667 port_id, phy_id, 0, 0);
3668 break;
3669 case HW_EVENT_MALFUNCTION:
3670 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3671 break;
3672 case HW_EVENT_BROADCAST_SES:
3673 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3674 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3675 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3676 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3677 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3678 GFP_ATOMIC);
3679 break;
3680 case HW_EVENT_INBOUND_CRC_ERROR:
3681 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3682 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3683 HW_EVENT_INBOUND_CRC_ERROR,
3684 port_id, phy_id, 0, 0);
3685 break;
3686 case HW_EVENT_HARD_RESET_RECEIVED:
3687 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3688 sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3689 break;
3690 case HW_EVENT_ID_FRAME_TIMEOUT:
3691 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3692 sas_phy_disconnected(sas_phy);
3693 phy->phy_attached = 0;
3694 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3695 GFP_ATOMIC);
3696 break;
3697 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3698 pm8001_dbg(pm8001_ha, MSG,
3699 "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3700 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3701 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3702 port_id, phy_id, 0, 0);
3703 sas_phy_disconnected(sas_phy);
3704 phy->phy_attached = 0;
3705 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3706 GFP_ATOMIC);
3707 break;
3708 case HW_EVENT_PORT_RESET_TIMER_TMO:
3709 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3710 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3711 port_id, phy_id, 0, 0);
3712 sas_phy_disconnected(sas_phy);
3713 phy->phy_attached = 0;
3714 sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3715 GFP_ATOMIC);
3716 if (pm8001_ha->phy[phy_id].reset_completion) {
3717 pm8001_ha->phy[phy_id].port_reset_status =
3718 PORT_RESET_TMO;
3719 complete(pm8001_ha->phy[phy_id].reset_completion);
3720 pm8001_ha->phy[phy_id].reset_completion = NULL;
3721 }
3722 break;
3723 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3724 pm8001_dbg(pm8001_ha, MSG,
3725 "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3726 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3727 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3728 port_id, phy_id, 0, 0);
3729 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3730 if (port->wide_port_phymap & (1 << i)) {
3731 phy = &pm8001_ha->phy[i];
3732 sas_notify_phy_event(&phy->sas_phy,
3733 PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3734 port->wide_port_phymap &= ~(1 << i);
3735 }
3736 }
3737 break;
3738 case HW_EVENT_PORT_RECOVER:
3739 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3740 hw_event_port_recover(pm8001_ha, piomb);
3741 break;
3742 case HW_EVENT_PORT_RESET_COMPLETE:
3743 pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3744 if (pm8001_ha->phy[phy_id].reset_completion) {
3745 pm8001_ha->phy[phy_id].port_reset_status =
3746 PORT_RESET_SUCCESS;
3747 complete(pm8001_ha->phy[phy_id].reset_completion);
3748 pm8001_ha->phy[phy_id].reset_completion = NULL;
3749 }
3750 break;
3751 case EVENT_BROADCAST_ASYNCH_EVENT:
3752 pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3753 break;
3754 default:
3755 pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3756 eventType);
3757 break;
3758 }
3759 return 0;
3760 }
3761
3762 /**
3763 * mpi_phy_stop_resp - SPCv specific
3764 * @pm8001_ha: our hba card information
3765 * @piomb: IO message buffer
3766 */
mpi_phy_stop_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3767 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3768 {
3769 struct phy_stop_resp *pPayload =
3770 (struct phy_stop_resp *)(piomb + 4);
3771 u32 status =
3772 le32_to_cpu(pPayload->status);
3773 u32 phyid =
3774 le32_to_cpu(pPayload->phyid) & 0xFF;
3775 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3776 pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3777 phyid, status);
3778 if (status == PHY_STOP_SUCCESS ||
3779 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3780 phy->phy_state = PHY_LINK_DISABLE;
3781 return 0;
3782 }
3783
3784 /**
3785 * mpi_set_controller_config_resp - SPCv specific
3786 * @pm8001_ha: our hba card information
3787 * @piomb: IO message buffer
3788 */
mpi_set_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3789 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3790 void *piomb)
3791 {
3792 struct set_ctrl_cfg_resp *pPayload =
3793 (struct set_ctrl_cfg_resp *)(piomb + 4);
3794 u32 status = le32_to_cpu(pPayload->status);
3795 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3796 u32 tag = le32_to_cpu(pPayload->tag);
3797
3798 pm8001_dbg(pm8001_ha, MSG,
3799 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3800 status, err_qlfr_pgcd);
3801 pm8001_tag_free(pm8001_ha, tag);
3802
3803 return 0;
3804 }
3805
3806 /**
3807 * mpi_get_controller_config_resp - SPCv specific
3808 * @pm8001_ha: our hba card information
3809 * @piomb: IO message buffer
3810 */
mpi_get_controller_config_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3811 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3812 void *piomb)
3813 {
3814 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3815
3816 return 0;
3817 }
3818
3819 /**
3820 * mpi_get_phy_profile_resp - SPCv specific
3821 * @pm8001_ha: our hba card information
3822 * @piomb: IO message buffer
3823 */
mpi_get_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3824 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3825 void *piomb)
3826 {
3827 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3828
3829 return 0;
3830 }
3831
3832 /**
3833 * mpi_flash_op_ext_resp - SPCv specific
3834 * @pm8001_ha: our hba card information
3835 * @piomb: IO message buffer
3836 */
mpi_flash_op_ext_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3837 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3838 {
3839 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3840
3841 return 0;
3842 }
3843
3844 /**
3845 * mpi_set_phy_profile_resp - SPCv specific
3846 * @pm8001_ha: our hba card information
3847 * @piomb: IO message buffer
3848 */
mpi_set_phy_profile_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3849 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3850 void *piomb)
3851 {
3852 u32 tag;
3853 u8 page_code;
3854 int rc = 0;
3855 struct set_phy_profile_resp *pPayload =
3856 (struct set_phy_profile_resp *)(piomb + 4);
3857 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3858 u32 status = le32_to_cpu(pPayload->status);
3859
3860 tag = le32_to_cpu(pPayload->tag);
3861 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3862 if (status) {
3863 /* status is FAILED */
3864 pm8001_dbg(pm8001_ha, FAIL,
3865 "PhyProfile command failed with status 0x%08X\n",
3866 status);
3867 rc = -1;
3868 } else {
3869 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3870 pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3871 page_code);
3872 rc = -1;
3873 }
3874 }
3875 pm8001_tag_free(pm8001_ha, tag);
3876 return rc;
3877 }
3878
3879 /**
3880 * mpi_kek_management_resp - SPCv specific
3881 * @pm8001_ha: our hba card information
3882 * @piomb: IO message buffer
3883 */
mpi_kek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3884 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3885 void *piomb)
3886 {
3887 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3888
3889 u32 status = le32_to_cpu(pPayload->status);
3890 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3891 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3892
3893 pm8001_dbg(pm8001_ha, MSG,
3894 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3895 status, kidx_new_curr_ksop, err_qlfr);
3896
3897 return 0;
3898 }
3899
3900 /**
3901 * mpi_dek_management_resp - SPCv specific
3902 * @pm8001_ha: our hba card information
3903 * @piomb: IO message buffer
3904 */
mpi_dek_management_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3905 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3906 void *piomb)
3907 {
3908 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3909
3910 return 0;
3911 }
3912
3913 /**
3914 * ssp_coalesced_comp_resp - SPCv specific
3915 * @pm8001_ha: our hba card information
3916 * @piomb: IO message buffer
3917 */
ssp_coalesced_comp_resp(struct pm8001_hba_info * pm8001_ha,void * piomb)3918 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3919 void *piomb)
3920 {
3921 pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3922
3923 return 0;
3924 }
3925
3926 /**
3927 * process_one_iomb - process one outbound Queue memory block
3928 * @pm8001_ha: our hba card information
3929 * @piomb: IO message buffer
3930 */
process_one_iomb(struct pm8001_hba_info * pm8001_ha,struct outbound_queue_table * circularQ,void * piomb)3931 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3932 struct outbound_queue_table *circularQ, void *piomb)
3933 {
3934 __le32 pHeader = *(__le32 *)piomb;
3935 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3936
3937 switch (opc) {
3938 case OPC_OUB_ECHO:
3939 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3940 break;
3941 case OPC_OUB_HW_EVENT:
3942 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3943 mpi_hw_event(pm8001_ha, piomb);
3944 break;
3945 case OPC_OUB_THERM_HW_EVENT:
3946 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3947 mpi_thermal_hw_event(pm8001_ha, piomb);
3948 break;
3949 case OPC_OUB_SSP_COMP:
3950 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3951 mpi_ssp_completion(pm8001_ha, piomb);
3952 break;
3953 case OPC_OUB_SMP_COMP:
3954 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3955 mpi_smp_completion(pm8001_ha, piomb);
3956 break;
3957 case OPC_OUB_LOCAL_PHY_CNTRL:
3958 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3959 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3960 break;
3961 case OPC_OUB_DEV_REGIST:
3962 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3963 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3964 break;
3965 case OPC_OUB_DEREG_DEV:
3966 pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3967 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3968 break;
3969 case OPC_OUB_GET_DEV_HANDLE:
3970 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3971 break;
3972 case OPC_OUB_SATA_COMP:
3973 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3974 mpi_sata_completion(pm8001_ha, circularQ, piomb);
3975 break;
3976 case OPC_OUB_SATA_EVENT:
3977 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3978 mpi_sata_event(pm8001_ha, circularQ, piomb);
3979 break;
3980 case OPC_OUB_SSP_EVENT:
3981 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3982 mpi_ssp_event(pm8001_ha, piomb);
3983 break;
3984 case OPC_OUB_DEV_HANDLE_ARRIV:
3985 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3986 /*This is for target*/
3987 break;
3988 case OPC_OUB_SSP_RECV_EVENT:
3989 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3990 /*This is for target*/
3991 break;
3992 case OPC_OUB_FW_FLASH_UPDATE:
3993 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3994 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3995 break;
3996 case OPC_OUB_GPIO_RESPONSE:
3997 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3998 break;
3999 case OPC_OUB_GPIO_EVENT:
4000 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
4001 break;
4002 case OPC_OUB_GENERAL_EVENT:
4003 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
4004 pm8001_mpi_general_event(pm8001_ha, piomb);
4005 break;
4006 case OPC_OUB_SSP_ABORT_RSP:
4007 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
4008 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4009 break;
4010 case OPC_OUB_SATA_ABORT_RSP:
4011 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
4012 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4013 break;
4014 case OPC_OUB_SAS_DIAG_MODE_START_END:
4015 pm8001_dbg(pm8001_ha, MSG,
4016 "OPC_OUB_SAS_DIAG_MODE_START_END\n");
4017 break;
4018 case OPC_OUB_SAS_DIAG_EXECUTE:
4019 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
4020 break;
4021 case OPC_OUB_GET_TIME_STAMP:
4022 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
4023 break;
4024 case OPC_OUB_SAS_HW_EVENT_ACK:
4025 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
4026 break;
4027 case OPC_OUB_PORT_CONTROL:
4028 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
4029 break;
4030 case OPC_OUB_SMP_ABORT_RSP:
4031 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
4032 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
4033 break;
4034 case OPC_OUB_GET_NVMD_DATA:
4035 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
4036 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
4037 break;
4038 case OPC_OUB_SET_NVMD_DATA:
4039 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
4040 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
4041 break;
4042 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
4043 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
4044 break;
4045 case OPC_OUB_SET_DEVICE_STATE:
4046 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
4047 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4048 break;
4049 case OPC_OUB_GET_DEVICE_STATE:
4050 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4051 break;
4052 case OPC_OUB_SET_DEV_INFO:
4053 pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4054 break;
4055 /* spcv specific commands */
4056 case OPC_OUB_PHY_START_RESP:
4057 pm8001_dbg(pm8001_ha, MSG,
4058 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
4059 mpi_phy_start_resp(pm8001_ha, piomb);
4060 break;
4061 case OPC_OUB_PHY_STOP_RESP:
4062 pm8001_dbg(pm8001_ha, MSG,
4063 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
4064 mpi_phy_stop_resp(pm8001_ha, piomb);
4065 break;
4066 case OPC_OUB_SET_CONTROLLER_CONFIG:
4067 pm8001_dbg(pm8001_ha, MSG,
4068 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
4069 mpi_set_controller_config_resp(pm8001_ha, piomb);
4070 break;
4071 case OPC_OUB_GET_CONTROLLER_CONFIG:
4072 pm8001_dbg(pm8001_ha, MSG,
4073 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
4074 mpi_get_controller_config_resp(pm8001_ha, piomb);
4075 break;
4076 case OPC_OUB_GET_PHY_PROFILE:
4077 pm8001_dbg(pm8001_ha, MSG,
4078 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
4079 mpi_get_phy_profile_resp(pm8001_ha, piomb);
4080 break;
4081 case OPC_OUB_FLASH_OP_EXT:
4082 pm8001_dbg(pm8001_ha, MSG,
4083 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4084 mpi_flash_op_ext_resp(pm8001_ha, piomb);
4085 break;
4086 case OPC_OUB_SET_PHY_PROFILE:
4087 pm8001_dbg(pm8001_ha, MSG,
4088 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4089 mpi_set_phy_profile_resp(pm8001_ha, piomb);
4090 break;
4091 case OPC_OUB_KEK_MANAGEMENT_RESP:
4092 pm8001_dbg(pm8001_ha, MSG,
4093 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4094 mpi_kek_management_resp(pm8001_ha, piomb);
4095 break;
4096 case OPC_OUB_DEK_MANAGEMENT_RESP:
4097 pm8001_dbg(pm8001_ha, MSG,
4098 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4099 mpi_dek_management_resp(pm8001_ha, piomb);
4100 break;
4101 case OPC_OUB_SSP_COALESCED_COMP_RESP:
4102 pm8001_dbg(pm8001_ha, MSG,
4103 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4104 ssp_coalesced_comp_resp(pm8001_ha, piomb);
4105 break;
4106 default:
4107 pm8001_dbg(pm8001_ha, DEVIO,
4108 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4109 break;
4110 }
4111 }
4112
print_scratchpad_registers(struct pm8001_hba_info * pm8001_ha)4113 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4114 {
4115 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4116 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4117 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4118 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4119 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4120 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4121 pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4122 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4123 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4124 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4125 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4126 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4127 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4128 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4129 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4130 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4131 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4132 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4133 pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4134 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4135 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4136 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6));
4137 pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4138 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7));
4139 }
4140
process_oq(struct pm8001_hba_info * pm8001_ha,u8 vec)4141 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4142 {
4143 struct outbound_queue_table *circularQ;
4144 void *pMsg1 = NULL;
4145 u8 bc;
4146 u32 ret = MPI_IO_STATUS_FAIL;
4147 u32 regval;
4148
4149 /*
4150 * Fatal errors are programmed to be signalled in irq vector
4151 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4152 * fatal_err_interrupt
4153 */
4154 if (vec == (pm8001_ha->max_q_num - 1)) {
4155 u32 mipsall_ready;
4156
4157 if (pm8001_ha->chip_id == chip_8008 ||
4158 pm8001_ha->chip_id == chip_8009)
4159 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4160 else
4161 mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4162
4163 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4164 if ((regval & mipsall_ready) != mipsall_ready) {
4165 pm8001_ha->controller_fatal_error = true;
4166 pm8001_dbg(pm8001_ha, FAIL,
4167 "Firmware Fatal error! Regval:0x%x\n",
4168 regval);
4169 pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4170 print_scratchpad_registers(pm8001_ha);
4171 return ret;
4172 }
4173 }
4174 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4175 spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4176 do {
4177 /* spurious interrupt during setup if kexec-ing and
4178 * driver doing a doorbell access w/ the pre-kexec oq
4179 * interrupt setup.
4180 */
4181 if (!circularQ->pi_virt)
4182 break;
4183 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4184 if (MPI_IO_STATUS_SUCCESS == ret) {
4185 /* process the outbound message */
4186 process_one_iomb(pm8001_ha, circularQ,
4187 (void *)(pMsg1 - 4));
4188 /* free the message from the outbound circular buffer */
4189 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4190 circularQ, bc);
4191 }
4192 if (MPI_IO_STATUS_BUSY == ret) {
4193 /* Update the producer index from SPC */
4194 circularQ->producer_index =
4195 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4196 if (le32_to_cpu(circularQ->producer_index) ==
4197 circularQ->consumer_idx)
4198 /* OQ is empty */
4199 break;
4200 }
4201 } while (1);
4202 spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4203 return ret;
4204 }
4205
4206 /* DMA_... to our direction translation. */
4207 static const u8 data_dir_flags[] = {
4208 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4209 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
4210 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
4211 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
4212 };
4213
build_smp_cmd(u32 deviceID,__le32 hTag,struct smp_req * psmp_cmd,int mode,int length)4214 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4215 struct smp_req *psmp_cmd, int mode, int length)
4216 {
4217 psmp_cmd->tag = hTag;
4218 psmp_cmd->device_id = cpu_to_le32(deviceID);
4219 if (mode == SMP_DIRECT) {
4220 length = length - 4; /* subtract crc */
4221 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4222 } else {
4223 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4224 }
4225 }
4226
4227 /**
4228 * pm80xx_chip_smp_req - send an SMP task to FW
4229 * @pm8001_ha: our hba card information.
4230 * @ccb: the ccb information this request used.
4231 */
pm80xx_chip_smp_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4232 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4233 struct pm8001_ccb_info *ccb)
4234 {
4235 int elem, rc;
4236 struct sas_task *task = ccb->task;
4237 struct domain_device *dev = task->dev;
4238 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4239 struct scatterlist *sg_req, *sg_resp;
4240 u32 req_len, resp_len;
4241 struct smp_req smp_cmd;
4242 u32 opc;
4243 struct inbound_queue_table *circularQ;
4244 char *preq_dma_addr = NULL;
4245 __le64 tmp_addr;
4246 u32 i, length;
4247
4248 memset(&smp_cmd, 0, sizeof(smp_cmd));
4249 /*
4250 * DMA-map SMP request, response buffers
4251 */
4252 sg_req = &task->smp_task.smp_req;
4253 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4254 if (!elem)
4255 return -ENOMEM;
4256 req_len = sg_dma_len(sg_req);
4257
4258 sg_resp = &task->smp_task.smp_resp;
4259 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4260 if (!elem) {
4261 rc = -ENOMEM;
4262 goto err_out;
4263 }
4264 resp_len = sg_dma_len(sg_resp);
4265 /* must be in dwords */
4266 if ((req_len & 0x3) || (resp_len & 0x3)) {
4267 rc = -EINVAL;
4268 goto err_out_2;
4269 }
4270
4271 opc = OPC_INB_SMP_REQUEST;
4272 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4273 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4274
4275 length = sg_req->length;
4276 pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4277 if (!(length - 8))
4278 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4279 else
4280 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4281
4282
4283 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4284 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4285
4286 /* INDIRECT MODE command settings. Use DMA */
4287 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4288 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4289 /* for SPCv indirect mode. Place the top 4 bytes of
4290 * SMP Request header here. */
4291 for (i = 0; i < 4; i++)
4292 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4293 /* exclude top 4 bytes for SMP req header */
4294 smp_cmd.long_smp_req.long_req_addr =
4295 cpu_to_le64((u64)sg_dma_address
4296 (&task->smp_task.smp_req) + 4);
4297 /* exclude 4 bytes for SMP req header and CRC */
4298 smp_cmd.long_smp_req.long_req_size =
4299 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4300 smp_cmd.long_smp_req.long_resp_addr =
4301 cpu_to_le64((u64)sg_dma_address
4302 (&task->smp_task.smp_resp));
4303 smp_cmd.long_smp_req.long_resp_size =
4304 cpu_to_le32((u32)sg_dma_len
4305 (&task->smp_task.smp_resp)-4);
4306 } else { /* DIRECT MODE */
4307 smp_cmd.long_smp_req.long_req_addr =
4308 cpu_to_le64((u64)sg_dma_address
4309 (&task->smp_task.smp_req));
4310 smp_cmd.long_smp_req.long_req_size =
4311 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4312 smp_cmd.long_smp_req.long_resp_addr =
4313 cpu_to_le64((u64)sg_dma_address
4314 (&task->smp_task.smp_resp));
4315 smp_cmd.long_smp_req.long_resp_size =
4316 cpu_to_le32
4317 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4318 }
4319 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4320 pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4321 for (i = 0; i < length; i++)
4322 if (i < 16) {
4323 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4324 pm8001_dbg(pm8001_ha, IO,
4325 "Byte[%d]:%x (DMA data:%x)\n",
4326 i, smp_cmd.smp_req16[i],
4327 *(preq_dma_addr));
4328 } else {
4329 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4330 pm8001_dbg(pm8001_ha, IO,
4331 "Byte[%d]:%x (DMA data:%x)\n",
4332 i, smp_cmd.smp_req[i],
4333 *(preq_dma_addr));
4334 }
4335 }
4336
4337 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4338 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4339 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4340 sizeof(smp_cmd), 0);
4341 if (rc)
4342 goto err_out_2;
4343 return 0;
4344
4345 err_out_2:
4346 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4347 DMA_FROM_DEVICE);
4348 err_out:
4349 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4350 DMA_TO_DEVICE);
4351 return rc;
4352 }
4353
check_enc_sas_cmd(struct sas_task * task)4354 static int check_enc_sas_cmd(struct sas_task *task)
4355 {
4356 u8 cmd = task->ssp_task.cmd->cmnd[0];
4357
4358 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4359 return 1;
4360 else
4361 return 0;
4362 }
4363
check_enc_sat_cmd(struct sas_task * task)4364 static int check_enc_sat_cmd(struct sas_task *task)
4365 {
4366 int ret = 0;
4367 switch (task->ata_task.fis.command) {
4368 case ATA_CMD_FPDMA_READ:
4369 case ATA_CMD_READ_EXT:
4370 case ATA_CMD_READ:
4371 case ATA_CMD_FPDMA_WRITE:
4372 case ATA_CMD_WRITE_EXT:
4373 case ATA_CMD_WRITE:
4374 case ATA_CMD_PIO_READ:
4375 case ATA_CMD_PIO_READ_EXT:
4376 case ATA_CMD_PIO_WRITE:
4377 case ATA_CMD_PIO_WRITE_EXT:
4378 ret = 1;
4379 break;
4380 default:
4381 ret = 0;
4382 break;
4383 }
4384 return ret;
4385 }
4386
4387 /**
4388 * pm80xx_chip_ssp_io_req - send an SSP task to FW
4389 * @pm8001_ha: our hba card information.
4390 * @ccb: the ccb information this request used.
4391 */
pm80xx_chip_ssp_io_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4392 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4393 struct pm8001_ccb_info *ccb)
4394 {
4395 struct sas_task *task = ccb->task;
4396 struct domain_device *dev = task->dev;
4397 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4398 struct ssp_ini_io_start_req ssp_cmd;
4399 u32 tag = ccb->ccb_tag;
4400 int ret;
4401 u64 phys_addr, end_addr;
4402 u32 end_addr_high, end_addr_low;
4403 struct inbound_queue_table *circularQ;
4404 u32 q_index, cpu_id;
4405 u32 opc = OPC_INB_SSPINIIOSTART;
4406
4407 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4408 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4409
4410 /* data address domain added for spcv; set to 0 by host,
4411 * used internally by controller
4412 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4413 */
4414 ssp_cmd.dad_dir_m_tlr =
4415 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4416 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4417 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4418 ssp_cmd.tag = cpu_to_le32(tag);
4419 if (task->ssp_task.enable_first_burst)
4420 ssp_cmd.ssp_iu.efb_prio_attr = 0x80;
4421 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4422 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4423 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4424 task->ssp_task.cmd->cmd_len);
4425 cpu_id = smp_processor_id();
4426 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4427 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4428
4429 /* Check if encryption is set */
4430 if (pm8001_ha->chip->encrypt &&
4431 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4432 pm8001_dbg(pm8001_ha, IO,
4433 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4434 task->ssp_task.cmd->cmnd[0]);
4435 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4436 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4437 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4438 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4439
4440 /* fill in PRD (scatter/gather) table, if any */
4441 if (task->num_scatter > 1) {
4442 pm8001_chip_make_sg(task->scatter,
4443 ccb->n_elem, ccb->buf_prd);
4444 phys_addr = ccb->ccb_dma_handle;
4445 ssp_cmd.enc_addr_low =
4446 cpu_to_le32(lower_32_bits(phys_addr));
4447 ssp_cmd.enc_addr_high =
4448 cpu_to_le32(upper_32_bits(phys_addr));
4449 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4450 } else if (task->num_scatter == 1) {
4451 u64 dma_addr = sg_dma_address(task->scatter);
4452
4453 ssp_cmd.enc_addr_low =
4454 cpu_to_le32(lower_32_bits(dma_addr));
4455 ssp_cmd.enc_addr_high =
4456 cpu_to_le32(upper_32_bits(dma_addr));
4457 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4458 ssp_cmd.enc_esgl = 0;
4459
4460 /* Check 4G Boundary */
4461 end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4462 end_addr_low = lower_32_bits(end_addr);
4463 end_addr_high = upper_32_bits(end_addr);
4464
4465 if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4466 pm8001_dbg(pm8001_ha, FAIL,
4467 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4468 dma_addr,
4469 le32_to_cpu(ssp_cmd.enc_len),
4470 end_addr_high, end_addr_low);
4471 pm8001_chip_make_sg(task->scatter, 1,
4472 ccb->buf_prd);
4473 phys_addr = ccb->ccb_dma_handle;
4474 ssp_cmd.enc_addr_low =
4475 cpu_to_le32(lower_32_bits(phys_addr));
4476 ssp_cmd.enc_addr_high =
4477 cpu_to_le32(upper_32_bits(phys_addr));
4478 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4479 }
4480 } else if (task->num_scatter == 0) {
4481 ssp_cmd.enc_addr_low = 0;
4482 ssp_cmd.enc_addr_high = 0;
4483 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4484 ssp_cmd.enc_esgl = 0;
4485 }
4486
4487 /* XTS mode. All other fields are 0 */
4488 ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4489
4490 /* set tweak values. Should be the start lba */
4491 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4492 (task->ssp_task.cmd->cmnd[3] << 16) |
4493 (task->ssp_task.cmd->cmnd[4] << 8) |
4494 (task->ssp_task.cmd->cmnd[5]));
4495 } else {
4496 pm8001_dbg(pm8001_ha, IO,
4497 "Sending Normal SAS command 0x%x inb q %x\n",
4498 task->ssp_task.cmd->cmnd[0], q_index);
4499 /* fill in PRD (scatter/gather) table, if any */
4500 if (task->num_scatter > 1) {
4501 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4502 ccb->buf_prd);
4503 phys_addr = ccb->ccb_dma_handle;
4504 ssp_cmd.addr_low =
4505 cpu_to_le32(lower_32_bits(phys_addr));
4506 ssp_cmd.addr_high =
4507 cpu_to_le32(upper_32_bits(phys_addr));
4508 ssp_cmd.esgl = cpu_to_le32(1<<31);
4509 } else if (task->num_scatter == 1) {
4510 u64 dma_addr = sg_dma_address(task->scatter);
4511
4512 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4513 ssp_cmd.addr_high =
4514 cpu_to_le32(upper_32_bits(dma_addr));
4515 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4516 ssp_cmd.esgl = 0;
4517
4518 /* Check 4G Boundary */
4519 end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4520 end_addr_low = lower_32_bits(end_addr);
4521 end_addr_high = upper_32_bits(end_addr);
4522 if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4523 pm8001_dbg(pm8001_ha, FAIL,
4524 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4525 dma_addr,
4526 le32_to_cpu(ssp_cmd.len),
4527 end_addr_high, end_addr_low);
4528 pm8001_chip_make_sg(task->scatter, 1,
4529 ccb->buf_prd);
4530 phys_addr = ccb->ccb_dma_handle;
4531 ssp_cmd.addr_low =
4532 cpu_to_le32(lower_32_bits(phys_addr));
4533 ssp_cmd.addr_high =
4534 cpu_to_le32(upper_32_bits(phys_addr));
4535 ssp_cmd.esgl = cpu_to_le32(1<<31);
4536 }
4537 } else if (task->num_scatter == 0) {
4538 ssp_cmd.addr_low = 0;
4539 ssp_cmd.addr_high = 0;
4540 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4541 ssp_cmd.esgl = 0;
4542 }
4543 }
4544 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4545 &ssp_cmd, sizeof(ssp_cmd), q_index);
4546 return ret;
4547 }
4548
pm80xx_chip_sata_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_ccb_info * ccb)4549 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4550 struct pm8001_ccb_info *ccb)
4551 {
4552 struct sas_task *task = ccb->task;
4553 struct domain_device *dev = task->dev;
4554 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4555 u32 tag = ccb->ccb_tag;
4556 int ret;
4557 u32 q_index, cpu_id;
4558 struct sata_start_req sata_cmd;
4559 u32 hdr_tag, ncg_tag = 0;
4560 u64 phys_addr, end_addr;
4561 u32 end_addr_high, end_addr_low;
4562 u32 ATAP = 0x0;
4563 u32 dir;
4564 struct inbound_queue_table *circularQ;
4565 unsigned long flags;
4566 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4567 memset(&sata_cmd, 0, sizeof(sata_cmd));
4568 cpu_id = smp_processor_id();
4569 q_index = (u32) (cpu_id) % (pm8001_ha->max_q_num);
4570 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4571
4572 if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4573 ATAP = 0x04; /* no data*/
4574 pm8001_dbg(pm8001_ha, IO, "no data\n");
4575 } else if (likely(!task->ata_task.device_control_reg_update)) {
4576 if (task->ata_task.use_ncq &&
4577 dev->sata_dev.class != ATA_DEV_ATAPI) {
4578 ATAP = 0x07; /* FPDMA */
4579 pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4580 } else if (task->ata_task.dma_xfer) {
4581 ATAP = 0x06; /* DMA */
4582 pm8001_dbg(pm8001_ha, IO, "DMA\n");
4583 } else {
4584 ATAP = 0x05; /* PIO*/
4585 pm8001_dbg(pm8001_ha, IO, "PIO\n");
4586 }
4587 }
4588 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4589 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4590 ncg_tag = hdr_tag;
4591 }
4592 dir = data_dir_flags[task->data_dir] << 8;
4593 sata_cmd.tag = cpu_to_le32(tag);
4594 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4595 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4596
4597 sata_cmd.sata_fis = task->ata_task.fis;
4598 if (likely(!task->ata_task.device_control_reg_update))
4599 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4600 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4601
4602 /* Check if encryption is set */
4603 if (pm8001_ha->chip->encrypt &&
4604 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4605 pm8001_dbg(pm8001_ha, IO,
4606 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4607 sata_cmd.sata_fis.command);
4608 opc = OPC_INB_SATA_DIF_ENC_IO;
4609
4610 /* set encryption bit */
4611 sata_cmd.ncqtag_atap_dir_m_dad =
4612 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4613 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4614 /* dad (bit 0-1) is 0 */
4615 /* fill in PRD (scatter/gather) table, if any */
4616 if (task->num_scatter > 1) {
4617 pm8001_chip_make_sg(task->scatter,
4618 ccb->n_elem, ccb->buf_prd);
4619 phys_addr = ccb->ccb_dma_handle;
4620 sata_cmd.enc_addr_low =
4621 cpu_to_le32(lower_32_bits(phys_addr));
4622 sata_cmd.enc_addr_high =
4623 cpu_to_le32(upper_32_bits(phys_addr));
4624 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4625 } else if (task->num_scatter == 1) {
4626 u64 dma_addr = sg_dma_address(task->scatter);
4627
4628 sata_cmd.enc_addr_low =
4629 cpu_to_le32(lower_32_bits(dma_addr));
4630 sata_cmd.enc_addr_high =
4631 cpu_to_le32(upper_32_bits(dma_addr));
4632 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4633 sata_cmd.enc_esgl = 0;
4634
4635 /* Check 4G Boundary */
4636 end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4637 end_addr_low = lower_32_bits(end_addr);
4638 end_addr_high = upper_32_bits(end_addr);
4639 if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4640 pm8001_dbg(pm8001_ha, FAIL,
4641 "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4642 dma_addr,
4643 le32_to_cpu(sata_cmd.enc_len),
4644 end_addr_high, end_addr_low);
4645 pm8001_chip_make_sg(task->scatter, 1,
4646 ccb->buf_prd);
4647 phys_addr = ccb->ccb_dma_handle;
4648 sata_cmd.enc_addr_low =
4649 cpu_to_le32(lower_32_bits(phys_addr));
4650 sata_cmd.enc_addr_high =
4651 cpu_to_le32(upper_32_bits(phys_addr));
4652 sata_cmd.enc_esgl =
4653 cpu_to_le32(1 << 31);
4654 }
4655 } else if (task->num_scatter == 0) {
4656 sata_cmd.enc_addr_low = 0;
4657 sata_cmd.enc_addr_high = 0;
4658 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4659 sata_cmd.enc_esgl = 0;
4660 }
4661 /* XTS mode. All other fields are 0 */
4662 sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4663
4664 /* set tweak values. Should be the start lba */
4665 sata_cmd.twk_val0 =
4666 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4667 (sata_cmd.sata_fis.lbah << 16) |
4668 (sata_cmd.sata_fis.lbam << 8) |
4669 (sata_cmd.sata_fis.lbal));
4670 sata_cmd.twk_val1 =
4671 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4672 (sata_cmd.sata_fis.lbam_exp));
4673 } else {
4674 pm8001_dbg(pm8001_ha, IO,
4675 "Sending Normal SATA command 0x%x inb %x\n",
4676 sata_cmd.sata_fis.command, q_index);
4677 /* dad (bit 0-1) is 0 */
4678 sata_cmd.ncqtag_atap_dir_m_dad =
4679 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4680 ((ATAP & 0x3f) << 10) | dir);
4681
4682 /* fill in PRD (scatter/gather) table, if any */
4683 if (task->num_scatter > 1) {
4684 pm8001_chip_make_sg(task->scatter,
4685 ccb->n_elem, ccb->buf_prd);
4686 phys_addr = ccb->ccb_dma_handle;
4687 sata_cmd.addr_low = lower_32_bits(phys_addr);
4688 sata_cmd.addr_high = upper_32_bits(phys_addr);
4689 sata_cmd.esgl = cpu_to_le32(1U << 31);
4690 } else if (task->num_scatter == 1) {
4691 u64 dma_addr = sg_dma_address(task->scatter);
4692
4693 sata_cmd.addr_low = lower_32_bits(dma_addr);
4694 sata_cmd.addr_high = upper_32_bits(dma_addr);
4695 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4696 sata_cmd.esgl = 0;
4697
4698 /* Check 4G Boundary */
4699 end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4700 end_addr_low = lower_32_bits(end_addr);
4701 end_addr_high = upper_32_bits(end_addr);
4702 if (end_addr_high != sata_cmd.addr_high) {
4703 pm8001_dbg(pm8001_ha, FAIL,
4704 "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4705 dma_addr,
4706 le32_to_cpu(sata_cmd.len),
4707 end_addr_high, end_addr_low);
4708 pm8001_chip_make_sg(task->scatter, 1,
4709 ccb->buf_prd);
4710 phys_addr = ccb->ccb_dma_handle;
4711 sata_cmd.addr_low = lower_32_bits(phys_addr);
4712 sata_cmd.addr_high = upper_32_bits(phys_addr);
4713 sata_cmd.esgl = cpu_to_le32(1U << 31);
4714 }
4715 } else if (task->num_scatter == 0) {
4716 sata_cmd.addr_low = 0;
4717 sata_cmd.addr_high = 0;
4718 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4719 sata_cmd.esgl = 0;
4720 }
4721
4722 /* scsi cdb */
4723 sata_cmd.atapi_scsi_cdb[0] =
4724 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4725 (task->ata_task.atapi_packet[1] << 8) |
4726 (task->ata_task.atapi_packet[2] << 16) |
4727 (task->ata_task.atapi_packet[3] << 24)));
4728 sata_cmd.atapi_scsi_cdb[1] =
4729 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4730 (task->ata_task.atapi_packet[5] << 8) |
4731 (task->ata_task.atapi_packet[6] << 16) |
4732 (task->ata_task.atapi_packet[7] << 24)));
4733 sata_cmd.atapi_scsi_cdb[2] =
4734 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4735 (task->ata_task.atapi_packet[9] << 8) |
4736 (task->ata_task.atapi_packet[10] << 16) |
4737 (task->ata_task.atapi_packet[11] << 24)));
4738 sata_cmd.atapi_scsi_cdb[3] =
4739 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4740 (task->ata_task.atapi_packet[13] << 8) |
4741 (task->ata_task.atapi_packet[14] << 16) |
4742 (task->ata_task.atapi_packet[15] << 24)));
4743 }
4744
4745 /* Check for read log for failed drive and return */
4746 if (sata_cmd.sata_fis.command == 0x2f) {
4747 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4748 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4749 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4750 struct task_status_struct *ts;
4751
4752 pm8001_ha_dev->id &= 0xDFFFFFFF;
4753 ts = &task->task_status;
4754
4755 spin_lock_irqsave(&task->task_state_lock, flags);
4756 ts->resp = SAS_TASK_COMPLETE;
4757 ts->stat = SAS_SAM_STAT_GOOD;
4758 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4759 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4760 task->task_state_flags |= SAS_TASK_STATE_DONE;
4761 if (unlikely((task->task_state_flags &
4762 SAS_TASK_STATE_ABORTED))) {
4763 spin_unlock_irqrestore(&task->task_state_lock,
4764 flags);
4765 pm8001_dbg(pm8001_ha, FAIL,
4766 "task 0x%p resp 0x%x stat 0x%x but aborted by upper layer\n",
4767 task, ts->resp,
4768 ts->stat);
4769 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4770 return 0;
4771 } else {
4772 spin_unlock_irqrestore(&task->task_state_lock,
4773 flags);
4774 pm8001_ccb_task_free_done(pm8001_ha, task,
4775 ccb, tag);
4776 atomic_dec(&pm8001_ha_dev->running_req);
4777 return 0;
4778 }
4779 }
4780 }
4781 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4782 &sata_cmd, sizeof(sata_cmd), q_index);
4783 return ret;
4784 }
4785
4786 /**
4787 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4788 * @pm8001_ha: our hba card information.
4789 * @phy_id: the phy id which we wanted to start up.
4790 */
4791 static int
pm80xx_chip_phy_start_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4792 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4793 {
4794 struct phy_start_req payload;
4795 struct inbound_queue_table *circularQ;
4796 int ret;
4797 u32 tag = 0x01;
4798 u32 opcode = OPC_INB_PHYSTART;
4799 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4800 memset(&payload, 0, sizeof(payload));
4801 payload.tag = cpu_to_le32(tag);
4802
4803 pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4804
4805 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4806 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4807 /* SSC Disable and SAS Analog ST configuration */
4808 /*
4809 payload.ase_sh_lm_slr_phyid =
4810 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4811 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4812 phy_id);
4813 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4814 */
4815
4816 payload.sas_identify.dev_type = SAS_END_DEVICE;
4817 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4818 memcpy(payload.sas_identify.sas_addr,
4819 &pm8001_ha->phy[phy_id].dev_sas_addr, SAS_ADDR_SIZE);
4820 payload.sas_identify.phy_id = phy_id;
4821 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4822 sizeof(payload), 0);
4823 return ret;
4824 }
4825
4826 /**
4827 * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4828 * @pm8001_ha: our hba card information.
4829 * @phy_id: the phy id which we wanted to start up.
4830 */
pm80xx_chip_phy_stop_req(struct pm8001_hba_info * pm8001_ha,u8 phy_id)4831 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4832 u8 phy_id)
4833 {
4834 struct phy_stop_req payload;
4835 struct inbound_queue_table *circularQ;
4836 int ret;
4837 u32 tag = 0x01;
4838 u32 opcode = OPC_INB_PHYSTOP;
4839 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4840 memset(&payload, 0, sizeof(payload));
4841 payload.tag = cpu_to_le32(tag);
4842 payload.phy_id = cpu_to_le32(phy_id);
4843 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4844 sizeof(payload), 0);
4845 return ret;
4846 }
4847
4848 /*
4849 * see comments on pm8001_mpi_reg_resp.
4850 */
pm80xx_chip_reg_dev_req(struct pm8001_hba_info * pm8001_ha,struct pm8001_device * pm8001_dev,u32 flag)4851 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4852 struct pm8001_device *pm8001_dev, u32 flag)
4853 {
4854 struct reg_dev_req payload;
4855 u32 opc;
4856 u32 stp_sspsmp_sata = 0x4;
4857 struct inbound_queue_table *circularQ;
4858 u32 linkrate, phy_id;
4859 int rc, tag = 0xdeadbeef;
4860 struct pm8001_ccb_info *ccb;
4861 u8 retryFlag = 0x1;
4862 u16 firstBurstSize = 0;
4863 u16 ITNT = 2000;
4864 struct domain_device *dev = pm8001_dev->sas_device;
4865 struct domain_device *parent_dev = dev->parent;
4866 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4867
4868 memset(&payload, 0, sizeof(payload));
4869 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4870 if (rc)
4871 return rc;
4872 ccb = &pm8001_ha->ccb_info[tag];
4873 ccb->device = pm8001_dev;
4874 ccb->ccb_tag = tag;
4875 payload.tag = cpu_to_le32(tag);
4876
4877 if (flag == 1) {
4878 stp_sspsmp_sata = 0x02; /*direct attached sata */
4879 } else {
4880 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4881 stp_sspsmp_sata = 0x00; /* stp*/
4882 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4883 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4884 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4885 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4886 }
4887 if (parent_dev && dev_is_expander(parent_dev->dev_type))
4888 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4889 else
4890 phy_id = pm8001_dev->attached_phy;
4891
4892 opc = OPC_INB_REG_DEV;
4893
4894 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4895 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4896
4897 payload.phyid_portid =
4898 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4899 ((phy_id & 0xFF) << 8));
4900
4901 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4902 ((linkrate & 0x0F) << 24) |
4903 ((stp_sspsmp_sata & 0x03) << 28));
4904 payload.firstburstsize_ITNexustimeout =
4905 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4906
4907 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4908 SAS_ADDR_SIZE);
4909
4910 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4911 sizeof(payload), 0);
4912 if (rc)
4913 pm8001_tag_free(pm8001_ha, tag);
4914
4915 return rc;
4916 }
4917
4918 /**
4919 * pm80xx_chip_phy_ctl_req - support the local phy operation
4920 * @pm8001_ha: our hba card information.
4921 * @phyId: the phy id which we wanted to operate
4922 * @phy_op: phy operation to request
4923 */
pm80xx_chip_phy_ctl_req(struct pm8001_hba_info * pm8001_ha,u32 phyId,u32 phy_op)4924 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4925 u32 phyId, u32 phy_op)
4926 {
4927 u32 tag;
4928 int rc;
4929 struct local_phy_ctl_req payload;
4930 struct inbound_queue_table *circularQ;
4931 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4932 memset(&payload, 0, sizeof(payload));
4933 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4934 if (rc)
4935 return rc;
4936 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4937 payload.tag = cpu_to_le32(tag);
4938 payload.phyop_phyid =
4939 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4940
4941 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4942 sizeof(payload), 0);
4943 if (rc)
4944 pm8001_tag_free(pm8001_ha, tag);
4945
4946 return rc;
4947 }
4948
pm80xx_chip_is_our_interrupt(struct pm8001_hba_info * pm8001_ha)4949 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4950 {
4951 #ifdef PM8001_USE_MSIX
4952 return 1;
4953 #else
4954 u32 value;
4955
4956 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4957 if (value)
4958 return 1;
4959 return 0;
4960 #endif
4961 }
4962
4963 /**
4964 * pm80xx_chip_isr - PM8001 isr handler.
4965 * @pm8001_ha: our hba card information.
4966 * @vec: irq number.
4967 */
4968 static irqreturn_t
pm80xx_chip_isr(struct pm8001_hba_info * pm8001_ha,u8 vec)4969 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4970 {
4971 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4972 pm8001_dbg(pm8001_ha, DEVIO,
4973 "irq vec %d, ODMR:0x%x\n",
4974 vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4975 process_oq(pm8001_ha, vec);
4976 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4977 return IRQ_HANDLED;
4978 }
4979
mpi_set_phy_profile_req(struct pm8001_hba_info * pm8001_ha,u32 operation,u32 phyid,u32 length,u32 * buf)4980 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4981 u32 operation, u32 phyid,
4982 u32 length, u32 *buf)
4983 {
4984 u32 tag, i, j = 0;
4985 int rc;
4986 struct set_phy_profile_req payload;
4987 struct inbound_queue_table *circularQ;
4988 u32 opc = OPC_INB_SET_PHY_PROFILE;
4989
4990 memset(&payload, 0, sizeof(payload));
4991 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4992 if (rc)
4993 pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4994 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4995 payload.tag = cpu_to_le32(tag);
4996 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4997 pm8001_dbg(pm8001_ha, INIT,
4998 " phy profile command for phy %x ,length is %d\n",
4999 payload.ppc_phyid, length);
5000 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
5001 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
5002 j++;
5003 }
5004 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5005 sizeof(payload), 0);
5006 if (rc)
5007 pm8001_tag_free(pm8001_ha, tag);
5008 }
5009
pm8001_set_phy_profile(struct pm8001_hba_info * pm8001_ha,u32 length,u8 * buf)5010 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
5011 u32 length, u8 *buf)
5012 {
5013 u32 i;
5014
5015 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
5016 mpi_set_phy_profile_req(pm8001_ha,
5017 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
5018 length = length + PHY_DWORD_LENGTH;
5019 }
5020 pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
5021 }
5022
pm8001_set_phy_profile_single(struct pm8001_hba_info * pm8001_ha,u32 phy,u32 length,u32 * buf)5023 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
5024 u32 phy, u32 length, u32 *buf)
5025 {
5026 u32 tag, opc;
5027 int rc, i;
5028 struct set_phy_profile_req payload;
5029 struct inbound_queue_table *circularQ;
5030
5031 memset(&payload, 0, sizeof(payload));
5032
5033 rc = pm8001_tag_alloc(pm8001_ha, &tag);
5034 if (rc)
5035 pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
5036
5037 circularQ = &pm8001_ha->inbnd_q_tbl[0];
5038 opc = OPC_INB_SET_PHY_PROFILE;
5039
5040 payload.tag = cpu_to_le32(tag);
5041 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
5042 | (phy & 0xFF));
5043
5044 for (i = 0; i < length; i++)
5045 payload.reserved[i] = cpu_to_le32(*(buf + i));
5046
5047 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
5048 sizeof(payload), 0);
5049 if (rc)
5050 pm8001_tag_free(pm8001_ha, tag);
5051
5052 pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
5053 }
5054 const struct pm8001_dispatch pm8001_80xx_dispatch = {
5055 .name = "pmc80xx",
5056 .chip_init = pm80xx_chip_init,
5057 .chip_soft_rst = pm80xx_chip_soft_rst,
5058 .chip_rst = pm80xx_hw_chip_rst,
5059 .chip_iounmap = pm8001_chip_iounmap,
5060 .isr = pm80xx_chip_isr,
5061 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
5062 .isr_process_oq = process_oq,
5063 .interrupt_enable = pm80xx_chip_interrupt_enable,
5064 .interrupt_disable = pm80xx_chip_interrupt_disable,
5065 .make_prd = pm8001_chip_make_sg,
5066 .smp_req = pm80xx_chip_smp_req,
5067 .ssp_io_req = pm80xx_chip_ssp_io_req,
5068 .sata_req = pm80xx_chip_sata_req,
5069 .phy_start_req = pm80xx_chip_phy_start_req,
5070 .phy_stop_req = pm80xx_chip_phy_stop_req,
5071 .reg_dev_req = pm80xx_chip_reg_dev_req,
5072 .dereg_dev_req = pm8001_chip_dereg_dev_req,
5073 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
5074 .task_abort = pm8001_chip_abort_task,
5075 .ssp_tm_req = pm8001_chip_ssp_tm_req,
5076 .get_nvmd_req = pm8001_chip_get_nvmd_req,
5077 .set_nvmd_req = pm8001_chip_set_nvmd_req,
5078 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
5079 .set_dev_state_req = pm8001_chip_set_dev_state_req,
5080 .fatal_errors = pm80xx_fatal_errors,
5081 };
5082