1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/reset.h>
21 #include <linux/dmaengine.h>
22
23 #include <linux/spi/spi.h>
24
25 #define SUN6I_AUTOSUSPEND_TIMEOUT 2000
26
27 #define SUN6I_FIFO_DEPTH 128
28 #define SUN8I_FIFO_DEPTH 64
29
30 #define SUN6I_GBL_CTL_REG 0x04
31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32 #define SUN6I_GBL_CTL_MASTER BIT(1)
33 #define SUN6I_GBL_CTL_TP BIT(7)
34 #define SUN6I_GBL_CTL_RST BIT(31)
35
36 #define SUN6I_TFR_CTL_REG 0x08
37 #define SUN6I_TFR_CTL_CPHA BIT(0)
38 #define SUN6I_TFR_CTL_CPOL BIT(1)
39 #define SUN6I_TFR_CTL_SPOL BIT(2)
40 #define SUN6I_TFR_CTL_CS_MASK 0x30
41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44 #define SUN6I_TFR_CTL_DHB BIT(8)
45 #define SUN6I_TFR_CTL_FBS BIT(12)
46 #define SUN6I_TFR_CTL_XCH BIT(31)
47
48 #define SUN6I_INT_CTL_REG 0x10
49 #define SUN6I_INT_CTL_RF_RDY BIT(0)
50 #define SUN6I_INT_CTL_TF_ERQ BIT(4)
51 #define SUN6I_INT_CTL_RF_OVF BIT(8)
52 #define SUN6I_INT_CTL_TC BIT(12)
53
54 #define SUN6I_INT_STA_REG 0x14
55
56 #define SUN6I_FIFO_CTL_REG 0x18
57 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
58 #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8)
59 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
60 #define SUN6I_FIFO_CTL_RF_RST BIT(15)
61 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
62 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
63 #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24)
64 #define SUN6I_FIFO_CTL_TF_RST BIT(31)
65
66 #define SUN6I_FIFO_STA_REG 0x1c
67 #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
68 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
69
70 #define SUN6I_CLK_CTL_REG 0x24
71 #define SUN6I_CLK_CTL_CDR2_MASK 0xff
72 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
73 #define SUN6I_CLK_CTL_CDR1_MASK 0xf
74 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
75 #define SUN6I_CLK_CTL_DRS BIT(12)
76
77 #define SUN6I_MAX_XFER_SIZE 0xffffff
78
79 #define SUN6I_BURST_CNT_REG 0x30
80
81 #define SUN6I_XMIT_CNT_REG 0x34
82
83 #define SUN6I_BURST_CTL_CNT_REG 0x38
84
85 #define SUN6I_TXDATA_REG 0x200
86 #define SUN6I_RXDATA_REG 0x300
87
88 struct sun6i_spi {
89 struct spi_master *master;
90 void __iomem *base_addr;
91 dma_addr_t dma_addr_rx;
92 dma_addr_t dma_addr_tx;
93 struct clk *hclk;
94 struct clk *mclk;
95 struct reset_control *rstc;
96
97 struct completion done;
98 struct completion dma_rx_done;
99
100 const u8 *tx_buf;
101 u8 *rx_buf;
102 int len;
103 unsigned long fifo_depth;
104 };
105
sun6i_spi_read(struct sun6i_spi * sspi,u32 reg)106 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
107 {
108 return readl(sspi->base_addr + reg);
109 }
110
sun6i_spi_write(struct sun6i_spi * sspi,u32 reg,u32 value)111 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
112 {
113 writel(value, sspi->base_addr + reg);
114 }
115
sun6i_spi_get_rx_fifo_count(struct sun6i_spi * sspi)116 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
117 {
118 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
119
120 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
121 }
122
sun6i_spi_get_tx_fifo_count(struct sun6i_spi * sspi)123 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
124 {
125 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
126
127 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
128 }
129
sun6i_spi_disable_interrupt(struct sun6i_spi * sspi,u32 mask)130 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
131 {
132 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
133
134 reg &= ~mask;
135 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
136 }
137
sun6i_spi_drain_fifo(struct sun6i_spi * sspi)138 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
139 {
140 u32 len;
141 u8 byte;
142
143 /* See how much data is available */
144 len = sun6i_spi_get_rx_fifo_count(sspi);
145
146 while (len--) {
147 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
148 if (sspi->rx_buf)
149 *sspi->rx_buf++ = byte;
150 }
151 }
152
sun6i_spi_fill_fifo(struct sun6i_spi * sspi)153 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
154 {
155 u32 cnt;
156 int len;
157 u8 byte;
158
159 /* See how much data we can fit */
160 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
161
162 len = min((int)cnt, sspi->len);
163
164 while (len--) {
165 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
166 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
167 sspi->len--;
168 }
169 }
170
sun6i_spi_set_cs(struct spi_device * spi,bool enable)171 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
172 {
173 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
174 u32 reg;
175
176 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
177 reg &= ~SUN6I_TFR_CTL_CS_MASK;
178 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
179
180 if (enable)
181 reg |= SUN6I_TFR_CTL_CS_LEVEL;
182 else
183 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
184
185 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
186 }
187
sun6i_spi_max_transfer_size(struct spi_device * spi)188 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
189 {
190 return SUN6I_MAX_XFER_SIZE - 1;
191 }
192
sun6i_spi_dma_rx_cb(void * param)193 static void sun6i_spi_dma_rx_cb(void *param)
194 {
195 struct sun6i_spi *sspi = param;
196
197 complete(&sspi->dma_rx_done);
198 }
199
sun6i_spi_prepare_dma(struct sun6i_spi * sspi,struct spi_transfer * tfr)200 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
201 struct spi_transfer *tfr)
202 {
203 struct dma_async_tx_descriptor *rxdesc, *txdesc;
204 struct spi_master *master = sspi->master;
205
206 rxdesc = NULL;
207 if (tfr->rx_buf) {
208 struct dma_slave_config rxconf = {
209 .direction = DMA_DEV_TO_MEM,
210 .src_addr = sspi->dma_addr_rx,
211 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
212 .src_maxburst = 8,
213 };
214
215 dmaengine_slave_config(master->dma_rx, &rxconf);
216
217 rxdesc = dmaengine_prep_slave_sg(master->dma_rx,
218 tfr->rx_sg.sgl,
219 tfr->rx_sg.nents,
220 DMA_DEV_TO_MEM,
221 DMA_PREP_INTERRUPT);
222 if (!rxdesc)
223 return -EINVAL;
224 rxdesc->callback_param = sspi;
225 rxdesc->callback = sun6i_spi_dma_rx_cb;
226 }
227
228 txdesc = NULL;
229 if (tfr->tx_buf) {
230 struct dma_slave_config txconf = {
231 .direction = DMA_MEM_TO_DEV,
232 .dst_addr = sspi->dma_addr_tx,
233 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
234 .dst_maxburst = 8,
235 };
236
237 dmaengine_slave_config(master->dma_tx, &txconf);
238
239 txdesc = dmaengine_prep_slave_sg(master->dma_tx,
240 tfr->tx_sg.sgl,
241 tfr->tx_sg.nents,
242 DMA_MEM_TO_DEV,
243 DMA_PREP_INTERRUPT);
244 if (!txdesc) {
245 if (rxdesc)
246 dmaengine_terminate_sync(master->dma_rx);
247 return -EINVAL;
248 }
249 }
250
251 if (tfr->rx_buf) {
252 dmaengine_submit(rxdesc);
253 dma_async_issue_pending(master->dma_rx);
254 }
255
256 if (tfr->tx_buf) {
257 dmaengine_submit(txdesc);
258 dma_async_issue_pending(master->dma_tx);
259 }
260
261 return 0;
262 }
263
sun6i_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * tfr)264 static int sun6i_spi_transfer_one(struct spi_master *master,
265 struct spi_device *spi,
266 struct spi_transfer *tfr)
267 {
268 struct sun6i_spi *sspi = spi_master_get_devdata(master);
269 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
270 unsigned int start, end, tx_time;
271 unsigned int trig_level;
272 unsigned int tx_len = 0, rx_len = 0;
273 bool use_dma;
274 int ret = 0;
275 u32 reg;
276
277 if (tfr->len > SUN6I_MAX_XFER_SIZE)
278 return -EINVAL;
279
280 reinit_completion(&sspi->done);
281 reinit_completion(&sspi->dma_rx_done);
282 sspi->tx_buf = tfr->tx_buf;
283 sspi->rx_buf = tfr->rx_buf;
284 sspi->len = tfr->len;
285 use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false;
286
287 /* Clear pending interrupts */
288 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
289
290 /* Reset FIFO */
291 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
292 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
293
294 reg = 0;
295
296 if (!use_dma) {
297 /*
298 * Setup FIFO interrupt trigger level
299 * Here we choose 3/4 of the full fifo depth, as it's
300 * the hardcoded value used in old generation of Allwinner
301 * SPI controller. (See spi-sun4i.c)
302 */
303 trig_level = sspi->fifo_depth / 4 * 3;
304 } else {
305 /*
306 * Setup FIFO DMA request trigger level
307 * We choose 1/2 of the full fifo depth, that value will
308 * be used as DMA burst length.
309 */
310 trig_level = sspi->fifo_depth / 2;
311
312 if (tfr->tx_buf)
313 reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
314 if (tfr->rx_buf)
315 reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
316 }
317
318 reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
319 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
320
321 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
322
323 /*
324 * Setup the transfer control register: Chip Select,
325 * polarities, etc.
326 */
327 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
328
329 if (spi->mode & SPI_CPOL)
330 reg |= SUN6I_TFR_CTL_CPOL;
331 else
332 reg &= ~SUN6I_TFR_CTL_CPOL;
333
334 if (spi->mode & SPI_CPHA)
335 reg |= SUN6I_TFR_CTL_CPHA;
336 else
337 reg &= ~SUN6I_TFR_CTL_CPHA;
338
339 if (spi->mode & SPI_LSB_FIRST)
340 reg |= SUN6I_TFR_CTL_FBS;
341 else
342 reg &= ~SUN6I_TFR_CTL_FBS;
343
344 /*
345 * If it's a TX only transfer, we don't want to fill the RX
346 * FIFO with bogus data
347 */
348 if (sspi->rx_buf) {
349 reg &= ~SUN6I_TFR_CTL_DHB;
350 rx_len = tfr->len;
351 } else {
352 reg |= SUN6I_TFR_CTL_DHB;
353 }
354
355 /* We want to control the chip select manually */
356 reg |= SUN6I_TFR_CTL_CS_MANUAL;
357
358 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
359
360 /* Ensure that we have a parent clock fast enough */
361 mclk_rate = clk_get_rate(sspi->mclk);
362 if (mclk_rate < (2 * tfr->speed_hz)) {
363 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
364 mclk_rate = clk_get_rate(sspi->mclk);
365 }
366
367 /*
368 * Setup clock divider.
369 *
370 * We have two choices there. Either we can use the clock
371 * divide rate 1, which is calculated thanks to this formula:
372 * SPI_CLK = MOD_CLK / (2 ^ cdr)
373 * Or we can use CDR2, which is calculated with the formula:
374 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
375 * Wether we use the former or the latter is set through the
376 * DRS bit.
377 *
378 * First try CDR2, and if we can't reach the expected
379 * frequency, fall back to CDR1.
380 */
381 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
382 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
383 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
384 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
385 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
386 } else {
387 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
388 reg = SUN6I_CLK_CTL_CDR1(div);
389 tfr->effective_speed_hz = mclk_rate / (1 << div);
390 }
391
392 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
393 /* Finally enable the bus - doing so before might raise SCK to HIGH */
394 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
395 reg |= SUN6I_GBL_CTL_BUS_ENABLE;
396 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
397
398 /* Setup the transfer now... */
399 if (sspi->tx_buf)
400 tx_len = tfr->len;
401
402 /* Setup the counters */
403 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
404 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
405 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
406
407 if (!use_dma) {
408 /* Fill the TX FIFO */
409 sun6i_spi_fill_fifo(sspi);
410 } else {
411 ret = sun6i_spi_prepare_dma(sspi, tfr);
412 if (ret) {
413 dev_warn(&master->dev,
414 "%s: prepare DMA failed, ret=%d",
415 dev_name(&spi->dev), ret);
416 return ret;
417 }
418 }
419
420 /* Enable the interrupts */
421 reg = SUN6I_INT_CTL_TC;
422
423 if (!use_dma) {
424 if (rx_len > sspi->fifo_depth)
425 reg |= SUN6I_INT_CTL_RF_RDY;
426 if (tx_len > sspi->fifo_depth)
427 reg |= SUN6I_INT_CTL_TF_ERQ;
428 }
429
430 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
431
432 /* Start the transfer */
433 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
434 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
435
436 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
437 start = jiffies;
438 timeout = wait_for_completion_timeout(&sspi->done,
439 msecs_to_jiffies(tx_time));
440
441 if (!use_dma) {
442 sun6i_spi_drain_fifo(sspi);
443 } else {
444 if (timeout && rx_len) {
445 /*
446 * Even though RX on the peripheral side has finished
447 * RX DMA might still be in flight
448 */
449 timeout = wait_for_completion_timeout(&sspi->dma_rx_done,
450 timeout);
451 if (!timeout)
452 dev_warn(&master->dev, "RX DMA timeout\n");
453 }
454 }
455
456 end = jiffies;
457 if (!timeout) {
458 dev_warn(&master->dev,
459 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
460 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
461 jiffies_to_msecs(end - start), tx_time);
462 ret = -ETIMEDOUT;
463 }
464
465 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
466
467 if (ret && use_dma) {
468 dmaengine_terminate_sync(master->dma_rx);
469 dmaengine_terminate_sync(master->dma_tx);
470 }
471
472 return ret;
473 }
474
sun6i_spi_handler(int irq,void * dev_id)475 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
476 {
477 struct sun6i_spi *sspi = dev_id;
478 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
479
480 /* Transfer complete */
481 if (status & SUN6I_INT_CTL_TC) {
482 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
483 complete(&sspi->done);
484 return IRQ_HANDLED;
485 }
486
487 /* Receive FIFO 3/4 full */
488 if (status & SUN6I_INT_CTL_RF_RDY) {
489 sun6i_spi_drain_fifo(sspi);
490 /* Only clear the interrupt _after_ draining the FIFO */
491 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
492 return IRQ_HANDLED;
493 }
494
495 /* Transmit FIFO 3/4 empty */
496 if (status & SUN6I_INT_CTL_TF_ERQ) {
497 sun6i_spi_fill_fifo(sspi);
498
499 if (!sspi->len)
500 /* nothing left to transmit */
501 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
502
503 /* Only clear the interrupt _after_ re-seeding the FIFO */
504 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
505
506 return IRQ_HANDLED;
507 }
508
509 return IRQ_NONE;
510 }
511
sun6i_spi_runtime_resume(struct device * dev)512 static int sun6i_spi_runtime_resume(struct device *dev)
513 {
514 struct spi_master *master = dev_get_drvdata(dev);
515 struct sun6i_spi *sspi = spi_master_get_devdata(master);
516 int ret;
517
518 ret = clk_prepare_enable(sspi->hclk);
519 if (ret) {
520 dev_err(dev, "Couldn't enable AHB clock\n");
521 goto out;
522 }
523
524 ret = clk_prepare_enable(sspi->mclk);
525 if (ret) {
526 dev_err(dev, "Couldn't enable module clock\n");
527 goto err;
528 }
529
530 ret = reset_control_deassert(sspi->rstc);
531 if (ret) {
532 dev_err(dev, "Couldn't deassert the device from reset\n");
533 goto err2;
534 }
535
536 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
537 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
538
539 return 0;
540
541 err2:
542 clk_disable_unprepare(sspi->mclk);
543 err:
544 clk_disable_unprepare(sspi->hclk);
545 out:
546 return ret;
547 }
548
sun6i_spi_runtime_suspend(struct device * dev)549 static int sun6i_spi_runtime_suspend(struct device *dev)
550 {
551 struct spi_master *master = dev_get_drvdata(dev);
552 struct sun6i_spi *sspi = spi_master_get_devdata(master);
553
554 reset_control_assert(sspi->rstc);
555 clk_disable_unprepare(sspi->mclk);
556 clk_disable_unprepare(sspi->hclk);
557
558 return 0;
559 }
560
sun6i_spi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)561 static bool sun6i_spi_can_dma(struct spi_master *master,
562 struct spi_device *spi,
563 struct spi_transfer *xfer)
564 {
565 struct sun6i_spi *sspi = spi_master_get_devdata(master);
566
567 /*
568 * If the number of spi words to transfer is less or equal than
569 * the fifo length we can just fill the fifo and wait for a single
570 * irq, so don't bother setting up dma
571 */
572 return xfer->len > sspi->fifo_depth;
573 }
574
sun6i_spi_probe(struct platform_device * pdev)575 static int sun6i_spi_probe(struct platform_device *pdev)
576 {
577 struct spi_master *master;
578 struct sun6i_spi *sspi;
579 struct resource *mem;
580 int ret = 0, irq;
581
582 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
583 if (!master) {
584 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
585 return -ENOMEM;
586 }
587
588 platform_set_drvdata(pdev, master);
589 sspi = spi_master_get_devdata(master);
590
591 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
592 if (IS_ERR(sspi->base_addr)) {
593 ret = PTR_ERR(sspi->base_addr);
594 goto err_free_master;
595 }
596
597 irq = platform_get_irq(pdev, 0);
598 if (irq < 0) {
599 ret = -ENXIO;
600 goto err_free_master;
601 }
602
603 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
604 0, "sun6i-spi", sspi);
605 if (ret) {
606 dev_err(&pdev->dev, "Cannot request IRQ\n");
607 goto err_free_master;
608 }
609
610 sspi->master = master;
611 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
612
613 master->max_speed_hz = 100 * 1000 * 1000;
614 master->min_speed_hz = 3 * 1000;
615 master->use_gpio_descriptors = true;
616 master->set_cs = sun6i_spi_set_cs;
617 master->transfer_one = sun6i_spi_transfer_one;
618 master->num_chipselect = 4;
619 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
620 master->bits_per_word_mask = SPI_BPW_MASK(8);
621 master->dev.of_node = pdev->dev.of_node;
622 master->auto_runtime_pm = true;
623 master->max_transfer_size = sun6i_spi_max_transfer_size;
624
625 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
626 if (IS_ERR(sspi->hclk)) {
627 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
628 ret = PTR_ERR(sspi->hclk);
629 goto err_free_master;
630 }
631
632 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
633 if (IS_ERR(sspi->mclk)) {
634 dev_err(&pdev->dev, "Unable to acquire module clock\n");
635 ret = PTR_ERR(sspi->mclk);
636 goto err_free_master;
637 }
638
639 init_completion(&sspi->done);
640 init_completion(&sspi->dma_rx_done);
641
642 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
643 if (IS_ERR(sspi->rstc)) {
644 dev_err(&pdev->dev, "Couldn't get reset controller\n");
645 ret = PTR_ERR(sspi->rstc);
646 goto err_free_master;
647 }
648
649 master->dma_tx = dma_request_chan(&pdev->dev, "tx");
650 if (IS_ERR(master->dma_tx)) {
651 /* Check tx to see if we need defer probing driver */
652 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) {
653 ret = -EPROBE_DEFER;
654 goto err_free_master;
655 }
656 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
657 master->dma_tx = NULL;
658 }
659
660 master->dma_rx = dma_request_chan(&pdev->dev, "rx");
661 if (IS_ERR(master->dma_rx)) {
662 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) {
663 ret = -EPROBE_DEFER;
664 goto err_free_dma_tx;
665 }
666 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
667 master->dma_rx = NULL;
668 }
669
670 if (master->dma_tx && master->dma_rx) {
671 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
672 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
673 master->can_dma = sun6i_spi_can_dma;
674 }
675
676 /*
677 * This wake-up/shutdown pattern is to be able to have the
678 * device woken up, even if runtime_pm is disabled
679 */
680 ret = sun6i_spi_runtime_resume(&pdev->dev);
681 if (ret) {
682 dev_err(&pdev->dev, "Couldn't resume the device\n");
683 goto err_free_dma_rx;
684 }
685
686 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
687 pm_runtime_use_autosuspend(&pdev->dev);
688 pm_runtime_set_active(&pdev->dev);
689 pm_runtime_enable(&pdev->dev);
690
691 ret = devm_spi_register_master(&pdev->dev, master);
692 if (ret) {
693 dev_err(&pdev->dev, "cannot register SPI master\n");
694 goto err_pm_disable;
695 }
696
697 return 0;
698
699 err_pm_disable:
700 pm_runtime_disable(&pdev->dev);
701 sun6i_spi_runtime_suspend(&pdev->dev);
702 err_free_dma_rx:
703 if (master->dma_rx)
704 dma_release_channel(master->dma_rx);
705 err_free_dma_tx:
706 if (master->dma_tx)
707 dma_release_channel(master->dma_tx);
708 err_free_master:
709 spi_master_put(master);
710 return ret;
711 }
712
sun6i_spi_remove(struct platform_device * pdev)713 static int sun6i_spi_remove(struct platform_device *pdev)
714 {
715 struct spi_master *master = platform_get_drvdata(pdev);
716
717 pm_runtime_force_suspend(&pdev->dev);
718
719 if (master->dma_tx)
720 dma_release_channel(master->dma_tx);
721 if (master->dma_rx)
722 dma_release_channel(master->dma_rx);
723 return 0;
724 }
725
726 static const struct of_device_id sun6i_spi_match[] = {
727 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
728 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
729 {}
730 };
731 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
732
733 static const struct dev_pm_ops sun6i_spi_pm_ops = {
734 .runtime_resume = sun6i_spi_runtime_resume,
735 .runtime_suspend = sun6i_spi_runtime_suspend,
736 };
737
738 static struct platform_driver sun6i_spi_driver = {
739 .probe = sun6i_spi_probe,
740 .remove = sun6i_spi_remove,
741 .driver = {
742 .name = "sun6i-spi",
743 .of_match_table = sun6i_spi_match,
744 .pm = &sun6i_spi_pm_ops,
745 },
746 };
747 module_platform_driver(sun6i_spi_driver);
748
749 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
750 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
751 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
752 MODULE_LICENSE("GPL");
753