1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
7 *
8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
11 *
12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14 * www.moxa.com.
15 * - Fixed x86_64 cleanness
16 */
17
18 #include <linux/module.h>
19 #include <linux/errno.h>
20 #include <linux/signal.h>
21 #include <linux/sched.h>
22 #include <linux/timer.h>
23 #include <linux/interrupt.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_reg.h>
28 #include <linux/major.h>
29 #include <linux/string.h>
30 #include <linux/fcntl.h>
31 #include <linux/ptrace.h>
32 #include <linux/ioport.h>
33 #include <linux/mm.h>
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/bitops.h>
37 #include <linux/slab.h>
38 #include <linux/ratelimit.h>
39
40 #include <asm/io.h>
41 #include <asm/irq.h>
42 #include <linux/uaccess.h>
43
44 /*
45 * Semi-public control interfaces
46 */
47
48 /*
49 * MOXA ioctls
50 */
51
52 #define MOXA 0x400
53 #define MOXA_SET_OP_MODE (MOXA + 66)
54 #define MOXA_GET_OP_MODE (MOXA + 67)
55
56 #define RS232_MODE 0
57 #define RS485_2WIRE_MODE 1
58 #define RS422_MODE 2
59 #define RS485_4WIRE_MODE 3
60 #define OP_MODE_MASK 3
61
62 /* --------------------------------------------------- */
63
64 /*
65 * Follow just what Moxa Must chip defines.
66 *
67 * When LCR register (offset 0x03) is written the following value, the Must chip
68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will
69 * change bank.
70 */
71 #define MOXA_MUST_ENTER_ENHANCED 0xBF
72
73 /* when enhanced mode is enabled, access to general bank register */
74 #define MOXA_MUST_GDL_REGISTER 0x07
75 #define MOXA_MUST_GDL_MASK 0x7F
76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80
77
78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */
79 /* enhanced register bank select and enhanced mode setting register */
80 /* This works only when LCR register equals to 0xBF */
81 #define MOXA_MUST_EFR_REGISTER 0x02
82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */
83 /* enhanced register bank set 0, 1, 2 */
84 #define MOXA_MUST_EFR_BANK0 0x00
85 #define MOXA_MUST_EFR_BANK1 0x40
86 #define MOXA_MUST_EFR_BANK2 0x80
87 #define MOXA_MUST_EFR_BANK3 0xC0
88 #define MOXA_MUST_EFR_BANK_MASK 0xC0
89
90 /* set XON1 value register, when LCR=0xBF and change to bank0 */
91 #define MOXA_MUST_XON1_REGISTER 0x04
92
93 /* set XON2 value register, when LCR=0xBF and change to bank0 */
94 #define MOXA_MUST_XON2_REGISTER 0x05
95
96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */
97 #define MOXA_MUST_XOFF1_REGISTER 0x06
98
99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */
100 #define MOXA_MUST_XOFF2_REGISTER 0x07
101
102 #define MOXA_MUST_RBRTL_REGISTER 0x04
103 #define MOXA_MUST_RBRTH_REGISTER 0x05
104 #define MOXA_MUST_RBRTI_REGISTER 0x06
105 #define MOXA_MUST_THRTL_REGISTER 0x07
106 #define MOXA_MUST_ENUM_REGISTER 0x04
107 #define MOXA_MUST_HWID_REGISTER 0x05
108 #define MOXA_MUST_ECR_REGISTER 0x06
109 #define MOXA_MUST_CSR_REGISTER 0x07
110
111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */
112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */
113
114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */
115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */
116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */
117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */
118
119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI)
120
121 /* GDA interrupt pending */
122 #define MOXA_MUST_IIR_GDA 0x1C
123 #define MOXA_MUST_IIR_RDA 0x04
124 #define MOXA_MUST_IIR_RTO 0x0C
125 #define MOXA_MUST_IIR_LSR 0x06
126
127 /* received Xon/Xoff or specical interrupt pending */
128 #define MOXA_MUST_IIR_XSC 0x10
129
130 /* RTS/CTS change state interrupt pending */
131 #define MOXA_MUST_IIR_RTSCTS 0x20
132 #define MOXA_MUST_IIR_MASK 0x3E
133
134 #define MOXA_MUST_MCR_XON_FLAG 0x40
135 #define MOXA_MUST_MCR_XON_ANY 0x80
136 #define MOXA_MUST_MCR_TX_XON 0x08
137
138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */
139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */
140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */
141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */
142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */
143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */
144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */
145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */
146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */
147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */
148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */
149
150 #define MXSERMAJOR 174
151
152 #define MXSER_BOARDS 4 /* Max. boards */
153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
155 #define MXSER_ISR_PASS_LIMIT 100
156
157 #define WAKEUP_CHARS 256
158
159 #define MXSER_BAUD_BASE 921600
160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16)
161
162 #define PCI_DEVICE_ID_POS104UL 0x1044
163 #define PCI_DEVICE_ID_CB108 0x1080
164 #define PCI_DEVICE_ID_CP102UF 0x1023
165 #define PCI_DEVICE_ID_CP112UL 0x1120
166 #define PCI_DEVICE_ID_CB114 0x1142
167 #define PCI_DEVICE_ID_CP114UL 0x1143
168 #define PCI_DEVICE_ID_CB134I 0x1341
169 #define PCI_DEVICE_ID_CP138U 0x1380
170
171 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU)
172 #define MXSER_HIGHBAUD 0x0100
173
174 enum mxser_must_hwid {
175 MOXA_OTHER_UART = 0x00,
176 MOXA_MUST_MU150_HWID = 0x01,
177 MOXA_MUST_MU860_HWID = 0x02,
178 };
179
180 static const struct {
181 u8 type;
182 u8 fifo_size;
183 u8 rx_high_water;
184 u8 rx_low_water;
185 speed_t max_baud;
186 } Gpci_uart_info[] = {
187 { MOXA_OTHER_UART, 16, 14, 1, 921600 },
188 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 },
189 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 }
190 };
191 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
192
193
194 /* driver_data correspond to the lines in the structure above
195 see also ISA probe function before you change something */
196 static const struct pci_device_id mxser_pcibrds[] = {
197 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 8 },
198 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
199 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 },
200 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 4 },
201 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 },
202 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 2 | MXSER_HIGHBAUD },
203 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 4 },
204 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 8 },
205 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 2 },
206 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 4 },
207 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 4 },
208 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 8 }, /* RC7000 */
209 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 8 },
210 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 2 },
211 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 2 },
212 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 8 },
213 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 8 },
214 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 4 },
215 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 8 },
216 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 4 },
217 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 4 },
218 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 8 },
219 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 4 },
220 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 4 },
221 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 2 },
222 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 2 },
223 { }
224 };
225 MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
226
227 static int ttymajor = MXSERMAJOR;
228
229 /* Variables for insmod */
230
231 MODULE_AUTHOR("Casper Yang");
232 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
233 module_param(ttymajor, int, 0);
234 MODULE_LICENSE("GPL");
235
236 struct mxser_board;
237
238 struct mxser_port {
239 struct tty_port port;
240 struct mxser_board *board;
241
242 unsigned long ioaddr;
243 unsigned long opmode_ioaddr;
244
245 u8 rx_high_water;
246 u8 rx_low_water;
247 int type; /* UART type */
248
249 unsigned char x_char; /* xon/xoff character */
250 u8 IER; /* Interrupt Enable Register */
251 u8 MCR; /* Modem control register */
252
253 unsigned char ldisc_stop_rx;
254
255 struct async_icount icount; /* kernel counters for 4 input interrupts */
256 unsigned int timeout;
257
258 u8 read_status_mask;
259 u8 ignore_status_mask;
260 u8 xmit_fifo_size;
261 unsigned int xmit_head;
262 unsigned int xmit_tail;
263 unsigned int xmit_cnt;
264
265 spinlock_t slock;
266 };
267
268 struct mxser_board {
269 unsigned int idx;
270 unsigned short nports;
271 int irq;
272 unsigned long vector;
273
274 enum mxser_must_hwid must_hwid;
275 speed_t max_baud;
276
277 struct mxser_port ports[];
278 };
279
280 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);
281 static struct tty_driver *mxvar_sdriver;
282
__mxser_must_set_EFR(unsigned long baseio,u8 clear,u8 set,bool restore_LCR)283 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set,
284 bool restore_LCR)
285 {
286 u8 oldlcr, efr;
287
288 oldlcr = inb(baseio + UART_LCR);
289 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR);
290
291 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
292 efr &= ~clear;
293 efr |= set;
294
295 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
296
297 if (restore_LCR)
298 outb(oldlcr, baseio + UART_LCR);
299
300 return oldlcr;
301 }
302
mxser_must_select_bank(unsigned long baseio,u8 bank)303 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank)
304 {
305 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank,
306 false);
307 }
308
mxser_set_must_xon1_value(unsigned long baseio,u8 value)309 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
310 {
311 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
312 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
313 outb(oldlcr, baseio + UART_LCR);
314 }
315
mxser_set_must_xoff1_value(unsigned long baseio,u8 value)316 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
317 {
318 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0);
319 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
320 outb(oldlcr, baseio + UART_LCR);
321 }
322
mxser_set_must_fifo_value(struct mxser_port * info)323 static void mxser_set_must_fifo_value(struct mxser_port *info)
324 {
325 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1);
326 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
327 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
328 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
329 outb(oldlcr, info->ioaddr + UART_LCR);
330 }
331
mxser_set_must_enum_value(unsigned long baseio,u8 value)332 static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
333 {
334 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
335 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
336 outb(oldlcr, baseio + UART_LCR);
337 }
338
mxser_get_must_hardware_id(unsigned long baseio)339 static u8 mxser_get_must_hardware_id(unsigned long baseio)
340 {
341 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2);
342 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER);
343 outb(oldlcr, baseio + UART_LCR);
344
345 return id;
346 }
347
mxser_must_set_EFR(unsigned long baseio,u8 clear,u8 set)348 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set)
349 {
350 __mxser_must_set_EFR(baseio, clear, set, true);
351 }
352
mxser_must_set_enhance_mode(unsigned long baseio,bool enable)353 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable)
354 {
355 mxser_must_set_EFR(baseio,
356 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE,
357 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0);
358 }
359
mxser_must_no_sw_flow_control(unsigned long baseio)360 static void mxser_must_no_sw_flow_control(unsigned long baseio)
361 {
362 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0);
363 }
364
mxser_must_set_tx_sw_flow_control(unsigned long baseio,bool enable)365 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable)
366 {
367 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK,
368 enable ? MOXA_MUST_EFR_SF_TX1 : 0);
369 }
370
mxser_must_set_rx_sw_flow_control(unsigned long baseio,bool enable)371 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable)
372 {
373 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK,
374 enable ? MOXA_MUST_EFR_SF_RX1 : 0);
375 }
376
mxser_must_get_hwid(unsigned long io)377 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
378 {
379 u8 oldmcr, hwid;
380 int i;
381
382 outb(0, io + UART_LCR);
383 mxser_must_set_enhance_mode(io, false);
384 oldmcr = inb(io + UART_MCR);
385 outb(0, io + UART_MCR);
386 mxser_set_must_xon1_value(io, 0x11);
387 if ((hwid = inb(io + UART_MCR)) != 0) {
388 outb(oldmcr, io + UART_MCR);
389 return MOXA_OTHER_UART;
390 }
391
392 hwid = mxser_get_must_hardware_id(io);
393 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */
394 if (hwid == Gpci_uart_info[i].type)
395 return hwid;
396
397 return MOXA_OTHER_UART;
398 }
399
mxser_16550A_or_MUST(struct mxser_port * info)400 static bool mxser_16550A_or_MUST(struct mxser_port *info)
401 {
402 return info->type == PORT_16550A || info->board->must_hwid;
403 }
404
mxser_process_txrx_fifo(struct mxser_port * info)405 static void mxser_process_txrx_fifo(struct mxser_port *info)
406 {
407 unsigned int i;
408
409 if (info->type == PORT_16450 || info->type == PORT_8250) {
410 info->rx_high_water = 1;
411 info->rx_low_water = 1;
412 info->xmit_fifo_size = 1;
413 return;
414 }
415
416 for (i = 0; i < UART_INFO_NUM; i++)
417 if (info->board->must_hwid == Gpci_uart_info[i].type) {
418 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
419 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
420 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
421 break;
422 }
423 }
424
__mxser_start_tx(struct mxser_port * info)425 static void __mxser_start_tx(struct mxser_port *info)
426 {
427 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
428 info->IER |= UART_IER_THRI;
429 outb(info->IER, info->ioaddr + UART_IER);
430 }
431
mxser_start_tx(struct mxser_port * info)432 static void mxser_start_tx(struct mxser_port *info)
433 {
434 unsigned long flags;
435
436 spin_lock_irqsave(&info->slock, flags);
437 __mxser_start_tx(info);
438 spin_unlock_irqrestore(&info->slock, flags);
439 }
440
__mxser_stop_tx(struct mxser_port * info)441 static void __mxser_stop_tx(struct mxser_port *info)
442 {
443 info->IER &= ~UART_IER_THRI;
444 outb(info->IER, info->ioaddr + UART_IER);
445 }
446
mxser_carrier_raised(struct tty_port * port)447 static int mxser_carrier_raised(struct tty_port *port)
448 {
449 struct mxser_port *mp = container_of(port, struct mxser_port, port);
450 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
451 }
452
mxser_dtr_rts(struct tty_port * port,int on)453 static void mxser_dtr_rts(struct tty_port *port, int on)
454 {
455 struct mxser_port *mp = container_of(port, struct mxser_port, port);
456 unsigned long flags;
457 u8 mcr;
458
459 spin_lock_irqsave(&mp->slock, flags);
460 mcr = inb(mp->ioaddr + UART_MCR);
461 if (on)
462 mcr |= UART_MCR_DTR | UART_MCR_RTS;
463 else
464 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS);
465 outb(mcr, mp->ioaddr + UART_MCR);
466 spin_unlock_irqrestore(&mp->slock, flags);
467 }
468
mxser_set_baud(struct tty_struct * tty,speed_t newspd)469 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd)
470 {
471 struct mxser_port *info = tty->driver_data;
472 unsigned int quot = 0, baud;
473 unsigned char cval;
474 u64 timeout;
475
476 if (newspd > info->board->max_baud)
477 return -1;
478
479 if (newspd == 134) {
480 quot = 2 * MXSER_BAUD_BASE / 269;
481 tty_encode_baud_rate(tty, 134, 134);
482 } else if (newspd) {
483 quot = MXSER_BAUD_BASE / newspd;
484 if (quot == 0)
485 quot = 1;
486 baud = MXSER_BAUD_BASE / quot;
487 tty_encode_baud_rate(tty, baud, baud);
488 } else {
489 quot = 0;
490 }
491
492 /*
493 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
494 * u64 domain
495 */
496 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
497 do_div(timeout, MXSER_BAUD_BASE);
498 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
499
500 if (quot) {
501 info->MCR |= UART_MCR_DTR;
502 outb(info->MCR, info->ioaddr + UART_MCR);
503 } else {
504 info->MCR &= ~UART_MCR_DTR;
505 outb(info->MCR, info->ioaddr + UART_MCR);
506 return 0;
507 }
508
509 cval = inb(info->ioaddr + UART_LCR);
510
511 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
512
513 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
514 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
515 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
516
517 #ifdef BOTHER
518 if (C_BAUD(tty) == BOTHER) {
519 quot = MXSER_BAUD_BASE % newspd;
520 quot *= 8;
521 if (quot % newspd > newspd / 2) {
522 quot /= newspd;
523 quot++;
524 } else
525 quot /= newspd;
526
527 mxser_set_must_enum_value(info->ioaddr, quot);
528 } else
529 #endif
530 mxser_set_must_enum_value(info->ioaddr, 0);
531
532 return 0;
533 }
534
mxser_handle_cts(struct tty_struct * tty,struct mxser_port * info,u8 msr)535 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info,
536 u8 msr)
537 {
538 bool cts = msr & UART_MSR_CTS;
539
540 if (tty->hw_stopped) {
541 if (cts) {
542 tty->hw_stopped = 0;
543
544 if (!mxser_16550A_or_MUST(info))
545 __mxser_start_tx(info);
546 tty_wakeup(tty);
547 }
548 return;
549 } else if (cts)
550 return;
551
552 tty->hw_stopped = 1;
553 if (!mxser_16550A_or_MUST(info))
554 __mxser_stop_tx(info);
555 }
556
557 /*
558 * This routine is called to set the UART divisor registers to match
559 * the specified baud rate for a serial port.
560 */
mxser_change_speed(struct tty_struct * tty)561 static void mxser_change_speed(struct tty_struct *tty)
562 {
563 struct mxser_port *info = tty->driver_data;
564 unsigned cflag, cval, fcr;
565
566 cflag = tty->termios.c_cflag;
567
568 mxser_set_baud(tty, tty_get_baud_rate(tty));
569
570 /* byte size and parity */
571 switch (cflag & CSIZE) {
572 default:
573 case CS5:
574 cval = UART_LCR_WLEN5;
575 break;
576 case CS6:
577 cval = UART_LCR_WLEN6;
578 break;
579 case CS7:
580 cval = UART_LCR_WLEN7;
581 break;
582 case CS8:
583 cval = UART_LCR_WLEN8;
584 break;
585 }
586
587 if (cflag & CSTOPB)
588 cval |= UART_LCR_STOP;
589 if (cflag & PARENB)
590 cval |= UART_LCR_PARITY;
591 if (!(cflag & PARODD))
592 cval |= UART_LCR_EPAR;
593 if (cflag & CMSPAR)
594 cval |= UART_LCR_SPAR;
595
596 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
597 if (info->board->must_hwid) {
598 fcr = UART_FCR_ENABLE_FIFO;
599 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
600 mxser_set_must_fifo_value(info);
601 } else
602 fcr = 0;
603 } else {
604 fcr = UART_FCR_ENABLE_FIFO;
605 if (info->board->must_hwid) {
606 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
607 mxser_set_must_fifo_value(info);
608 } else {
609 switch (info->rx_high_water) {
610 case 1:
611 fcr |= UART_FCR_TRIGGER_1;
612 break;
613 case 4:
614 fcr |= UART_FCR_TRIGGER_4;
615 break;
616 case 8:
617 fcr |= UART_FCR_TRIGGER_8;
618 break;
619 default:
620 fcr |= UART_FCR_TRIGGER_14;
621 break;
622 }
623 }
624 }
625
626 /* CTS flow control flag and modem status interrupts */
627 info->IER &= ~UART_IER_MSI;
628 info->MCR &= ~UART_MCR_AFE;
629 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
630 if (cflag & CRTSCTS) {
631 info->IER |= UART_IER_MSI;
632 if (mxser_16550A_or_MUST(info)) {
633 info->MCR |= UART_MCR_AFE;
634 } else {
635 mxser_handle_cts(tty, info,
636 inb(info->ioaddr + UART_MSR));
637 }
638 }
639 outb(info->MCR, info->ioaddr + UART_MCR);
640 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
641 if (~cflag & CLOCAL)
642 info->IER |= UART_IER_MSI;
643 outb(info->IER, info->ioaddr + UART_IER);
644
645 /*
646 * Set up parity check flag
647 */
648 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
649 if (I_INPCK(tty))
650 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
651 if (I_BRKINT(tty) || I_PARMRK(tty))
652 info->read_status_mask |= UART_LSR_BI;
653
654 info->ignore_status_mask = 0;
655
656 if (I_IGNBRK(tty)) {
657 info->ignore_status_mask |= UART_LSR_BI;
658 info->read_status_mask |= UART_LSR_BI;
659 /*
660 * If we're ignore parity and break indicators, ignore
661 * overruns too. (For real raw support).
662 */
663 if (I_IGNPAR(tty)) {
664 info->ignore_status_mask |=
665 UART_LSR_OE |
666 UART_LSR_PE |
667 UART_LSR_FE;
668 info->read_status_mask |=
669 UART_LSR_OE |
670 UART_LSR_PE |
671 UART_LSR_FE;
672 }
673 }
674 if (info->board->must_hwid) {
675 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
676 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
677 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty));
678 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty));
679 }
680
681
682 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
683 outb(cval, info->ioaddr + UART_LCR);
684 }
685
mxser_check_modem_status(struct tty_struct * tty,struct mxser_port * port,int status)686 static void mxser_check_modem_status(struct tty_struct *tty,
687 struct mxser_port *port, int status)
688 {
689 /* update input line counters */
690 if (status & UART_MSR_TERI)
691 port->icount.rng++;
692 if (status & UART_MSR_DDSR)
693 port->icount.dsr++;
694 if (status & UART_MSR_DDCD)
695 port->icount.dcd++;
696 if (status & UART_MSR_DCTS)
697 port->icount.cts++;
698 wake_up_interruptible(&port->port.delta_msr_wait);
699
700 if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) {
701 if (status & UART_MSR_DCD)
702 wake_up_interruptible(&port->port.open_wait);
703 }
704
705 if (tty_port_cts_enabled(&port->port))
706 mxser_handle_cts(tty, port, status);
707 }
708
mxser_activate(struct tty_port * port,struct tty_struct * tty)709 static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
710 {
711 struct mxser_port *info = container_of(port, struct mxser_port, port);
712 unsigned long page;
713 unsigned long flags;
714 int ret;
715
716 page = __get_free_page(GFP_KERNEL);
717 if (!page)
718 return -ENOMEM;
719
720 spin_lock_irqsave(&info->slock, flags);
721
722 if (!info->type) {
723 set_bit(TTY_IO_ERROR, &tty->flags);
724 spin_unlock_irqrestore(&info->slock, flags);
725 ret = 0;
726 goto err_free_xmit;
727 }
728 info->port.xmit_buf = (unsigned char *) page;
729
730 /*
731 * Clear the FIFO buffers and disable them
732 * (they will be reenabled in mxser_change_speed())
733 */
734 if (info->board->must_hwid)
735 outb((UART_FCR_CLEAR_RCVR |
736 UART_FCR_CLEAR_XMIT |
737 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
738 else
739 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
740 info->ioaddr + UART_FCR);
741
742 /*
743 * At this point there's no way the LSR could still be 0xFF;
744 * if it is, then bail out, because there's likely no UART
745 * here.
746 */
747 if (inb(info->ioaddr + UART_LSR) == 0xff) {
748 spin_unlock_irqrestore(&info->slock, flags);
749 if (capable(CAP_SYS_ADMIN)) {
750 set_bit(TTY_IO_ERROR, &tty->flags);
751 return 0;
752 }
753
754 ret = -ENODEV;
755 goto err_free_xmit;
756 }
757
758 /*
759 * Clear the interrupt registers.
760 */
761 (void) inb(info->ioaddr + UART_LSR);
762 (void) inb(info->ioaddr + UART_RX);
763 (void) inb(info->ioaddr + UART_IIR);
764 (void) inb(info->ioaddr + UART_MSR);
765
766 /*
767 * Now, initialize the UART
768 */
769 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
770 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
771 outb(info->MCR, info->ioaddr + UART_MCR);
772
773 /*
774 * Finally, enable interrupts
775 */
776 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
777
778 if (info->board->must_hwid)
779 info->IER |= MOXA_MUST_IER_EGDAI;
780 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
781
782 /*
783 * And clear the interrupt registers again for luck.
784 */
785 (void) inb(info->ioaddr + UART_LSR);
786 (void) inb(info->ioaddr + UART_RX);
787 (void) inb(info->ioaddr + UART_IIR);
788 (void) inb(info->ioaddr + UART_MSR);
789
790 clear_bit(TTY_IO_ERROR, &tty->flags);
791 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
792
793 /*
794 * and set the speed of the serial port
795 */
796 mxser_change_speed(tty);
797 spin_unlock_irqrestore(&info->slock, flags);
798
799 return 0;
800 err_free_xmit:
801 free_page(page);
802 info->port.xmit_buf = NULL;
803 return ret;
804 }
805
806 /*
807 * This routine will shutdown a serial port
808 */
mxser_shutdown_port(struct tty_port * port)809 static void mxser_shutdown_port(struct tty_port *port)
810 {
811 struct mxser_port *info = container_of(port, struct mxser_port, port);
812 unsigned long flags;
813
814 spin_lock_irqsave(&info->slock, flags);
815
816 /*
817 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
818 * here so the queue might never be waken up
819 */
820 wake_up_interruptible(&info->port.delta_msr_wait);
821
822 /*
823 * Free the xmit buffer, if necessary
824 */
825 if (info->port.xmit_buf) {
826 free_page((unsigned long) info->port.xmit_buf);
827 info->port.xmit_buf = NULL;
828 }
829
830 info->IER = 0;
831 outb(0x00, info->ioaddr + UART_IER);
832
833 /* clear Rx/Tx FIFO's */
834 if (info->board->must_hwid)
835 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
836 MOXA_MUST_FCR_GDA_MODE_ENABLE,
837 info->ioaddr + UART_FCR);
838 else
839 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
840 info->ioaddr + UART_FCR);
841
842 /* read data port to reset things */
843 (void) inb(info->ioaddr + UART_RX);
844
845
846 if (info->board->must_hwid)
847 mxser_must_no_sw_flow_control(info->ioaddr);
848
849 spin_unlock_irqrestore(&info->slock, flags);
850 }
851
852 /*
853 * This routine is called whenever a serial port is opened. It
854 * enables interrupts for a serial port, linking in its async structure into
855 * the IRQ chain. It also performs the serial-specific
856 * initialization for the tty structure.
857 */
mxser_open(struct tty_struct * tty,struct file * filp)858 static int mxser_open(struct tty_struct *tty, struct file *filp)
859 {
860 struct tty_port *tport = tty->port;
861 struct mxser_port *port = container_of(tport, struct mxser_port, port);
862
863 tty->driver_data = port;
864
865 return tty_port_open(tport, tty, filp);
866 }
867
mxser_flush_buffer(struct tty_struct * tty)868 static void mxser_flush_buffer(struct tty_struct *tty)
869 {
870 struct mxser_port *info = tty->driver_data;
871 char fcr;
872 unsigned long flags;
873
874
875 spin_lock_irqsave(&info->slock, flags);
876 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
877
878 fcr = inb(info->ioaddr + UART_FCR);
879 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
880 info->ioaddr + UART_FCR);
881 outb(fcr, info->ioaddr + UART_FCR);
882
883 spin_unlock_irqrestore(&info->slock, flags);
884
885 tty_wakeup(tty);
886 }
887
888
mxser_close_port(struct tty_port * port)889 static void mxser_close_port(struct tty_port *port)
890 {
891 struct mxser_port *info = container_of(port, struct mxser_port, port);
892 unsigned long timeout;
893 /*
894 * At this point we stop accepting input. To do this, we
895 * disable the receive line status interrupts, and tell the
896 * interrupt driver to stop checking the data ready bit in the
897 * line status register.
898 */
899 info->IER &= ~UART_IER_RLSI;
900 if (info->board->must_hwid)
901 info->IER &= ~MOXA_MUST_RECV_ISR;
902
903 outb(info->IER, info->ioaddr + UART_IER);
904 /*
905 * Before we drop DTR, make sure the UART transmitter
906 * has completely drained; this is especially
907 * important if there is a transmit FIFO!
908 */
909 timeout = jiffies + HZ;
910 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
911 schedule_timeout_interruptible(5);
912 if (time_after(jiffies, timeout))
913 break;
914 }
915 }
916
917 /*
918 * This routine is called when the serial port gets closed. First, we
919 * wait for the last remaining data to be sent. Then, we unlink its
920 * async structure from the interrupt chain if necessary, and we free
921 * that IRQ if nothing is left in the chain.
922 */
mxser_close(struct tty_struct * tty,struct file * filp)923 static void mxser_close(struct tty_struct *tty, struct file *filp)
924 {
925 struct mxser_port *info = tty->driver_data;
926 struct tty_port *port = &info->port;
927
928 if (info == NULL)
929 return;
930 if (tty_port_close_start(port, tty, filp) == 0)
931 return;
932 mutex_lock(&port->mutex);
933 mxser_close_port(port);
934 mxser_flush_buffer(tty);
935 if (tty_port_initialized(port) && C_HUPCL(tty))
936 tty_port_lower_dtr_rts(port);
937 mxser_shutdown_port(port);
938 tty_port_set_initialized(port, 0);
939 mutex_unlock(&port->mutex);
940 /* Right now the tty_port set is done outside of the close_end helper
941 as we don't yet have everyone using refcounts */
942 tty_port_close_end(port, tty);
943 tty_port_tty_set(port, NULL);
944 }
945
mxser_write(struct tty_struct * tty,const unsigned char * buf,int count)946 static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
947 {
948 int c, total = 0;
949 struct mxser_port *info = tty->driver_data;
950 unsigned long flags;
951
952 if (!info->port.xmit_buf)
953 return 0;
954
955 while (1) {
956 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
957 SERIAL_XMIT_SIZE - info->xmit_head));
958 if (c <= 0)
959 break;
960
961 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
962 spin_lock_irqsave(&info->slock, flags);
963 info->xmit_head = (info->xmit_head + c) &
964 (SERIAL_XMIT_SIZE - 1);
965 info->xmit_cnt += c;
966 spin_unlock_irqrestore(&info->slock, flags);
967
968 buf += c;
969 count -= c;
970 total += c;
971 }
972
973 if (info->xmit_cnt && !tty->flow.stopped)
974 if (!tty->hw_stopped || mxser_16550A_or_MUST(info))
975 mxser_start_tx(info);
976
977 return total;
978 }
979
mxser_put_char(struct tty_struct * tty,unsigned char ch)980 static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
981 {
982 struct mxser_port *info = tty->driver_data;
983 unsigned long flags;
984
985 if (!info->port.xmit_buf)
986 return 0;
987
988 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
989 return 0;
990
991 spin_lock_irqsave(&info->slock, flags);
992 info->port.xmit_buf[info->xmit_head++] = ch;
993 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
994 info->xmit_cnt++;
995 spin_unlock_irqrestore(&info->slock, flags);
996
997 return 1;
998 }
999
1000
mxser_flush_chars(struct tty_struct * tty)1001 static void mxser_flush_chars(struct tty_struct *tty)
1002 {
1003 struct mxser_port *info = tty->driver_data;
1004
1005 if (!info->xmit_cnt || tty->flow.stopped || !info->port.xmit_buf ||
1006 (tty->hw_stopped && !mxser_16550A_or_MUST(info)))
1007 return;
1008
1009 mxser_start_tx(info);
1010 }
1011
mxser_write_room(struct tty_struct * tty)1012 static unsigned int mxser_write_room(struct tty_struct *tty)
1013 {
1014 struct mxser_port *info = tty->driver_data;
1015 int ret;
1016
1017 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
1018 return ret < 0 ? 0 : ret;
1019 }
1020
mxser_chars_in_buffer(struct tty_struct * tty)1021 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty)
1022 {
1023 struct mxser_port *info = tty->driver_data;
1024 return info->xmit_cnt;
1025 }
1026
1027 /*
1028 * ------------------------------------------------------------
1029 * friends of mxser_ioctl()
1030 * ------------------------------------------------------------
1031 */
mxser_get_serial_info(struct tty_struct * tty,struct serial_struct * ss)1032 static int mxser_get_serial_info(struct tty_struct *tty,
1033 struct serial_struct *ss)
1034 {
1035 struct mxser_port *info = tty->driver_data;
1036 struct tty_port *port = &info->port;
1037 unsigned int closing_wait, close_delay;
1038
1039 mutex_lock(&port->mutex);
1040
1041 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
1042 closing_wait = info->port.closing_wait;
1043 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1044 closing_wait = jiffies_to_msecs(closing_wait) / 10;
1045
1046 ss->type = info->type;
1047 ss->line = tty->index;
1048 ss->port = info->ioaddr;
1049 ss->irq = info->board->irq;
1050 ss->flags = info->port.flags;
1051 ss->baud_base = MXSER_BAUD_BASE;
1052 ss->close_delay = close_delay;
1053 ss->closing_wait = closing_wait;
1054 ss->custom_divisor = MXSER_CUSTOM_DIVISOR,
1055 mutex_unlock(&port->mutex);
1056 return 0;
1057 }
1058
mxser_set_serial_info(struct tty_struct * tty,struct serial_struct * ss)1059 static int mxser_set_serial_info(struct tty_struct *tty,
1060 struct serial_struct *ss)
1061 {
1062 struct mxser_port *info = tty->driver_data;
1063 struct tty_port *port = &info->port;
1064 speed_t baud;
1065 unsigned long sl_flags;
1066 unsigned int old_speed, close_delay, closing_wait;
1067 int retval = 0;
1068
1069 if (tty_io_error(tty))
1070 return -EIO;
1071
1072 mutex_lock(&port->mutex);
1073
1074 if (ss->irq != info->board->irq ||
1075 ss->port != info->ioaddr) {
1076 mutex_unlock(&port->mutex);
1077 return -EINVAL;
1078 }
1079
1080 old_speed = port->flags & ASYNC_SPD_MASK;
1081
1082 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1083 closing_wait = ss->closing_wait;
1084 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1085 closing_wait = msecs_to_jiffies(closing_wait * 10);
1086
1087 if (!capable(CAP_SYS_ADMIN)) {
1088 if ((ss->baud_base != MXSER_BAUD_BASE) ||
1089 (close_delay != port->close_delay) ||
1090 (closing_wait != port->closing_wait) ||
1091 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) {
1092 mutex_unlock(&port->mutex);
1093 return -EPERM;
1094 }
1095 port->flags = (port->flags & ~ASYNC_USR_MASK) |
1096 (ss->flags & ASYNC_USR_MASK);
1097 } else {
1098 /*
1099 * OK, past this point, all the error checking has been done.
1100 * At this point, we start making changes.....
1101 */
1102 port->flags = ((port->flags & ~ASYNC_FLAGS) |
1103 (ss->flags & ASYNC_FLAGS));
1104 port->close_delay = close_delay;
1105 port->closing_wait = closing_wait;
1106 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
1107 (ss->baud_base != MXSER_BAUD_BASE ||
1108 ss->custom_divisor !=
1109 MXSER_CUSTOM_DIVISOR)) {
1110 if (ss->custom_divisor == 0) {
1111 mutex_unlock(&port->mutex);
1112 return -EINVAL;
1113 }
1114 baud = ss->baud_base / ss->custom_divisor;
1115 tty_encode_baud_rate(tty, baud, baud);
1116 }
1117
1118 info->type = ss->type;
1119
1120 mxser_process_txrx_fifo(info);
1121 }
1122
1123 if (tty_port_initialized(port)) {
1124 if (old_speed != (port->flags & ASYNC_SPD_MASK)) {
1125 spin_lock_irqsave(&info->slock, sl_flags);
1126 mxser_change_speed(tty);
1127 spin_unlock_irqrestore(&info->slock, sl_flags);
1128 }
1129 } else {
1130 retval = mxser_activate(port, tty);
1131 if (retval == 0)
1132 tty_port_set_initialized(port, 1);
1133 }
1134 mutex_unlock(&port->mutex);
1135 return retval;
1136 }
1137
1138 /*
1139 * mxser_get_lsr_info - get line status register info
1140 *
1141 * Purpose: Let user call ioctl() to get info when the UART physically
1142 * is emptied. On bus types like RS485, the transmitter must
1143 * release the bus after transmitting. This must be done when
1144 * the transmit shift register is empty, not be done when the
1145 * transmit holding register is empty. This functionality
1146 * allows an RS485 driver to be written in user space.
1147 */
mxser_get_lsr_info(struct mxser_port * info,unsigned int __user * value)1148 static int mxser_get_lsr_info(struct mxser_port *info,
1149 unsigned int __user *value)
1150 {
1151 unsigned char status;
1152 unsigned int result;
1153 unsigned long flags;
1154
1155 spin_lock_irqsave(&info->slock, flags);
1156 status = inb(info->ioaddr + UART_LSR);
1157 spin_unlock_irqrestore(&info->slock, flags);
1158 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1159 return put_user(result, value);
1160 }
1161
mxser_tiocmget(struct tty_struct * tty)1162 static int mxser_tiocmget(struct tty_struct *tty)
1163 {
1164 struct mxser_port *info = tty->driver_data;
1165 unsigned char control, status;
1166 unsigned long flags;
1167
1168 if (tty_io_error(tty))
1169 return -EIO;
1170
1171 spin_lock_irqsave(&info->slock, flags);
1172 control = info->MCR;
1173 status = inb(info->ioaddr + UART_MSR);
1174 if (status & UART_MSR_ANY_DELTA)
1175 mxser_check_modem_status(tty, info, status);
1176 spin_unlock_irqrestore(&info->slock, flags);
1177
1178 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1179 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1180 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1181 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1182 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1183 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1184 }
1185
mxser_tiocmset(struct tty_struct * tty,unsigned int set,unsigned int clear)1186 static int mxser_tiocmset(struct tty_struct *tty,
1187 unsigned int set, unsigned int clear)
1188 {
1189 struct mxser_port *info = tty->driver_data;
1190 unsigned long flags;
1191
1192 if (tty_io_error(tty))
1193 return -EIO;
1194
1195 spin_lock_irqsave(&info->slock, flags);
1196
1197 if (set & TIOCM_RTS)
1198 info->MCR |= UART_MCR_RTS;
1199 if (set & TIOCM_DTR)
1200 info->MCR |= UART_MCR_DTR;
1201
1202 if (clear & TIOCM_RTS)
1203 info->MCR &= ~UART_MCR_RTS;
1204 if (clear & TIOCM_DTR)
1205 info->MCR &= ~UART_MCR_DTR;
1206
1207 outb(info->MCR, info->ioaddr + UART_MCR);
1208 spin_unlock_irqrestore(&info->slock, flags);
1209 return 0;
1210 }
1211
mxser_cflags_changed(struct mxser_port * info,unsigned long arg,struct async_icount * cprev)1212 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1213 struct async_icount *cprev)
1214 {
1215 struct async_icount cnow;
1216 unsigned long flags;
1217 int ret;
1218
1219 spin_lock_irqsave(&info->slock, flags);
1220 cnow = info->icount; /* atomic copy */
1221 spin_unlock_irqrestore(&info->slock, flags);
1222
1223 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1224 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1225 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1226 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1227
1228 *cprev = cnow;
1229
1230 return ret;
1231 }
1232
1233 /* We should likely switch to TIOCGRS485/TIOCSRS485. */
mxser_ioctl_op_mode(struct mxser_port * port,int index,bool set,int __user * u_opmode)1234 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set,
1235 int __user *u_opmode)
1236 {
1237 int opmode, p = index % 4;
1238 int shiftbit = p * 2;
1239 u8 val;
1240
1241 if (port->board->must_hwid != MOXA_MUST_MU860_HWID)
1242 return -EFAULT;
1243
1244 if (set) {
1245 if (get_user(opmode, u_opmode))
1246 return -EFAULT;
1247
1248 if (opmode & ~OP_MODE_MASK)
1249 return -EINVAL;
1250
1251 spin_lock_irq(&port->slock);
1252 val = inb(port->opmode_ioaddr);
1253 val &= ~(OP_MODE_MASK << shiftbit);
1254 val |= (opmode << shiftbit);
1255 outb(val, port->opmode_ioaddr);
1256 spin_unlock_irq(&port->slock);
1257
1258 return 0;
1259 }
1260
1261 spin_lock_irq(&port->slock);
1262 opmode = inb(port->opmode_ioaddr) >> shiftbit;
1263 spin_unlock_irq(&port->slock);
1264
1265 return put_user(opmode & OP_MODE_MASK, u_opmode);
1266 }
1267
mxser_ioctl(struct tty_struct * tty,unsigned int cmd,unsigned long arg)1268 static int mxser_ioctl(struct tty_struct *tty,
1269 unsigned int cmd, unsigned long arg)
1270 {
1271 struct mxser_port *info = tty->driver_data;
1272 struct async_icount cnow;
1273 unsigned long flags;
1274 void __user *argp = (void __user *)arg;
1275
1276 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE)
1277 return mxser_ioctl_op_mode(info, tty->index,
1278 cmd == MOXA_SET_OP_MODE, argp);
1279
1280 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1281 return -EIO;
1282
1283 switch (cmd) {
1284 case TIOCSERGETLSR: /* Get line status register */
1285 return mxser_get_lsr_info(info, argp);
1286 /*
1287 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1288 * - mask passed in arg for lines of interest
1289 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1290 * Caller should use TIOCGICOUNT to see which one it was
1291 */
1292 case TIOCMIWAIT:
1293 spin_lock_irqsave(&info->slock, flags);
1294 cnow = info->icount; /* note the counters on entry */
1295 spin_unlock_irqrestore(&info->slock, flags);
1296
1297 return wait_event_interruptible(info->port.delta_msr_wait,
1298 mxser_cflags_changed(info, arg, &cnow));
1299 default:
1300 return -ENOIOCTLCMD;
1301 }
1302 return 0;
1303 }
1304
1305 /*
1306 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1307 * Return: write counters to the user passed counter struct
1308 * NB: both 1->0 and 0->1 transitions are counted except for
1309 * RI where only 0->1 is counted.
1310 */
1311
mxser_get_icount(struct tty_struct * tty,struct serial_icounter_struct * icount)1312 static int mxser_get_icount(struct tty_struct *tty,
1313 struct serial_icounter_struct *icount)
1314
1315 {
1316 struct mxser_port *info = tty->driver_data;
1317 struct async_icount cnow;
1318 unsigned long flags;
1319
1320 spin_lock_irqsave(&info->slock, flags);
1321 cnow = info->icount;
1322 spin_unlock_irqrestore(&info->slock, flags);
1323
1324 icount->frame = cnow.frame;
1325 icount->brk = cnow.brk;
1326 icount->overrun = cnow.overrun;
1327 icount->buf_overrun = cnow.buf_overrun;
1328 icount->parity = cnow.parity;
1329 icount->rx = cnow.rx;
1330 icount->tx = cnow.tx;
1331 icount->cts = cnow.cts;
1332 icount->dsr = cnow.dsr;
1333 icount->rng = cnow.rng;
1334 icount->dcd = cnow.dcd;
1335 return 0;
1336 }
1337
mxser_stoprx(struct tty_struct * tty)1338 static void mxser_stoprx(struct tty_struct *tty)
1339 {
1340 struct mxser_port *info = tty->driver_data;
1341
1342 info->ldisc_stop_rx = 1;
1343 if (I_IXOFF(tty)) {
1344 if (info->board->must_hwid) {
1345 info->IER &= ~MOXA_MUST_RECV_ISR;
1346 outb(info->IER, info->ioaddr + UART_IER);
1347 } else {
1348 info->x_char = STOP_CHAR(tty);
1349 outb(0, info->ioaddr + UART_IER);
1350 info->IER |= UART_IER_THRI;
1351 outb(info->IER, info->ioaddr + UART_IER);
1352 }
1353 }
1354
1355 if (C_CRTSCTS(tty)) {
1356 info->MCR &= ~UART_MCR_RTS;
1357 outb(info->MCR, info->ioaddr + UART_MCR);
1358 }
1359 }
1360
1361 /*
1362 * This routine is called by the upper-layer tty layer to signal that
1363 * incoming characters should be throttled.
1364 */
mxser_throttle(struct tty_struct * tty)1365 static void mxser_throttle(struct tty_struct *tty)
1366 {
1367 mxser_stoprx(tty);
1368 }
1369
mxser_unthrottle(struct tty_struct * tty)1370 static void mxser_unthrottle(struct tty_struct *tty)
1371 {
1372 struct mxser_port *info = tty->driver_data;
1373
1374 /* startrx */
1375 info->ldisc_stop_rx = 0;
1376 if (I_IXOFF(tty)) {
1377 if (info->x_char)
1378 info->x_char = 0;
1379 else {
1380 if (info->board->must_hwid) {
1381 info->IER |= MOXA_MUST_RECV_ISR;
1382 outb(info->IER, info->ioaddr + UART_IER);
1383 } else {
1384 info->x_char = START_CHAR(tty);
1385 outb(0, info->ioaddr + UART_IER);
1386 info->IER |= UART_IER_THRI;
1387 outb(info->IER, info->ioaddr + UART_IER);
1388 }
1389 }
1390 }
1391
1392 if (C_CRTSCTS(tty)) {
1393 info->MCR |= UART_MCR_RTS;
1394 outb(info->MCR, info->ioaddr + UART_MCR);
1395 }
1396 }
1397
1398 /*
1399 * mxser_stop() and mxser_start()
1400 *
1401 * This routines are called before setting or resetting tty->flow.stopped.
1402 * They enable or disable transmitter interrupts, as necessary.
1403 */
mxser_stop(struct tty_struct * tty)1404 static void mxser_stop(struct tty_struct *tty)
1405 {
1406 struct mxser_port *info = tty->driver_data;
1407 unsigned long flags;
1408
1409 spin_lock_irqsave(&info->slock, flags);
1410 if (info->IER & UART_IER_THRI)
1411 __mxser_stop_tx(info);
1412 spin_unlock_irqrestore(&info->slock, flags);
1413 }
1414
mxser_start(struct tty_struct * tty)1415 static void mxser_start(struct tty_struct *tty)
1416 {
1417 struct mxser_port *info = tty->driver_data;
1418 unsigned long flags;
1419
1420 spin_lock_irqsave(&info->slock, flags);
1421 if (info->xmit_cnt && info->port.xmit_buf)
1422 __mxser_start_tx(info);
1423 spin_unlock_irqrestore(&info->slock, flags);
1424 }
1425
mxser_set_termios(struct tty_struct * tty,struct ktermios * old_termios)1426 static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1427 {
1428 struct mxser_port *info = tty->driver_data;
1429 unsigned long flags;
1430
1431 spin_lock_irqsave(&info->slock, flags);
1432 mxser_change_speed(tty);
1433 spin_unlock_irqrestore(&info->slock, flags);
1434
1435 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1436 tty->hw_stopped = 0;
1437 mxser_start(tty);
1438 }
1439
1440 /* Handle sw stopped */
1441 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1442 tty->flow.stopped = 0;
1443
1444 if (info->board->must_hwid) {
1445 spin_lock_irqsave(&info->slock, flags);
1446 mxser_must_set_rx_sw_flow_control(info->ioaddr, false);
1447 spin_unlock_irqrestore(&info->slock, flags);
1448 }
1449
1450 mxser_start(tty);
1451 }
1452 }
1453
1454 /*
1455 * mxser_wait_until_sent() --- wait until the transmitter is empty
1456 */
mxser_wait_until_sent(struct tty_struct * tty,int timeout)1457 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1458 {
1459 struct mxser_port *info = tty->driver_data;
1460 unsigned long orig_jiffies, char_time;
1461 unsigned long flags;
1462 int lsr;
1463
1464 if (info->type == PORT_UNKNOWN)
1465 return;
1466
1467 if (info->xmit_fifo_size == 0)
1468 return; /* Just in case.... */
1469
1470 orig_jiffies = jiffies;
1471 /*
1472 * Set the check interval to be 1/5 of the estimated time to
1473 * send a single character, and make it at least 1. The check
1474 * interval should also be less than the timeout.
1475 *
1476 * Note: we have to use pretty tight timings here to satisfy
1477 * the NIST-PCTS.
1478 */
1479 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
1480 char_time = char_time / 5;
1481 if (char_time == 0)
1482 char_time = 1;
1483 if (timeout && timeout < char_time)
1484 char_time = timeout;
1485 /*
1486 * If the transmitter hasn't cleared in twice the approximate
1487 * amount of time to send the entire FIFO, it probably won't
1488 * ever clear. This assumes the UART isn't doing flow
1489 * control, which is currently the case. Hence, if it ever
1490 * takes longer than info->timeout, this is probably due to a
1491 * UART bug of some kind. So, we clamp the timeout parameter at
1492 * 2*info->timeout.
1493 */
1494 if (!timeout || timeout > 2 * info->timeout)
1495 timeout = 2 * info->timeout;
1496
1497 spin_lock_irqsave(&info->slock, flags);
1498 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
1499 spin_unlock_irqrestore(&info->slock, flags);
1500 schedule_timeout_interruptible(char_time);
1501 spin_lock_irqsave(&info->slock, flags);
1502 if (signal_pending(current))
1503 break;
1504 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1505 break;
1506 }
1507 spin_unlock_irqrestore(&info->slock, flags);
1508 set_current_state(TASK_RUNNING);
1509 }
1510
1511 /*
1512 * This routine is called by tty_hangup() when a hangup is signaled.
1513 */
mxser_hangup(struct tty_struct * tty)1514 static void mxser_hangup(struct tty_struct *tty)
1515 {
1516 struct mxser_port *info = tty->driver_data;
1517
1518 mxser_flush_buffer(tty);
1519 tty_port_hangup(&info->port);
1520 }
1521
1522 /*
1523 * mxser_rs_break() --- routine which turns the break handling on or off
1524 */
mxser_rs_break(struct tty_struct * tty,int break_state)1525 static int mxser_rs_break(struct tty_struct *tty, int break_state)
1526 {
1527 struct mxser_port *info = tty->driver_data;
1528 unsigned long flags;
1529 u8 lcr;
1530
1531 spin_lock_irqsave(&info->slock, flags);
1532 lcr = inb(info->ioaddr + UART_LCR);
1533 if (break_state == -1)
1534 lcr |= UART_LCR_SBC;
1535 else
1536 lcr &= ~UART_LCR_SBC;
1537 outb(lcr, info->ioaddr + UART_LCR);
1538 spin_unlock_irqrestore(&info->slock, flags);
1539
1540 return 0;
1541 }
1542
mxser_receive_chars_new(struct tty_struct * tty,struct mxser_port * port,u8 status)1543 static bool mxser_receive_chars_new(struct tty_struct *tty,
1544 struct mxser_port *port, u8 status)
1545 {
1546 enum mxser_must_hwid hwid = port->board->must_hwid;
1547 u8 gdl;
1548
1549 if (hwid == MOXA_OTHER_UART)
1550 return false;
1551 if (status & UART_LSR_BRK_ERROR_BITS)
1552 return false;
1553 if (hwid == MOXA_MUST_MU860_HWID && (status & MOXA_MUST_LSR_RERR))
1554 return false;
1555 if (status & MOXA_MUST_LSR_RERR)
1556 return false;
1557
1558 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
1559 if (hwid == MOXA_MUST_MU150_HWID)
1560 gdl &= MOXA_MUST_GDL_MASK;
1561
1562 if (gdl >= tty->receive_room && !port->ldisc_stop_rx)
1563 mxser_stoprx(tty);
1564
1565 while (gdl--) {
1566 u8 ch = inb(port->ioaddr + UART_RX);
1567 tty_insert_flip_char(&port->port, ch, 0);
1568 }
1569
1570 return true;
1571 }
1572
mxser_receive_chars_old(struct tty_struct * tty,struct mxser_port * port,u8 status)1573 static u8 mxser_receive_chars_old(struct tty_struct *tty,
1574 struct mxser_port *port, u8 status)
1575 {
1576 enum mxser_must_hwid hwid = port->board->must_hwid;
1577 int recv_room = tty->receive_room;
1578 int ignored = 0;
1579 int max = 256;
1580 int cnt = 0;
1581 u8 ch;
1582
1583 do {
1584 if (max-- < 0)
1585 break;
1586
1587 ch = inb(port->ioaddr + UART_RX);
1588 if (hwid && (status & UART_LSR_OE))
1589 outb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
1590 MOXA_MUST_FCR_GDA_MODE_ENABLE,
1591 port->ioaddr + UART_FCR);
1592 status &= port->read_status_mask;
1593 if (status & port->ignore_status_mask) {
1594 if (++ignored > 100)
1595 break;
1596 } else {
1597 char flag = 0;
1598 if (status & UART_LSR_BRK_ERROR_BITS) {
1599 if (status & UART_LSR_BI) {
1600 flag = TTY_BREAK;
1601 port->icount.brk++;
1602
1603 if (port->port.flags & ASYNC_SAK)
1604 do_SAK(tty);
1605 } else if (status & UART_LSR_PE) {
1606 flag = TTY_PARITY;
1607 port->icount.parity++;
1608 } else if (status & UART_LSR_FE) {
1609 flag = TTY_FRAME;
1610 port->icount.frame++;
1611 } else if (status & UART_LSR_OE) {
1612 flag = TTY_OVERRUN;
1613 port->icount.overrun++;
1614 }
1615 }
1616 tty_insert_flip_char(&port->port, ch, flag);
1617 cnt++;
1618 if (cnt >= recv_room) {
1619 if (!port->ldisc_stop_rx)
1620 mxser_stoprx(tty);
1621 break;
1622 }
1623
1624 }
1625
1626 if (hwid)
1627 break;
1628
1629 status = inb(port->ioaddr + UART_LSR);
1630 } while (status & UART_LSR_DR);
1631
1632 return status;
1633 }
1634
mxser_receive_chars(struct tty_struct * tty,struct mxser_port * port,u8 status)1635 static u8 mxser_receive_chars(struct tty_struct *tty,
1636 struct mxser_port *port, u8 status)
1637 {
1638 if (tty->receive_room == 0 && !port->ldisc_stop_rx)
1639 mxser_stoprx(tty);
1640
1641 if (!mxser_receive_chars_new(tty, port, status))
1642 status = mxser_receive_chars_old(tty, port, status);
1643
1644 tty_flip_buffer_push(&port->port);
1645
1646 return status;
1647 }
1648
mxser_transmit_chars(struct tty_struct * tty,struct mxser_port * port)1649 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1650 {
1651 int count, cnt;
1652
1653 if (port->x_char) {
1654 outb(port->x_char, port->ioaddr + UART_TX);
1655 port->x_char = 0;
1656 port->icount.tx++;
1657 return;
1658 }
1659
1660 if (port->port.xmit_buf == NULL)
1661 return;
1662
1663 if (!port->xmit_cnt || tty->flow.stopped ||
1664 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) {
1665 __mxser_stop_tx(port);
1666 return;
1667 }
1668
1669 cnt = port->xmit_cnt;
1670 count = port->xmit_fifo_size;
1671 do {
1672 outb(port->port.xmit_buf[port->xmit_tail++],
1673 port->ioaddr + UART_TX);
1674 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
1675 if (!--port->xmit_cnt)
1676 break;
1677 } while (--count > 0);
1678
1679 port->icount.tx += (cnt - port->xmit_cnt);
1680
1681 if (port->xmit_cnt < WAKEUP_CHARS)
1682 tty_wakeup(tty);
1683
1684 if (!port->xmit_cnt)
1685 __mxser_stop_tx(port);
1686 }
1687
mxser_port_isr(struct mxser_port * port)1688 static bool mxser_port_isr(struct mxser_port *port)
1689 {
1690 struct tty_struct *tty;
1691 u8 iir, msr, status;
1692 bool error = false;
1693
1694 iir = inb(port->ioaddr + UART_IIR);
1695 if (iir & UART_IIR_NO_INT)
1696 return true;
1697
1698 iir &= MOXA_MUST_IIR_MASK;
1699 tty = tty_port_tty_get(&port->port);
1700 if (!tty) {
1701 status = inb(port->ioaddr + UART_LSR);
1702 outb(MOXA_MUST_FCR_GDA_MODE_ENABLE | UART_FCR_ENABLE_FIFO |
1703 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
1704 port->ioaddr + UART_FCR);
1705 inb(port->ioaddr + UART_MSR);
1706
1707 error = true;
1708 goto put_tty;
1709 }
1710
1711 status = inb(port->ioaddr + UART_LSR);
1712
1713 if (port->board->must_hwid) {
1714 if (iir == MOXA_MUST_IIR_GDA ||
1715 iir == MOXA_MUST_IIR_RDA ||
1716 iir == MOXA_MUST_IIR_RTO ||
1717 iir == MOXA_MUST_IIR_LSR)
1718 status = mxser_receive_chars(tty, port, status);
1719 } else {
1720 status &= port->read_status_mask;
1721 if (status & UART_LSR_DR)
1722 status = mxser_receive_chars(tty, port, status);
1723 }
1724
1725 msr = inb(port->ioaddr + UART_MSR);
1726 if (msr & UART_MSR_ANY_DELTA)
1727 mxser_check_modem_status(tty, port, msr);
1728
1729 if (port->board->must_hwid) {
1730 if (iir == 0x02 && (status & UART_LSR_THRE))
1731 mxser_transmit_chars(tty, port);
1732 } else {
1733 if (status & UART_LSR_THRE)
1734 mxser_transmit_chars(tty, port);
1735 }
1736
1737 put_tty:
1738 tty_kref_put(tty);
1739
1740 return error;
1741 }
1742
1743 /*
1744 * This is the serial driver's generic interrupt routine
1745 */
mxser_interrupt(int irq,void * dev_id)1746 static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1747 {
1748 struct mxser_board *brd = dev_id;
1749 struct mxser_port *port;
1750 unsigned int int_cnt, pass_counter = 0;
1751 unsigned int i, max = brd->nports;
1752 int handled = IRQ_NONE;
1753 u8 irqbits, bits, mask = BIT(max) - 1;
1754
1755 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
1756 irqbits = inb(brd->vector) & mask;
1757 if (irqbits == mask)
1758 break;
1759
1760 handled = IRQ_HANDLED;
1761 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
1762 if (irqbits == mask)
1763 break;
1764 if (bits & irqbits)
1765 continue;
1766 port = &brd->ports[i];
1767
1768 int_cnt = 0;
1769 spin_lock(&port->slock);
1770 do {
1771 if (mxser_port_isr(port))
1772 break;
1773 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
1774 spin_unlock(&port->slock);
1775 }
1776 }
1777
1778 return handled;
1779 }
1780
1781 static const struct tty_operations mxser_ops = {
1782 .open = mxser_open,
1783 .close = mxser_close,
1784 .write = mxser_write,
1785 .put_char = mxser_put_char,
1786 .flush_chars = mxser_flush_chars,
1787 .write_room = mxser_write_room,
1788 .chars_in_buffer = mxser_chars_in_buffer,
1789 .flush_buffer = mxser_flush_buffer,
1790 .ioctl = mxser_ioctl,
1791 .throttle = mxser_throttle,
1792 .unthrottle = mxser_unthrottle,
1793 .set_termios = mxser_set_termios,
1794 .stop = mxser_stop,
1795 .start = mxser_start,
1796 .hangup = mxser_hangup,
1797 .break_ctl = mxser_rs_break,
1798 .wait_until_sent = mxser_wait_until_sent,
1799 .tiocmget = mxser_tiocmget,
1800 .tiocmset = mxser_tiocmset,
1801 .set_serial = mxser_set_serial_info,
1802 .get_serial = mxser_get_serial_info,
1803 .get_icount = mxser_get_icount,
1804 };
1805
1806 static const struct tty_port_operations mxser_port_ops = {
1807 .carrier_raised = mxser_carrier_raised,
1808 .dtr_rts = mxser_dtr_rts,
1809 .activate = mxser_activate,
1810 .shutdown = mxser_shutdown_port,
1811 };
1812
1813 /*
1814 * The MOXA Smartio/Industio serial driver boot-time initialization code!
1815 */
1816
mxser_initbrd(struct mxser_board * brd,bool high_baud)1817 static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
1818 {
1819 struct mxser_port *info;
1820 unsigned int i;
1821 bool is_mu860;
1822
1823 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr);
1824 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID;
1825
1826 for (i = 0; i < UART_INFO_NUM; i++) {
1827 if (Gpci_uart_info[i].type == brd->must_hwid) {
1828 brd->max_baud = Gpci_uart_info[i].max_baud;
1829
1830 /* exception....CP-102 */
1831 if (high_baud)
1832 brd->max_baud = 921600;
1833 break;
1834 }
1835 }
1836
1837 if (is_mu860) {
1838 /* set to RS232 mode by default */
1839 outb(0, brd->vector + 4);
1840 outb(0, brd->vector + 0x0c);
1841 }
1842
1843 for (i = 0; i < brd->nports; i++) {
1844 info = &brd->ports[i];
1845 if (is_mu860) {
1846 if (i < 4)
1847 info->opmode_ioaddr = brd->vector + 4;
1848 else
1849 info->opmode_ioaddr = brd->vector + 0x0c;
1850 }
1851 tty_port_init(&info->port);
1852 info->port.ops = &mxser_port_ops;
1853 info->board = brd;
1854 info->ldisc_stop_rx = 0;
1855
1856 /* Enhance mode enabled here */
1857 if (brd->must_hwid != MOXA_OTHER_UART)
1858 mxser_must_set_enhance_mode(info->ioaddr, true);
1859
1860 info->type = PORT_16550A;
1861
1862 mxser_process_txrx_fifo(info);
1863
1864 info->port.close_delay = 5 * HZ / 10;
1865 info->port.closing_wait = 30 * HZ;
1866 spin_lock_init(&info->slock);
1867
1868 /* before set INT ISR, disable all int */
1869 outb(inb(info->ioaddr + UART_IER) & 0xf0,
1870 info->ioaddr + UART_IER);
1871 }
1872 }
1873
mxser_probe(struct pci_dev * pdev,const struct pci_device_id * ent)1874 static int mxser_probe(struct pci_dev *pdev,
1875 const struct pci_device_id *ent)
1876 {
1877 struct mxser_board *brd;
1878 unsigned int i, base;
1879 unsigned long ioaddress;
1880 unsigned short nports = MXSER_NPORTS(ent->driver_data);
1881 struct device *tty_dev;
1882 int retval = -EINVAL;
1883
1884 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS);
1885 if (i >= MXSER_BOARDS) {
1886 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
1887 "not configured\n", MXSER_BOARDS);
1888 goto err;
1889 }
1890
1891 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports),
1892 GFP_KERNEL);
1893 if (!brd)
1894 goto err;
1895
1896 brd->idx = i;
1897 __set_bit(brd->idx, mxser_boards);
1898 base = i * MXSER_PORTS_PER_BOARD;
1899
1900 retval = pcim_enable_device(pdev);
1901 if (retval) {
1902 dev_err(&pdev->dev, "PCI enable failed\n");
1903 goto err_zero;
1904 }
1905
1906 /* io address */
1907 ioaddress = pci_resource_start(pdev, 2);
1908 retval = pci_request_region(pdev, 2, "mxser(IO)");
1909 if (retval)
1910 goto err_zero;
1911
1912 brd->nports = nports;
1913 for (i = 0; i < nports; i++)
1914 brd->ports[i].ioaddr = ioaddress + 8 * i;
1915
1916 /* vector */
1917 ioaddress = pci_resource_start(pdev, 3);
1918 retval = pci_request_region(pdev, 3, "mxser(vector)");
1919 if (retval)
1920 goto err_zero;
1921 brd->vector = ioaddress;
1922
1923 /* irq */
1924 brd->irq = pdev->irq;
1925
1926 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD);
1927
1928 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt,
1929 IRQF_SHARED, "mxser", brd);
1930 if (retval) {
1931 dev_err(&pdev->dev, "request irq failed");
1932 goto err_relbrd;
1933 }
1934
1935 for (i = 0; i < nports; i++) {
1936 tty_dev = tty_port_register_device(&brd->ports[i].port,
1937 mxvar_sdriver, base + i, &pdev->dev);
1938 if (IS_ERR(tty_dev)) {
1939 retval = PTR_ERR(tty_dev);
1940 for (; i > 0; i--)
1941 tty_unregister_device(mxvar_sdriver,
1942 base + i - 1);
1943 goto err_relbrd;
1944 }
1945 }
1946
1947 pci_set_drvdata(pdev, brd);
1948
1949 return 0;
1950 err_relbrd:
1951 for (i = 0; i < nports; i++)
1952 tty_port_destroy(&brd->ports[i].port);
1953 err_zero:
1954 __clear_bit(brd->idx, mxser_boards);
1955 err:
1956 return retval;
1957 }
1958
mxser_remove(struct pci_dev * pdev)1959 static void mxser_remove(struct pci_dev *pdev)
1960 {
1961 struct mxser_board *brd = pci_get_drvdata(pdev);
1962 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD;
1963
1964 for (i = 0; i < brd->nports; i++) {
1965 tty_unregister_device(mxvar_sdriver, base + i);
1966 tty_port_destroy(&brd->ports[i].port);
1967 }
1968
1969 __clear_bit(brd->idx, mxser_boards);
1970 }
1971
1972 static struct pci_driver mxser_driver = {
1973 .name = "mxser",
1974 .id_table = mxser_pcibrds,
1975 .probe = mxser_probe,
1976 .remove = mxser_remove
1977 };
1978
mxser_module_init(void)1979 static int __init mxser_module_init(void)
1980 {
1981 int retval;
1982
1983 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW |
1984 TTY_DRIVER_DYNAMIC_DEV);
1985 if (IS_ERR(mxvar_sdriver))
1986 return PTR_ERR(mxvar_sdriver);
1987
1988 /* Initialize the tty_driver structure */
1989 mxvar_sdriver->name = "ttyMI";
1990 mxvar_sdriver->major = ttymajor;
1991 mxvar_sdriver->minor_start = 0;
1992 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
1993 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
1994 mxvar_sdriver->init_termios = tty_std_termios;
1995 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
1996 tty_set_operations(mxvar_sdriver, &mxser_ops);
1997
1998 retval = tty_register_driver(mxvar_sdriver);
1999 if (retval) {
2000 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2001 "tty driver !\n");
2002 goto err_put;
2003 }
2004
2005 retval = pci_register_driver(&mxser_driver);
2006 if (retval) {
2007 printk(KERN_ERR "mxser: can't register pci driver\n");
2008 goto err_unr;
2009 }
2010
2011 return 0;
2012 err_unr:
2013 tty_unregister_driver(mxvar_sdriver);
2014 err_put:
2015 tty_driver_kref_put(mxvar_sdriver);
2016 return retval;
2017 }
2018
mxser_module_exit(void)2019 static void __exit mxser_module_exit(void)
2020 {
2021 pci_unregister_driver(&mxser_driver);
2022 tty_unregister_driver(mxvar_sdriver);
2023 tty_driver_kref_put(mxvar_sdriver);
2024 }
2025
2026 module_init(mxser_module_init);
2027 module_exit(mxser_module_exit);
2028