1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 */
4
5 #ifndef UFS_QCOM_H_
6 #define UFS_QCOM_H_
7
8 #include <linux/reset-controller.h>
9 #include <linux/reset.h>
10 #include <ufs/ufshcd.h>
11
12 #define MAX_UFS_QCOM_HOSTS 1
13 #define MAX_U32 (~(u32)0)
14 #define MPHY_TX_FSM_STATE 0x41
15 #define TX_FSM_HIBERN8 0x1
16 #define HBRN8_POLL_TOUT_MS 100
17 #define DEFAULT_CLK_RATE_HZ 1000000
18 #define BUS_VECTOR_NAME_LEN 32
19 #define MAX_SUPP_MAC 64
20
21 #define UFS_HW_VER_MAJOR_MASK GENMASK(31, 28)
22 #define UFS_HW_VER_MINOR_MASK GENMASK(27, 16)
23 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
24
25 /* vendor specific pre-defined parameters */
26 #define SLOW 1
27 #define FAST 2
28
29 #define UFS_QCOM_LIMIT_HS_RATE PA_HS_MODE_B
30
31 /* QCOM UFS host controller vendor specific registers */
32 enum {
33 REG_UFS_SYS1CLK_1US = 0xC0,
34 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
35 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
36 REG_UFS_PA_ERR_CODE = 0xCC,
37 /* On older UFS revisions, this register is called "RETRY_TIMER_REG" */
38 REG_UFS_PARAM0 = 0xD0,
39 /* On older UFS revisions, this register is called "REG_UFS_PA_LINK_STARTUP_TIMER" */
40 REG_UFS_CFG0 = 0xD8,
41 REG_UFS_CFG1 = 0xDC,
42 REG_UFS_CFG2 = 0xE0,
43 REG_UFS_HW_VERSION = 0xE4,
44
45 UFS_TEST_BUS = 0xE8,
46 UFS_TEST_BUS_CTRL_0 = 0xEC,
47 UFS_TEST_BUS_CTRL_1 = 0xF0,
48 UFS_TEST_BUS_CTRL_2 = 0xF4,
49 UFS_UNIPRO_CFG = 0xF8,
50
51 /*
52 * QCOM UFS host controller vendor specific registers
53 * added in HW Version 3.0.0
54 */
55 UFS_AH8_CFG = 0xFC,
56 };
57
58 /* QCOM UFS host controller vendor specific debug registers */
59 enum {
60 UFS_DBG_RD_REG_UAWM = 0x100,
61 UFS_DBG_RD_REG_UARM = 0x200,
62 UFS_DBG_RD_REG_TXUC = 0x300,
63 UFS_DBG_RD_REG_RXUC = 0x400,
64 UFS_DBG_RD_REG_DFC = 0x500,
65 UFS_DBG_RD_REG_TRLUT = 0x600,
66 UFS_DBG_RD_REG_TMRLUT = 0x700,
67 UFS_UFS_DBG_RD_REG_OCSC = 0x800,
68
69 UFS_UFS_DBG_RD_DESC_RAM = 0x1500,
70 UFS_UFS_DBG_RD_PRDT_RAM = 0x1700,
71 UFS_UFS_DBG_RD_RESP_RAM = 0x1800,
72 UFS_UFS_DBG_RD_EDTL_RAM = 0x1900,
73 };
74
75 enum {
76 UFS_MEM_CQIS_VS = 0x8,
77 };
78
79 #define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x) (0x000 + x)
80 #define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x) (0x400 + x)
81
82 /* bit definitions for REG_UFS_CFG0 register */
83 #define QUNIPRO_G4_SEL BIT(5)
84
85 /* bit definitions for REG_UFS_CFG1 register */
86 #define QUNIPRO_SEL BIT(0)
87 #define UFS_PHY_SOFT_RESET BIT(1)
88 #define UTP_DBG_RAMS_EN BIT(17)
89 #define TEST_BUS_EN BIT(18)
90 #define TEST_BUS_SEL GENMASK(22, 19)
91 #define UFS_REG_TEST_BUS_EN BIT(30)
92
93 #define UFS_PHY_RESET_ENABLE 1
94 #define UFS_PHY_RESET_DISABLE 0
95
96 /* bit definitions for REG_UFS_CFG2 register */
97 #define UAWM_HW_CGC_EN BIT(0)
98 #define UARM_HW_CGC_EN BIT(1)
99 #define TXUC_HW_CGC_EN BIT(2)
100 #define RXUC_HW_CGC_EN BIT(3)
101 #define DFC_HW_CGC_EN BIT(4)
102 #define TRLUT_HW_CGC_EN BIT(5)
103 #define TMRLUT_HW_CGC_EN BIT(6)
104 #define OCSC_HW_CGC_EN BIT(7)
105
106 /* bit definition for UFS_UFS_TEST_BUS_CTRL_n */
107 #define TEST_BUS_SUB_SEL_MASK GENMASK(4, 0) /* All XXX_SEL fields are 5 bits wide */
108
109 #define REG_UFS_CFG2_CGC_EN_ALL (UAWM_HW_CGC_EN | UARM_HW_CGC_EN |\
110 TXUC_HW_CGC_EN | RXUC_HW_CGC_EN |\
111 DFC_HW_CGC_EN | TRLUT_HW_CGC_EN |\
112 TMRLUT_HW_CGC_EN | OCSC_HW_CGC_EN)
113
114 /* bit offset */
115 #define OFFSET_CLK_NS_REG 0xa
116
117 /* bit masks */
118 #define MASK_TX_SYMBOL_CLK_1US_REG GENMASK(9, 0)
119 #define MASK_CLK_NS_REG GENMASK(23, 10)
120
121 /* QUniPro Vendor specific attributes */
122 #define PA_VS_CONFIG_REG1 0x9000
123 #define DME_VS_CORE_CLK_CTRL 0xD002
124 /* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
125 #define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT BIT(8)
126 #define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK 0xFF
127
128 static inline void
ufs_qcom_get_controller_revision(struct ufs_hba * hba,u8 * major,u16 * minor,u16 * step)129 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
130 u8 *major, u16 *minor, u16 *step)
131 {
132 u32 ver = ufshcd_readl(hba, REG_UFS_HW_VERSION);
133
134 *major = FIELD_GET(UFS_HW_VER_MAJOR_MASK, ver);
135 *minor = FIELD_GET(UFS_HW_VER_MINOR_MASK, ver);
136 *step = FIELD_GET(UFS_HW_VER_STEP_MASK, ver);
137 };
138
ufs_qcom_assert_reset(struct ufs_hba * hba)139 static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
140 {
141 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE),
142 REG_UFS_CFG1);
143
144 /*
145 * Make sure assertion of ufs phy reset is written to
146 * register before returning
147 */
148 mb();
149 }
150
ufs_qcom_deassert_reset(struct ufs_hba * hba)151 static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
152 {
153 ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE),
154 REG_UFS_CFG1);
155
156 /*
157 * Make sure de-assertion of ufs phy reset is written to
158 * register before returning
159 */
160 mb();
161 }
162
163 /* Host controller hardware version: major.minor.step */
164 struct ufs_hw_version {
165 u16 step;
166 u16 minor;
167 u8 major;
168 };
169
170 struct ufs_qcom_testbus {
171 u8 select_major;
172 u8 select_minor;
173 };
174
175 struct gpio_desc;
176
177 struct ufs_qcom_host {
178 /*
179 * Set this capability if host controller supports the QUniPro mode
180 * and if driver wants the Host controller to operate in QUniPro mode.
181 * Note: By default this capability will be kept enabled if host
182 * controller supports the QUniPro mode.
183 */
184 #define UFS_QCOM_CAP_QUNIPRO 0x1
185
186 /*
187 * Set this capability if host controller can retain the secure
188 * configuration even after UFS controller core power collapse.
189 */
190 #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE 0x2
191 u32 caps;
192
193 struct phy *generic_phy;
194 struct ufs_hba *hba;
195 struct ufs_pa_layer_attr dev_req_params;
196 struct clk *rx_l0_sync_clk;
197 struct clk *tx_l0_sync_clk;
198 struct clk *rx_l1_sync_clk;
199 struct clk *tx_l1_sync_clk;
200 bool is_lane_clks_enabled;
201
202 void __iomem *dev_ref_clk_ctrl_mmio;
203 bool is_dev_ref_clk_enabled;
204 struct ufs_hw_version hw_ver;
205 #ifdef CONFIG_SCSI_UFS_CRYPTO
206 void __iomem *ice_mmio;
207 #endif
208
209 u32 dev_ref_clk_en_mask;
210
211 struct ufs_qcom_testbus testbus;
212
213 /* Reset control of HCI */
214 struct reset_control *core_reset;
215 struct reset_controller_dev rcdev;
216
217 struct gpio_desc *device_reset;
218 };
219
220 static inline u32
ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host * host,u32 reg)221 ufs_qcom_get_debug_reg_offset(struct ufs_qcom_host *host, u32 reg)
222 {
223 if (host->hw_ver.major <= 0x02)
224 return UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(reg);
225
226 return UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(reg);
227 };
228
229 #define ufs_qcom_is_link_off(hba) ufshcd_is_link_off(hba)
230 #define ufs_qcom_is_link_active(hba) ufshcd_is_link_active(hba)
231 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
232
233 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
234
ufs_qcom_cap_qunipro(struct ufs_qcom_host * host)235 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
236 {
237 return host->caps & UFS_QCOM_CAP_QUNIPRO;
238 }
239
240 /* ufs-qcom-ice.c */
241
242 #ifdef CONFIG_SCSI_UFS_CRYPTO
243 int ufs_qcom_ice_init(struct ufs_qcom_host *host);
244 int ufs_qcom_ice_enable(struct ufs_qcom_host *host);
245 int ufs_qcom_ice_resume(struct ufs_qcom_host *host);
246 int ufs_qcom_ice_program_key(struct ufs_hba *hba,
247 const union ufs_crypto_cfg_entry *cfg, int slot);
248 #else
ufs_qcom_ice_init(struct ufs_qcom_host * host)249 static inline int ufs_qcom_ice_init(struct ufs_qcom_host *host)
250 {
251 return 0;
252 }
ufs_qcom_ice_enable(struct ufs_qcom_host * host)253 static inline int ufs_qcom_ice_enable(struct ufs_qcom_host *host)
254 {
255 return 0;
256 }
ufs_qcom_ice_resume(struct ufs_qcom_host * host)257 static inline int ufs_qcom_ice_resume(struct ufs_qcom_host *host)
258 {
259 return 0;
260 }
261 #define ufs_qcom_ice_program_key NULL
262 #endif /* !CONFIG_SCSI_UFS_CRYPTO */
263
264 #endif /* UFS_QCOM_H_ */
265