1 /*
2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
3 *
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 * Sven Neumann <neo@directfb.org>
6 *
7 *
8 * Card specific code is based on XFree86's savage driver.
9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 * 0.4.0 (neo)
16 * - hardware accelerated clear and move
17 *
18 * 0.3.2 (dok)
19 * - wait for vertical retrace before writing to cr67
20 * at the beginning of savagefb_set_par
21 * - use synchronization registers cr23 and cr26
22 *
23 * 0.3.1 (dok)
24 * - reset 3D engine
25 * - don't return alpha bits for 32bit format
26 *
27 * 0.3.0 (dok)
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
30 * - code cleanup
31 *
32 * 0.2.0 (dok)
33 * - first working version
34 *
35 *
36 * TODO
37 * - clock validations in decode_var
38 *
39 * BUGS
40 * - white margin on bootup
41 *
42 */
43
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/errno.h>
47 #include <linux/string.h>
48 #include <linux/mm.h>
49 #include <linux/slab.h>
50 #include <linux/delay.h>
51 #include <linux/fb.h>
52 #include <linux/pci.h>
53 #include <linux/init.h>
54 #include <linux/console.h>
55
56 #include <asm/io.h>
57 #include <asm/irq.h>
58
59 #include "savagefb.h"
60
61
62 #define SAVAGEFB_VERSION "0.4.0_2.6"
63
64 /* --------------------------------------------------------------------- */
65
66
67 static char *mode_option = NULL;
68
69 #ifdef MODULE
70
71 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
72 MODULE_LICENSE("GPL");
73 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
74
75 #endif
76
77
78 /* --------------------------------------------------------------------- */
79
vgaHWSeqReset(struct savagefb_par * par,int start)80 static void vgaHWSeqReset(struct savagefb_par *par, int start)
81 {
82 if (start)
83 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
84 else
85 VGAwSEQ(0x00, 0x03, par); /* End Reset */
86 }
87
vgaHWProtect(struct savagefb_par * par,int on)88 static void vgaHWProtect(struct savagefb_par *par, int on)
89 {
90 unsigned char tmp;
91
92 if (on) {
93 /*
94 * Turn off screen and disable sequencer.
95 */
96 tmp = VGArSEQ(0x01, par);
97
98 vgaHWSeqReset(par, 1); /* start synchronous reset */
99 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
100
101 VGAenablePalette(par);
102 } else {
103 /*
104 * Reenable sequencer, then turn on screen.
105 */
106
107 tmp = VGArSEQ(0x01, par);
108
109 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
110 vgaHWSeqReset(par, 0); /* clear synchronous reset */
111
112 VGAdisablePalette(par);
113 }
114 }
115
vgaHWRestore(struct savagefb_par * par,struct savage_reg * reg)116 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
117 {
118 int i;
119
120 VGAwMISC(reg->MiscOutReg, par);
121
122 for (i = 1; i < 5; i++)
123 VGAwSEQ(i, reg->Sequencer[i], par);
124
125 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
126 CRTC[17] */
127 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
128
129 for (i = 0; i < 25; i++)
130 VGAwCR(i, reg->CRTC[i], par);
131
132 for (i = 0; i < 9; i++)
133 VGAwGR(i, reg->Graphics[i], par);
134
135 VGAenablePalette(par);
136
137 for (i = 0; i < 21; i++)
138 VGAwATTR(i, reg->Attribute[i], par);
139
140 VGAdisablePalette(par);
141 }
142
vgaHWInit(struct fb_var_screeninfo * var,struct savagefb_par * par,struct xtimings * timings,struct savage_reg * reg)143 static void vgaHWInit(struct fb_var_screeninfo *var,
144 struct savagefb_par *par,
145 struct xtimings *timings,
146 struct savage_reg *reg)
147 {
148 reg->MiscOutReg = 0x23;
149
150 if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
151 reg->MiscOutReg |= 0x40;
152
153 if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
154 reg->MiscOutReg |= 0x80;
155
156 /*
157 * Time Sequencer
158 */
159 reg->Sequencer[0x00] = 0x00;
160 reg->Sequencer[0x01] = 0x01;
161 reg->Sequencer[0x02] = 0x0F;
162 reg->Sequencer[0x03] = 0x00; /* Font select */
163 reg->Sequencer[0x04] = 0x0E; /* Misc */
164
165 /*
166 * CRTC Controller
167 */
168 reg->CRTC[0x00] = (timings->HTotal >> 3) - 5;
169 reg->CRTC[0x01] = (timings->HDisplay >> 3) - 1;
170 reg->CRTC[0x02] = (timings->HSyncStart >> 3) - 1;
171 reg->CRTC[0x03] = (((timings->HSyncEnd >> 3) - 1) & 0x1f) | 0x80;
172 reg->CRTC[0x04] = (timings->HSyncStart >> 3);
173 reg->CRTC[0x05] = ((((timings->HSyncEnd >> 3) - 1) & 0x20) << 2) |
174 (((timings->HSyncEnd >> 3)) & 0x1f);
175 reg->CRTC[0x06] = (timings->VTotal - 2) & 0xFF;
176 reg->CRTC[0x07] = (((timings->VTotal - 2) & 0x100) >> 8) |
177 (((timings->VDisplay - 1) & 0x100) >> 7) |
178 ((timings->VSyncStart & 0x100) >> 6) |
179 (((timings->VSyncStart - 1) & 0x100) >> 5) |
180 0x10 |
181 (((timings->VTotal - 2) & 0x200) >> 4) |
182 (((timings->VDisplay - 1) & 0x200) >> 3) |
183 ((timings->VSyncStart & 0x200) >> 2);
184 reg->CRTC[0x08] = 0x00;
185 reg->CRTC[0x09] = (((timings->VSyncStart - 1) & 0x200) >> 4) | 0x40;
186
187 if (timings->dblscan)
188 reg->CRTC[0x09] |= 0x80;
189
190 reg->CRTC[0x0a] = 0x00;
191 reg->CRTC[0x0b] = 0x00;
192 reg->CRTC[0x0c] = 0x00;
193 reg->CRTC[0x0d] = 0x00;
194 reg->CRTC[0x0e] = 0x00;
195 reg->CRTC[0x0f] = 0x00;
196 reg->CRTC[0x10] = timings->VSyncStart & 0xff;
197 reg->CRTC[0x11] = (timings->VSyncEnd & 0x0f) | 0x20;
198 reg->CRTC[0x12] = (timings->VDisplay - 1) & 0xff;
199 reg->CRTC[0x13] = var->xres_virtual >> 4;
200 reg->CRTC[0x14] = 0x00;
201 reg->CRTC[0x15] = (timings->VSyncStart - 1) & 0xff;
202 reg->CRTC[0x16] = (timings->VSyncEnd - 1) & 0xff;
203 reg->CRTC[0x17] = 0xc3;
204 reg->CRTC[0x18] = 0xff;
205
206 /*
207 * are these unnecessary?
208 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
209 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
210 */
211
212 /*
213 * Graphics Display Controller
214 */
215 reg->Graphics[0x00] = 0x00;
216 reg->Graphics[0x01] = 0x00;
217 reg->Graphics[0x02] = 0x00;
218 reg->Graphics[0x03] = 0x00;
219 reg->Graphics[0x04] = 0x00;
220 reg->Graphics[0x05] = 0x40;
221 reg->Graphics[0x06] = 0x05; /* only map 64k VGA memory !!!! */
222 reg->Graphics[0x07] = 0x0F;
223 reg->Graphics[0x08] = 0xFF;
224
225
226 reg->Attribute[0x00] = 0x00; /* standard colormap translation */
227 reg->Attribute[0x01] = 0x01;
228 reg->Attribute[0x02] = 0x02;
229 reg->Attribute[0x03] = 0x03;
230 reg->Attribute[0x04] = 0x04;
231 reg->Attribute[0x05] = 0x05;
232 reg->Attribute[0x06] = 0x06;
233 reg->Attribute[0x07] = 0x07;
234 reg->Attribute[0x08] = 0x08;
235 reg->Attribute[0x09] = 0x09;
236 reg->Attribute[0x0a] = 0x0A;
237 reg->Attribute[0x0b] = 0x0B;
238 reg->Attribute[0x0c] = 0x0C;
239 reg->Attribute[0x0d] = 0x0D;
240 reg->Attribute[0x0e] = 0x0E;
241 reg->Attribute[0x0f] = 0x0F;
242 reg->Attribute[0x10] = 0x41;
243 reg->Attribute[0x11] = 0xFF;
244 reg->Attribute[0x12] = 0x0F;
245 reg->Attribute[0x13] = 0x00;
246 reg->Attribute[0x14] = 0x00;
247 }
248
249 /* -------------------- Hardware specific routines ------------------------- */
250
251 /*
252 * Hardware Acceleration for SavageFB
253 */
254
255 /* Wait for fifo space */
256 static void
savage3D_waitfifo(struct savagefb_par * par,int space)257 savage3D_waitfifo(struct savagefb_par *par, int space)
258 {
259 int slots = MAXFIFO - space;
260
261 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
262 }
263
264 static void
savage4_waitfifo(struct savagefb_par * par,int space)265 savage4_waitfifo(struct savagefb_par *par, int space)
266 {
267 int slots = MAXFIFO - space;
268
269 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
270 }
271
272 static void
savage2000_waitfifo(struct savagefb_par * par,int space)273 savage2000_waitfifo(struct savagefb_par *par, int space)
274 {
275 int slots = MAXFIFO - space;
276
277 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
278 }
279
280 /* Wait for idle accelerator */
281 static void
savage3D_waitidle(struct savagefb_par * par)282 savage3D_waitidle(struct savagefb_par *par)
283 {
284 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
285 }
286
287 static void
savage4_waitidle(struct savagefb_par * par)288 savage4_waitidle(struct savagefb_par *par)
289 {
290 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
291 }
292
293 static void
savage2000_waitidle(struct savagefb_par * par)294 savage2000_waitidle(struct savagefb_par *par)
295 {
296 while ((savage_in32(0x48C60, par) & 0x009fffff));
297 }
298
299 #ifdef CONFIG_FB_SAVAGE_ACCEL
300 static void
SavageSetup2DEngine(struct savagefb_par * par)301 SavageSetup2DEngine(struct savagefb_par *par)
302 {
303 unsigned long GlobalBitmapDescriptor;
304
305 GlobalBitmapDescriptor = 1 | 8 | BCI_BD_BW_DISABLE;
306 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
307 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
308
309 switch(par->chip) {
310 case S3_SAVAGE3D:
311 case S3_SAVAGE_MX:
312 /* Disable BCI */
313 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
314 /* Setup BCI command overflow buffer */
315 savage_out32(0x48C14,
316 (par->cob_offset >> 11) | (par->cob_index << 29),
317 par);
318 /* Program shadow status update. */
319 savage_out32(0x48C10, 0x78207220, par);
320 savage_out32(0x48C0C, 0, par);
321 /* Enable BCI and command overflow buffer */
322 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
323 break;
324 case S3_SAVAGE4:
325 case S3_TWISTER:
326 case S3_PROSAVAGE:
327 case S3_PROSAVAGEDDR:
328 case S3_SUPERSAVAGE:
329 /* Disable BCI */
330 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
331 /* Program shadow status update */
332 savage_out32(0x48C10, 0x00700040, par);
333 savage_out32(0x48C0C, 0, par);
334 /* Enable BCI without the COB */
335 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
336 break;
337 case S3_SAVAGE2000:
338 /* Disable BCI */
339 savage_out32(0x48C18, 0, par);
340 /* Setup BCI command overflow buffer */
341 savage_out32(0x48C18,
342 (par->cob_offset >> 7) | (par->cob_index),
343 par);
344 /* Disable shadow status update */
345 savage_out32(0x48A30, 0, par);
346 /* Enable BCI and command overflow buffer */
347 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
348 par);
349 break;
350 default:
351 break;
352 }
353 /* Turn on 16-bit register access. */
354 vga_out8(0x3d4, 0x31, par);
355 vga_out8(0x3d5, 0x0c, par);
356
357 /* Set stride to use GBD. */
358 vga_out8(0x3d4, 0x50, par);
359 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
360
361 /* Enable 2D engine. */
362 vga_out8(0x3d4, 0x40, par);
363 vga_out8(0x3d5, 0x01, par);
364
365 savage_out32(MONO_PAT_0, ~0, par);
366 savage_out32(MONO_PAT_1, ~0, par);
367
368 /* Setup plane masks */
369 savage_out32(0x8128, ~0, par); /* enable all write planes */
370 savage_out32(0x812C, ~0, par); /* enable all read planes */
371 savage_out16(0x8134, 0x27, par);
372 savage_out16(0x8136, 0x07, par);
373
374 /* Now set the GBD */
375 par->bci_ptr = 0;
376 par->SavageWaitFifo(par, 4);
377
378 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
379 BCI_SEND(0);
380 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
381 BCI_SEND(GlobalBitmapDescriptor);
382
383 /*
384 * I don't know why, sending this twice fixes the initial black screen,
385 * prevents X from crashing at least in Toshiba laptops with SavageIX.
386 * --Tony
387 */
388 par->bci_ptr = 0;
389 par->SavageWaitFifo(par, 4);
390
391 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD1);
392 BCI_SEND(0);
393 BCI_SEND(BCI_CMD_SETREG | (1 << 16) | BCI_GBD2);
394 BCI_SEND(GlobalBitmapDescriptor);
395 }
396
savagefb_set_clip(struct fb_info * info)397 static void savagefb_set_clip(struct fb_info *info)
398 {
399 struct savagefb_par *par = info->par;
400 int cmd;
401
402 cmd = BCI_CMD_NOP | BCI_CMD_CLIP_NEW;
403 par->bci_ptr = 0;
404 par->SavageWaitFifo(par,3);
405 BCI_SEND(cmd);
406 BCI_SEND(BCI_CLIP_TL(0, 0));
407 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
408 }
409 #else
SavageSetup2DEngine(struct savagefb_par * par)410 static void SavageSetup2DEngine(struct savagefb_par *par) {}
411
412 #endif
413
SavageCalcClock(long freq,int min_m,int min_n1,int max_n1,int min_n2,int max_n2,long freq_min,long freq_max,unsigned int * mdiv,unsigned int * ndiv,unsigned int * r)414 static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,
415 int min_n2, int max_n2, long freq_min,
416 long freq_max, unsigned int *mdiv,
417 unsigned int *ndiv, unsigned int *r)
418 {
419 long diff, best_diff;
420 unsigned int m;
421 unsigned char n1, n2, best_n1=16+2, best_n2=2, best_m=125+2;
422
423 if (freq < freq_min / (1 << max_n2)) {
424 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
425 freq = freq_min / (1 << max_n2);
426 }
427 if (freq > freq_max / (1 << min_n2)) {
428 printk(KERN_ERR "invalid frequency %ld Khz\n", freq);
429 freq = freq_max / (1 << min_n2);
430 }
431
432 /* work out suitable timings */
433 best_diff = freq;
434
435 for (n2=min_n2; n2<=max_n2; n2++) {
436 for (n1=min_n1+2; n1<=max_n1+2; n1++) {
437 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
438 BASE_FREQ;
439 if (m < min_m+2 || m > 127+2)
440 continue;
441 if ((m * BASE_FREQ >= freq_min * n1) &&
442 (m * BASE_FREQ <= freq_max * n1)) {
443 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
444 if (diff < 0)
445 diff = -diff;
446 if (diff < best_diff) {
447 best_diff = diff;
448 best_m = m;
449 best_n1 = n1;
450 best_n2 = n2;
451 }
452 }
453 }
454 }
455
456 *ndiv = best_n1 - 2;
457 *r = best_n2;
458 *mdiv = best_m - 2;
459 }
460
common_calc_clock(long freq,int min_m,int min_n1,int max_n1,int min_n2,int max_n2,long freq_min,long freq_max,unsigned char * mdiv,unsigned char * ndiv)461 static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,
462 int min_n2, int max_n2, long freq_min,
463 long freq_max, unsigned char *mdiv,
464 unsigned char *ndiv)
465 {
466 long diff, best_diff;
467 unsigned int m;
468 unsigned char n1, n2;
469 unsigned char best_n1 = 16+2, best_n2 = 2, best_m = 125+2;
470
471 best_diff = freq;
472
473 for (n2 = min_n2; n2 <= max_n2; n2++) {
474 for (n1 = min_n1+2; n1 <= max_n1+2; n1++) {
475 m = (freq * n1 * (1 << n2) + HALF_BASE_FREQ) /
476 BASE_FREQ;
477 if (m < min_m + 2 || m > 127+2)
478 continue;
479 if ((m * BASE_FREQ >= freq_min * n1) &&
480 (m * BASE_FREQ <= freq_max * n1)) {
481 diff = freq * (1 << n2) * n1 - BASE_FREQ * m;
482 if (diff < 0)
483 diff = -diff;
484 if (diff < best_diff) {
485 best_diff = diff;
486 best_m = m;
487 best_n1 = n1;
488 best_n2 = n2;
489 }
490 }
491 }
492 }
493
494 if (max_n1 == 63)
495 *ndiv = (best_n1 - 2) | (best_n2 << 6);
496 else
497 *ndiv = (best_n1 - 2) | (best_n2 << 5);
498
499 *mdiv = best_m - 2;
500
501 return 0;
502 }
503
504 #ifdef SAVAGEFB_DEBUG
505 /* This function is used to debug, it prints out the contents of s3 regs */
506
SavagePrintRegs(struct savagefb_par * par)507 static void SavagePrintRegs(struct savagefb_par *par)
508 {
509 unsigned char i;
510 int vgaCRIndex = 0x3d4;
511 int vgaCRReg = 0x3d5;
512
513 printk(KERN_DEBUG "SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
514 "xF");
515
516 for (i = 0; i < 0x70; i++) {
517 if (!(i % 16))
518 printk(KERN_DEBUG "\nSR%xx ", i >> 4);
519 vga_out8(0x3c4, i, par);
520 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
521 }
522
523 printk(KERN_DEBUG "\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
524 "xD xE xF");
525
526 for (i = 0; i < 0xB7; i++) {
527 if (!(i % 16))
528 printk(KERN_DEBUG "\nCR%xx ", i >> 4);
529 vga_out8(vgaCRIndex, i, par);
530 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
531 }
532
533 printk(KERN_DEBUG "\n\n");
534 }
535 #endif
536
537 /* --------------------------------------------------------------------- */
538
savage_get_default_par(struct savagefb_par * par,struct savage_reg * reg)539 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
540 {
541 unsigned char cr3a, cr53, cr66;
542
543 vga_out16(0x3d4, 0x4838, par);
544 vga_out16(0x3d4, 0xa039, par);
545 vga_out16(0x3c4, 0x0608, par);
546
547 vga_out8(0x3d4, 0x66, par);
548 cr66 = vga_in8(0x3d5, par);
549 vga_out8(0x3d5, cr66 | 0x80, par);
550 vga_out8(0x3d4, 0x3a, par);
551 cr3a = vga_in8(0x3d5, par);
552 vga_out8(0x3d5, cr3a | 0x80, par);
553 vga_out8(0x3d4, 0x53, par);
554 cr53 = vga_in8(0x3d5, par);
555 vga_out8(0x3d5, cr53 & 0x7f, par);
556
557 vga_out8(0x3d4, 0x66, par);
558 vga_out8(0x3d5, cr66, par);
559 vga_out8(0x3d4, 0x3a, par);
560 vga_out8(0x3d5, cr3a, par);
561
562 vga_out8(0x3d4, 0x66, par);
563 vga_out8(0x3d5, cr66, par);
564 vga_out8(0x3d4, 0x3a, par);
565 vga_out8(0x3d5, cr3a, par);
566
567 /* unlock extended seq regs */
568 vga_out8(0x3c4, 0x08, par);
569 reg->SR08 = vga_in8(0x3c5, par);
570 vga_out8(0x3c5, 0x06, par);
571
572 /* now save all the extended regs we need */
573 vga_out8(0x3d4, 0x31, par);
574 reg->CR31 = vga_in8(0x3d5, par);
575 vga_out8(0x3d4, 0x32, par);
576 reg->CR32 = vga_in8(0x3d5, par);
577 vga_out8(0x3d4, 0x34, par);
578 reg->CR34 = vga_in8(0x3d5, par);
579 vga_out8(0x3d4, 0x36, par);
580 reg->CR36 = vga_in8(0x3d5, par);
581 vga_out8(0x3d4, 0x3a, par);
582 reg->CR3A = vga_in8(0x3d5, par);
583 vga_out8(0x3d4, 0x40, par);
584 reg->CR40 = vga_in8(0x3d5, par);
585 vga_out8(0x3d4, 0x42, par);
586 reg->CR42 = vga_in8(0x3d5, par);
587 vga_out8(0x3d4, 0x45, par);
588 reg->CR45 = vga_in8(0x3d5, par);
589 vga_out8(0x3d4, 0x50, par);
590 reg->CR50 = vga_in8(0x3d5, par);
591 vga_out8(0x3d4, 0x51, par);
592 reg->CR51 = vga_in8(0x3d5, par);
593 vga_out8(0x3d4, 0x53, par);
594 reg->CR53 = vga_in8(0x3d5, par);
595 vga_out8(0x3d4, 0x58, par);
596 reg->CR58 = vga_in8(0x3d5, par);
597 vga_out8(0x3d4, 0x60, par);
598 reg->CR60 = vga_in8(0x3d5, par);
599 vga_out8(0x3d4, 0x66, par);
600 reg->CR66 = vga_in8(0x3d5, par);
601 vga_out8(0x3d4, 0x67, par);
602 reg->CR67 = vga_in8(0x3d5, par);
603 vga_out8(0x3d4, 0x68, par);
604 reg->CR68 = vga_in8(0x3d5, par);
605 vga_out8(0x3d4, 0x69, par);
606 reg->CR69 = vga_in8(0x3d5, par);
607 vga_out8(0x3d4, 0x6f, par);
608 reg->CR6F = vga_in8(0x3d5, par);
609
610 vga_out8(0x3d4, 0x33, par);
611 reg->CR33 = vga_in8(0x3d5, par);
612 vga_out8(0x3d4, 0x86, par);
613 reg->CR86 = vga_in8(0x3d5, par);
614 vga_out8(0x3d4, 0x88, par);
615 reg->CR88 = vga_in8(0x3d5, par);
616 vga_out8(0x3d4, 0x90, par);
617 reg->CR90 = vga_in8(0x3d5, par);
618 vga_out8(0x3d4, 0x91, par);
619 reg->CR91 = vga_in8(0x3d5, par);
620 vga_out8(0x3d4, 0xb0, par);
621 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
622
623 /* extended mode timing regs */
624 vga_out8(0x3d4, 0x3b, par);
625 reg->CR3B = vga_in8(0x3d5, par);
626 vga_out8(0x3d4, 0x3c, par);
627 reg->CR3C = vga_in8(0x3d5, par);
628 vga_out8(0x3d4, 0x43, par);
629 reg->CR43 = vga_in8(0x3d5, par);
630 vga_out8(0x3d4, 0x5d, par);
631 reg->CR5D = vga_in8(0x3d5, par);
632 vga_out8(0x3d4, 0x5e, par);
633 reg->CR5E = vga_in8(0x3d5, par);
634 vga_out8(0x3d4, 0x65, par);
635 reg->CR65 = vga_in8(0x3d5, par);
636
637 /* save seq extended regs for DCLK PLL programming */
638 vga_out8(0x3c4, 0x0e, par);
639 reg->SR0E = vga_in8(0x3c5, par);
640 vga_out8(0x3c4, 0x0f, par);
641 reg->SR0F = vga_in8(0x3c5, par);
642 vga_out8(0x3c4, 0x10, par);
643 reg->SR10 = vga_in8(0x3c5, par);
644 vga_out8(0x3c4, 0x11, par);
645 reg->SR11 = vga_in8(0x3c5, par);
646 vga_out8(0x3c4, 0x12, par);
647 reg->SR12 = vga_in8(0x3c5, par);
648 vga_out8(0x3c4, 0x13, par);
649 reg->SR13 = vga_in8(0x3c5, par);
650 vga_out8(0x3c4, 0x29, par);
651 reg->SR29 = vga_in8(0x3c5, par);
652
653 vga_out8(0x3c4, 0x15, par);
654 reg->SR15 = vga_in8(0x3c5, par);
655 vga_out8(0x3c4, 0x30, par);
656 reg->SR30 = vga_in8(0x3c5, par);
657 vga_out8(0x3c4, 0x18, par);
658 reg->SR18 = vga_in8(0x3c5, par);
659
660 /* Save flat panel expansion registers. */
661 if (par->chip == S3_SAVAGE_MX) {
662 int i;
663
664 for (i = 0; i < 8; i++) {
665 vga_out8(0x3c4, 0x54+i, par);
666 reg->SR54[i] = vga_in8(0x3c5, par);
667 }
668 }
669
670 vga_out8(0x3d4, 0x66, par);
671 cr66 = vga_in8(0x3d5, par);
672 vga_out8(0x3d5, cr66 | 0x80, par);
673 vga_out8(0x3d4, 0x3a, par);
674 cr3a = vga_in8(0x3d5, par);
675 vga_out8(0x3d5, cr3a | 0x80, par);
676
677 /* now save MIU regs */
678 if (par->chip != S3_SAVAGE_MX) {
679 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
680 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
681 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
682 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
683 }
684
685 vga_out8(0x3d4, 0x3a, par);
686 vga_out8(0x3d5, cr3a, par);
687 vga_out8(0x3d4, 0x66, par);
688 vga_out8(0x3d5, cr66, par);
689 }
690
savage_set_default_par(struct savagefb_par * par,struct savage_reg * reg)691 static void savage_set_default_par(struct savagefb_par *par,
692 struct savage_reg *reg)
693 {
694 unsigned char cr3a, cr53, cr66;
695
696 vga_out16(0x3d4, 0x4838, par);
697 vga_out16(0x3d4, 0xa039, par);
698 vga_out16(0x3c4, 0x0608, par);
699
700 vga_out8(0x3d4, 0x66, par);
701 cr66 = vga_in8(0x3d5, par);
702 vga_out8(0x3d5, cr66 | 0x80, par);
703 vga_out8(0x3d4, 0x3a, par);
704 cr3a = vga_in8(0x3d5, par);
705 vga_out8(0x3d5, cr3a | 0x80, par);
706 vga_out8(0x3d4, 0x53, par);
707 cr53 = vga_in8(0x3d5, par);
708 vga_out8(0x3d5, cr53 & 0x7f, par);
709
710 vga_out8(0x3d4, 0x66, par);
711 vga_out8(0x3d5, cr66, par);
712 vga_out8(0x3d4, 0x3a, par);
713 vga_out8(0x3d5, cr3a, par);
714
715 vga_out8(0x3d4, 0x66, par);
716 vga_out8(0x3d5, cr66, par);
717 vga_out8(0x3d4, 0x3a, par);
718 vga_out8(0x3d5, cr3a, par);
719
720 /* unlock extended seq regs */
721 vga_out8(0x3c4, 0x08, par);
722 vga_out8(0x3c5, reg->SR08, par);
723 vga_out8(0x3c5, 0x06, par);
724
725 /* now restore all the extended regs we need */
726 vga_out8(0x3d4, 0x31, par);
727 vga_out8(0x3d5, reg->CR31, par);
728 vga_out8(0x3d4, 0x32, par);
729 vga_out8(0x3d5, reg->CR32, par);
730 vga_out8(0x3d4, 0x34, par);
731 vga_out8(0x3d5, reg->CR34, par);
732 vga_out8(0x3d4, 0x36, par);
733 vga_out8(0x3d5,reg->CR36, par);
734 vga_out8(0x3d4, 0x3a, par);
735 vga_out8(0x3d5, reg->CR3A, par);
736 vga_out8(0x3d4, 0x40, par);
737 vga_out8(0x3d5, reg->CR40, par);
738 vga_out8(0x3d4, 0x42, par);
739 vga_out8(0x3d5, reg->CR42, par);
740 vga_out8(0x3d4, 0x45, par);
741 vga_out8(0x3d5, reg->CR45, par);
742 vga_out8(0x3d4, 0x50, par);
743 vga_out8(0x3d5, reg->CR50, par);
744 vga_out8(0x3d4, 0x51, par);
745 vga_out8(0x3d5, reg->CR51, par);
746 vga_out8(0x3d4, 0x53, par);
747 vga_out8(0x3d5, reg->CR53, par);
748 vga_out8(0x3d4, 0x58, par);
749 vga_out8(0x3d5, reg->CR58, par);
750 vga_out8(0x3d4, 0x60, par);
751 vga_out8(0x3d5, reg->CR60, par);
752 vga_out8(0x3d4, 0x66, par);
753 vga_out8(0x3d5, reg->CR66, par);
754 vga_out8(0x3d4, 0x67, par);
755 vga_out8(0x3d5, reg->CR67, par);
756 vga_out8(0x3d4, 0x68, par);
757 vga_out8(0x3d5, reg->CR68, par);
758 vga_out8(0x3d4, 0x69, par);
759 vga_out8(0x3d5, reg->CR69, par);
760 vga_out8(0x3d4, 0x6f, par);
761 vga_out8(0x3d5, reg->CR6F, par);
762
763 vga_out8(0x3d4, 0x33, par);
764 vga_out8(0x3d5, reg->CR33, par);
765 vga_out8(0x3d4, 0x86, par);
766 vga_out8(0x3d5, reg->CR86, par);
767 vga_out8(0x3d4, 0x88, par);
768 vga_out8(0x3d5, reg->CR88, par);
769 vga_out8(0x3d4, 0x90, par);
770 vga_out8(0x3d5, reg->CR90, par);
771 vga_out8(0x3d4, 0x91, par);
772 vga_out8(0x3d5, reg->CR91, par);
773 vga_out8(0x3d4, 0xb0, par);
774 vga_out8(0x3d5, reg->CRB0, par);
775
776 /* extended mode timing regs */
777 vga_out8(0x3d4, 0x3b, par);
778 vga_out8(0x3d5, reg->CR3B, par);
779 vga_out8(0x3d4, 0x3c, par);
780 vga_out8(0x3d5, reg->CR3C, par);
781 vga_out8(0x3d4, 0x43, par);
782 vga_out8(0x3d5, reg->CR43, par);
783 vga_out8(0x3d4, 0x5d, par);
784 vga_out8(0x3d5, reg->CR5D, par);
785 vga_out8(0x3d4, 0x5e, par);
786 vga_out8(0x3d5, reg->CR5E, par);
787 vga_out8(0x3d4, 0x65, par);
788 vga_out8(0x3d5, reg->CR65, par);
789
790 /* save seq extended regs for DCLK PLL programming */
791 vga_out8(0x3c4, 0x0e, par);
792 vga_out8(0x3c5, reg->SR0E, par);
793 vga_out8(0x3c4, 0x0f, par);
794 vga_out8(0x3c5, reg->SR0F, par);
795 vga_out8(0x3c4, 0x10, par);
796 vga_out8(0x3c5, reg->SR10, par);
797 vga_out8(0x3c4, 0x11, par);
798 vga_out8(0x3c5, reg->SR11, par);
799 vga_out8(0x3c4, 0x12, par);
800 vga_out8(0x3c5, reg->SR12, par);
801 vga_out8(0x3c4, 0x13, par);
802 vga_out8(0x3c5, reg->SR13, par);
803 vga_out8(0x3c4, 0x29, par);
804 vga_out8(0x3c5, reg->SR29, par);
805
806 vga_out8(0x3c4, 0x15, par);
807 vga_out8(0x3c5, reg->SR15, par);
808 vga_out8(0x3c4, 0x30, par);
809 vga_out8(0x3c5, reg->SR30, par);
810 vga_out8(0x3c4, 0x18, par);
811 vga_out8(0x3c5, reg->SR18, par);
812
813 /* Save flat panel expansion registers. */
814 if (par->chip == S3_SAVAGE_MX) {
815 int i;
816
817 for (i = 0; i < 8; i++) {
818 vga_out8(0x3c4, 0x54+i, par);
819 vga_out8(0x3c5, reg->SR54[i], par);
820 }
821 }
822
823 vga_out8(0x3d4, 0x66, par);
824 cr66 = vga_in8(0x3d5, par);
825 vga_out8(0x3d5, cr66 | 0x80, par);
826 vga_out8(0x3d4, 0x3a, par);
827 cr3a = vga_in8(0x3d5, par);
828 vga_out8(0x3d5, cr3a | 0x80, par);
829
830 /* now save MIU regs */
831 if (par->chip != S3_SAVAGE_MX) {
832 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
833 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
834 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
835 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
836 }
837
838 vga_out8(0x3d4, 0x3a, par);
839 vga_out8(0x3d5, cr3a, par);
840 vga_out8(0x3d4, 0x66, par);
841 vga_out8(0x3d5, cr66, par);
842 }
843
savage_update_var(struct fb_var_screeninfo * var,const struct fb_videomode * modedb)844 static void savage_update_var(struct fb_var_screeninfo *var,
845 const struct fb_videomode *modedb)
846 {
847 var->xres = var->xres_virtual = modedb->xres;
848 var->yres = modedb->yres;
849 if (var->yres_virtual < var->yres)
850 var->yres_virtual = var->yres;
851 var->xoffset = var->yoffset = 0;
852 var->pixclock = modedb->pixclock;
853 var->left_margin = modedb->left_margin;
854 var->right_margin = modedb->right_margin;
855 var->upper_margin = modedb->upper_margin;
856 var->lower_margin = modedb->lower_margin;
857 var->hsync_len = modedb->hsync_len;
858 var->vsync_len = modedb->vsync_len;
859 var->sync = modedb->sync;
860 var->vmode = modedb->vmode;
861 }
862
savagefb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)863 static int savagefb_check_var(struct fb_var_screeninfo *var,
864 struct fb_info *info)
865 {
866 struct savagefb_par *par = info->par;
867 int memlen, vramlen, mode_valid = 0;
868
869 DBG("savagefb_check_var");
870
871 if (!var->pixclock)
872 return -EINVAL;
873
874 var->transp.offset = 0;
875 var->transp.length = 0;
876 switch (var->bits_per_pixel) {
877 case 8:
878 var->red.offset = var->green.offset =
879 var->blue.offset = 0;
880 var->red.length = var->green.length =
881 var->blue.length = var->bits_per_pixel;
882 break;
883 case 16:
884 var->red.offset = 11;
885 var->red.length = 5;
886 var->green.offset = 5;
887 var->green.length = 6;
888 var->blue.offset = 0;
889 var->blue.length = 5;
890 break;
891 case 32:
892 var->transp.offset = 24;
893 var->transp.length = 8;
894 var->red.offset = 16;
895 var->red.length = 8;
896 var->green.offset = 8;
897 var->green.length = 8;
898 var->blue.offset = 0;
899 var->blue.length = 8;
900 break;
901
902 default:
903 return -EINVAL;
904 }
905
906 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
907 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
908 mode_valid = 1;
909
910 /* calculate modeline if supported by monitor */
911 if (!mode_valid && info->monspecs.gtf) {
912 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
913 mode_valid = 1;
914 }
915
916 if (!mode_valid) {
917 const struct fb_videomode *mode;
918
919 mode = fb_find_best_mode(var, &info->modelist);
920 if (mode) {
921 savage_update_var(var, mode);
922 mode_valid = 1;
923 }
924 }
925
926 if (!mode_valid && info->monspecs.modedb_len)
927 return -EINVAL;
928
929 /* Is the mode larger than the LCD panel? */
930 if (par->SavagePanelWidth &&
931 (var->xres > par->SavagePanelWidth ||
932 var->yres > par->SavagePanelHeight)) {
933 printk(KERN_INFO "Mode (%dx%d) larger than the LCD panel "
934 "(%dx%d)\n", var->xres, var->yres,
935 par->SavagePanelWidth,
936 par->SavagePanelHeight);
937 return -1;
938 }
939
940 if (var->yres_virtual < var->yres)
941 var->yres_virtual = var->yres;
942 if (var->xres_virtual < var->xres)
943 var->xres_virtual = var->xres;
944
945 vramlen = info->fix.smem_len;
946
947 memlen = var->xres_virtual * var->bits_per_pixel *
948 var->yres_virtual / 8;
949 if (memlen > vramlen) {
950 var->yres_virtual = vramlen * 8 /
951 (var->xres_virtual * var->bits_per_pixel);
952 memlen = var->xres_virtual * var->bits_per_pixel *
953 var->yres_virtual / 8;
954 }
955
956 /* we must round yres/xres down, we already rounded y/xres_virtual up
957 if it was possible. We should return -EINVAL, but I disagree */
958 if (var->yres_virtual < var->yres)
959 var->yres = var->yres_virtual;
960 if (var->xres_virtual < var->xres)
961 var->xres = var->xres_virtual;
962 if (var->xoffset + var->xres > var->xres_virtual)
963 var->xoffset = var->xres_virtual - var->xres;
964 if (var->yoffset + var->yres > var->yres_virtual)
965 var->yoffset = var->yres_virtual - var->yres;
966
967 return 0;
968 }
969
970
savagefb_decode_var(struct fb_var_screeninfo * var,struct savagefb_par * par,struct savage_reg * reg)971 static int savagefb_decode_var(struct fb_var_screeninfo *var,
972 struct savagefb_par *par,
973 struct savage_reg *reg)
974 {
975 struct xtimings timings;
976 int width, dclk, i, j; /*, refresh; */
977 unsigned int m, n, r;
978 unsigned char tmp = 0;
979 unsigned int pixclock = var->pixclock;
980
981 DBG("savagefb_decode_var");
982
983 memset(&timings, 0, sizeof(timings));
984
985 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
986 timings.Clock = 1000000000 / pixclock;
987 if (timings.Clock < 1) timings.Clock = 1;
988 timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
989 timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
990 timings.HDisplay = var->xres;
991 timings.HSyncStart = timings.HDisplay + var->right_margin;
992 timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
993 timings.HTotal = timings.HSyncEnd + var->left_margin;
994 timings.VDisplay = var->yres;
995 timings.VSyncStart = timings.VDisplay + var->lower_margin;
996 timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
997 timings.VTotal = timings.VSyncEnd + var->upper_margin;
998 timings.sync = var->sync;
999
1000
1001 par->depth = var->bits_per_pixel;
1002 par->vwidth = var->xres_virtual;
1003
1004 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
1005 timings.HDisplay *= 2;
1006 timings.HSyncStart *= 2;
1007 timings.HSyncEnd *= 2;
1008 timings.HTotal *= 2;
1009 }
1010
1011 /*
1012 * This will allocate the datastructure and initialize all of the
1013 * generic VGA registers.
1014 */
1015 vgaHWInit(var, par, &timings, reg);
1016
1017 /* We need to set CR67 whether or not we use the BIOS. */
1018
1019 dclk = timings.Clock;
1020 reg->CR67 = 0x00;
1021
1022 switch(var->bits_per_pixel) {
1023 case 8:
1024 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1025 reg->CR67 = 0x10; /* 8bpp, 2 pixels/clock */
1026 else
1027 reg->CR67 = 0x00; /* 8bpp, 1 pixel/clock */
1028 break;
1029 case 15:
1030 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1031 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1032 reg->CR67 = 0x30; /* 15bpp, 2 pixel/clock */
1033 else
1034 reg->CR67 = 0x20; /* 15bpp, 1 pixels/clock */
1035 break;
1036 case 16:
1037 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1038 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1039 reg->CR67 = 0x50; /* 16bpp, 2 pixel/clock */
1040 else
1041 reg->CR67 = 0x40; /* 16bpp, 1 pixels/clock */
1042 break;
1043 case 24:
1044 reg->CR67 = 0x70;
1045 break;
1046 case 32:
1047 reg->CR67 = 0xd0;
1048 break;
1049 }
1050
1051 /*
1052 * Either BIOS use is disabled, or we failed to find a suitable
1053 * match. Fall back to traditional register-crunching.
1054 */
1055
1056 vga_out8(0x3d4, 0x3a, par);
1057 tmp = vga_in8(0x3d5, par);
1058 if (1 /*FIXME:psav->pci_burst*/)
1059 reg->CR3A = (tmp & 0x7f) | 0x15;
1060 else
1061 reg->CR3A = tmp | 0x95;
1062
1063 reg->CR53 = 0x00;
1064 reg->CR31 = 0x8c;
1065 reg->CR66 = 0x89;
1066
1067 vga_out8(0x3d4, 0x58, par);
1068 reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1069 reg->CR58 |= 0x13;
1070
1071 reg->SR15 = 0x03 | 0x80;
1072 reg->SR18 = 0x00;
1073 reg->CR43 = reg->CR45 = reg->CR65 = 0x00;
1074
1075 vga_out8(0x3d4, 0x40, par);
1076 reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1077
1078 reg->MMPR0 = 0x010400;
1079 reg->MMPR1 = 0x00;
1080 reg->MMPR2 = 0x0808;
1081 reg->MMPR3 = 0x08080810;
1082
1083 SavageCalcClock(dclk, 1, 1, 127, 0, 4, 180000, 360000, &m, &n, &r);
1084 /* m = 107; n = 4; r = 2; */
1085
1086 if (par->MCLK <= 0) {
1087 reg->SR10 = 255;
1088 reg->SR11 = 255;
1089 } else {
1090 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1091 ®->SR11, ®->SR10);
1092 /* reg->SR10 = 80; // MCLK == 286000 */
1093 /* reg->SR11 = 125; */
1094 }
1095
1096 reg->SR12 = (r << 6) | (n & 0x3f);
1097 reg->SR13 = m & 0xff;
1098 reg->SR29 = (r & 4) | (m & 0x100) >> 5 | (n & 0x40) >> 2;
1099
1100 if (var->bits_per_pixel < 24)
1101 reg->MMPR0 -= 0x8000;
1102 else
1103 reg->MMPR0 -= 0x4000;
1104
1105 if (timings.interlaced)
1106 reg->CR42 = 0x20;
1107 else
1108 reg->CR42 = 0x00;
1109
1110 reg->CR34 = 0x10; /* display fifo */
1111
1112 i = ((((timings.HTotal >> 3) - 5) & 0x100) >> 8) |
1113 ((((timings.HDisplay >> 3) - 1) & 0x100) >> 7) |
1114 ((((timings.HSyncStart >> 3) - 1) & 0x100) >> 6) |
1115 ((timings.HSyncStart & 0x800) >> 7);
1116
1117 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 64)
1118 i |= 0x08;
1119 if ((timings.HSyncEnd >> 3) - (timings.HSyncStart >> 3) > 32)
1120 i |= 0x20;
1121
1122 j = (reg->CRTC[0] + ((i & 0x01) << 8) +
1123 reg->CRTC[4] + ((i & 0x10) << 4) + 1) / 2;
1124
1125 if (j - (reg->CRTC[4] + ((i & 0x10) << 4)) < 4) {
1126 if (reg->CRTC[4] + ((i & 0x10) << 4) + 4 <=
1127 reg->CRTC[0] + ((i & 0x01) << 8))
1128 j = reg->CRTC[4] + ((i & 0x10) << 4) + 4;
1129 else
1130 j = reg->CRTC[0] + ((i & 0x01) << 8) + 1;
1131 }
1132
1133 reg->CR3B = j & 0xff;
1134 i |= (j & 0x100) >> 2;
1135 reg->CR3C = (reg->CRTC[0] + ((i & 0x01) << 8)) / 2;
1136 reg->CR5D = i;
1137 reg->CR5E = (((timings.VTotal - 2) & 0x400) >> 10) |
1138 (((timings.VDisplay - 1) & 0x400) >> 9) |
1139 (((timings.VSyncStart) & 0x400) >> 8) |
1140 (((timings.VSyncStart) & 0x400) >> 6) | 0x40;
1141 width = (var->xres_virtual * ((var->bits_per_pixel+7) / 8)) >> 3;
1142 reg->CR91 = reg->CRTC[19] = 0xff & width;
1143 reg->CR51 = (0x300 & width) >> 4;
1144 reg->CR90 = 0x80 | (width >> 8);
1145 reg->MiscOutReg |= 0x0c;
1146
1147 /* Set frame buffer description. */
1148
1149 if (var->bits_per_pixel <= 8)
1150 reg->CR50 = 0;
1151 else if (var->bits_per_pixel <= 16)
1152 reg->CR50 = 0x10;
1153 else
1154 reg->CR50 = 0x30;
1155
1156 if (var->xres_virtual <= 640)
1157 reg->CR50 |= 0x40;
1158 else if (var->xres_virtual == 800)
1159 reg->CR50 |= 0x80;
1160 else if (var->xres_virtual == 1024)
1161 reg->CR50 |= 0x00;
1162 else if (var->xres_virtual == 1152)
1163 reg->CR50 |= 0x01;
1164 else if (var->xres_virtual == 1280)
1165 reg->CR50 |= 0xc0;
1166 else if (var->xres_virtual == 1600)
1167 reg->CR50 |= 0x81;
1168 else
1169 reg->CR50 |= 0xc1; /* Use GBD */
1170
1171 if (par->chip == S3_SAVAGE2000)
1172 reg->CR33 = 0x08;
1173 else
1174 reg->CR33 = 0x20;
1175
1176 reg->CRTC[0x17] = 0xeb;
1177
1178 reg->CR67 |= 1;
1179
1180 vga_out8(0x3d4, 0x36, par);
1181 reg->CR36 = vga_in8(0x3d5, par);
1182 vga_out8(0x3d4, 0x68, par);
1183 reg->CR68 = vga_in8(0x3d5, par);
1184 reg->CR69 = 0;
1185 vga_out8(0x3d4, 0x6f, par);
1186 reg->CR6F = vga_in8(0x3d5, par);
1187 vga_out8(0x3d4, 0x86, par);
1188 reg->CR86 = vga_in8(0x3d5, par);
1189 vga_out8(0x3d4, 0x88, par);
1190 reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1191 vga_out8(0x3d4, 0xb0, par);
1192 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1193
1194 return 0;
1195 }
1196
1197 /* --------------------------------------------------------------------- */
1198
1199 /*
1200 * Set a single color register. Return != 0 for invalid regno.
1201 */
savagefb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1202 static int savagefb_setcolreg(unsigned regno,
1203 unsigned red,
1204 unsigned green,
1205 unsigned blue,
1206 unsigned transp,
1207 struct fb_info *info)
1208 {
1209 struct savagefb_par *par = info->par;
1210
1211 if (regno >= NR_PALETTE)
1212 return -EINVAL;
1213
1214 par->palette[regno].red = red;
1215 par->palette[regno].green = green;
1216 par->palette[regno].blue = blue;
1217 par->palette[regno].transp = transp;
1218
1219 switch (info->var.bits_per_pixel) {
1220 case 8:
1221 vga_out8(0x3c8, regno, par);
1222
1223 vga_out8(0x3c9, red >> 10, par);
1224 vga_out8(0x3c9, green >> 10, par);
1225 vga_out8(0x3c9, blue >> 10, par);
1226 break;
1227
1228 case 16:
1229 if (regno < 16)
1230 ((u32 *)info->pseudo_palette)[regno] =
1231 ((red & 0xf800) ) |
1232 ((green & 0xfc00) >> 5) |
1233 ((blue & 0xf800) >> 11);
1234 break;
1235
1236 case 24:
1237 if (regno < 16)
1238 ((u32 *)info->pseudo_palette)[regno] =
1239 ((red & 0xff00) << 8) |
1240 ((green & 0xff00) ) |
1241 ((blue & 0xff00) >> 8);
1242 break;
1243 case 32:
1244 if (regno < 16)
1245 ((u32 *)info->pseudo_palette)[regno] =
1246 ((transp & 0xff00) << 16) |
1247 ((red & 0xff00) << 8) |
1248 ((green & 0xff00) ) |
1249 ((blue & 0xff00) >> 8);
1250 break;
1251
1252 default:
1253 return 1;
1254 }
1255
1256 return 0;
1257 }
1258
savagefb_set_par_int(struct savagefb_par * par,struct savage_reg * reg)1259 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
1260 {
1261 unsigned char tmp, cr3a, cr66, cr67;
1262
1263 DBG("savagefb_set_par_int");
1264
1265 par->SavageWaitIdle(par);
1266
1267 vga_out8(0x3c2, 0x23, par);
1268
1269 vga_out16(0x3d4, 0x4838, par);
1270 vga_out16(0x3d4, 0xa539, par);
1271 vga_out16(0x3c4, 0x0608, par);
1272
1273 vgaHWProtect(par, 1);
1274
1275 /*
1276 * Some Savage/MX and /IX systems go nuts when trying to exit the
1277 * server after WindowMaker has displayed a gradient background. I
1278 * haven't been able to find what causes it, but a non-destructive
1279 * switch to mode 3 here seems to eliminate the issue.
1280 */
1281
1282 VerticalRetraceWait(par);
1283 vga_out8(0x3d4, 0x67, par);
1284 cr67 = vga_in8(0x3d5, par);
1285 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1286
1287 vga_out8(0x3d4, 0x23, par);
1288 vga_out8(0x3d5, 0x00, par);
1289 vga_out8(0x3d4, 0x26, par);
1290 vga_out8(0x3d5, 0x00, par);
1291
1292 /* restore extended regs */
1293 vga_out8(0x3d4, 0x66, par);
1294 vga_out8(0x3d5, reg->CR66, par);
1295 vga_out8(0x3d4, 0x3a, par);
1296 vga_out8(0x3d5, reg->CR3A, par);
1297 vga_out8(0x3d4, 0x31, par);
1298 vga_out8(0x3d5, reg->CR31, par);
1299 vga_out8(0x3d4, 0x32, par);
1300 vga_out8(0x3d5, reg->CR32, par);
1301 vga_out8(0x3d4, 0x58, par);
1302 vga_out8(0x3d5, reg->CR58, par);
1303 vga_out8(0x3d4, 0x53, par);
1304 vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1305
1306 vga_out16(0x3c4, 0x0608, par);
1307
1308 /* Restore DCLK registers. */
1309
1310 vga_out8(0x3c4, 0x0e, par);
1311 vga_out8(0x3c5, reg->SR0E, par);
1312 vga_out8(0x3c4, 0x0f, par);
1313 vga_out8(0x3c5, reg->SR0F, par);
1314 vga_out8(0x3c4, 0x29, par);
1315 vga_out8(0x3c5, reg->SR29, par);
1316 vga_out8(0x3c4, 0x15, par);
1317 vga_out8(0x3c5, reg->SR15, par);
1318
1319 /* Restore flat panel expansion registers. */
1320 if (par->chip == S3_SAVAGE_MX) {
1321 int i;
1322
1323 for (i = 0; i < 8; i++) {
1324 vga_out8(0x3c4, 0x54+i, par);
1325 vga_out8(0x3c5, reg->SR54[i], par);
1326 }
1327 }
1328
1329 vgaHWRestore (par, reg);
1330
1331 /* extended mode timing registers */
1332 vga_out8(0x3d4, 0x53, par);
1333 vga_out8(0x3d5, reg->CR53, par);
1334 vga_out8(0x3d4, 0x5d, par);
1335 vga_out8(0x3d5, reg->CR5D, par);
1336 vga_out8(0x3d4, 0x5e, par);
1337 vga_out8(0x3d5, reg->CR5E, par);
1338 vga_out8(0x3d4, 0x3b, par);
1339 vga_out8(0x3d5, reg->CR3B, par);
1340 vga_out8(0x3d4, 0x3c, par);
1341 vga_out8(0x3d5, reg->CR3C, par);
1342 vga_out8(0x3d4, 0x43, par);
1343 vga_out8(0x3d5, reg->CR43, par);
1344 vga_out8(0x3d4, 0x65, par);
1345 vga_out8(0x3d5, reg->CR65, par);
1346
1347 /* restore the desired video mode with cr67 */
1348 vga_out8(0x3d4, 0x67, par);
1349 /* following part not present in X11 driver */
1350 cr67 = vga_in8(0x3d5, par) & 0xf;
1351 vga_out8(0x3d5, 0x50 | cr67, par);
1352 mdelay(10);
1353 vga_out8(0x3d4, 0x67, par);
1354 /* end of part */
1355 vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1356
1357 /* other mode timing and extended regs */
1358 vga_out8(0x3d4, 0x34, par);
1359 vga_out8(0x3d5, reg->CR34, par);
1360 vga_out8(0x3d4, 0x40, par);
1361 vga_out8(0x3d5, reg->CR40, par);
1362 vga_out8(0x3d4, 0x42, par);
1363 vga_out8(0x3d5, reg->CR42, par);
1364 vga_out8(0x3d4, 0x45, par);
1365 vga_out8(0x3d5, reg->CR45, par);
1366 vga_out8(0x3d4, 0x50, par);
1367 vga_out8(0x3d5, reg->CR50, par);
1368 vga_out8(0x3d4, 0x51, par);
1369 vga_out8(0x3d5, reg->CR51, par);
1370
1371 /* memory timings */
1372 vga_out8(0x3d4, 0x36, par);
1373 vga_out8(0x3d5, reg->CR36, par);
1374 vga_out8(0x3d4, 0x60, par);
1375 vga_out8(0x3d5, reg->CR60, par);
1376 vga_out8(0x3d4, 0x68, par);
1377 vga_out8(0x3d5, reg->CR68, par);
1378 vga_out8(0x3d4, 0x69, par);
1379 vga_out8(0x3d5, reg->CR69, par);
1380 vga_out8(0x3d4, 0x6f, par);
1381 vga_out8(0x3d5, reg->CR6F, par);
1382
1383 vga_out8(0x3d4, 0x33, par);
1384 vga_out8(0x3d5, reg->CR33, par);
1385 vga_out8(0x3d4, 0x86, par);
1386 vga_out8(0x3d5, reg->CR86, par);
1387 vga_out8(0x3d4, 0x88, par);
1388 vga_out8(0x3d5, reg->CR88, par);
1389 vga_out8(0x3d4, 0x90, par);
1390 vga_out8(0x3d5, reg->CR90, par);
1391 vga_out8(0x3d4, 0x91, par);
1392 vga_out8(0x3d5, reg->CR91, par);
1393
1394 if (par->chip == S3_SAVAGE4) {
1395 vga_out8(0x3d4, 0xb0, par);
1396 vga_out8(0x3d5, reg->CRB0, par);
1397 }
1398
1399 vga_out8(0x3d4, 0x32, par);
1400 vga_out8(0x3d5, reg->CR32, par);
1401
1402 /* unlock extended seq regs */
1403 vga_out8(0x3c4, 0x08, par);
1404 vga_out8(0x3c5, 0x06, par);
1405
1406 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1407 * that we should leave the default SR10 and SR11 values there.
1408 */
1409 if (reg->SR10 != 255) {
1410 vga_out8(0x3c4, 0x10, par);
1411 vga_out8(0x3c5, reg->SR10, par);
1412 vga_out8(0x3c4, 0x11, par);
1413 vga_out8(0x3c5, reg->SR11, par);
1414 }
1415
1416 /* restore extended seq regs for dclk */
1417 vga_out8(0x3c4, 0x0e, par);
1418 vga_out8(0x3c5, reg->SR0E, par);
1419 vga_out8(0x3c4, 0x0f, par);
1420 vga_out8(0x3c5, reg->SR0F, par);
1421 vga_out8(0x3c4, 0x12, par);
1422 vga_out8(0x3c5, reg->SR12, par);
1423 vga_out8(0x3c4, 0x13, par);
1424 vga_out8(0x3c5, reg->SR13, par);
1425 vga_out8(0x3c4, 0x29, par);
1426 vga_out8(0x3c5, reg->SR29, par);
1427 vga_out8(0x3c4, 0x18, par);
1428 vga_out8(0x3c5, reg->SR18, par);
1429
1430 /* load new m, n pll values for dclk & mclk */
1431 vga_out8(0x3c4, 0x15, par);
1432 tmp = vga_in8(0x3c5, par) & ~0x21;
1433
1434 vga_out8(0x3c5, tmp | 0x03, par);
1435 vga_out8(0x3c5, tmp | 0x23, par);
1436 vga_out8(0x3c5, tmp | 0x03, par);
1437 vga_out8(0x3c5, reg->SR15, par);
1438 udelay(100);
1439
1440 vga_out8(0x3c4, 0x30, par);
1441 vga_out8(0x3c5, reg->SR30, par);
1442 vga_out8(0x3c4, 0x08, par);
1443 vga_out8(0x3c5, reg->SR08, par);
1444
1445 /* now write out cr67 in full, possibly starting STREAMS */
1446 VerticalRetraceWait(par);
1447 vga_out8(0x3d4, 0x67, par);
1448 vga_out8(0x3d5, reg->CR67, par);
1449
1450 vga_out8(0x3d4, 0x66, par);
1451 cr66 = vga_in8(0x3d5, par);
1452 vga_out8(0x3d5, cr66 | 0x80, par);
1453 vga_out8(0x3d4, 0x3a, par);
1454 cr3a = vga_in8(0x3d5, par);
1455 vga_out8(0x3d5, cr3a | 0x80, par);
1456
1457 if (par->chip != S3_SAVAGE_MX) {
1458 VerticalRetraceWait(par);
1459 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1460 par->SavageWaitIdle(par);
1461 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1462 par->SavageWaitIdle(par);
1463 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1464 par->SavageWaitIdle(par);
1465 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1466 }
1467
1468 vga_out8(0x3d4, 0x66, par);
1469 vga_out8(0x3d5, cr66, par);
1470 vga_out8(0x3d4, 0x3a, par);
1471 vga_out8(0x3d5, cr3a, par);
1472
1473 SavageSetup2DEngine(par);
1474 vgaHWProtect(par, 0);
1475 }
1476
savagefb_update_start(struct savagefb_par * par,int base)1477 static void savagefb_update_start(struct savagefb_par *par, int base)
1478 {
1479 /* program the start address registers */
1480 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1481 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1482 vga_out8(0x3d4, 0x69, par);
1483 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1484 }
1485
1486
savagefb_set_fix(struct fb_info * info)1487 static void savagefb_set_fix(struct fb_info *info)
1488 {
1489 info->fix.line_length = info->var.xres_virtual *
1490 info->var.bits_per_pixel / 8;
1491
1492 if (info->var.bits_per_pixel == 8) {
1493 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1494 info->fix.xpanstep = 4;
1495 } else {
1496 info->fix.visual = FB_VISUAL_TRUECOLOR;
1497 info->fix.xpanstep = 2;
1498 }
1499
1500 }
1501
savagefb_set_par(struct fb_info * info)1502 static int savagefb_set_par(struct fb_info *info)
1503 {
1504 struct savagefb_par *par = info->par;
1505 struct fb_var_screeninfo *var = &info->var;
1506 int err;
1507
1508 DBG("savagefb_set_par");
1509 err = savagefb_decode_var(var, par, &par->state);
1510 if (err)
1511 return err;
1512
1513 if (par->dacSpeedBpp <= 0) {
1514 if (var->bits_per_pixel > 24)
1515 par->dacSpeedBpp = par->clock[3];
1516 else if (var->bits_per_pixel >= 24)
1517 par->dacSpeedBpp = par->clock[2];
1518 else if ((var->bits_per_pixel > 8) && (var->bits_per_pixel < 24))
1519 par->dacSpeedBpp = par->clock[1];
1520 else if (var->bits_per_pixel <= 8)
1521 par->dacSpeedBpp = par->clock[0];
1522 }
1523
1524 /* Set ramdac limits */
1525 par->maxClock = par->dacSpeedBpp;
1526 par->minClock = 10000;
1527
1528 savagefb_set_par_int(par, &par->state);
1529 fb_set_cmap(&info->cmap, info);
1530 savagefb_set_fix(info);
1531 savagefb_set_clip(info);
1532
1533 SavagePrintRegs(par);
1534 return 0;
1535 }
1536
1537 /*
1538 * Pan or Wrap the Display
1539 */
savagefb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1540 static int savagefb_pan_display(struct fb_var_screeninfo *var,
1541 struct fb_info *info)
1542 {
1543 struct savagefb_par *par = info->par;
1544 int base;
1545
1546 base = (var->yoffset * info->fix.line_length
1547 + (var->xoffset & ~1) * ((info->var.bits_per_pixel+7) / 8)) >> 2;
1548
1549 savagefb_update_start(par, base);
1550 return 0;
1551 }
1552
savagefb_blank(int blank,struct fb_info * info)1553 static int savagefb_blank(int blank, struct fb_info *info)
1554 {
1555 struct savagefb_par *par = info->par;
1556 u8 sr8 = 0, srd = 0;
1557
1558 if (par->display_type == DISP_CRT) {
1559 vga_out8(0x3c4, 0x08, par);
1560 sr8 = vga_in8(0x3c5, par);
1561 sr8 |= 0x06;
1562 vga_out8(0x3c5, sr8, par);
1563 vga_out8(0x3c4, 0x0d, par);
1564 srd = vga_in8(0x3c5, par);
1565 srd &= 0x50;
1566
1567 switch (blank) {
1568 case FB_BLANK_UNBLANK:
1569 case FB_BLANK_NORMAL:
1570 break;
1571 case FB_BLANK_VSYNC_SUSPEND:
1572 srd |= 0x10;
1573 break;
1574 case FB_BLANK_HSYNC_SUSPEND:
1575 srd |= 0x40;
1576 break;
1577 case FB_BLANK_POWERDOWN:
1578 srd |= 0x50;
1579 break;
1580 }
1581
1582 vga_out8(0x3c4, 0x0d, par);
1583 vga_out8(0x3c5, srd, par);
1584 }
1585
1586 if (par->display_type == DISP_LCD ||
1587 par->display_type == DISP_DFP) {
1588 switch(blank) {
1589 case FB_BLANK_UNBLANK:
1590 case FB_BLANK_NORMAL:
1591 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1592 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1593 break;
1594 case FB_BLANK_VSYNC_SUSPEND:
1595 case FB_BLANK_HSYNC_SUSPEND:
1596 case FB_BLANK_POWERDOWN:
1597 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1598 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1599 break;
1600 }
1601 }
1602
1603 return (blank == FB_BLANK_NORMAL) ? 1 : 0;
1604 }
1605
savagefb_open(struct fb_info * info,int user)1606 static int savagefb_open(struct fb_info *info, int user)
1607 {
1608 struct savagefb_par *par = info->par;
1609
1610 mutex_lock(&par->open_lock);
1611
1612 if (!par->open_count) {
1613 memset(&par->vgastate, 0, sizeof(par->vgastate));
1614 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
1615 VGA_SAVE_MODE;
1616 par->vgastate.vgabase = par->mmio.vbase + 0x8000;
1617 save_vga(&par->vgastate);
1618 savage_get_default_par(par, &par->initial);
1619 }
1620
1621 par->open_count++;
1622 mutex_unlock(&par->open_lock);
1623 return 0;
1624 }
1625
savagefb_release(struct fb_info * info,int user)1626 static int savagefb_release(struct fb_info *info, int user)
1627 {
1628 struct savagefb_par *par = info->par;
1629
1630 mutex_lock(&par->open_lock);
1631
1632 if (par->open_count == 1) {
1633 savage_set_default_par(par, &par->initial);
1634 restore_vga(&par->vgastate);
1635 }
1636
1637 par->open_count--;
1638 mutex_unlock(&par->open_lock);
1639 return 0;
1640 }
1641
1642 static const struct fb_ops savagefb_ops = {
1643 .owner = THIS_MODULE,
1644 .fb_open = savagefb_open,
1645 .fb_release = savagefb_release,
1646 .fb_check_var = savagefb_check_var,
1647 .fb_set_par = savagefb_set_par,
1648 .fb_setcolreg = savagefb_setcolreg,
1649 .fb_pan_display = savagefb_pan_display,
1650 .fb_blank = savagefb_blank,
1651 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1652 .fb_fillrect = savagefb_fillrect,
1653 .fb_copyarea = savagefb_copyarea,
1654 .fb_imageblit = savagefb_imageblit,
1655 .fb_sync = savagefb_sync,
1656 #else
1657 .fb_fillrect = cfb_fillrect,
1658 .fb_copyarea = cfb_copyarea,
1659 .fb_imageblit = cfb_imageblit,
1660 #endif
1661 };
1662
1663 /* --------------------------------------------------------------------- */
1664
1665 static const struct fb_var_screeninfo savagefb_var800x600x8 = {
1666 .accel_flags = FB_ACCELF_TEXT,
1667 .xres = 800,
1668 .yres = 600,
1669 .xres_virtual = 800,
1670 .yres_virtual = 600,
1671 .bits_per_pixel = 8,
1672 .pixclock = 25000,
1673 .left_margin = 88,
1674 .right_margin = 40,
1675 .upper_margin = 23,
1676 .lower_margin = 1,
1677 .hsync_len = 128,
1678 .vsync_len = 4,
1679 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
1680 .vmode = FB_VMODE_NONINTERLACED
1681 };
1682
savage_enable_mmio(struct savagefb_par * par)1683 static void savage_enable_mmio(struct savagefb_par *par)
1684 {
1685 unsigned char val;
1686
1687 DBG("savage_enable_mmio\n");
1688
1689 val = vga_in8(0x3c3, par);
1690 vga_out8(0x3c3, val | 0x01, par);
1691 val = vga_in8(0x3cc, par);
1692 vga_out8(0x3c2, val | 0x01, par);
1693
1694 if (par->chip >= S3_SAVAGE4) {
1695 vga_out8(0x3d4, 0x40, par);
1696 val = vga_in8(0x3d5, par);
1697 vga_out8(0x3d5, val | 1, par);
1698 }
1699 }
1700
1701
savage_disable_mmio(struct savagefb_par * par)1702 static void savage_disable_mmio(struct savagefb_par *par)
1703 {
1704 unsigned char val;
1705
1706 DBG("savage_disable_mmio\n");
1707
1708 if (par->chip >= S3_SAVAGE4) {
1709 vga_out8(0x3d4, 0x40, par);
1710 val = vga_in8(0x3d5, par);
1711 vga_out8(0x3d5, val | 1, par);
1712 }
1713 }
1714
1715
savage_map_mmio(struct fb_info * info)1716 static int savage_map_mmio(struct fb_info *info)
1717 {
1718 struct savagefb_par *par = info->par;
1719 DBG("savage_map_mmio");
1720
1721 if (S3_SAVAGE3D_SERIES(par->chip))
1722 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1723 SAVAGE_NEWMMIO_REGBASE_S3;
1724 else
1725 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1726 SAVAGE_NEWMMIO_REGBASE_S4;
1727
1728 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1729
1730 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1731 if (!par->mmio.vbase) {
1732 printk("savagefb: unable to map memory mapped IO\n");
1733 return -ENOMEM;
1734 } else
1735 printk(KERN_INFO "savagefb: mapped io at %p\n",
1736 par->mmio.vbase);
1737
1738 info->fix.mmio_start = par->mmio.pbase;
1739 info->fix.mmio_len = par->mmio.len;
1740
1741 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1742 par->bci_ptr = 0;
1743
1744 savage_enable_mmio(par);
1745
1746 return 0;
1747 }
1748
savage_unmap_mmio(struct fb_info * info)1749 static void savage_unmap_mmio(struct fb_info *info)
1750 {
1751 struct savagefb_par *par = info->par;
1752 DBG("savage_unmap_mmio");
1753
1754 savage_disable_mmio(par);
1755
1756 if (par->mmio.vbase) {
1757 iounmap(par->mmio.vbase);
1758 par->mmio.vbase = NULL;
1759 }
1760 }
1761
savage_map_video(struct fb_info * info,int video_len)1762 static int savage_map_video(struct fb_info *info, int video_len)
1763 {
1764 struct savagefb_par *par = info->par;
1765 int resource;
1766
1767 DBG("savage_map_video");
1768
1769 if (S3_SAVAGE3D_SERIES(par->chip))
1770 resource = 0;
1771 else
1772 resource = 1;
1773
1774 par->video.pbase = pci_resource_start(par->pcidev, resource);
1775 par->video.len = video_len;
1776 par->video.vbase = ioremap_wc(par->video.pbase, par->video.len);
1777
1778 if (!par->video.vbase) {
1779 printk("savagefb: unable to map screen memory\n");
1780 return -ENOMEM;
1781 } else
1782 printk(KERN_INFO "savagefb: mapped framebuffer at %p, "
1783 "pbase == %x\n", par->video.vbase, par->video.pbase);
1784
1785 info->fix.smem_start = par->video.pbase;
1786 info->fix.smem_len = par->video.len - par->cob_size;
1787 info->screen_base = par->video.vbase;
1788 par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len);
1789
1790 /* Clear framebuffer, it's all white in memory after boot */
1791 memset_io(par->video.vbase, 0, par->video.len);
1792
1793 return 0;
1794 }
1795
savage_unmap_video(struct fb_info * info)1796 static void savage_unmap_video(struct fb_info *info)
1797 {
1798 struct savagefb_par *par = info->par;
1799
1800 DBG("savage_unmap_video");
1801
1802 if (par->video.vbase) {
1803 arch_phys_wc_del(par->video.wc_cookie);
1804 iounmap(par->video.vbase);
1805 par->video.vbase = NULL;
1806 info->screen_base = NULL;
1807 }
1808 }
1809
savage_init_hw(struct savagefb_par * par)1810 static int savage_init_hw(struct savagefb_par *par)
1811 {
1812 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp;
1813
1814 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 };
1815 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
1816 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1817 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1818 int videoRam, videoRambytes, dvi;
1819
1820 DBG("savage_init_hw");
1821
1822 /* unprotect CRTC[0-7] */
1823 vga_out8(0x3d4, 0x11, par);
1824 tmp = vga_in8(0x3d5, par);
1825 vga_out8(0x3d5, tmp & 0x7f, par);
1826
1827 /* unlock extended regs */
1828 vga_out16(0x3d4, 0x4838, par);
1829 vga_out16(0x3d4, 0xa039, par);
1830 vga_out16(0x3c4, 0x0608, par);
1831
1832 vga_out8(0x3d4, 0x40, par);
1833 tmp = vga_in8(0x3d5, par);
1834 vga_out8(0x3d5, tmp & ~0x01, par);
1835
1836 /* unlock sys regs */
1837 vga_out8(0x3d4, 0x38, par);
1838 vga_out8(0x3d5, 0x48, par);
1839
1840 /* Unlock system registers. */
1841 vga_out16(0x3d4, 0x4838, par);
1842
1843 /* Next go on to detect amount of installed ram */
1844
1845 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1846 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1847
1848 /* Compute the amount of video memory and offscreen memory. */
1849
1850 switch (par->chip) {
1851 case S3_SAVAGE3D:
1852 videoRam = RamSavage3D[(config1 & 0xC0) >> 6 ] * 1024;
1853 break;
1854
1855 case S3_SAVAGE4:
1856 /*
1857 * The Savage4 has one ugly special case to consider. On
1858 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1859 * when it really means 8MB. Why do it the same when you
1860 * can do it different...
1861 */
1862 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1863 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1864 RamSavage4[1] = 8;
1865 fallthrough;
1866
1867 case S3_SAVAGE2000:
1868 videoRam = RamSavage4[(config1 & 0xE0) >> 5] * 1024;
1869 break;
1870
1871 case S3_SAVAGE_MX:
1872 case S3_SUPERSAVAGE:
1873 videoRam = RamSavageMX[(config1 & 0x0E) >> 1] * 1024;
1874 break;
1875
1876 case S3_PROSAVAGE:
1877 case S3_PROSAVAGEDDR:
1878 case S3_TWISTER:
1879 videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
1880 break;
1881
1882 default:
1883 /* How did we get here? */
1884 videoRam = 0;
1885 break;
1886 }
1887
1888 videoRambytes = videoRam * 1024;
1889
1890 printk(KERN_INFO "savagefb: probed videoram: %dk\n", videoRam);
1891
1892 /* reset graphics engine to avoid memory corruption */
1893 vga_out8(0x3d4, 0x66, par);
1894 cr66 = vga_in8(0x3d5, par);
1895 vga_out8(0x3d5, cr66 | 0x02, par);
1896 usleep_range(10000, 11000);
1897
1898 vga_out8(0x3d4, 0x66, par);
1899 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1900 usleep_range(10000, 11000);
1901
1902
1903 /*
1904 * reset memory interface, 3D engine, AGP master, PCI master,
1905 * master engine unit, motion compensation/LPB
1906 */
1907 vga_out8(0x3d4, 0x3f, par);
1908 cr3f = vga_in8(0x3d5, par);
1909 vga_out8(0x3d5, cr3f | 0x08, par);
1910 usleep_range(10000, 11000);
1911
1912 vga_out8(0x3d4, 0x3f, par);
1913 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1914 usleep_range(10000, 11000);
1915
1916 /* Savage ramdac speeds */
1917 par->numClocks = 4;
1918 par->clock[0] = 250000;
1919 par->clock[1] = 250000;
1920 par->clock[2] = 220000;
1921 par->clock[3] = 220000;
1922
1923 /* detect current mclk */
1924 vga_out8(0x3c4, 0x08, par);
1925 sr8 = vga_in8(0x3c5, par);
1926 vga_out8(0x3c5, 0x06, par);
1927 vga_out8(0x3c4, 0x10, par);
1928 n = vga_in8(0x3c5, par);
1929 vga_out8(0x3c4, 0x11, par);
1930 m = vga_in8(0x3c5, par);
1931 vga_out8(0x3c4, 0x08, par);
1932 vga_out8(0x3c5, sr8, par);
1933 m &= 0x7f;
1934 n1 = n & 0x1f;
1935 n2 = (n >> 5) & 0x03;
1936 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1937 printk(KERN_INFO "savagefb: Detected current MCLK value of %d kHz\n",
1938 par->MCLK);
1939
1940 /* check for DVI/flat panel */
1941 dvi = 0;
1942
1943 if (par->chip == S3_SAVAGE4) {
1944 unsigned char sr30 = 0x00;
1945
1946 vga_out8(0x3c4, 0x30, par);
1947 /* clear bit 1 */
1948 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1949 sr30 = vga_in8(0x3c5, par);
1950 if (sr30 & 0x02 /*0x04 */) {
1951 dvi = 1;
1952 printk("savagefb: Digital Flat Panel Detected\n");
1953 }
1954 }
1955
1956 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1957 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1958 par->display_type = DISP_LCD;
1959 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1960 par->display_type = DISP_DFP;
1961 else
1962 par->display_type = DISP_CRT;
1963
1964 /* Check LCD panel parrmation */
1965
1966 if (par->display_type == DISP_LCD) {
1967 unsigned char cr6b = VGArCR(0x6b, par);
1968
1969 int panelX = (VGArSEQ(0x61, par) +
1970 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1971 int panelY = (VGArSEQ(0x69, par) +
1972 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1973
1974 char * sTechnology = "Unknown";
1975
1976 /* OK, I admit it. I don't know how to limit the max dot clock
1977 * for LCD panels of various sizes. I thought I copied the
1978 * formula from the BIOS, but many users have parrmed me of
1979 * my folly.
1980 *
1981 * Instead, I'll abandon any attempt to automatically limit the
1982 * clock, and add an LCDClock option to XF86Config. Some day,
1983 * I should come back to this.
1984 */
1985
1986 enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */
1987 ActiveCRT = 0x01,
1988 ActiveLCD = 0x02,
1989 ActiveTV = 0x04,
1990 ActiveCRT2 = 0x20,
1991 ActiveDUO = 0x80
1992 };
1993
1994 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1995 sTechnology = "TFT";
1996 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
1997 sTechnology = "DSTN";
1998 } else {
1999 sTechnology = "STN";
2000 }
2001
2002 printk(KERN_INFO "savagefb: %dx%d %s LCD panel detected %s\n",
2003 panelX, panelY, sTechnology,
2004 cr6b & ActiveLCD ? "and active" : "but not active");
2005
2006 if (cr6b & ActiveLCD) {
2007 /*
2008 * If the LCD is active and panel expansion is enabled,
2009 * we probably want to kill the HW cursor.
2010 */
2011
2012 printk(KERN_INFO "savagefb: Limiting video mode to "
2013 "%dx%d\n", panelX, panelY);
2014
2015 par->SavagePanelWidth = panelX;
2016 par->SavagePanelHeight = panelY;
2017
2018 } else
2019 par->display_type = DISP_CRT;
2020 }
2021
2022 savage_get_default_par(par, &par->state);
2023 par->save = par->state;
2024
2025 if (S3_SAVAGE4_SERIES(par->chip)) {
2026 /*
2027 * The Savage4 and ProSavage have COB coherency bugs which
2028 * render the buffer useless. We disable it.
2029 */
2030 par->cob_index = 2;
2031 par->cob_size = 0x8000 << par->cob_index;
2032 par->cob_offset = videoRambytes;
2033 } else {
2034 /* We use 128kB for the COB on all chips. */
2035
2036 par->cob_index = 7;
2037 par->cob_size = 0x400 << par->cob_index;
2038 par->cob_offset = videoRambytes - par->cob_size;
2039 }
2040
2041 return videoRambytes;
2042 }
2043
savage_init_fb_info(struct fb_info * info,struct pci_dev * dev,const struct pci_device_id * id)2044 static int savage_init_fb_info(struct fb_info *info, struct pci_dev *dev,
2045 const struct pci_device_id *id)
2046 {
2047 struct savagefb_par *par = info->par;
2048 int err = 0;
2049
2050 par->pcidev = dev;
2051
2052 info->fix.type = FB_TYPE_PACKED_PIXELS;
2053 info->fix.type_aux = 0;
2054 info->fix.ypanstep = 1;
2055 info->fix.ywrapstep = 0;
2056 info->fix.accel = id->driver_data;
2057
2058 switch (info->fix.accel) {
2059 case FB_ACCEL_SUPERSAVAGE:
2060 par->chip = S3_SUPERSAVAGE;
2061 snprintf(info->fix.id, 16, "SuperSavage");
2062 break;
2063 case FB_ACCEL_SAVAGE4:
2064 par->chip = S3_SAVAGE4;
2065 snprintf(info->fix.id, 16, "Savage4");
2066 break;
2067 case FB_ACCEL_SAVAGE3D:
2068 par->chip = S3_SAVAGE3D;
2069 snprintf(info->fix.id, 16, "Savage3D");
2070 break;
2071 case FB_ACCEL_SAVAGE3D_MV:
2072 par->chip = S3_SAVAGE3D;
2073 snprintf(info->fix.id, 16, "Savage3D-MV");
2074 break;
2075 case FB_ACCEL_SAVAGE2000:
2076 par->chip = S3_SAVAGE2000;
2077 snprintf(info->fix.id, 16, "Savage2000");
2078 break;
2079 case FB_ACCEL_SAVAGE_MX_MV:
2080 par->chip = S3_SAVAGE_MX;
2081 snprintf(info->fix.id, 16, "Savage/MX-MV");
2082 break;
2083 case FB_ACCEL_SAVAGE_MX:
2084 par->chip = S3_SAVAGE_MX;
2085 snprintf(info->fix.id, 16, "Savage/MX");
2086 break;
2087 case FB_ACCEL_SAVAGE_IX_MV:
2088 par->chip = S3_SAVAGE_MX;
2089 snprintf(info->fix.id, 16, "Savage/IX-MV");
2090 break;
2091 case FB_ACCEL_SAVAGE_IX:
2092 par->chip = S3_SAVAGE_MX;
2093 snprintf(info->fix.id, 16, "Savage/IX");
2094 break;
2095 case FB_ACCEL_PROSAVAGE_PM:
2096 par->chip = S3_PROSAVAGE;
2097 snprintf(info->fix.id, 16, "ProSavagePM");
2098 break;
2099 case FB_ACCEL_PROSAVAGE_KM:
2100 par->chip = S3_PROSAVAGE;
2101 snprintf(info->fix.id, 16, "ProSavageKM");
2102 break;
2103 case FB_ACCEL_S3TWISTER_P:
2104 par->chip = S3_TWISTER;
2105 snprintf(info->fix.id, 16, "TwisterP");
2106 break;
2107 case FB_ACCEL_S3TWISTER_K:
2108 par->chip = S3_TWISTER;
2109 snprintf(info->fix.id, 16, "TwisterK");
2110 break;
2111 case FB_ACCEL_PROSAVAGE_DDR:
2112 par->chip = S3_PROSAVAGEDDR;
2113 snprintf(info->fix.id, 16, "ProSavageDDR");
2114 break;
2115 case FB_ACCEL_PROSAVAGE_DDRK:
2116 par->chip = S3_PROSAVAGEDDR;
2117 snprintf(info->fix.id, 16, "ProSavage8");
2118 break;
2119 }
2120
2121 if (S3_SAVAGE3D_SERIES(par->chip)) {
2122 par->SavageWaitIdle = savage3D_waitidle;
2123 par->SavageWaitFifo = savage3D_waitfifo;
2124 } else if (S3_SAVAGE4_SERIES(par->chip) ||
2125 S3_SUPERSAVAGE == par->chip) {
2126 par->SavageWaitIdle = savage4_waitidle;
2127 par->SavageWaitFifo = savage4_waitfifo;
2128 } else {
2129 par->SavageWaitIdle = savage2000_waitidle;
2130 par->SavageWaitFifo = savage2000_waitfifo;
2131 }
2132
2133 info->var.nonstd = 0;
2134 info->var.activate = FB_ACTIVATE_NOW;
2135 info->var.width = -1;
2136 info->var.height = -1;
2137 info->var.accel_flags = 0;
2138
2139 info->fbops = &savagefb_ops;
2140 info->flags = FBINFO_DEFAULT |
2141 FBINFO_HWACCEL_YPAN |
2142 FBINFO_HWACCEL_XPAN;
2143
2144 info->pseudo_palette = par->pseudo_palette;
2145
2146 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2147 /* FIFO size + padding for commands */
2148 info->pixmap.addr = kcalloc(8, 1024, GFP_KERNEL);
2149
2150 err = -ENOMEM;
2151 if (info->pixmap.addr) {
2152 info->pixmap.size = 8*1024;
2153 info->pixmap.scan_align = 4;
2154 info->pixmap.buf_align = 4;
2155 info->pixmap.access_align = 32;
2156
2157 err = fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
2158 if (!err)
2159 info->flags |= FBINFO_HWACCEL_COPYAREA |
2160 FBINFO_HWACCEL_FILLRECT |
2161 FBINFO_HWACCEL_IMAGEBLIT;
2162 else
2163 kfree(info->pixmap.addr);
2164 }
2165 #endif
2166 return err;
2167 }
2168
2169 /* --------------------------------------------------------------------- */
2170
savagefb_probe(struct pci_dev * dev,const struct pci_device_id * id)2171 static int savagefb_probe(struct pci_dev *dev, const struct pci_device_id *id)
2172 {
2173 struct fb_info *info;
2174 struct savagefb_par *par;
2175 u_int h_sync, v_sync;
2176 int err, lpitch;
2177 int video_len;
2178
2179 DBG("savagefb_probe");
2180
2181 info = framebuffer_alloc(sizeof(struct savagefb_par), &dev->dev);
2182 if (!info)
2183 return -ENOMEM;
2184 par = info->par;
2185 mutex_init(&par->open_lock);
2186 err = pci_enable_device(dev);
2187 if (err)
2188 goto failed_enable;
2189
2190 if ((err = pci_request_regions(dev, "savagefb"))) {
2191 printk(KERN_ERR "cannot request PCI regions\n");
2192 goto failed_enable;
2193 }
2194
2195 err = -ENOMEM;
2196
2197 if ((err = savage_init_fb_info(info, dev, id)))
2198 goto failed_init;
2199
2200 err = savage_map_mmio(info);
2201 if (err)
2202 goto failed_mmio;
2203
2204 video_len = savage_init_hw(par);
2205 /* FIXME: can't be negative */
2206 if (video_len < 0) {
2207 err = video_len;
2208 goto failed_mmio;
2209 }
2210
2211 err = savage_map_video(info, video_len);
2212 if (err)
2213 goto failed_video;
2214
2215 INIT_LIST_HEAD(&info->modelist);
2216 #if defined(CONFIG_FB_SAVAGE_I2C)
2217 savagefb_create_i2c_busses(info);
2218 savagefb_probe_i2c_connector(info, &par->edid);
2219 fb_edid_to_monspecs(par->edid, &info->monspecs);
2220 kfree(par->edid);
2221 fb_videomode_to_modelist(info->monspecs.modedb,
2222 info->monspecs.modedb_len,
2223 &info->modelist);
2224 #endif
2225 info->var = savagefb_var800x600x8;
2226 /* if a panel was detected, default to a CVT mode instead */
2227 if (par->SavagePanelWidth) {
2228 struct fb_videomode cvt_mode;
2229
2230 memset(&cvt_mode, 0, sizeof(cvt_mode));
2231 cvt_mode.xres = par->SavagePanelWidth;
2232 cvt_mode.yres = par->SavagePanelHeight;
2233 cvt_mode.refresh = 60;
2234 /* FIXME: if we know there is only the panel
2235 * we can enable reduced blanking as well */
2236 if (fb_find_mode_cvt(&cvt_mode, 0, 0))
2237 printk(KERN_WARNING "No CVT mode found for panel\n");
2238 else if (fb_find_mode(&info->var, info, NULL, NULL, 0,
2239 &cvt_mode, 0) != 3)
2240 info->var = savagefb_var800x600x8;
2241 }
2242
2243 if (mode_option) {
2244 fb_find_mode(&info->var, info, mode_option,
2245 info->monspecs.modedb, info->monspecs.modedb_len,
2246 NULL, 8);
2247 } else if (info->monspecs.modedb != NULL) {
2248 const struct fb_videomode *mode;
2249
2250 mode = fb_find_best_display(&info->monspecs, &info->modelist);
2251 savage_update_var(&info->var, mode);
2252 }
2253
2254 /* maximize virtual vertical length */
2255 lpitch = info->var.xres_virtual*((info->var.bits_per_pixel + 7) >> 3);
2256 info->var.yres_virtual = info->fix.smem_len/lpitch;
2257
2258 if (info->var.yres_virtual < info->var.yres) {
2259 err = -ENOMEM;
2260 goto failed;
2261 }
2262
2263 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2264 /*
2265 * The clipping coordinates are masked with 0xFFF, so limit our
2266 * virtual resolutions to these sizes.
2267 */
2268 if (info->var.yres_virtual > 0x1000)
2269 info->var.yres_virtual = 0x1000;
2270
2271 if (info->var.xres_virtual > 0x1000)
2272 info->var.xres_virtual = 0x1000;
2273 #endif
2274 savagefb_check_var(&info->var, info);
2275 savagefb_set_fix(info);
2276
2277 /*
2278 * Calculate the hsync and vsync frequencies. Note that
2279 * we split the 1e12 constant up so that we can preserve
2280 * the precision and fit the results into 32-bit registers.
2281 * (1953125000 * 512 = 1e12)
2282 */
2283 h_sync = 1953125000 / info->var.pixclock;
2284 h_sync = h_sync * 512 / (info->var.xres + info->var.left_margin +
2285 info->var.right_margin +
2286 info->var.hsync_len);
2287 v_sync = h_sync / (info->var.yres + info->var.upper_margin +
2288 info->var.lower_margin + info->var.vsync_len);
2289
2290 printk(KERN_INFO "savagefb v" SAVAGEFB_VERSION ": "
2291 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2292 info->fix.smem_len >> 10,
2293 info->var.xres, info->var.yres,
2294 h_sync / 1000, h_sync % 1000, v_sync);
2295
2296
2297 fb_destroy_modedb(info->monspecs.modedb);
2298 info->monspecs.modedb = NULL;
2299
2300 err = register_framebuffer(info);
2301 if (err < 0)
2302 goto failed;
2303
2304 printk(KERN_INFO "fb: S3 %s frame buffer device\n",
2305 info->fix.id);
2306
2307 /*
2308 * Our driver data
2309 */
2310 pci_set_drvdata(dev, info);
2311
2312 return 0;
2313
2314 failed:
2315 #ifdef CONFIG_FB_SAVAGE_I2C
2316 savagefb_delete_i2c_busses(info);
2317 #endif
2318 fb_alloc_cmap(&info->cmap, 0, 0);
2319 savage_unmap_video(info);
2320 failed_video:
2321 savage_unmap_mmio(info);
2322 failed_mmio:
2323 kfree(info->pixmap.addr);
2324 failed_init:
2325 pci_release_regions(dev);
2326 failed_enable:
2327 framebuffer_release(info);
2328
2329 return err;
2330 }
2331
savagefb_remove(struct pci_dev * dev)2332 static void savagefb_remove(struct pci_dev *dev)
2333 {
2334 struct fb_info *info = pci_get_drvdata(dev);
2335
2336 DBG("savagefb_remove");
2337
2338 if (info) {
2339 unregister_framebuffer(info);
2340
2341 #ifdef CONFIG_FB_SAVAGE_I2C
2342 savagefb_delete_i2c_busses(info);
2343 #endif
2344 fb_alloc_cmap(&info->cmap, 0, 0);
2345 savage_unmap_video(info);
2346 savage_unmap_mmio(info);
2347 kfree(info->pixmap.addr);
2348 pci_release_regions(dev);
2349 framebuffer_release(info);
2350 }
2351 }
2352
savagefb_suspend_late(struct device * dev,pm_message_t mesg)2353 static int savagefb_suspend_late(struct device *dev, pm_message_t mesg)
2354 {
2355 struct fb_info *info = dev_get_drvdata(dev);
2356 struct savagefb_par *par = info->par;
2357
2358 DBG("savagefb_suspend");
2359
2360 if (mesg.event == PM_EVENT_PRETHAW)
2361 mesg.event = PM_EVENT_FREEZE;
2362 par->pm_state = mesg.event;
2363 dev->power.power_state = mesg;
2364
2365 /*
2366 * For PM_EVENT_FREEZE, do not power down so the console
2367 * can remain active.
2368 */
2369 if (mesg.event == PM_EVENT_FREEZE)
2370 return 0;
2371
2372 console_lock();
2373 fb_set_suspend(info, 1);
2374
2375 if (info->fbops->fb_sync)
2376 info->fbops->fb_sync(info);
2377
2378 savagefb_blank(FB_BLANK_POWERDOWN, info);
2379 savage_set_default_par(par, &par->save);
2380 savage_disable_mmio(par);
2381 console_unlock();
2382
2383 return 0;
2384 }
2385
savagefb_suspend(struct device * dev)2386 static int __maybe_unused savagefb_suspend(struct device *dev)
2387 {
2388 return savagefb_suspend_late(dev, PMSG_SUSPEND);
2389 }
2390
savagefb_hibernate(struct device * dev)2391 static int __maybe_unused savagefb_hibernate(struct device *dev)
2392 {
2393 return savagefb_suspend_late(dev, PMSG_HIBERNATE);
2394 }
2395
savagefb_freeze(struct device * dev)2396 static int __maybe_unused savagefb_freeze(struct device *dev)
2397 {
2398 return savagefb_suspend_late(dev, PMSG_FREEZE);
2399 }
2400
savagefb_resume(struct device * dev)2401 static int __maybe_unused savagefb_resume(struct device *dev)
2402 {
2403 struct fb_info *info = dev_get_drvdata(dev);
2404 struct savagefb_par *par = info->par;
2405 int cur_state = par->pm_state;
2406
2407 DBG("savage_resume");
2408
2409 par->pm_state = PM_EVENT_ON;
2410
2411 /*
2412 * The adapter was not powered down coming back from a
2413 * PM_EVENT_FREEZE.
2414 */
2415 if (cur_state == PM_EVENT_FREEZE)
2416 return 0;
2417
2418 console_lock();
2419
2420 savage_enable_mmio(par);
2421 savage_init_hw(par);
2422 savagefb_set_par(info);
2423 fb_set_suspend(info, 0);
2424 savagefb_blank(FB_BLANK_UNBLANK, info);
2425 console_unlock();
2426
2427 return 0;
2428 }
2429
2430 static const struct dev_pm_ops savagefb_pm_ops = {
2431 #ifdef CONFIG_PM_SLEEP
2432 .suspend = savagefb_suspend,
2433 .resume = savagefb_resume,
2434 .freeze = savagefb_freeze,
2435 .thaw = savagefb_resume,
2436 .poweroff = savagefb_hibernate,
2437 .restore = savagefb_resume,
2438 #endif
2439 };
2440
2441 static const struct pci_device_id savagefb_devices[] = {
2442 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX128,
2443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2444
2445 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64,
2446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2447
2448 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_MX64C,
2449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2450
2451 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128SDR,
2452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2453
2454 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX128DDR,
2455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2456
2457 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64SDR,
2458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2459
2460 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IX64DDR,
2461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2462
2463 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCSDR,
2464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2465
2466 {PCI_VENDOR_ID_S3, PCI_CHIP_SUPSAV_IXCDDR,
2467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SUPERSAVAGE},
2468
2469 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4,
2470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE4},
2471
2472 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D,
2473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D},
2474
2475 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE3D_MV,
2476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE3D_MV},
2477
2478 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000,
2479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE2000},
2480
2481 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX_MV,
2482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX_MV},
2483
2484 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_MX,
2485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_MX},
2486
2487 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX_MV,
2488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX_MV},
2489
2490 {PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE_IX,
2491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_SAVAGE_IX},
2492
2493 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_PM,
2494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_PM},
2495
2496 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_KM,
2497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_KM},
2498
2499 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_P,
2500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_P},
2501
2502 {PCI_VENDOR_ID_S3, PCI_CHIP_S3TWISTER_K,
2503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_S3TWISTER_K},
2504
2505 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDR,
2506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDR},
2507
2508 {PCI_VENDOR_ID_S3, PCI_CHIP_PROSAVAGE_DDRK,
2509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_PROSAVAGE_DDRK},
2510
2511 {0, 0, 0, 0, 0, 0, 0}
2512 };
2513
2514 MODULE_DEVICE_TABLE(pci, savagefb_devices);
2515
2516 static struct pci_driver savagefb_driver = {
2517 .name = "savagefb",
2518 .id_table = savagefb_devices,
2519 .probe = savagefb_probe,
2520 .driver.pm = &savagefb_pm_ops,
2521 .remove = savagefb_remove,
2522 };
2523
2524 /* **************************** exit-time only **************************** */
2525
savage_done(void)2526 static void __exit savage_done(void)
2527 {
2528 DBG("savage_done");
2529 pci_unregister_driver(&savagefb_driver);
2530 }
2531
2532
2533 /* ************************* init in-kernel code ************************** */
2534
savagefb_setup(char * options)2535 static int __init savagefb_setup(char *options)
2536 {
2537 #ifndef MODULE
2538 char *this_opt;
2539
2540 if (!options || !*options)
2541 return 0;
2542
2543 while ((this_opt = strsep(&options, ",")) != NULL) {
2544 mode_option = this_opt;
2545 }
2546 #endif /* !MODULE */
2547 return 0;
2548 }
2549
savagefb_init(void)2550 static int __init savagefb_init(void)
2551 {
2552 char *option;
2553
2554 DBG("savagefb_init");
2555
2556 if (fb_get_options("savagefb", &option))
2557 return -ENODEV;
2558
2559 savagefb_setup(option);
2560 return pci_register_driver(&savagefb_driver);
2561
2562 }
2563
2564 module_init(savagefb_init);
2565 module_exit(savage_done);
2566
2567 module_param(mode_option, charp, 0);
2568 MODULE_PARM_DESC(mode_option, "Specify initial video mode");
2569