1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * sp5100_tco : TCO timer driver for sp5100 chipsets
4 *
5 * (c) Copyright 2009 Google Inc., All Rights Reserved.
6 *
7 * Based on i8xx_tco.c:
8 * (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
9 * Reserved.
10 * https://www.kernelconcepts.de
11 *
12 * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
13 * AMD Publication 45482 "AMD SB800-Series Southbridges Register
14 * Reference Guide"
15 * AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
16 * for AMD Family 16h Models 00h-0Fh Processors"
17 * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
18 * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
19 * for AMD Family 16h Models 30h-3Fh Processors"
20 * AMD Publication 55570-B1-PUB "Processor Programming Reference (PPR)
21 * for AMD Family 17h Model 18h, Revision B1
22 * Processors (PUB)
23 * AMD Publication 55772-A1-PUB "Processor Programming Reference (PPR)
24 * for AMD Family 17h Model 20h, Revision A1
25 * Processors (PUB)
26 */
27
28 /*
29 * Includes, defines, variables, module parameters, ...
30 */
31
32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33
34 #include <linux/init.h>
35 #include <linux/io.h>
36 #include <linux/ioport.h>
37 #include <linux/module.h>
38 #include <linux/moduleparam.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/types.h>
42 #include <linux/watchdog.h>
43
44 #include "sp5100_tco.h"
45
46 #define TCO_DRIVER_NAME "sp5100-tco"
47
48 /* internal variables */
49
50 enum tco_reg_layout {
51 sp5100, sb800, efch, efch_mmio
52 };
53
54 struct sp5100_tco {
55 struct watchdog_device wdd;
56 void __iomem *tcobase;
57 enum tco_reg_layout tco_reg_layout;
58 };
59
60 /* the watchdog platform device */
61 static struct platform_device *sp5100_tco_platform_device;
62 /* the associated PCI device */
63 static struct pci_dev *sp5100_tco_pci;
64
65 /* module parameters */
66
67 #define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
68 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
69 module_param(heartbeat, int, 0);
70 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
71 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
72
73 static bool nowayout = WATCHDOG_NOWAYOUT;
74 module_param(nowayout, bool, 0);
75 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
76 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
77
78 /*
79 * Some TCO specific functions
80 */
81
tco_reg_layout(struct pci_dev * dev)82 static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
83 {
84 if (dev->vendor == PCI_VENDOR_ID_ATI &&
85 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
86 dev->revision < 0x40) {
87 return sp5100;
88 } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
89 sp5100_tco_pci->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
90 sp5100_tco_pci->revision >= AMD_ZEN_SMBUS_PCI_REV) {
91 return efch_mmio;
92 } else if ((dev->vendor == PCI_VENDOR_ID_AMD || dev->vendor == PCI_VENDOR_ID_HYGON) &&
93 ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
94 dev->revision >= 0x41) ||
95 (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
96 dev->revision >= 0x49))) {
97 return efch;
98 }
99 return sb800;
100 }
101
tco_timer_start(struct watchdog_device * wdd)102 static int tco_timer_start(struct watchdog_device *wdd)
103 {
104 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
105 u32 val;
106
107 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
108 val |= SP5100_WDT_START_STOP_BIT;
109 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
110
111 /* This must be a distinct write. */
112 val |= SP5100_WDT_TRIGGER_BIT;
113 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
114
115 return 0;
116 }
117
tco_timer_stop(struct watchdog_device * wdd)118 static int tco_timer_stop(struct watchdog_device *wdd)
119 {
120 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
121 u32 val;
122
123 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
124 val &= ~SP5100_WDT_START_STOP_BIT;
125 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
126
127 return 0;
128 }
129
tco_timer_ping(struct watchdog_device * wdd)130 static int tco_timer_ping(struct watchdog_device *wdd)
131 {
132 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
133 u32 val;
134
135 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
136 val |= SP5100_WDT_TRIGGER_BIT;
137 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
138
139 return 0;
140 }
141
tco_timer_set_timeout(struct watchdog_device * wdd,unsigned int t)142 static int tco_timer_set_timeout(struct watchdog_device *wdd,
143 unsigned int t)
144 {
145 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
146
147 /* Write new heartbeat to watchdog */
148 writel(t, SP5100_WDT_COUNT(tco->tcobase));
149
150 wdd->timeout = t;
151
152 return 0;
153 }
154
sp5100_tco_read_pm_reg8(u8 index)155 static u8 sp5100_tco_read_pm_reg8(u8 index)
156 {
157 outb(index, SP5100_IO_PM_INDEX_REG);
158 return inb(SP5100_IO_PM_DATA_REG);
159 }
160
sp5100_tco_update_pm_reg8(u8 index,u8 reset,u8 set)161 static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
162 {
163 u8 val;
164
165 outb(index, SP5100_IO_PM_INDEX_REG);
166 val = inb(SP5100_IO_PM_DATA_REG);
167 val &= reset;
168 val |= set;
169 outb(val, SP5100_IO_PM_DATA_REG);
170 }
171
tco_timer_enable(struct sp5100_tco * tco)172 static void tco_timer_enable(struct sp5100_tco *tco)
173 {
174 u32 val;
175
176 switch (tco->tco_reg_layout) {
177 case sb800:
178 /* For SB800 or later */
179 /* Set the Watchdog timer resolution to 1 sec */
180 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
181 0xff, SB800_PM_WATCHDOG_SECOND_RES);
182
183 /* Enable watchdog decode bit and watchdog timer */
184 sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
185 ~SB800_PM_WATCHDOG_DISABLE,
186 SB800_PCI_WATCHDOG_DECODE_EN);
187 break;
188 case sp5100:
189 /* For SP5100 or SB7x0 */
190 /* Enable watchdog decode bit */
191 pci_read_config_dword(sp5100_tco_pci,
192 SP5100_PCI_WATCHDOG_MISC_REG,
193 &val);
194
195 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
196
197 pci_write_config_dword(sp5100_tco_pci,
198 SP5100_PCI_WATCHDOG_MISC_REG,
199 val);
200
201 /* Enable Watchdog timer and set the resolution to 1 sec */
202 sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
203 ~SP5100_PM_WATCHDOG_DISABLE,
204 SP5100_PM_WATCHDOG_SECOND_RES);
205 break;
206 case efch:
207 /* Set the Watchdog timer resolution to 1 sec and enable */
208 sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
209 ~EFCH_PM_WATCHDOG_DISABLE,
210 EFCH_PM_DECODEEN_SECOND_RES);
211 break;
212 default:
213 break;
214 }
215 }
216
sp5100_tco_read_pm_reg32(u8 index)217 static u32 sp5100_tco_read_pm_reg32(u8 index)
218 {
219 u32 val = 0;
220 int i;
221
222 for (i = 3; i >= 0; i--)
223 val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
224
225 return val;
226 }
227
sp5100_tco_request_region(struct device * dev,u32 mmio_addr,const char * dev_name)228 static u32 sp5100_tco_request_region(struct device *dev,
229 u32 mmio_addr,
230 const char *dev_name)
231 {
232 if (!devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
233 dev_name)) {
234 dev_dbg(dev, "MMIO address 0x%08x already in use\n", mmio_addr);
235 return 0;
236 }
237
238 return mmio_addr;
239 }
240
sp5100_tco_prepare_base(struct sp5100_tco * tco,u32 mmio_addr,u32 alt_mmio_addr,const char * dev_name)241 static u32 sp5100_tco_prepare_base(struct sp5100_tco *tco,
242 u32 mmio_addr,
243 u32 alt_mmio_addr,
244 const char *dev_name)
245 {
246 struct device *dev = tco->wdd.parent;
247
248 dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n", mmio_addr);
249
250 if (!mmio_addr && !alt_mmio_addr)
251 return -ENODEV;
252
253 /* Check for MMIO address and alternate MMIO address conflicts */
254 if (mmio_addr)
255 mmio_addr = sp5100_tco_request_region(dev, mmio_addr, dev_name);
256
257 if (!mmio_addr && alt_mmio_addr)
258 mmio_addr = sp5100_tco_request_region(dev, alt_mmio_addr, dev_name);
259
260 if (!mmio_addr) {
261 dev_err(dev, "Failed to reserve MMIO or alternate MMIO region\n");
262 return -EBUSY;
263 }
264
265 tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
266 if (!tco->tcobase) {
267 dev_err(dev, "MMIO address 0x%08x failed mapping\n", mmio_addr);
268 devm_release_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
269 return -ENOMEM;
270 }
271
272 dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
273
274 return 0;
275 }
276
sp5100_tco_timer_init(struct sp5100_tco * tco)277 static int sp5100_tco_timer_init(struct sp5100_tco *tco)
278 {
279 struct watchdog_device *wdd = &tco->wdd;
280 struct device *dev = wdd->parent;
281 u32 val;
282
283 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
284 if (val & SP5100_WDT_DISABLED) {
285 dev_err(dev, "Watchdog hardware is disabled\n");
286 return -ENODEV;
287 }
288
289 /*
290 * Save WatchDogFired status, because WatchDogFired flag is
291 * cleared here.
292 */
293 if (val & SP5100_WDT_FIRED)
294 wdd->bootstatus = WDIOF_CARDRESET;
295
296 /* Set watchdog action to reset the system */
297 val &= ~SP5100_WDT_ACTION_RESET;
298 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
299
300 /* Set a reasonable heartbeat before we stop the timer */
301 tco_timer_set_timeout(wdd, wdd->timeout);
302
303 /*
304 * Stop the TCO before we change anything so we don't race with
305 * a zeroed timer.
306 */
307 tco_timer_stop(wdd);
308
309 return 0;
310 }
311
efch_read_pm_reg8(void __iomem * addr,u8 index)312 static u8 efch_read_pm_reg8(void __iomem *addr, u8 index)
313 {
314 return readb(addr + index);
315 }
316
efch_update_pm_reg8(void __iomem * addr,u8 index,u8 reset,u8 set)317 static void efch_update_pm_reg8(void __iomem *addr, u8 index, u8 reset, u8 set)
318 {
319 u8 val;
320
321 val = readb(addr + index);
322 val &= reset;
323 val |= set;
324 writeb(val, addr + index);
325 }
326
tco_timer_enable_mmio(void __iomem * addr)327 static void tco_timer_enable_mmio(void __iomem *addr)
328 {
329 efch_update_pm_reg8(addr, EFCH_PM_DECODEEN3,
330 ~EFCH_PM_WATCHDOG_DISABLE,
331 EFCH_PM_DECODEEN_SECOND_RES);
332 }
333
sp5100_tco_setupdevice_mmio(struct device * dev,struct watchdog_device * wdd)334 static int sp5100_tco_setupdevice_mmio(struct device *dev,
335 struct watchdog_device *wdd)
336 {
337 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
338 const char *dev_name = SB800_DEVNAME;
339 u32 mmio_addr = 0, alt_mmio_addr = 0;
340 struct resource *res;
341 void __iomem *addr;
342 int ret;
343 u32 val;
344
345 res = request_mem_region_muxed(EFCH_PM_ACPI_MMIO_PM_ADDR,
346 EFCH_PM_ACPI_MMIO_PM_SIZE,
347 "sp5100_tco");
348
349 if (!res) {
350 dev_err(dev,
351 "Memory region 0x%08x already in use\n",
352 EFCH_PM_ACPI_MMIO_PM_ADDR);
353 return -EBUSY;
354 }
355
356 addr = ioremap(EFCH_PM_ACPI_MMIO_PM_ADDR, EFCH_PM_ACPI_MMIO_PM_SIZE);
357 if (!addr) {
358 dev_err(dev, "Address mapping failed\n");
359 ret = -ENOMEM;
360 goto out;
361 }
362
363 /*
364 * EFCH_PM_DECODEEN_WDT_TMREN is dual purpose. This bitfield
365 * enables sp5100_tco register MMIO space decoding. The bitfield
366 * also starts the timer operation. Enable if not already enabled.
367 */
368 val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
369 if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
370 efch_update_pm_reg8(addr, EFCH_PM_DECODEEN, 0xff,
371 EFCH_PM_DECODEEN_WDT_TMREN);
372 }
373
374 /* Error if the timer could not be enabled */
375 val = efch_read_pm_reg8(addr, EFCH_PM_DECODEEN);
376 if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
377 dev_err(dev, "Failed to enable the timer\n");
378 ret = -EFAULT;
379 goto out;
380 }
381
382 mmio_addr = EFCH_PM_WDT_ADDR;
383
384 /* Determine alternate MMIO base address */
385 val = efch_read_pm_reg8(addr, EFCH_PM_ISACONTROL);
386 if (val & EFCH_PM_ISACONTROL_MMIOEN)
387 alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
388 EFCH_PM_ACPI_MMIO_WDT_OFFSET;
389
390 ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
391 if (!ret) {
392 tco_timer_enable_mmio(addr);
393 ret = sp5100_tco_timer_init(tco);
394 }
395
396 out:
397 if (addr)
398 iounmap(addr);
399
400 release_resource(res);
401 kfree(res);
402
403 return ret;
404 }
405
sp5100_tco_setupdevice(struct device * dev,struct watchdog_device * wdd)406 static int sp5100_tco_setupdevice(struct device *dev,
407 struct watchdog_device *wdd)
408 {
409 struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
410 const char *dev_name;
411 u32 mmio_addr = 0, val;
412 u32 alt_mmio_addr = 0;
413 int ret;
414
415 if (tco->tco_reg_layout == efch_mmio)
416 return sp5100_tco_setupdevice_mmio(dev, wdd);
417
418 /* Request the IO ports used by this driver */
419 if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
420 SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
421 dev_err(dev, "I/O address 0x%04x already in use\n",
422 SP5100_IO_PM_INDEX_REG);
423 return -EBUSY;
424 }
425
426 /*
427 * Determine type of southbridge chipset.
428 */
429 switch (tco->tco_reg_layout) {
430 case sp5100:
431 dev_name = SP5100_DEVNAME;
432 mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
433 0xfffffff8;
434
435 /*
436 * Secondly, find the watchdog timer MMIO address
437 * from SBResource_MMIO register.
438 */
439
440 /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
441 pci_read_config_dword(sp5100_tco_pci,
442 SP5100_SB_RESOURCE_MMIO_BASE,
443 &val);
444
445 /* Verify MMIO is enabled and using bar0 */
446 if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
447 alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
448 break;
449 case sb800:
450 dev_name = SB800_DEVNAME;
451 mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
452 0xfffffff8;
453
454 /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
455 val = sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
456
457 /* Verify MMIO is enabled and using bar0 */
458 if ((val & SB800_ACPI_MMIO_MASK) == SB800_ACPI_MMIO_DECODE_EN)
459 alt_mmio_addr = (val & ~0xfff) + SB800_PM_WDT_MMIO_OFFSET;
460 break;
461 case efch:
462 dev_name = SB800_DEVNAME;
463 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
464 if (val & EFCH_PM_DECODEEN_WDT_TMREN)
465 mmio_addr = EFCH_PM_WDT_ADDR;
466
467 val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
468 if (val & EFCH_PM_ISACONTROL_MMIOEN)
469 alt_mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
470 EFCH_PM_ACPI_MMIO_WDT_OFFSET;
471 break;
472 default:
473 return -ENODEV;
474 }
475
476 ret = sp5100_tco_prepare_base(tco, mmio_addr, alt_mmio_addr, dev_name);
477 if (!ret) {
478 /* Setup the watchdog timer */
479 tco_timer_enable(tco);
480 ret = sp5100_tco_timer_init(tco);
481 }
482
483 release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
484 return ret;
485 }
486
487 static struct watchdog_info sp5100_tco_wdt_info = {
488 .identity = "SP5100 TCO timer",
489 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
490 };
491
492 static const struct watchdog_ops sp5100_tco_wdt_ops = {
493 .owner = THIS_MODULE,
494 .start = tco_timer_start,
495 .stop = tco_timer_stop,
496 .ping = tco_timer_ping,
497 .set_timeout = tco_timer_set_timeout,
498 };
499
sp5100_tco_probe(struct platform_device * pdev)500 static int sp5100_tco_probe(struct platform_device *pdev)
501 {
502 struct device *dev = &pdev->dev;
503 struct watchdog_device *wdd;
504 struct sp5100_tco *tco;
505 int ret;
506
507 tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
508 if (!tco)
509 return -ENOMEM;
510
511 tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
512
513 wdd = &tco->wdd;
514 wdd->parent = dev;
515 wdd->info = &sp5100_tco_wdt_info;
516 wdd->ops = &sp5100_tco_wdt_ops;
517 wdd->timeout = WATCHDOG_HEARTBEAT;
518 wdd->min_timeout = 1;
519 wdd->max_timeout = 0xffff;
520
521 watchdog_init_timeout(wdd, heartbeat, NULL);
522 watchdog_set_nowayout(wdd, nowayout);
523 watchdog_stop_on_reboot(wdd);
524 watchdog_stop_on_unregister(wdd);
525 watchdog_set_drvdata(wdd, tco);
526
527 ret = sp5100_tco_setupdevice(dev, wdd);
528 if (ret)
529 return ret;
530
531 ret = devm_watchdog_register_device(dev, wdd);
532 if (ret)
533 return ret;
534
535 /* Show module parameters */
536 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
537 wdd->timeout, nowayout);
538
539 return 0;
540 }
541
542 static struct platform_driver sp5100_tco_driver = {
543 .probe = sp5100_tco_probe,
544 .driver = {
545 .name = TCO_DRIVER_NAME,
546 },
547 };
548
549 /*
550 * Data for PCI driver interface
551 *
552 * This data only exists for exporting the supported
553 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
554 * register a pci_driver, because someone else might
555 * want to register another driver on the same PCI id.
556 */
557 static const struct pci_device_id sp5100_tco_pci_tbl[] = {
558 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
559 PCI_ANY_ID, },
560 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
561 PCI_ANY_ID, },
562 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
563 PCI_ANY_ID, },
564 { PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
565 PCI_ANY_ID, },
566 { 0, }, /* End of list */
567 };
568 MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
569
sp5100_tco_init(void)570 static int __init sp5100_tco_init(void)
571 {
572 struct pci_dev *dev = NULL;
573 int err;
574
575 /* Match the PCI device */
576 for_each_pci_dev(dev) {
577 if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
578 sp5100_tco_pci = dev;
579 break;
580 }
581 }
582
583 if (!sp5100_tco_pci)
584 return -ENODEV;
585
586 pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
587
588 err = platform_driver_register(&sp5100_tco_driver);
589 if (err)
590 return err;
591
592 sp5100_tco_platform_device =
593 platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
594 if (IS_ERR(sp5100_tco_platform_device)) {
595 err = PTR_ERR(sp5100_tco_platform_device);
596 goto unreg_platform_driver;
597 }
598
599 return 0;
600
601 unreg_platform_driver:
602 platform_driver_unregister(&sp5100_tco_driver);
603 return err;
604 }
605
sp5100_tco_exit(void)606 static void __exit sp5100_tco_exit(void)
607 {
608 platform_device_unregister(sp5100_tco_platform_device);
609 platform_driver_unregister(&sp5100_tco_driver);
610 }
611
612 module_init(sp5100_tco_init);
613 module_exit(sp5100_tco_exit);
614
615 MODULE_AUTHOR("Priyanka Gupta");
616 MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
617 MODULE_LICENSE("GPL");
618